Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	425	1			T12	4		T26	3		T40	2
auto[ReadAddrCrossIntoMailbox]	296	1			T12	4		T26	3		T91	2
auto[ReadAddrCrossOutOfMailbox]	308	1			T12	3		T26	1		T40	3
auto[ReadAddrCrossAllMailbox]	237	1			T12	3		T26	2		T91	6
auto[ReadAddrOutsideMailbox]	3648	1			T1	4		T3	4		T8	12

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2413

1

T1

2

T3

2

T8

6

auto[1]

2501

1

T1

2

T3

2

T8

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	857	1			T8	2		T11	2		T12	9
read_ops[0x0b]	834	1			T3	2		T8	2		T12	9
read_ops[0x3b]	828	1			T8	2		T12	14		T26	11
read_ops[0x6b]	787	1			T1	2		T12	7		T26	11
read_ops[0xbb]	787	1			T3	2		T11	2		T12	12
read_ops[0xeb]	821	1			T1	2		T8	6		T12	13

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T26	1		T116	1		T18	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T26	1		T31	1		T116	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T12	1		T91	1		T18	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T91	1		T47	1		T227	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T116	1		T262	1		T227	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T116	1		T44	1		T262	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	27	1			T12	1		T91	1		T40	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T91	1		T47	1		T44	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	320	1			T8	1		T11	1		T12	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	308	1			T8	1		T11	1		T12	5
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T26	1		T48	1		T18	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T12	1		T44	1		T215	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T44	1		T48	1		T18	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T26	1		T46	1		T44	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T44	1		T18	1		T198	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T18	2		T19	3		T227	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T195	1		T199	2		T263	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T44	1		T170	1		T215	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	307	1			T3	1		T8	1		T12	4
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	310	1			T3	1		T8	1		T12	4
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T44	1		T172	1		T264	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T46	1		T227	2		T20	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T26	1		T227	2		T215	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T46	1		T18	1		T197	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T20	1		T198	1		T162	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T12	2		T46	1		T44	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T47	1		T20	1		T265	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T44	1		T48	1		T19	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	315	1			T8	1		T12	6		T26	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	307	1			T8	1		T12	6		T26	7
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T40	1		T266	1		T20	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T18	2		T19	1		T227	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T12	2		T26	1		T48	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T44	1		T227	1		T266	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T12	1		T40	1		T47	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T170	1		T198	2		T195	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T26	1		T91	1		T47	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T26	1		T91	1		T227	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T1	1		T12	1		T26	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T1	1		T12	3		T26	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T12	1		T40	1		T248	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T12	1		T48	1		T18	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T227	1		T20	1		T170	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T19	1		T170	1		T198	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T40	2		T266	1		T195	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T197	1		T266	1		T170	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T12	1		T40	1		T20	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T12	1		T20	1		T257	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	286	1			T3	1		T11	1		T26	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	312	1			T3	1		T11	1		T12	8
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T248	3		T227	1		T266	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T12	1		T46	1		T248	3
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T12	1		T20	1		T225	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T18	1		T19	1		T20	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T26	1		T233	1		T172	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T47	1		T19	2		T35	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T91	1		T40	1		T19	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T91	1		T266	1		T195	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	285	1			T1	1		T8	3		T12	5
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	313	1			T1	1		T8	3		T12	6