Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	804	1			T12	10		T14	7		T15	14
all_values[1]	804	1			T12	10		T14	7		T15	14
all_values[2]	804	1			T12	10		T14	7		T15	14
all_values[3]	804	1			T12	10		T14	7		T15	14
all_values[4]	804	1			T12	10		T14	7		T15	14
all_values[5]	804	1			T12	10		T14	7		T15	14
all_values[6]	804	1			T12	10		T14	7		T15	14
all_values[7]	804	1			T12	10		T14	7		T15	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3422

1

T12

45

T14

32

T15

53

auto[1]

3010

1

T12

35

T14

24

T15

59

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2578

1

T12

27

T14

19

T15

48

auto[1]

3854

1

T12

53

T14

37

T15

64

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3682

1

T12

40

T14

32

T15

66

auto[1]

2750

1

T12

40

T14

24

T15

46

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	153	1			T12	3		T15	2		T16	5
all_values[0]	auto[0]	auto[0]	auto[1]	68	1			T12	1		T14	1		T15	1
all_values[0]	auto[0]	auto[1]	auto[0]	131	1			T12	3		T14	1		T15	4
all_values[0]	auto[0]	auto[1]	auto[1]	95	1			T15	2		T16	2		T17	2
all_values[0]	auto[1]	auto[0]	auto[1]	192	1			T12	1		T14	2		T15	3
all_values[0]	auto[1]	auto[1]	auto[1]	165	1			T12	2		T14	3		T15	2
all_values[1]	auto[0]	auto[0]	auto[0]	161	1			T12	3		T14	3		T15	1
all_values[1]	auto[0]	auto[0]	auto[1]	93	1			T12	1		T14	2		T15	2
all_values[1]	auto[0]	auto[1]	auto[0]	147	1			T15	1		T16	4		T17	2
all_values[1]	auto[0]	auto[1]	auto[1]	63	1			T12	1		T15	2		T16	4
all_values[1]	auto[1]	auto[0]	auto[1]	182	1			T12	3		T15	2		T16	12
all_values[1]	auto[1]	auto[1]	auto[1]	158	1			T12	2		T14	2		T15	6
all_values[2]	auto[0]	auto[0]	auto[0]	152	1			T12	2		T14	2		T15	2
all_values[2]	auto[0]	auto[0]	auto[1]	78	1			T12	1		T15	1		T16	1
all_values[2]	auto[0]	auto[1]	auto[0]	146	1			T15	4		T16	3		T17	1
all_values[2]	auto[0]	auto[1]	auto[1]	90	1			T12	1		T14	1		T15	1
all_values[2]	auto[1]	auto[0]	auto[1]	177	1			T12	4		T14	2		T15	3
all_values[2]	auto[1]	auto[1]	auto[1]	161	1			T12	2		T14	2		T15	3
all_values[3]	auto[0]	auto[0]	auto[0]	177	1			T12	4		T14	2		T15	4
all_values[3]	auto[0]	auto[0]	auto[1]	71	1			T15	1		T16	3		T17	1
all_values[3]	auto[0]	auto[1]	auto[0]	123	1			T12	1		T14	2		T15	4
all_values[3]	auto[0]	auto[1]	auto[1]	71	1			T12	2		T14	1		T15	1
all_values[3]	auto[1]	auto[0]	auto[1]	177	1			T12	2		T14	1		T15	3
all_values[3]	auto[1]	auto[1]	auto[1]	185	1			T12	1		T14	1		T15	1
all_values[4]	auto[0]	auto[0]	auto[0]	167	1			T12	1		T14	1		T16	5
all_values[4]	auto[0]	auto[0]	auto[1]	79	1			T12	1		T15	1		T16	3
all_values[4]	auto[0]	auto[1]	auto[0]	122	1			T14	2		T15	3		T16	3
all_values[4]	auto[0]	auto[1]	auto[1]	89	1			T12	2		T14	1		T15	2
all_values[4]	auto[1]	auto[0]	auto[1]	171	1			T12	1		T14	2		T15	1
all_values[4]	auto[1]	auto[1]	auto[1]	176	1			T12	5		T14	1		T15	7
all_values[5]	auto[0]	auto[0]	auto[0]	268	1			T12	1		T14	4		T15	4
all_values[5]	auto[0]	auto[1]	auto[0]	198	1			T12	2		T15	4		T16	2
all_values[5]	auto[1]	auto[0]	auto[1]	174	1			T12	4		T14	2		T15	4
all_values[5]	auto[1]	auto[1]	auto[1]	164	1			T12	3		T14	1		T15	2
all_values[6]	auto[0]	auto[0]	auto[0]	173	1			T12	1		T14	1		T15	5
all_values[6]	auto[0]	auto[0]	auto[1]	73	1			T14	1		T15	2		T16	1
all_values[6]	auto[0]	auto[1]	auto[0]	159	1			T12	4		T14	1		T15	2
all_values[6]	auto[0]	auto[1]	auto[1]	79	1			T14	2		T16	6		T17	1
all_values[6]	auto[1]	auto[0]	auto[1]	176	1			T12	4		T15	4		T16	6
all_values[6]	auto[1]	auto[1]	auto[1]	144	1			T12	1		T14	2		T15	1
all_values[7]	auto[0]	auto[0]	auto[0]	182	1			T12	1		T15	5		T16	8
all_values[7]	auto[0]	auto[0]	auto[1]	80	1			T12	2		T14	3		T16	3
all_values[7]	auto[0]	auto[1]	auto[0]	119	1			T12	1		T15	3		T16	1
all_values[7]	auto[0]	auto[1]	auto[1]	75	1			T12	1		T14	1		T15	2
all_values[7]	auto[1]	auto[0]	auto[1]	198	1			T12	4		T14	3		T15	2
all_values[7]	auto[1]	auto[1]	auto[1]	150	1			T12	1		T15	2		T16	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal