Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1876

1

T10

1

T12

7

T13

11

auto[1]

1742

1

T10

1

T12

7

T13

8

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2102

1

T10

2

T12

14

T13

19

auto[1]

1516

1

T24

3

T14

3

T84

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2807

1

T10

2

T12

10

T13

11

auto[1]

811

1

T12

4

T13

8

T25

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	730	1			T12	3		T13	2		T25	1
valid[1]	754	1			T10	1		T12	1		T13	7
valid[2]	717	1			T10	1		T12	4		T13	2
valid[3]	684	1			T12	3		T13	4		T24	1
valid[4]	733	1			T12	3		T13	4		T25	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	139	1			T12	1		T25	1		T31	1
auto[0]	auto[0]	valid[0]	auto[1]	142	1			T14	1		T86	1		T87	1
auto[0]	auto[0]	valid[1]	auto[0]	147	1			T12	1		T13	3		T31	2
auto[0]	auto[0]	valid[1]	auto[1]	177	1			T24	1		T84	1		T86	5
auto[0]	auto[0]	valid[2]	auto[0]	129	1			T10	1		T12	2		T13	1
auto[0]	auto[0]	valid[2]	auto[1]	183	1			T24	1		T84	2		T86	6
auto[0]	auto[0]	valid[3]	auto[0]	132	1			T13	3		T31	1		T32	2
auto[0]	auto[0]	valid[3]	auto[1]	141	1			T86	3		T88	2		T87	2
auto[0]	auto[0]	valid[4]	auto[0]	135	1			T12	1		T13	1		T32	2
auto[0]	auto[0]	valid[4]	auto[1]	141	1			T84	1		T86	4		T90	7
auto[0]	auto[1]	valid[0]	auto[0]	119	1			T12	2		T13	1		T33	3
auto[0]	auto[1]	valid[0]	auto[1]	177	1			T14	1		T84	2		T86	8
auto[0]	auto[1]	valid[1]	auto[0]	135	1			T10	1		T13	1		T33	2
auto[0]	auto[1]	valid[1]	auto[1]	142	1			T14	1		T86	2		T88	1
auto[0]	auto[1]	valid[2]	auto[0]	111	1			T12	2		T13	1		T14	1
auto[0]	auto[1]	valid[2]	auto[1]	135	1			T84	1		T86	4		T88	1
auto[0]	auto[1]	valid[3]	auto[0]	103	1			T31	3		T316	1		T20	3
auto[0]	auto[1]	valid[3]	auto[1]	138	1			T24	1		T86	2		T90	2
auto[0]	auto[1]	valid[4]	auto[0]	141	1			T12	1		T31	1		T32	2
auto[0]	auto[1]	valid[4]	auto[1]	140	1			T86	5		T87	5		T90	3
auto[1]	auto[0]	valid[0]	auto[0]	71	1			T13	1		T31	1		T32	1
auto[1]	auto[0]	valid[1]	auto[0]	82	1			T13	1		T31	1		T14	3
auto[1]	auto[0]	valid[2]	auto[0]	81	1			T31	2		T33	2		T16	3
auto[1]	auto[0]	valid[3]	auto[0]	89	1			T12	1		T13	1		T33	2
auto[1]	auto[0]	valid[4]	auto[0]	87	1			T12	1		T25	1		T31	1
auto[1]	auto[1]	valid[0]	auto[0]	82	1			T32	1		T16	1		T17	1
auto[1]	auto[1]	valid[1]	auto[0]	71	1			T13	2		T31	1		T33	1
auto[1]	auto[1]	valid[2]	auto[0]	78	1			T31	1		T32	1		T33	2
auto[1]	auto[1]	valid[3]	auto[0]	81	1			T12	2		T33	1		T16	1
auto[1]	auto[1]	valid[4]	auto[0]	89	1			T13	3		T32	2		T18	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal