Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53104

1

T9

13

T10

142

T12

404

auto[1]

16197

1

T24

3

T14

55

T84

130

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49772

1

T9

7

T10

93

T12

271

auto[1]

19529

1

T9

6

T10

49

T12

133

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35769	1			T9	4		T10	68		T12	228
others[1]	5840	1			T9	1		T10	11		T12	31
others[2]	5887	1			T9	3		T10	12		T12	24
others[3]	6441	1			T9	1		T10	9		T12	31
interest[1]	3878	1			T9	1		T10	8		T12	23
interest[4]	23498	1			T9	4		T10	49		T12	153
interest[64]	11486	1			T9	3		T10	34		T12	67

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17298	1			T9	2		T10	44		T12	154
auto[0]	auto[0]	others[1]	2879	1			T10	5		T12	20		T13	20
auto[0]	auto[0]	others[2]	2853	1			T9	1		T10	11		T12	13
auto[0]	auto[0]	others[3]	3090	1			T9	1		T10	5		T12	23
auto[0]	auto[0]	interest[1]	1873	1			T9	1		T10	8		T12	17
auto[0]	auto[0]	interest[4]	11238	1			T9	2		T10	33		T12	109
auto[0]	auto[0]	interest[64]	5582	1			T9	2		T10	20		T12	44
auto[0]	auto[1]	others[0]	8471	1			T24	3		T14	28		T84	64
auto[0]	auto[1]	others[1]	1324	1			T14	2		T84	16		T86	33
auto[0]	auto[1]	others[2]	1378	1			T14	3		T84	13		T86	39
auto[0]	auto[1]	others[3]	1534	1			T14	10		T84	10		T86	40
auto[0]	auto[1]	interest[1]	881	1			T14	2		T84	6		T86	25
auto[0]	auto[1]	interest[4]	5727	1			T24	3		T14	17		T84	48
auto[0]	auto[1]	interest[64]	2609	1			T14	10		T84	21		T86	88
auto[1]	auto[0]	others[0]	10000	1			T9	2		T10	24		T12	74
auto[1]	auto[0]	others[1]	1637	1			T9	1		T10	6		T12	11
auto[1]	auto[0]	others[2]	1656	1			T9	2		T10	1		T12	11
auto[1]	auto[0]	others[3]	1817	1			T10	4		T12	8		T13	12
auto[1]	auto[0]	interest[1]	1124	1			T12	6		T13	4		T31	6
auto[1]	auto[0]	interest[4]	6533	1			T9	2		T10	16		T12	44
auto[1]	auto[0]	interest[64]	3295	1			T9	1		T10	14		T12	23

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal