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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1149
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T119 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2279486915 Jul 12 06:42:20 PM PDT 24 Jul 12 06:42:26 PM PDT 24 28378228 ps
T147 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.822389069 Jul 12 06:42:21 PM PDT 24 Jul 12 06:42:26 PM PDT 24 18546202 ps
T103 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.687826768 Jul 12 06:42:20 PM PDT 24 Jul 12 06:42:43 PM PDT 24 295829810 ps
T1042 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2248577579 Jul 12 06:42:09 PM PDT 24 Jul 12 06:42:12 PM PDT 24 73286846 ps
T154 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.587832477 Jul 12 06:42:47 PM PDT 24 Jul 12 06:42:57 PM PDT 24 329411073 ps
T80 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1266487245 Jul 12 06:42:16 PM PDT 24 Jul 12 06:42:21 PM PDT 24 40938772 ps
T112 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2381402875 Jul 12 06:43:29 PM PDT 24 Jul 12 06:43:34 PM PDT 24 379090139 ps
T1043 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1627271918 Jul 12 06:42:38 PM PDT 24 Jul 12 06:42:43 PM PDT 24 12766390 ps
T1044 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3320773845 Jul 12 06:42:23 PM PDT 24 Jul 12 06:42:28 PM PDT 24 15998336 ps
T107 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1082206521 Jul 12 06:42:29 PM PDT 24 Jul 12 06:42:35 PM PDT 24 218035246 ps
T120 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4138948809 Jul 12 06:42:13 PM PDT 24 Jul 12 06:42:18 PM PDT 24 158583022 ps
T121 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3027029999 Jul 12 06:42:18 PM PDT 24 Jul 12 06:42:55 PM PDT 24 3258165215 ps
T155 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1170696668 Jul 12 06:42:14 PM PDT 24 Jul 12 06:42:22 PM PDT 24 2336160973 ps
T1045 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.621317298 Jul 12 06:42:23 PM PDT 24 Jul 12 06:42:29 PM PDT 24 108106787 ps
T110 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2858360770 Jul 12 06:42:22 PM PDT 24 Jul 12 06:42:30 PM PDT 24 467513818 ps
T1046 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1760282874 Jul 12 06:42:13 PM PDT 24 Jul 12 06:42:17 PM PDT 24 57585583 ps
T122 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2735953163 Jul 12 06:42:33 PM PDT 24 Jul 12 06:42:38 PM PDT 24 98282589 ps
T1047 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.308709983 Jul 12 06:42:53 PM PDT 24 Jul 12 06:42:57 PM PDT 24 48157812 ps
T81 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3989456059 Jul 12 06:42:16 PM PDT 24 Jul 12 06:42:21 PM PDT 24 32448643 ps
T1048 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.654219100 Jul 12 06:42:22 PM PDT 24 Jul 12 06:42:27 PM PDT 24 81134920 ps
T1049 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1028131903 Jul 12 06:42:18 PM PDT 24 Jul 12 06:42:25 PM PDT 24 621817388 ps
T1050 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.842427923 Jul 12 06:42:42 PM PDT 24 Jul 12 06:42:45 PM PDT 24 15497266 ps
T1051 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3084639835 Jul 12 06:42:45 PM PDT 24 Jul 12 06:42:47 PM PDT 24 17935917 ps
T1052 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.315504565 Jul 12 06:42:43 PM PDT 24 Jul 12 06:42:52 PM PDT 24 1090900033 ps
T156 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3620243333 Jul 12 06:42:41 PM PDT 24 Jul 12 06:42:49 PM PDT 24 1589321401 ps
T1053 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4156855971 Jul 12 06:42:54 PM PDT 24 Jul 12 06:42:57 PM PDT 24 24851427 ps
T1054 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1458661091 Jul 12 06:42:31 PM PDT 24 Jul 12 06:42:34 PM PDT 24 38631835 ps
T1055 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2048565010 Jul 12 06:42:37 PM PDT 24 Jul 12 06:42:42 PM PDT 24 36903828 ps
T1056 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.347846573 Jul 12 06:42:24 PM PDT 24 Jul 12 06:42:29 PM PDT 24 56128285 ps
T1057 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.659956326 Jul 12 06:42:35 PM PDT 24 Jul 12 06:42:41 PM PDT 24 72613396 ps
T1058 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3750547786 Jul 12 06:42:36 PM PDT 24 Jul 12 06:42:41 PM PDT 24 36778340 ps
T1059 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.93674892 Jul 12 06:42:35 PM PDT 24 Jul 12 06:42:40 PM PDT 24 189676078 ps
T1060 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2376168924 Jul 12 06:42:36 PM PDT 24 Jul 12 06:42:40 PM PDT 24 14117064 ps
T1061 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1406275392 Jul 12 06:42:35 PM PDT 24 Jul 12 06:42:41 PM PDT 24 135901747 ps
T1062 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4119315396 Jul 12 06:42:36 PM PDT 24 Jul 12 06:42:42 PM PDT 24 488605143 ps
T127 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2162066856 Jul 12 06:42:23 PM PDT 24 Jul 12 06:42:29 PM PDT 24 92344173 ps
T1063 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2382997100 Jul 12 06:42:24 PM PDT 24 Jul 12 06:42:35 PM PDT 24 558650935 ps
T1064 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1671693632 Jul 12 06:42:26 PM PDT 24 Jul 12 06:42:30 PM PDT 24 19649140 ps
T1065 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2142612835 Jul 12 06:42:37 PM PDT 24 Jul 12 06:42:42 PM PDT 24 13322058 ps
T1066 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2920247766 Jul 12 06:42:23 PM PDT 24 Jul 12 06:42:28 PM PDT 24 10430077 ps
T111 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2646756141 Jul 12 06:42:22 PM PDT 24 Jul 12 06:42:29 PM PDT 24 64291893 ps
T1067 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1819128366 Jul 12 06:42:38 PM PDT 24 Jul 12 06:42:43 PM PDT 24 19608079 ps
T1068 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1271913771 Jul 12 06:42:20 PM PDT 24 Jul 12 06:42:26 PM PDT 24 21753453 ps
T1069 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3366975767 Jul 12 06:42:38 PM PDT 24 Jul 12 06:42:46 PM PDT 24 62919976 ps
T108 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1571410618 Jul 12 06:42:13 PM PDT 24 Jul 12 06:42:21 PM PDT 24 148018503 ps
T181 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.205508768 Jul 12 06:42:36 PM PDT 24 Jul 12 06:42:57 PM PDT 24 1382990367 ps
T109 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3080423633 Jul 12 06:42:23 PM PDT 24 Jul 12 06:42:31 PM PDT 24 119187088 ps
T1070 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3576755820 Jul 12 06:42:23 PM PDT 24 Jul 12 06:42:42 PM PDT 24 2623932844 ps
T1071 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1022023232 Jul 12 06:42:18 PM PDT 24 Jul 12 06:42:24 PM PDT 24 217127924 ps
T1072 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3990751628 Jul 12 06:42:38 PM PDT 24 Jul 12 06:42:45 PM PDT 24 245084117 ps
T1073 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2551127848 Jul 12 06:42:32 PM PDT 24 Jul 12 06:42:35 PM PDT 24 27153992 ps
T1074 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2501933252 Jul 12 06:42:36 PM PDT 24 Jul 12 06:42:40 PM PDT 24 12747838 ps
T1075 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1617070426 Jul 12 06:42:54 PM PDT 24 Jul 12 06:42:58 PM PDT 24 58797317 ps
T1076 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1529899886 Jul 12 06:42:22 PM PDT 24 Jul 12 06:42:34 PM PDT 24 1301033223 ps
T123 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2025032279 Jul 12 06:42:30 PM PDT 24 Jul 12 06:42:33 PM PDT 24 129845677 ps
T180 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1126244641 Jul 12 06:42:30 PM PDT 24 Jul 12 06:42:39 PM PDT 24 311515715 ps
T124 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4267043082 Jul 12 06:42:25 PM PDT 24 Jul 12 06:42:30 PM PDT 24 59916902 ps
T1077 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2694193563 Jul 12 06:42:22 PM PDT 24 Jul 12 06:42:29 PM PDT 24 74908476 ps
T1078 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2371662173 Jul 12 06:42:40 PM PDT 24 Jul 12 06:42:44 PM PDT 24 20217308 ps
T1079 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1947629955 Jul 12 06:42:53 PM PDT 24 Jul 12 06:42:57 PM PDT 24 15888052 ps
T1080 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2602995634 Jul 12 06:42:22 PM PDT 24 Jul 12 06:42:28 PM PDT 24 20258494 ps
T1081 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1244083134 Jul 12 06:42:12 PM PDT 24 Jul 12 06:42:18 PM PDT 24 172759895 ps
T1082 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3175314523 Jul 12 06:42:35 PM PDT 24 Jul 12 06:42:40 PM PDT 24 40471005 ps
T157 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1555796472 Jul 12 06:42:13 PM PDT 24 Jul 12 06:42:18 PM PDT 24 59525526 ps
T183 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2176162960 Jul 12 06:42:35 PM PDT 24 Jul 12 06:42:45 PM PDT 24 433217918 ps
T1083 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2362935939 Jul 12 06:42:38 PM PDT 24 Jul 12 06:42:42 PM PDT 24 74587099 ps
T1084 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2577861730 Jul 12 06:42:35 PM PDT 24 Jul 12 06:42:39 PM PDT 24 22052056 ps
T1085 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3456222076 Jul 12 06:42:37 PM PDT 24 Jul 12 06:42:42 PM PDT 24 30480638 ps
T179 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3147330008 Jul 12 06:42:23 PM PDT 24 Jul 12 06:42:48 PM PDT 24 7336484262 ps
T1086 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.51521108 Jul 12 06:42:22 PM PDT 24 Jul 12 06:42:29 PM PDT 24 43908899 ps
T1087 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1334124191 Jul 12 06:42:20 PM PDT 24 Jul 12 06:42:45 PM PDT 24 3371101635 ps
T1088 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1761537111 Jul 12 06:42:16 PM PDT 24 Jul 12 06:42:21 PM PDT 24 43505292 ps
T160 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3092705080 Jul 12 06:42:35 PM PDT 24 Jul 12 06:42:42 PM PDT 24 479343332 ps
T125 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3535664999 Jul 12 06:42:26 PM PDT 24 Jul 12 06:42:33 PM PDT 24 273054562 ps
T158 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3156498368 Jul 12 06:42:37 PM PDT 24 Jul 12 06:42:48 PM PDT 24 361075206 ps
T159 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3470044670 Jul 12 06:42:33 PM PDT 24 Jul 12 06:42:50 PM PDT 24 371928537 ps
T1089 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2859543830 Jul 12 06:42:39 PM PDT 24 Jul 12 06:42:44 PM PDT 24 15520083 ps
T1090 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2713094473 Jul 12 06:42:43 PM PDT 24 Jul 12 06:42:48 PM PDT 24 188089299 ps
T1091 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3284529161 Jul 12 06:43:00 PM PDT 24 Jul 12 06:43:04 PM PDT 24 18175970 ps
T1092 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3072665093 Jul 12 06:42:35 PM PDT 24 Jul 12 06:42:39 PM PDT 24 45641651 ps
T1093 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2884348084 Jul 12 06:42:18 PM PDT 24 Jul 12 06:42:24 PM PDT 24 83545564 ps
T1094 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2827960902 Jul 12 06:42:20 PM PDT 24 Jul 12 06:42:26 PM PDT 24 229727515 ps
T1095 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1988104192 Jul 12 06:42:15 PM PDT 24 Jul 12 06:42:23 PM PDT 24 56580552 ps
T1096 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3981088599 Jul 12 06:42:28 PM PDT 24 Jul 12 06:42:31 PM PDT 24 39027937 ps
T126 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.49376011 Jul 12 06:42:33 PM PDT 24 Jul 12 06:42:37 PM PDT 24 27813863 ps
T1097 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2071151928 Jul 12 06:42:19 PM PDT 24 Jul 12 06:42:25 PM PDT 24 64746370 ps
T1098 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3802938310 Jul 12 06:42:27 PM PDT 24 Jul 12 06:42:32 PM PDT 24 204617085 ps
T82 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1645151669 Jul 12 06:42:24 PM PDT 24 Jul 12 06:42:29 PM PDT 24 124709145 ps
T1099 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.20143084 Jul 12 06:42:34 PM PDT 24 Jul 12 06:42:40 PM PDT 24 931418035 ps
T1100 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2601250349 Jul 12 06:42:34 PM PDT 24 Jul 12 06:42:37 PM PDT 24 23844852 ps
T129 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.46318523 Jul 12 06:42:13 PM PDT 24 Jul 12 06:42:19 PM PDT 24 44806661 ps
T128 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1991895393 Jul 12 06:42:19 PM PDT 24 Jul 12 06:42:25 PM PDT 24 637384769 ps
T130 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.858239125 Jul 12 06:42:18 PM PDT 24 Jul 12 06:42:42 PM PDT 24 2085796016 ps
T1101 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3288027090 Jul 12 06:42:29 PM PDT 24 Jul 12 06:42:32 PM PDT 24 17896545 ps
T1102 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2497425634 Jul 12 06:42:47 PM PDT 24 Jul 12 06:42:51 PM PDT 24 208193246 ps
T1103 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.80071909 Jul 12 06:42:37 PM PDT 24 Jul 12 06:42:41 PM PDT 24 41943118 ps
T1104 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.839675933 Jul 12 06:42:46 PM PDT 24 Jul 12 06:42:48 PM PDT 24 50559126 ps
T173 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2293382523 Jul 12 06:42:36 PM PDT 24 Jul 12 06:42:42 PM PDT 24 63911252 ps
T1105 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3739668242 Jul 12 06:42:23 PM PDT 24 Jul 12 06:42:29 PM PDT 24 19726867 ps
T1106 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3597983439 Jul 12 06:42:26 PM PDT 24 Jul 12 06:42:30 PM PDT 24 16609731 ps
T1107 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2275839030 Jul 12 06:42:49 PM PDT 24 Jul 12 06:42:52 PM PDT 24 11431996 ps
T1108 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2771682429 Jul 12 06:42:28 PM PDT 24 Jul 12 06:42:38 PM PDT 24 214527444 ps
T1109 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3902822391 Jul 12 06:42:17 PM PDT 24 Jul 12 06:42:23 PM PDT 24 33596759 ps
T182 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.277718984 Jul 12 06:42:23 PM PDT 24 Jul 12 06:42:41 PM PDT 24 2149474517 ps
T177 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1042547549 Jul 12 06:42:28 PM PDT 24 Jul 12 06:42:42 PM PDT 24 300149544 ps
T1110 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3712478882 Jul 12 06:42:23 PM PDT 24 Jul 12 06:42:30 PM PDT 24 85709341 ps
T1111 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2840257353 Jul 12 06:42:37 PM PDT 24 Jul 12 06:42:42 PM PDT 24 14164729 ps
T1112 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2800493812 Jul 12 06:42:14 PM PDT 24 Jul 12 06:42:58 PM PDT 24 22492515930 ps
T1113 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2070622483 Jul 12 06:42:34 PM PDT 24 Jul 12 06:42:42 PM PDT 24 13129681 ps
T1114 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3930997218 Jul 12 06:42:21 PM PDT 24 Jul 12 06:42:27 PM PDT 24 601163176 ps
T1115 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.925747266 Jul 12 06:42:20 PM PDT 24 Jul 12 06:42:24 PM PDT 24 52984633 ps
T1116 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3795072342 Jul 12 06:42:21 PM PDT 24 Jul 12 06:42:30 PM PDT 24 224203651 ps
T1117 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4158147248 Jul 12 06:42:34 PM PDT 24 Jul 12 06:42:41 PM PDT 24 229898286 ps
T1118 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1212749821 Jul 12 06:42:21 PM PDT 24 Jul 12 06:42:34 PM PDT 24 357933227 ps
T1119 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1527271793 Jul 12 06:42:41 PM PDT 24 Jul 12 06:42:45 PM PDT 24 42962291 ps
T1120 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1971303764 Jul 12 06:42:35 PM PDT 24 Jul 12 06:42:39 PM PDT 24 34896541 ps
T176 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1268383168 Jul 12 06:42:33 PM PDT 24 Jul 12 06:42:40 PM PDT 24 784261036 ps
T1121 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2538028817 Jul 12 06:42:12 PM PDT 24 Jul 12 06:42:23 PM PDT 24 652290048 ps
T1122 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4034777487 Jul 12 06:42:26 PM PDT 24 Jul 12 06:42:33 PM PDT 24 695694376 ps
T1123 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1649581019 Jul 12 06:42:14 PM PDT 24 Jul 12 06:42:27 PM PDT 24 615723461 ps
T184 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2009557616 Jul 12 06:42:32 PM PDT 24 Jul 12 06:42:40 PM PDT 24 1893770181 ps
T1124 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.326135076 Jul 12 06:42:14 PM PDT 24 Jul 12 06:42:23 PM PDT 24 776772518 ps
T1125 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2019120927 Jul 12 06:42:40 PM PDT 24 Jul 12 06:42:44 PM PDT 24 65157931 ps
T1126 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2436751453 Jul 12 06:42:35 PM PDT 24 Jul 12 06:42:42 PM PDT 24 422120569 ps
T1127 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3975104108 Jul 12 06:42:36 PM PDT 24 Jul 12 06:42:40 PM PDT 24 21673196 ps
T1128 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.355418252 Jul 12 06:42:16 PM PDT 24 Jul 12 06:42:21 PM PDT 24 14200743 ps
T1129 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2853792368 Jul 12 06:42:23 PM PDT 24 Jul 12 06:42:31 PM PDT 24 231268878 ps
T83 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3672365500 Jul 12 06:42:13 PM PDT 24 Jul 12 06:42:18 PM PDT 24 172341634 ps
T1130 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1654213 Jul 12 06:42:10 PM PDT 24 Jul 12 06:42:14 PM PDT 24 11728703 ps
T1131 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3552065140 Jul 12 06:42:24 PM PDT 24 Jul 12 06:42:31 PM PDT 24 102679950 ps
T1132 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1800056670 Jul 12 06:42:18 PM PDT 24 Jul 12 06:42:24 PM PDT 24 60295511 ps
T1133 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2333101407 Jul 12 06:42:35 PM PDT 24 Jul 12 06:42:40 PM PDT 24 46425537 ps
T1134 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1770732137 Jul 12 06:42:19 PM PDT 24 Jul 12 06:42:27 PM PDT 24 228915551 ps
T1135 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.549156641 Jul 12 06:42:29 PM PDT 24 Jul 12 06:42:34 PM PDT 24 47207176 ps
T1136 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1740358778 Jul 12 06:42:18 PM PDT 24 Jul 12 06:42:23 PM PDT 24 38430722 ps
T1137 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3153183530 Jul 12 06:42:13 PM PDT 24 Jul 12 06:42:19 PM PDT 24 57372443 ps
T1138 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.380709083 Jul 12 06:42:15 PM PDT 24 Jul 12 06:42:22 PM PDT 24 67644293 ps
T1139 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2497810043 Jul 12 06:42:22 PM PDT 24 Jul 12 06:42:39 PM PDT 24 1216709508 ps
T1140 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3459198662 Jul 12 06:42:34 PM PDT 24 Jul 12 06:42:43 PM PDT 24 285875535 ps
T1141 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1556769417 Jul 12 06:42:22 PM PDT 24 Jul 12 06:42:28 PM PDT 24 27959104 ps
T1142 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1823149960 Jul 12 06:42:32 PM PDT 24 Jul 12 06:42:35 PM PDT 24 18500808 ps
T1143 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.267207829 Jul 12 06:42:35 PM PDT 24 Jul 12 06:42:38 PM PDT 24 43422635 ps
T1144 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2531569433 Jul 12 06:42:58 PM PDT 24 Jul 12 06:43:03 PM PDT 24 27879184 ps
T178 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3170791697 Jul 12 06:42:26 PM PDT 24 Jul 12 06:42:50 PM PDT 24 1707718904 ps
T1145 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.951020203 Jul 12 06:42:37 PM PDT 24 Jul 12 06:42:44 PM PDT 24 247573681 ps
T1146 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1509517291 Jul 12 06:42:16 PM PDT 24 Jul 12 06:42:39 PM PDT 24 1884975854 ps
T1147 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2583746890 Jul 12 06:42:39 PM PDT 24 Jul 12 06:42:47 PM PDT 24 235347837 ps
T1148 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.106989308 Jul 12 06:42:18 PM PDT 24 Jul 12 06:42:23 PM PDT 24 210608862 ps
T1149 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2072105769 Jul 12 06:42:32 PM PDT 24 Jul 12 06:42:36 PM PDT 24 424454840 ps

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2004264130
Short name T10
Test name
Test status
Simulation time 134358187536 ps
CPU time 299.73 seconds
Started Jul 12 06:23:45 PM PDT 24
Finished Jul 12 06:28:45 PM PDT 24
Peak memory 255780 kb
Host smart-455cfb0f-841e-45e6-98dc-b9aac0f3ad4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004264130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2004264130
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.162650951
Short name T12
Test name
Test status
Simulation time 266760960321 ps
CPU time 629.14 seconds
Started Jul 12 06:23:06 PM PDT 24
Finished Jul 12 06:33:36 PM PDT 24
Peak memory 266268 kb
Host smart-50f6df4b-e7a5-4655-8176-6d9834fbd8b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162650951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.162650951
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2314258455
Short name T20
Test name
Test status
Simulation time 489378857382 ps
CPU time 658.44 seconds
Started Jul 12 06:27:36 PM PDT 24
Finished Jul 12 06:38:36 PM PDT 24
Peak memory 273828 kb
Host smart-62d695e1-9d80-4110-84ad-91426c7c2851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314258455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2314258455
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3773293164
Short name T100
Test name
Test status
Simulation time 174001041 ps
CPU time 1.88 seconds
Started Jul 12 06:42:34 PM PDT 24
Finished Jul 12 06:42:38 PM PDT 24
Peak memory 215572 kb
Host smart-b292bdf5-4889-4f82-b8ed-870ab9fa3e18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773293164 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3773293164
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.907920088
Short name T17
Test name
Test status
Simulation time 27300486881 ps
CPU time 291.37 seconds
Started Jul 12 06:25:08 PM PDT 24
Finished Jul 12 06:30:00 PM PDT 24
Peak memory 266772 kb
Host smart-cb76c4b9-9e22-4407-bc59-9aa8c3c93f2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907920088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.907920088
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.234183617
Short name T19
Test name
Test status
Simulation time 20256236254 ps
CPU time 302.63 seconds
Started Jul 12 06:23:27 PM PDT 24
Finished Jul 12 06:28:31 PM PDT 24
Peak memory 283288 kb
Host smart-7fff14aa-4258-4633-bda5-98003427f665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234183617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.234183617
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2547156426
Short name T66
Test name
Test status
Simulation time 19716235 ps
CPU time 0.76 seconds
Started Jul 12 06:21:28 PM PDT 24
Finished Jul 12 06:21:30 PM PDT 24
Peak memory 217052 kb
Host smart-8b8939bc-44a7-4076-995b-4a20c2ca7d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547156426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2547156426
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.692235751
Short name T44
Test name
Test status
Simulation time 64844497967 ps
CPU time 161.08 seconds
Started Jul 12 06:23:12 PM PDT 24
Finished Jul 12 06:25:54 PM PDT 24
Peak memory 250260 kb
Host smart-733bc6e0-f10b-404c-ac9a-86ed06df5cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692235751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
692235751
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.4011333833
Short name T199
Test name
Test status
Simulation time 29040943501 ps
CPU time 173.12 seconds
Started Jul 12 06:23:48 PM PDT 24
Finished Jul 12 06:26:41 PM PDT 24
Peak memory 269876 kb
Host smart-78c78ccc-eecb-4f58-811b-599a27353f36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011333833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.4011333833
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2190163784
Short name T21
Test name
Test status
Simulation time 360397121 ps
CPU time 1.22 seconds
Started Jul 12 06:22:04 PM PDT 24
Finished Jul 12 06:22:06 PM PDT 24
Peak memory 236760 kb
Host smart-a858cc00-96fb-47a0-9654-dca64dc6d84e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190163784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2190163784
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1555142966
Short name T186
Test name
Test status
Simulation time 160131182804 ps
CPU time 447.26 seconds
Started Jul 12 06:24:35 PM PDT 24
Finished Jul 12 06:32:03 PM PDT 24
Peak memory 286684 kb
Host smart-57a71237-7425-44b1-87bf-62b475f4582c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555142966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1555142966
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3714240410
Short name T149
Test name
Test status
Simulation time 3378012297 ps
CPU time 13.45 seconds
Started Jul 12 06:25:15 PM PDT 24
Finished Jul 12 06:25:31 PM PDT 24
Peak memory 250264 kb
Host smart-d99b0561-4eb0-4b95-90cf-84fadae54fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714240410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3714240410
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3398224694
Short name T54
Test name
Test status
Simulation time 124865322614 ps
CPU time 486.12 seconds
Started Jul 12 06:23:56 PM PDT 24
Finished Jul 12 06:32:03 PM PDT 24
Peak memory 275028 kb
Host smart-9e35f9bc-ad91-476b-8483-7eb96500052a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398224694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3398224694
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.687826768
Short name T103
Test name
Test status
Simulation time 295829810 ps
CPU time 18.8 seconds
Started Jul 12 06:42:20 PM PDT 24
Finished Jul 12 06:42:43 PM PDT 24
Peak memory 215416 kb
Host smart-0cd1959e-7eb7-4fc3-a72a-cf3551f3c65c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687826768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.687826768
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3322030693
Short name T161
Test name
Test status
Simulation time 67374464711 ps
CPU time 127.83 seconds
Started Jul 12 06:25:53 PM PDT 24
Finished Jul 12 06:28:02 PM PDT 24
Peak memory 273108 kb
Host smart-9bac8f6a-63b3-4db7-8796-994d42453e17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322030693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3322030693
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1398537622
Short name T117
Test name
Test status
Simulation time 75984087 ps
CPU time 2.48 seconds
Started Jul 12 06:42:08 PM PDT 24
Finished Jul 12 06:42:12 PM PDT 24
Peak memory 215460 kb
Host smart-d06b1233-b575-4b57-8154-275e4f78dafd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398537622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
398537622
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3070727059
Short name T106
Test name
Test status
Simulation time 345799467 ps
CPU time 5.12 seconds
Started Jul 12 06:42:22 PM PDT 24
Finished Jul 12 06:42:31 PM PDT 24
Peak memory 215780 kb
Host smart-c833cf58-fd43-4e34-b994-8699d82ff12c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070727059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
070727059
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2721224393
Short name T234
Test name
Test status
Simulation time 291257476890 ps
CPU time 359.73 seconds
Started Jul 12 06:26:21 PM PDT 24
Finished Jul 12 06:32:23 PM PDT 24
Peak memory 267624 kb
Host smart-b28cc3fb-d5eb-4b4f-8801-a178a5284b04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721224393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2721224393
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3972249677
Short name T26
Test name
Test status
Simulation time 80776036143 ps
CPU time 259.63 seconds
Started Jul 12 06:23:56 PM PDT 24
Finished Jul 12 06:28:16 PM PDT 24
Peak memory 257284 kb
Host smart-a98b7403-a5ea-4adc-8f20-e45f089c4402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972249677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3972249677
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.682836809
Short name T39
Test name
Test status
Simulation time 15210842 ps
CPU time 1.01 seconds
Started Jul 12 06:23:51 PM PDT 24
Finished Jul 12 06:23:53 PM PDT 24
Peak memory 217576 kb
Host smart-1b6c38f7-5335-433e-97c5-a4c615dd737a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682836809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.682836809
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2130461281
Short name T278
Test name
Test status
Simulation time 74139358849 ps
CPU time 541.95 seconds
Started Jul 12 06:28:22 PM PDT 24
Finished Jul 12 06:37:24 PM PDT 24
Peak memory 266752 kb
Host smart-0d4d41a1-52b9-41f1-a97e-94c2098d612e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130461281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2130461281
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.903422706
Short name T32
Test name
Test status
Simulation time 2317933922 ps
CPU time 15.46 seconds
Started Jul 12 06:26:22 PM PDT 24
Finished Jul 12 06:26:40 PM PDT 24
Peak memory 217420 kb
Host smart-9b194d1e-13ab-4ea6-9531-3b1aa743a956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903422706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.903422706
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2654980682
Short name T285
Test name
Test status
Simulation time 174973454492 ps
CPU time 337.91 seconds
Started Jul 12 06:25:25 PM PDT 24
Finished Jul 12 06:31:04 PM PDT 24
Peak memory 258160 kb
Host smart-06ea18cd-dc3d-42f6-8a89-d78f49c02946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654980682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2654980682
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.952175987
Short name T170
Test name
Test status
Simulation time 9231148840 ps
CPU time 58.79 seconds
Started Jul 12 06:26:31 PM PDT 24
Finished Jul 12 06:27:32 PM PDT 24
Peak memory 255476 kb
Host smart-7a0af55d-c9c4-475b-9ca0-1668a4b2eced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952175987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.952175987
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1749862537
Short name T90
Test name
Test status
Simulation time 2853819682 ps
CPU time 9.11 seconds
Started Jul 12 06:26:21 PM PDT 24
Finished Jul 12 06:26:33 PM PDT 24
Peak memory 217440 kb
Host smart-55ccfa37-13f4-498d-b18e-8d21e5ef5622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749862537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1749862537
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.246179891
Short name T52
Test name
Test status
Simulation time 227235998905 ps
CPU time 575.92 seconds
Started Jul 12 06:24:56 PM PDT 24
Finished Jul 12 06:34:33 PM PDT 24
Peak memory 258244 kb
Host smart-5d6af994-7b54-458f-ae61-4a2fb972eb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246179891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.246179891
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3623836883
Short name T76
Test name
Test status
Simulation time 17196430 ps
CPU time 0.73 seconds
Started Jul 12 06:21:54 PM PDT 24
Finished Jul 12 06:21:55 PM PDT 24
Peak memory 206312 kb
Host smart-2265ce9f-8b46-40fe-afd9-acf0adafcf25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623836883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
623836883
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2687949019
Short name T257
Test name
Test status
Simulation time 20405704437 ps
CPU time 150.05 seconds
Started Jul 12 06:27:56 PM PDT 24
Finished Jul 12 06:30:27 PM PDT 24
Peak memory 251720 kb
Host smart-714bc41a-4943-48bb-a7c0-443eaffd04d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687949019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2687949019
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1473366494
Short name T291
Test name
Test status
Simulation time 38871428343 ps
CPU time 545.88 seconds
Started Jul 12 06:23:41 PM PDT 24
Finished Jul 12 06:32:48 PM PDT 24
Peak memory 299572 kb
Host smart-b96e10b8-cef0-4934-b490-e3db91956b9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473366494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1473366494
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.966571799
Short name T34
Test name
Test status
Simulation time 26710326734 ps
CPU time 262.6 seconds
Started Jul 12 06:22:36 PM PDT 24
Finished Jul 12 06:27:00 PM PDT 24
Peak memory 257508 kb
Host smart-ec2166cf-2532-449d-8079-5d98eed6a667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966571799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.966571799
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3170791697
Short name T178
Test name
Test status
Simulation time 1707718904 ps
CPU time 19.76 seconds
Started Jul 12 06:42:26 PM PDT 24
Finished Jul 12 06:42:50 PM PDT 24
Peak memory 215576 kb
Host smart-7e2383a3-da8c-49b9-8113-528e18d4534b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170791697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3170791697
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1223433997
Short name T58
Test name
Test status
Simulation time 10158820415 ps
CPU time 89.27 seconds
Started Jul 12 06:27:36 PM PDT 24
Finished Jul 12 06:29:06 PM PDT 24
Peak memory 234016 kb
Host smart-c396c8bb-a2a9-490d-b8da-25323b911ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223433997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1223433997
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2266709034
Short name T978
Test name
Test status
Simulation time 591909630471 ps
CPU time 1409.71 seconds
Started Jul 12 06:28:35 PM PDT 24
Finished Jul 12 06:52:06 PM PDT 24
Peak memory 307372 kb
Host smart-a83cb394-1668-4183-b1cd-b1db8de0df3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266709034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2266709034
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3067869711
Short name T280
Test name
Test status
Simulation time 510879255782 ps
CPU time 1015.66 seconds
Started Jul 12 06:28:44 PM PDT 24
Finished Jul 12 06:45:41 PM PDT 24
Peak memory 282504 kb
Host smart-b927c09b-9fb3-47d6-aca7-899c8ff77d5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067869711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3067869711
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.465635540
Short name T105
Test name
Test status
Simulation time 444802774 ps
CPU time 5.05 seconds
Started Jul 12 06:42:34 PM PDT 24
Finished Jul 12 06:42:42 PM PDT 24
Peak memory 215764 kb
Host smart-8fc85b0c-b38b-405d-bb1b-0c1cda21bf05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465635540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.465635540
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.322861881
Short name T46
Test name
Test status
Simulation time 43308512251 ps
CPU time 78.33 seconds
Started Jul 12 06:24:31 PM PDT 24
Finished Jul 12 06:25:50 PM PDT 24
Peak memory 272440 kb
Host smart-91bdaac3-3a5e-412f-8454-d0a5cf96e628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322861881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.322861881
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3696775015
Short name T191
Test name
Test status
Simulation time 7590983460 ps
CPU time 95.27 seconds
Started Jul 12 06:28:06 PM PDT 24
Finished Jul 12 06:29:43 PM PDT 24
Peak memory 266088 kb
Host smart-081ab07f-a6dc-4097-8cda-e02101ffd4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696775015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3696775015
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1047944518
Short name T41
Test name
Test status
Simulation time 17806517959 ps
CPU time 67.39 seconds
Started Jul 12 06:27:34 PM PDT 24
Finished Jul 12 06:28:42 PM PDT 24
Peak memory 250264 kb
Host smart-79a924b0-dea7-4577-83f2-a412a4022424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047944518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1047944518
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3962052735
Short name T45
Test name
Test status
Simulation time 4969035689 ps
CPU time 10.43 seconds
Started Jul 12 06:29:13 PM PDT 24
Finished Jul 12 06:29:24 PM PDT 24
Peak memory 225680 kb
Host smart-8f160a45-7cf0-4c84-8c10-6e77066d09e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962052735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3962052735
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3147330008
Short name T179
Test name
Test status
Simulation time 7336484262 ps
CPU time 20.43 seconds
Started Jul 12 06:42:23 PM PDT 24
Finished Jul 12 06:42:48 PM PDT 24
Peak memory 215560 kb
Host smart-3e2314ed-8182-4382-b083-fd78d6bf87f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147330008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3147330008
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.205508768
Short name T181
Test name
Test status
Simulation time 1382990367 ps
CPU time 17.87 seconds
Started Jul 12 06:42:36 PM PDT 24
Finished Jul 12 06:42:57 PM PDT 24
Peak memory 215476 kb
Host smart-249ba04f-9769-431d-81c3-39b3cc8cdf43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205508768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.205508768
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.4268505080
Short name T306
Test name
Test status
Simulation time 236857124 ps
CPU time 8.97 seconds
Started Jul 12 06:25:21 PM PDT 24
Finished Jul 12 06:25:31 PM PDT 24
Peak memory 255280 kb
Host smart-57addad0-9802-4f31-8859-8dfc954c3f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268505080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.4268505080
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.464861218
Short name T322
Test name
Test status
Simulation time 56550839552 ps
CPU time 182.26 seconds
Started Jul 12 06:22:04 PM PDT 24
Finished Jul 12 06:25:07 PM PDT 24
Peak memory 274948 kb
Host smart-9dbaff2c-b1f3-40b6-bcb4-a5215a1cb613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464861218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.464861218
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3973870383
Short name T293
Test name
Test status
Simulation time 18930312078 ps
CPU time 131.19 seconds
Started Jul 12 06:24:10 PM PDT 24
Finished Jul 12 06:26:21 PM PDT 24
Peak memory 266764 kb
Host smart-173720b6-d098-4229-85c2-7cda1263508d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973870383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3973870383
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.788097350
Short name T189
Test name
Test status
Simulation time 152075799936 ps
CPU time 184.78 seconds
Started Jul 12 06:24:23 PM PDT 24
Finished Jul 12 06:27:28 PM PDT 24
Peak memory 255572 kb
Host smart-c6903170-fee0-4f51-a5cb-fd726805a152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788097350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.788097350
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.27780038
Short name T427
Test name
Test status
Simulation time 31035112954 ps
CPU time 36.31 seconds
Started Jul 12 06:24:49 PM PDT 24
Finished Jul 12 06:25:26 PM PDT 24
Peak memory 225756 kb
Host smart-249e3c5b-5d55-4b38-958b-6137638bd9cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27780038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress
_all.27780038
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1492476116
Short name T31
Test name
Test status
Simulation time 81287284055 ps
CPU time 106.75 seconds
Started Jul 12 06:25:15 PM PDT 24
Finished Jul 12 06:27:04 PM PDT 24
Peak memory 255072 kb
Host smart-cfcaf9c8-a4d6-40f2-aac5-36ff7cf13c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492476116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1492476116
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1645151669
Short name T82
Test name
Test status
Simulation time 124709145 ps
CPU time 1.32 seconds
Started Jul 12 06:42:24 PM PDT 24
Finished Jul 12 06:42:29 PM PDT 24
Peak memory 216308 kb
Host smart-eb4320c3-021f-4200-90fe-1f1eaff1eca6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645151669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1645151669
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1266487245
Short name T80
Test name
Test status
Simulation time 40938772 ps
CPU time 1.06 seconds
Started Jul 12 06:42:16 PM PDT 24
Finished Jul 12 06:42:21 PM PDT 24
Peak memory 207092 kb
Host smart-65e771b8-0ec6-497b-be68-b421daf452c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266487245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1266487245
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1921579968
Short name T116
Test name
Test status
Simulation time 3559403627 ps
CPU time 10.81 seconds
Started Jul 12 06:24:07 PM PDT 24
Finished Jul 12 06:24:19 PM PDT 24
Peak memory 233844 kb
Host smart-9eceb62d-ccef-4518-acd3-299ed7568d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921579968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1921579968
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2538028817
Short name T1121
Test name
Test status
Simulation time 652290048 ps
CPU time 8.25 seconds
Started Jul 12 06:42:12 PM PDT 24
Finished Jul 12 06:42:23 PM PDT 24
Peak memory 207336 kb
Host smart-271b6d76-3225-40bb-bc23-99dc174d5afd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538028817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2538028817
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2497810043
Short name T1139
Test name
Test status
Simulation time 1216709508 ps
CPU time 12.5 seconds
Started Jul 12 06:42:22 PM PDT 24
Finished Jul 12 06:42:39 PM PDT 24
Peak memory 207068 kb
Host smart-d4fd78e5-8fc1-444a-a045-b3fa2806b653
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497810043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2497810043
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1555796472
Short name T157
Test name
Test status
Simulation time 59525526 ps
CPU time 1.77 seconds
Started Jul 12 06:42:13 PM PDT 24
Finished Jul 12 06:42:18 PM PDT 24
Peak memory 215548 kb
Host smart-fe61626b-3f2e-4cb0-9be2-b6695da39402
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555796472 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1555796472
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3535664999
Short name T125
Test name
Test status
Simulation time 273054562 ps
CPU time 3.06 seconds
Started Jul 12 06:42:26 PM PDT 24
Finished Jul 12 06:42:33 PM PDT 24
Peak memory 215276 kb
Host smart-11d37eda-84ab-4773-9c86-88d792fb3a3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535664999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
535664999
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2248577579
Short name T1042
Test name
Test status
Simulation time 73286846 ps
CPU time 0.7 seconds
Started Jul 12 06:42:09 PM PDT 24
Finished Jul 12 06:42:12 PM PDT 24
Peak memory 204332 kb
Host smart-d612d463-467c-403a-b2e2-b7dc3be6acd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248577579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
248577579
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3153183530
Short name T1137
Test name
Test status
Simulation time 57372443 ps
CPU time 1.3 seconds
Started Jul 12 06:42:13 PM PDT 24
Finished Jul 12 06:42:19 PM PDT 24
Peak memory 215564 kb
Host smart-78394bf5-d0bf-4686-99e1-542de03a1d8a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153183530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3153183530
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2920247766
Short name T1066
Test name
Test status
Simulation time 10430077 ps
CPU time 0.67 seconds
Started Jul 12 06:42:23 PM PDT 24
Finished Jul 12 06:42:28 PM PDT 24
Peak memory 203872 kb
Host smart-1dc4e595-03f4-4124-b866-e16db6817119
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920247766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2920247766
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.326135076
Short name T1124
Test name
Test status
Simulation time 776772518 ps
CPU time 4.43 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:42:23 PM PDT 24
Peak memory 216660 kb
Host smart-f852756c-2c54-4d94-a8ef-5fbaa8395209
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326135076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.326135076
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2858360770
Short name T110
Test name
Test status
Simulation time 467513818 ps
CPU time 3 seconds
Started Jul 12 06:42:22 PM PDT 24
Finished Jul 12 06:42:30 PM PDT 24
Peak memory 216556 kb
Host smart-76074fc9-db97-4df3-b882-c06822b17474
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858360770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
858360770
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1649581019
Short name T1123
Test name
Test status
Simulation time 615723461 ps
CPU time 8.71 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:42:27 PM PDT 24
Peak memory 207332 kb
Host smart-1e65ace9-dd41-473c-a515-e20ab76b0c0d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649581019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1649581019
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.867789493
Short name T1035
Test name
Test status
Simulation time 4114850073 ps
CPU time 35.81 seconds
Started Jul 12 06:42:38 PM PDT 24
Finished Jul 12 06:43:18 PM PDT 24
Peak memory 207128 kb
Host smart-1209bcac-6833-44b4-b53b-7d3ff35cd4f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867789493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.867789493
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3672365500
Short name T83
Test name
Test status
Simulation time 172341634 ps
CPU time 1.35 seconds
Started Jul 12 06:42:13 PM PDT 24
Finished Jul 12 06:42:18 PM PDT 24
Peak memory 207276 kb
Host smart-b46cce03-1eec-4aef-903f-4a75a6ecbe2b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672365500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3672365500
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1244083134
Short name T1081
Test name
Test status
Simulation time 172759895 ps
CPU time 2.33 seconds
Started Jul 12 06:42:12 PM PDT 24
Finished Jul 12 06:42:18 PM PDT 24
Peak memory 216636 kb
Host smart-163945f7-0d6e-4056-b8fe-4e2a488ea606
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244083134 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1244083134
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3739668242
Short name T1105
Test name
Test status
Simulation time 19726867 ps
CPU time 0.73 seconds
Started Jul 12 06:42:23 PM PDT 24
Finished Jul 12 06:42:29 PM PDT 24
Peak memory 203828 kb
Host smart-84c5c2bc-1507-4142-bb59-f78936705945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739668242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
739668242
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.46318523
Short name T129
Test name
Test status
Simulation time 44806661 ps
CPU time 1.94 seconds
Started Jul 12 06:42:13 PM PDT 24
Finished Jul 12 06:42:19 PM PDT 24
Peak memory 215536 kb
Host smart-6f55e462-4c31-4cdd-b6da-dcc283a027de
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46318523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_d
evice_mem_partial_access.46318523
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1654213
Short name T1130
Test name
Test status
Simulation time 11728703 ps
CPU time 0.65 seconds
Started Jul 12 06:42:10 PM PDT 24
Finished Jul 12 06:42:14 PM PDT 24
Peak memory 203908 kb
Host smart-0a0c8e93-ed25-4581-8930-936ee230a3f3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_w
alk.1654213
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2701588647
Short name T143
Test name
Test status
Simulation time 29124558 ps
CPU time 1.79 seconds
Started Jul 12 06:42:28 PM PDT 24
Finished Jul 12 06:42:33 PM PDT 24
Peak memory 215312 kb
Host smart-10f7e1b1-cb59-4f2c-b6c4-2ed493bd4c97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701588647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2701588647
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1571410618
Short name T108
Test name
Test status
Simulation time 148018503 ps
CPU time 3.79 seconds
Started Jul 12 06:42:13 PM PDT 24
Finished Jul 12 06:42:21 PM PDT 24
Peak memory 216072 kb
Host smart-8464095b-1705-4369-9dc7-64cdc3526fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571410618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
571410618
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2382997100
Short name T1063
Test name
Test status
Simulation time 558650935 ps
CPU time 6.85 seconds
Started Jul 12 06:42:24 PM PDT 24
Finished Jul 12 06:42:35 PM PDT 24
Peak memory 215988 kb
Host smart-d836fe2a-fa8f-476c-94f8-48518e1002f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382997100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2382997100
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1799691431
Short name T114
Test name
Test status
Simulation time 246641858 ps
CPU time 3.92 seconds
Started Jul 12 06:42:26 PM PDT 24
Finished Jul 12 06:42:33 PM PDT 24
Peak memory 217148 kb
Host smart-1f38a330-16b2-4c5f-bd3c-c4136f21a1da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799691431 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1799691431
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2071151928
Short name T1097
Test name
Test status
Simulation time 64746370 ps
CPU time 1.98 seconds
Started Jul 12 06:42:19 PM PDT 24
Finished Jul 12 06:42:25 PM PDT 24
Peak memory 215472 kb
Host smart-68418d52-ba13-452f-9347-f60d8fee23fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071151928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2071151928
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3320773845
Short name T1044
Test name
Test status
Simulation time 15998336 ps
CPU time 0.77 seconds
Started Jul 12 06:42:23 PM PDT 24
Finished Jul 12 06:42:28 PM PDT 24
Peak memory 204316 kb
Host smart-0b710c26-a0d7-4a44-baaf-113aa66c7244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320773845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3320773845
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1556769417
Short name T1141
Test name
Test status
Simulation time 27959104 ps
CPU time 1.85 seconds
Started Jul 12 06:42:22 PM PDT 24
Finished Jul 12 06:42:28 PM PDT 24
Peak memory 207292 kb
Host smart-f59cdd2c-8903-4111-ae91-17c7a3d04468
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556769417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1556769417
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3795072342
Short name T1116
Test name
Test status
Simulation time 224203651 ps
CPU time 4.54 seconds
Started Jul 12 06:42:21 PM PDT 24
Finished Jul 12 06:42:30 PM PDT 24
Peak memory 216748 kb
Host smart-353dc99d-d4dd-4901-8d1a-220832d7e22d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795072342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3795072342
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1529899886
Short name T1076
Test name
Test status
Simulation time 1301033223 ps
CPU time 7.73 seconds
Started Jul 12 06:42:22 PM PDT 24
Finished Jul 12 06:42:34 PM PDT 24
Peak memory 215436 kb
Host smart-1aecfbe0-e1e9-4647-86cf-31d4c9630fac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529899886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1529899886
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.93674892
Short name T1059
Test name
Test status
Simulation time 189676078 ps
CPU time 1.73 seconds
Started Jul 12 06:42:35 PM PDT 24
Finished Jul 12 06:42:40 PM PDT 24
Peak memory 215476 kb
Host smart-912d5b03-6e9b-4489-87a8-8714812d275e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93674892 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.93674892
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1579038510
Short name T118
Test name
Test status
Simulation time 450380349 ps
CPU time 2.81 seconds
Started Jul 12 06:42:42 PM PDT 24
Finished Jul 12 06:42:48 PM PDT 24
Peak memory 215564 kb
Host smart-bc297651-1022-4e9d-aee2-bbc8678040d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579038510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1579038510
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2070622483
Short name T1113
Test name
Test status
Simulation time 13129681 ps
CPU time 0.71 seconds
Started Jul 12 06:42:34 PM PDT 24
Finished Jul 12 06:42:42 PM PDT 24
Peak memory 203980 kb
Host smart-325981db-9a68-4c32-b096-2ec9a05b044c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070622483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2070622483
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2551127848
Short name T1073
Test name
Test status
Simulation time 27153992 ps
CPU time 1.64 seconds
Started Jul 12 06:42:32 PM PDT 24
Finished Jul 12 06:42:35 PM PDT 24
Peak memory 207236 kb
Host smart-cd53cab7-5296-49ae-9eae-897f2b07a944
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551127848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2551127848
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1012966013
Short name T98
Test name
Test status
Simulation time 1188386753 ps
CPU time 6.24 seconds
Started Jul 12 06:42:33 PM PDT 24
Finished Jul 12 06:42:41 PM PDT 24
Peak memory 216008 kb
Host smart-baba3e7e-6d89-4297-8778-e53646780969
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012966013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1012966013
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.587832477
Short name T154
Test name
Test status
Simulation time 329411073 ps
CPU time 7.47 seconds
Started Jul 12 06:42:47 PM PDT 24
Finished Jul 12 06:42:57 PM PDT 24
Peak memory 215508 kb
Host smart-c1d42b2b-7cad-4611-91d6-2cc6299b2967
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587832477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.587832477
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3552065140
Short name T1131
Test name
Test status
Simulation time 102679950 ps
CPU time 2.73 seconds
Started Jul 12 06:42:24 PM PDT 24
Finished Jul 12 06:42:31 PM PDT 24
Peak memory 216688 kb
Host smart-8aeb7a1d-fc47-46f5-95e4-50cab1901ad3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552065140 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3552065140
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1913253498
Short name T145
Test name
Test status
Simulation time 77633476 ps
CPU time 1.44 seconds
Started Jul 12 06:42:23 PM PDT 24
Finished Jul 12 06:42:29 PM PDT 24
Peak memory 207348 kb
Host smart-db7d34a7-bbd9-4f6b-9ae2-6d0ff4b93d14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913253498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1913253498
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1627271918
Short name T1043
Test name
Test status
Simulation time 12766390 ps
CPU time 0.78 seconds
Started Jul 12 06:42:38 PM PDT 24
Finished Jul 12 06:42:43 PM PDT 24
Peak memory 204332 kb
Host smart-b81c3d34-eb4b-4a46-8979-c6992641172b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627271918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1627271918
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.549156641
Short name T1135
Test name
Test status
Simulation time 47207176 ps
CPU time 3.06 seconds
Started Jul 12 06:42:29 PM PDT 24
Finished Jul 12 06:42:34 PM PDT 24
Peak memory 215528 kb
Host smart-4f9dfc0b-a0a7-46a3-be33-55da295ef1df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549156641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.549156641
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.20143084
Short name T1099
Test name
Test status
Simulation time 931418035 ps
CPU time 3.46 seconds
Started Jul 12 06:42:34 PM PDT 24
Finished Jul 12 06:42:40 PM PDT 24
Peak memory 215656 kb
Host smart-c63cf047-0537-4c4b-b026-bb4457b88033
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20143084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.20143084
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4158147248
Short name T1117
Test name
Test status
Simulation time 229898286 ps
CPU time 4 seconds
Started Jul 12 06:42:34 PM PDT 24
Finished Jul 12 06:42:41 PM PDT 24
Peak memory 217396 kb
Host smart-feb1b9cf-5219-4d79-bd73-b7f76327fc99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158147248 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.4158147248
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2025032279
Short name T123
Test name
Test status
Simulation time 129845677 ps
CPU time 1.22 seconds
Started Jul 12 06:42:30 PM PDT 24
Finished Jul 12 06:42:33 PM PDT 24
Peak memory 215488 kb
Host smart-363da6e4-361f-44a2-b2b1-bebd847f523a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025032279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2025032279
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1458661091
Short name T1054
Test name
Test status
Simulation time 38631835 ps
CPU time 0.72 seconds
Started Jul 12 06:42:31 PM PDT 24
Finished Jul 12 06:42:34 PM PDT 24
Peak memory 203964 kb
Host smart-ba8ce849-94d9-43d4-85f1-ff4d4efa4d14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458661091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1458661091
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4034777487
Short name T1122
Test name
Test status
Simulation time 695694376 ps
CPU time 3.15 seconds
Started Jul 12 06:42:26 PM PDT 24
Finished Jul 12 06:42:33 PM PDT 24
Peak memory 215536 kb
Host smart-58d1077a-789f-4f11-9f72-caa6a11a8be2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034777487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.4034777487
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3080423633
Short name T109
Test name
Test status
Simulation time 119187088 ps
CPU time 3.66 seconds
Started Jul 12 06:42:23 PM PDT 24
Finished Jul 12 06:42:31 PM PDT 24
Peak memory 215756 kb
Host smart-55223360-3c3d-47c5-b6ee-6f042ca8f5ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080423633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3080423633
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2771682429
Short name T1108
Test name
Test status
Simulation time 214527444 ps
CPU time 6.97 seconds
Started Jul 12 06:42:28 PM PDT 24
Finished Jul 12 06:42:38 PM PDT 24
Peak memory 215484 kb
Host smart-d81f19b8-3527-4475-8970-282bda913576
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771682429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2771682429
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1406275392
Short name T1061
Test name
Test status
Simulation time 135901747 ps
CPU time 2.74 seconds
Started Jul 12 06:42:35 PM PDT 24
Finished Jul 12 06:42:41 PM PDT 24
Peak memory 216636 kb
Host smart-9b5b8b51-154d-4c8d-9ecf-b70776ce1365
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406275392 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1406275392
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2735953163
Short name T122
Test name
Test status
Simulation time 98282589 ps
CPU time 2.67 seconds
Started Jul 12 06:42:33 PM PDT 24
Finished Jul 12 06:42:38 PM PDT 24
Peak memory 215504 kb
Host smart-4493516d-a343-412f-a98e-b4370bd284b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735953163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2735953163
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1671693632
Short name T1064
Test name
Test status
Simulation time 19649140 ps
CPU time 0.7 seconds
Started Jul 12 06:42:26 PM PDT 24
Finished Jul 12 06:42:30 PM PDT 24
Peak memory 203956 kb
Host smart-fffe9d55-7b70-48b8-9dfd-0266d795ffa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671693632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1671693632
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.951020203
Short name T1145
Test name
Test status
Simulation time 247573681 ps
CPU time 2.88 seconds
Started Jul 12 06:42:37 PM PDT 24
Finished Jul 12 06:42:44 PM PDT 24
Peak memory 215540 kb
Host smart-d761370e-cdc0-4a99-bf1f-c4fc1ad73b7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951020203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.951020203
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1082206521
Short name T107
Test name
Test status
Simulation time 218035246 ps
CPU time 4.33 seconds
Started Jul 12 06:42:29 PM PDT 24
Finished Jul 12 06:42:35 PM PDT 24
Peak memory 215824 kb
Host smart-f5d3f094-380b-4b1c-85e8-27dfb900a7d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082206521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1082206521
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1126244641
Short name T180
Test name
Test status
Simulation time 311515715 ps
CPU time 7.34 seconds
Started Jul 12 06:42:30 PM PDT 24
Finished Jul 12 06:42:39 PM PDT 24
Peak memory 216256 kb
Host smart-790d8e50-f793-4599-bf5b-99232fe8d39a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126244641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1126244641
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2293382523
Short name T173
Test name
Test status
Simulation time 63911252 ps
CPU time 1.92 seconds
Started Jul 12 06:42:36 PM PDT 24
Finished Jul 12 06:42:42 PM PDT 24
Peak memory 215568 kb
Host smart-02eb56ed-062c-454d-824f-ae53d1256ca9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293382523 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2293382523
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1617070426
Short name T1075
Test name
Test status
Simulation time 58797317 ps
CPU time 1.3 seconds
Started Jul 12 06:42:54 PM PDT 24
Finished Jul 12 06:42:58 PM PDT 24
Peak memory 215456 kb
Host smart-5eeae2cd-a373-419f-bea9-5b57ab6a84a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617070426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1617070426
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3361615115
Short name T1040
Test name
Test status
Simulation time 11582572 ps
CPU time 0.75 seconds
Started Jul 12 06:42:36 PM PDT 24
Finished Jul 12 06:42:40 PM PDT 24
Peak memory 204344 kb
Host smart-3700c33d-4b64-4231-8e22-f2cee74314b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361615115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3361615115
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.759135573
Short name T146
Test name
Test status
Simulation time 28871122 ps
CPU time 1.73 seconds
Started Jul 12 06:42:37 PM PDT 24
Finished Jul 12 06:42:42 PM PDT 24
Peak memory 215556 kb
Host smart-59616e5b-8a9d-46c2-b6b0-a9c1e588a165
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759135573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.759135573
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2583746890
Short name T1147
Test name
Test status
Simulation time 235347837 ps
CPU time 3.69 seconds
Started Jul 12 06:42:39 PM PDT 24
Finished Jul 12 06:42:47 PM PDT 24
Peak memory 216764 kb
Host smart-bb63e6b1-f85a-4256-a633-d2d9d8b624e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583746890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2583746890
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.659956326
Short name T1057
Test name
Test status
Simulation time 72613396 ps
CPU time 2.51 seconds
Started Jul 12 06:42:35 PM PDT 24
Finished Jul 12 06:42:41 PM PDT 24
Peak memory 217536 kb
Host smart-f7979b40-9144-425f-a7c4-f67c4a7c0afd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659956326 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.659956326
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2072105769
Short name T1149
Test name
Test status
Simulation time 424454840 ps
CPU time 2.5 seconds
Started Jul 12 06:42:32 PM PDT 24
Finished Jul 12 06:42:36 PM PDT 24
Peak memory 215496 kb
Host smart-17b4820d-a7f0-4f8d-b275-33879013c399
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072105769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2072105769
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.370185140
Short name T1033
Test name
Test status
Simulation time 20029660 ps
CPU time 0.72 seconds
Started Jul 12 06:42:35 PM PDT 24
Finished Jul 12 06:42:39 PM PDT 24
Peak memory 203964 kb
Host smart-e5cd774c-098d-451a-9f78-373d684916b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370185140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.370185140
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3366975767
Short name T1069
Test name
Test status
Simulation time 62919976 ps
CPU time 3.84 seconds
Started Jul 12 06:42:38 PM PDT 24
Finished Jul 12 06:42:46 PM PDT 24
Peak memory 215528 kb
Host smart-04fefaec-9b40-4b78-919e-f375101a61ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366975767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3366975767
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3092705080
Short name T160
Test name
Test status
Simulation time 479343332 ps
CPU time 3.14 seconds
Started Jul 12 06:42:35 PM PDT 24
Finished Jul 12 06:42:42 PM PDT 24
Peak memory 215724 kb
Host smart-2f8f2f17-e349-48ae-8949-39a8603d840f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092705080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3092705080
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2176162960
Short name T183
Test name
Test status
Simulation time 433217918 ps
CPU time 6.47 seconds
Started Jul 12 06:42:35 PM PDT 24
Finished Jul 12 06:42:45 PM PDT 24
Peak memory 215512 kb
Host smart-08829005-654d-4aac-a82a-478fc0c4dfdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176162960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2176162960
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4119315396
Short name T1062
Test name
Test status
Simulation time 488605143 ps
CPU time 2.71 seconds
Started Jul 12 06:42:36 PM PDT 24
Finished Jul 12 06:42:42 PM PDT 24
Peak memory 216548 kb
Host smart-d0c73d42-f8bb-4bbb-9b0a-ec65c5f181a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119315396 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.4119315396
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.49376011
Short name T126
Test name
Test status
Simulation time 27813863 ps
CPU time 1.93 seconds
Started Jul 12 06:42:33 PM PDT 24
Finished Jul 12 06:42:37 PM PDT 24
Peak memory 207352 kb
Host smart-f991e2a6-d5db-4d0c-b4fd-5fb61563c4fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49376011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.49376011
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3175314523
Short name T1082
Test name
Test status
Simulation time 40471005 ps
CPU time 0.74 seconds
Started Jul 12 06:42:35 PM PDT 24
Finished Jul 12 06:42:40 PM PDT 24
Peak memory 204296 kb
Host smart-fa831815-8b63-412d-8b69-fe4c4368e709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175314523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3175314523
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2713094473
Short name T1090
Test name
Test status
Simulation time 188089299 ps
CPU time 2.74 seconds
Started Jul 12 06:42:43 PM PDT 24
Finished Jul 12 06:42:48 PM PDT 24
Peak memory 215560 kb
Host smart-d2549310-3a11-4c8e-a870-0cdcaca21a02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713094473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2713094473
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2601250349
Short name T1100
Test name
Test status
Simulation time 23844852 ps
CPU time 1.72 seconds
Started Jul 12 06:42:34 PM PDT 24
Finished Jul 12 06:42:37 PM PDT 24
Peak memory 215764 kb
Host smart-5bf104c4-9fcc-4ad9-8880-3d103cde8ad2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601250349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2601250349
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3156498368
Short name T158
Test name
Test status
Simulation time 361075206 ps
CPU time 8.11 seconds
Started Jul 12 06:42:37 PM PDT 24
Finished Jul 12 06:42:48 PM PDT 24
Peak memory 215968 kb
Host smart-1f63a818-6d80-4bbf-93a1-8eab78c6a1b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156498368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3156498368
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2381402875
Short name T112
Test name
Test status
Simulation time 379090139 ps
CPU time 2.59 seconds
Started Jul 12 06:43:29 PM PDT 24
Finished Jul 12 06:43:34 PM PDT 24
Peak memory 216632 kb
Host smart-47af69b7-8888-4dd6-9251-b86a56832d6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381402875 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2381402875
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3990751628
Short name T1072
Test name
Test status
Simulation time 245084117 ps
CPU time 2.08 seconds
Started Jul 12 06:42:38 PM PDT 24
Finished Jul 12 06:42:45 PM PDT 24
Peak memory 215424 kb
Host smart-646ea6e5-aeee-4b11-b66d-14b8a5fd527e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990751628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3990751628
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1819128366
Short name T1067
Test name
Test status
Simulation time 19608079 ps
CPU time 0.66 seconds
Started Jul 12 06:42:38 PM PDT 24
Finished Jul 12 06:42:43 PM PDT 24
Peak memory 203988 kb
Host smart-6c73f29f-d44f-4a38-8e7d-42682d7b0a0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819128366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1819128366
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3620243333
Short name T156
Test name
Test status
Simulation time 1589321401 ps
CPU time 4.49 seconds
Started Jul 12 06:42:41 PM PDT 24
Finished Jul 12 06:42:49 PM PDT 24
Peak memory 215440 kb
Host smart-09727eb8-65ad-4b1b-bbc7-ddb8abd2c5e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620243333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3620243333
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.315504565
Short name T1052
Test name
Test status
Simulation time 1090900033 ps
CPU time 7.41 seconds
Started Jul 12 06:42:43 PM PDT 24
Finished Jul 12 06:42:52 PM PDT 24
Peak memory 222436 kb
Host smart-e1ad0b5a-9918-4007-af40-0398a335b88c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315504565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.315504565
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2531569433
Short name T1144
Test name
Test status
Simulation time 27879184 ps
CPU time 1.79 seconds
Started Jul 12 06:42:58 PM PDT 24
Finished Jul 12 06:43:03 PM PDT 24
Peak memory 215460 kb
Host smart-b8150e3f-cdff-4b17-a35b-c9fe68b6abd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531569433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2531569433
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2019120927
Short name T1125
Test name
Test status
Simulation time 65157931 ps
CPU time 0.72 seconds
Started Jul 12 06:42:40 PM PDT 24
Finished Jul 12 06:42:44 PM PDT 24
Peak memory 204220 kb
Host smart-aedf1f37-d791-4398-810c-c8f853909491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019120927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2019120927
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2436751453
Short name T1126
Test name
Test status
Simulation time 422120569 ps
CPU time 4.03 seconds
Started Jul 12 06:42:35 PM PDT 24
Finished Jul 12 06:42:42 PM PDT 24
Peak memory 215460 kb
Host smart-e6ecd10f-5544-4f52-a7c6-b23f2cc62eb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436751453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2436751453
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1268383168
Short name T176
Test name
Test status
Simulation time 784261036 ps
CPU time 4.33 seconds
Started Jul 12 06:42:33 PM PDT 24
Finished Jul 12 06:42:40 PM PDT 24
Peak memory 215712 kb
Host smart-01a23d2f-eb90-4339-acdd-87dd518aeda5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268383168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1268383168
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3459198662
Short name T1140
Test name
Test status
Simulation time 285875535 ps
CPU time 7.25 seconds
Started Jul 12 06:42:34 PM PDT 24
Finished Jul 12 06:42:43 PM PDT 24
Peak memory 215496 kb
Host smart-0b7d1af9-fd19-4fe8-b5a9-2ad49ab24172
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459198662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3459198662
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3470044670
Short name T159
Test name
Test status
Simulation time 371928537 ps
CPU time 8.14 seconds
Started Jul 12 06:42:33 PM PDT 24
Finished Jul 12 06:42:50 PM PDT 24
Peak memory 215452 kb
Host smart-886671c7-0fc1-4478-bbcb-75a1232cc9d8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470044670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3470044670
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3027029999
Short name T121
Test name
Test status
Simulation time 3258165215 ps
CPU time 33.71 seconds
Started Jul 12 06:42:18 PM PDT 24
Finished Jul 12 06:42:55 PM PDT 24
Peak memory 215468 kb
Host smart-ba44445a-fc5a-4e31-aa0a-313e68df892b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027029999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3027029999
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.51521108
Short name T1086
Test name
Test status
Simulation time 43908899 ps
CPU time 3.03 seconds
Started Jul 12 06:42:22 PM PDT 24
Finished Jul 12 06:42:29 PM PDT 24
Peak memory 218184 kb
Host smart-0273b3a5-980a-40ab-a706-fc7b655c4ff7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51521108 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.51521108
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.380709083
Short name T1138
Test name
Test status
Simulation time 67644293 ps
CPU time 2.04 seconds
Started Jul 12 06:42:15 PM PDT 24
Finished Jul 12 06:42:22 PM PDT 24
Peak memory 215556 kb
Host smart-2979a9af-41f6-4ca8-96e5-c1ce48471945
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380709083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.380709083
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1760282874
Short name T1046
Test name
Test status
Simulation time 57585583 ps
CPU time 0.76 seconds
Started Jul 12 06:42:13 PM PDT 24
Finished Jul 12 06:42:17 PM PDT 24
Peak memory 204000 kb
Host smart-69433a30-72c1-41e4-bd7b-9c114cc63404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760282874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
760282874
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4138948809
Short name T120
Test name
Test status
Simulation time 158583022 ps
CPU time 1.31 seconds
Started Jul 12 06:42:13 PM PDT 24
Finished Jul 12 06:42:18 PM PDT 24
Peak memory 215496 kb
Host smart-2e51d7d2-ae5a-4c3c-90fd-7182d6c4651e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138948809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.4138948809
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2980917682
Short name T1039
Test name
Test status
Simulation time 29117049 ps
CPU time 0.66 seconds
Started Jul 12 06:42:23 PM PDT 24
Finished Jul 12 06:42:28 PM PDT 24
Peak memory 204192 kb
Host smart-9e7be583-1c3f-4eca-a966-9b74426a8aa1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980917682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2980917682
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1988104192
Short name T1095
Test name
Test status
Simulation time 56580552 ps
CPU time 3.44 seconds
Started Jul 12 06:42:15 PM PDT 24
Finished Jul 12 06:42:23 PM PDT 24
Peak memory 215412 kb
Host smart-f5b2f773-c45e-4e58-8632-ac9bf9569722
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988104192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1988104192
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.248742906
Short name T104
Test name
Test status
Simulation time 143692966 ps
CPU time 1.61 seconds
Started Jul 12 06:42:19 PM PDT 24
Finished Jul 12 06:42:24 PM PDT 24
Peak memory 215876 kb
Host smart-ce2308ca-e056-49b9-acb7-26b624fc4026
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248742906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.248742906
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1334124191
Short name T1087
Test name
Test status
Simulation time 3371101635 ps
CPU time 20.54 seconds
Started Jul 12 06:42:20 PM PDT 24
Finished Jul 12 06:42:45 PM PDT 24
Peak memory 216952 kb
Host smart-7dcfe816-6794-429b-be95-1ebb7e97534e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334124191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1334124191
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.267207829
Short name T1143
Test name
Test status
Simulation time 43422635 ps
CPU time 0.74 seconds
Started Jul 12 06:42:35 PM PDT 24
Finished Jul 12 06:42:38 PM PDT 24
Peak memory 204020 kb
Host smart-e0726871-7833-41ff-ad30-3753301260ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267207829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.267207829
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3072665093
Short name T1092
Test name
Test status
Simulation time 45641651 ps
CPU time 0.69 seconds
Started Jul 12 06:42:35 PM PDT 24
Finished Jul 12 06:42:39 PM PDT 24
Peak memory 203968 kb
Host smart-595340e8-e8d6-41ca-a8d9-b29be2a76d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072665093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3072665093
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3284529161
Short name T1091
Test name
Test status
Simulation time 18175970 ps
CPU time 0.77 seconds
Started Jul 12 06:43:00 PM PDT 24
Finished Jul 12 06:43:04 PM PDT 24
Peak memory 204040 kb
Host smart-2905b695-2370-4d35-bb37-5556f6fbe92b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284529161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3284529161
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1400401898
Short name T1038
Test name
Test status
Simulation time 12426753 ps
CPU time 0.73 seconds
Started Jul 12 06:42:49 PM PDT 24
Finished Jul 12 06:42:51 PM PDT 24
Peak memory 204280 kb
Host smart-0d797e1c-1705-45a1-a519-7df6c03d9830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400401898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1400401898
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2333101407
Short name T1133
Test name
Test status
Simulation time 46425537 ps
CPU time 0.79 seconds
Started Jul 12 06:42:35 PM PDT 24
Finished Jul 12 06:42:40 PM PDT 24
Peak memory 204032 kb
Host smart-2288035f-dc52-458d-8abb-4276aeadd2f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333101407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2333101407
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3084639835
Short name T1051
Test name
Test status
Simulation time 17935917 ps
CPU time 0.73 seconds
Started Jul 12 06:42:45 PM PDT 24
Finished Jul 12 06:42:47 PM PDT 24
Peak memory 204316 kb
Host smart-2bdd6ef5-443b-43f5-8366-43e600cc5c86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084639835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3084639835
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1527271793
Short name T1119
Test name
Test status
Simulation time 42962291 ps
CPU time 0.74 seconds
Started Jul 12 06:42:41 PM PDT 24
Finished Jul 12 06:42:45 PM PDT 24
Peak memory 203964 kb
Host smart-f893800f-a4ab-4edb-b184-e2bb9fa4d812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527271793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1527271793
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2501933252
Short name T1074
Test name
Test status
Simulation time 12747838 ps
CPU time 0.71 seconds
Started Jul 12 06:42:36 PM PDT 24
Finished Jul 12 06:42:40 PM PDT 24
Peak memory 204004 kb
Host smart-a8d720d7-ac2d-461c-b42e-377d64954f12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501933252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2501933252
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.842427923
Short name T1050
Test name
Test status
Simulation time 15497266 ps
CPU time 0.76 seconds
Started Jul 12 06:42:42 PM PDT 24
Finished Jul 12 06:42:45 PM PDT 24
Peak memory 204020 kb
Host smart-d7b74380-4bd8-401b-a5be-9afa43fbc4be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842427923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.842427923
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1881413479
Short name T1037
Test name
Test status
Simulation time 37114885 ps
CPU time 0.73 seconds
Started Jul 12 06:42:48 PM PDT 24
Finished Jul 12 06:42:52 PM PDT 24
Peak memory 204032 kb
Host smart-b714628b-b021-4832-9b24-8f4fd1d241df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881413479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1881413479
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.858239125
Short name T130
Test name
Test status
Simulation time 2085796016 ps
CPU time 20.55 seconds
Started Jul 12 06:42:18 PM PDT 24
Finished Jul 12 06:42:42 PM PDT 24
Peak memory 215540 kb
Host smart-5c0920fb-9a6d-4f17-b99e-47558dc6c2e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858239125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.858239125
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1509517291
Short name T1146
Test name
Test status
Simulation time 1884975854 ps
CPU time 13.78 seconds
Started Jul 12 06:42:16 PM PDT 24
Finished Jul 12 06:42:39 PM PDT 24
Peak memory 215476 kb
Host smart-60725488-55ef-4557-a4c0-f61cd0651b6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509517291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1509517291
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1740358778
Short name T1136
Test name
Test status
Simulation time 38430722 ps
CPU time 0.95 seconds
Started Jul 12 06:42:18 PM PDT 24
Finished Jul 12 06:42:23 PM PDT 24
Peak memory 207108 kb
Host smart-1821f7e7-f4bb-4495-bc5b-5f20d0261b00
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740358778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1740358778
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1170696668
Short name T155
Test name
Test status
Simulation time 2336160973 ps
CPU time 4.24 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:42:22 PM PDT 24
Peak memory 218332 kb
Host smart-b3ee20a8-4b1d-4226-93fb-4218db7eefaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170696668 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1170696668
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4267043082
Short name T124
Test name
Test status
Simulation time 59916902 ps
CPU time 1.13 seconds
Started Jul 12 06:42:25 PM PDT 24
Finished Jul 12 06:42:30 PM PDT 24
Peak memory 215612 kb
Host smart-41ab0bef-27c4-44b3-b958-e5f08a5f1599
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267043082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
267043082
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1761537111
Short name T1088
Test name
Test status
Simulation time 43505292 ps
CPU time 0.74 seconds
Started Jul 12 06:42:16 PM PDT 24
Finished Jul 12 06:42:21 PM PDT 24
Peak memory 204116 kb
Host smart-907f3273-2a6f-4b1b-a920-bef93577ac26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761537111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
761537111
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2279486915
Short name T119
Test name
Test status
Simulation time 28378228 ps
CPU time 2 seconds
Started Jul 12 06:42:20 PM PDT 24
Finished Jul 12 06:42:26 PM PDT 24
Peak memory 215528 kb
Host smart-378d7e9b-f7a0-4977-a0c1-27838c6f36da
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279486915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2279486915
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.355418252
Short name T1128
Test name
Test status
Simulation time 14200743 ps
CPU time 0.69 seconds
Started Jul 12 06:42:16 PM PDT 24
Finished Jul 12 06:42:21 PM PDT 24
Peak memory 203852 kb
Host smart-36e2ac7e-ee38-4b7d-b4f3-bd5c9cfc5c61
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355418252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.355418252
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1022023232
Short name T1071
Test name
Test status
Simulation time 217127924 ps
CPU time 2.78 seconds
Started Jul 12 06:42:18 PM PDT 24
Finished Jul 12 06:42:24 PM PDT 24
Peak memory 215548 kb
Host smart-443cf95c-a6d9-4722-90bc-3426cb2f9e5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022023232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1022023232
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3902822391
Short name T1109
Test name
Test status
Simulation time 33596759 ps
CPU time 2.19 seconds
Started Jul 12 06:42:17 PM PDT 24
Finished Jul 12 06:42:23 PM PDT 24
Peak memory 216060 kb
Host smart-03de5678-d382-4e6d-9f6d-b3b87db62958
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902822391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
902822391
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1025006803
Short name T101
Test name
Test status
Simulation time 265434986 ps
CPU time 7.36 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:42:25 PM PDT 24
Peak memory 215520 kb
Host smart-3e6cedc9-9b57-40ce-b3c2-eb2cd4b7e572
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025006803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1025006803
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2142612835
Short name T1065
Test name
Test status
Simulation time 13322058 ps
CPU time 0.73 seconds
Started Jul 12 06:42:37 PM PDT 24
Finished Jul 12 06:42:42 PM PDT 24
Peak memory 203960 kb
Host smart-829df738-b02e-4dab-85b7-2fbf091aea9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142612835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2142612835
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4156855971
Short name T1053
Test name
Test status
Simulation time 24851427 ps
CPU time 0.75 seconds
Started Jul 12 06:42:54 PM PDT 24
Finished Jul 12 06:42:57 PM PDT 24
Peak memory 203948 kb
Host smart-cf16832a-ab28-41ea-983a-581337a65cbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156855971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4156855971
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.80071909
Short name T1103
Test name
Test status
Simulation time 41943118 ps
CPU time 0.69 seconds
Started Jul 12 06:42:37 PM PDT 24
Finished Jul 12 06:42:41 PM PDT 24
Peak memory 203960 kb
Host smart-33dd5874-9d0f-45c0-8517-53649d4b36ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80071909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.80071909
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2840257353
Short name T1111
Test name
Test status
Simulation time 14164729 ps
CPU time 0.71 seconds
Started Jul 12 06:42:37 PM PDT 24
Finished Jul 12 06:42:42 PM PDT 24
Peak memory 203980 kb
Host smart-a636314a-84cd-4c8a-bccd-754da2b3d550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840257353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2840257353
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2362935939
Short name T1083
Test name
Test status
Simulation time 74587099 ps
CPU time 0.71 seconds
Started Jul 12 06:42:38 PM PDT 24
Finished Jul 12 06:42:42 PM PDT 24
Peak memory 203980 kb
Host smart-607a7139-04a3-4eb6-90e1-311882a71f39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362935939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2362935939
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2987917959
Short name T1032
Test name
Test status
Simulation time 24431100 ps
CPU time 0.69 seconds
Started Jul 12 06:42:37 PM PDT 24
Finished Jul 12 06:42:41 PM PDT 24
Peak memory 203972 kb
Host smart-d700700e-a2f2-4c22-8b4a-66bbba343e4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987917959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2987917959
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.260842644
Short name T1036
Test name
Test status
Simulation time 114681719 ps
CPU time 0.72 seconds
Started Jul 12 06:42:47 PM PDT 24
Finished Jul 12 06:42:49 PM PDT 24
Peak memory 204084 kb
Host smart-2722bbc5-bbca-4e43-80b5-bd36d648d2f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260842644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.260842644
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1971303764
Short name T1120
Test name
Test status
Simulation time 34896541 ps
CPU time 0.71 seconds
Started Jul 12 06:42:35 PM PDT 24
Finished Jul 12 06:42:39 PM PDT 24
Peak memory 204320 kb
Host smart-37e34ab9-45ba-4fbc-b377-ece781736045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971303764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1971303764
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2371662173
Short name T1078
Test name
Test status
Simulation time 20217308 ps
CPU time 0.83 seconds
Started Jul 12 06:42:40 PM PDT 24
Finished Jul 12 06:42:44 PM PDT 24
Peak memory 204068 kb
Host smart-0cdffe7e-9eff-480f-878d-129c993030cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371662173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2371662173
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1947629955
Short name T1079
Test name
Test status
Simulation time 15888052 ps
CPU time 0.74 seconds
Started Jul 12 06:42:53 PM PDT 24
Finished Jul 12 06:42:57 PM PDT 24
Peak memory 203964 kb
Host smart-3f6baeb6-cc08-4158-b55c-84eccdd59646
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947629955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1947629955
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1212749821
Short name T1118
Test name
Test status
Simulation time 357933227 ps
CPU time 8.05 seconds
Started Jul 12 06:42:21 PM PDT 24
Finished Jul 12 06:42:34 PM PDT 24
Peak memory 207280 kb
Host smart-4fa46489-b2e1-4d45-891c-eb8562654082
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212749821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1212749821
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2800493812
Short name T1112
Test name
Test status
Simulation time 22492515930 ps
CPU time 38.92 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:42:58 PM PDT 24
Peak memory 207428 kb
Host smart-9976640d-99fb-4635-bcb2-82570e63839a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800493812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2800493812
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3989456059
Short name T81
Test name
Test status
Simulation time 32448643 ps
CPU time 1.17 seconds
Started Jul 12 06:42:16 PM PDT 24
Finished Jul 12 06:42:21 PM PDT 24
Peak memory 216480 kb
Host smart-20be92fa-abaa-4119-afd8-bdfb26cc6262
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989456059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3989456059
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.106989308
Short name T1148
Test name
Test status
Simulation time 210608862 ps
CPU time 1.68 seconds
Started Jul 12 06:42:18 PM PDT 24
Finished Jul 12 06:42:23 PM PDT 24
Peak memory 215616 kb
Host smart-d5ce8289-2f6f-45e6-a5b4-fd91a0bdcffa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106989308 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.106989308
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1271913771
Short name T1068
Test name
Test status
Simulation time 21753453 ps
CPU time 1.31 seconds
Started Jul 12 06:42:20 PM PDT 24
Finished Jul 12 06:42:26 PM PDT 24
Peak memory 215540 kb
Host smart-d64bb073-a720-411e-837e-3a77a84d0a90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271913771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
271913771
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1954008794
Short name T1041
Test name
Test status
Simulation time 14283075 ps
CPU time 0.83 seconds
Started Jul 12 06:42:25 PM PDT 24
Finished Jul 12 06:42:29 PM PDT 24
Peak memory 204068 kb
Host smart-5d710681-0aa9-4234-8571-cb4af73ccbaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954008794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
954008794
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3288027090
Short name T1101
Test name
Test status
Simulation time 17896545 ps
CPU time 1.23 seconds
Started Jul 12 06:42:29 PM PDT 24
Finished Jul 12 06:42:32 PM PDT 24
Peak memory 215356 kb
Host smart-74efd18c-a3d3-4f3d-977f-f3a85bb1cc7b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288027090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3288027090
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3981088599
Short name T1096
Test name
Test status
Simulation time 39027937 ps
CPU time 0.66 seconds
Started Jul 12 06:42:28 PM PDT 24
Finished Jul 12 06:42:31 PM PDT 24
Peak memory 204200 kb
Host smart-b8e30797-7f56-4064-855d-52b9ef505162
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981088599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3981088599
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2497425634
Short name T1102
Test name
Test status
Simulation time 208193246 ps
CPU time 2.96 seconds
Started Jul 12 06:42:47 PM PDT 24
Finished Jul 12 06:42:51 PM PDT 24
Peak memory 215496 kb
Host smart-d0c60d20-2643-4929-8fcc-04130c96663c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497425634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2497425634
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3994705323
Short name T113
Test name
Test status
Simulation time 572334241 ps
CPU time 1.68 seconds
Started Jul 12 06:42:12 PM PDT 24
Finished Jul 12 06:42:18 PM PDT 24
Peak memory 215748 kb
Host smart-e6a3ae87-e00b-4e7c-b474-c0e0d3f390cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994705323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
994705323
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1042547549
Short name T177
Test name
Test status
Simulation time 300149544 ps
CPU time 11.38 seconds
Started Jul 12 06:42:28 PM PDT 24
Finished Jul 12 06:42:42 PM PDT 24
Peak memory 215464 kb
Host smart-38967a24-a95e-4970-8737-ebc36aef8e85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042547549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1042547549
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2275839030
Short name T1107
Test name
Test status
Simulation time 11431996 ps
CPU time 0.73 seconds
Started Jul 12 06:42:49 PM PDT 24
Finished Jul 12 06:42:52 PM PDT 24
Peak memory 203972 kb
Host smart-98c57f3d-d2c6-4442-b8ff-3ffbbee01f64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275839030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2275839030
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.308709983
Short name T1047
Test name
Test status
Simulation time 48157812 ps
CPU time 0.72 seconds
Started Jul 12 06:42:53 PM PDT 24
Finished Jul 12 06:42:57 PM PDT 24
Peak memory 203932 kb
Host smart-b28794e2-6f17-4764-8b12-b520017c2ce3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308709983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.308709983
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3750547786
Short name T1058
Test name
Test status
Simulation time 36778340 ps
CPU time 0.75 seconds
Started Jul 12 06:42:36 PM PDT 24
Finished Jul 12 06:42:41 PM PDT 24
Peak memory 204304 kb
Host smart-224974e3-99f9-47ee-976c-0243ff756f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750547786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3750547786
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3975104108
Short name T1127
Test name
Test status
Simulation time 21673196 ps
CPU time 0.7 seconds
Started Jul 12 06:42:36 PM PDT 24
Finished Jul 12 06:42:40 PM PDT 24
Peak memory 204348 kb
Host smart-b3bb3aaf-f853-460d-b9bd-786587cf9d0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975104108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3975104108
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.839675933
Short name T1104
Test name
Test status
Simulation time 50559126 ps
CPU time 0.75 seconds
Started Jul 12 06:42:46 PM PDT 24
Finished Jul 12 06:42:48 PM PDT 24
Peak memory 204296 kb
Host smart-19fc6e11-aa83-4f20-a796-ceef3b4db94d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839675933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.839675933
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2376168924
Short name T1060
Test name
Test status
Simulation time 14117064 ps
CPU time 0.77 seconds
Started Jul 12 06:42:36 PM PDT 24
Finished Jul 12 06:42:40 PM PDT 24
Peak memory 204064 kb
Host smart-a9990a54-359e-463e-b181-cb293dec67c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376168924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2376168924
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3456222076
Short name T1085
Test name
Test status
Simulation time 30480638 ps
CPU time 0.77 seconds
Started Jul 12 06:42:37 PM PDT 24
Finished Jul 12 06:42:42 PM PDT 24
Peak memory 204052 kb
Host smart-50c2a7dd-67fe-4ac4-9a96-6c5e486857b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456222076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3456222076
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2577861730
Short name T1084
Test name
Test status
Simulation time 22052056 ps
CPU time 0.73 seconds
Started Jul 12 06:42:35 PM PDT 24
Finished Jul 12 06:42:39 PM PDT 24
Peak memory 203988 kb
Host smart-3a5211ee-3918-4184-badc-949faa1f8ec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577861730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2577861730
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2048565010
Short name T1055
Test name
Test status
Simulation time 36903828 ps
CPU time 0.69 seconds
Started Jul 12 06:42:37 PM PDT 24
Finished Jul 12 06:42:42 PM PDT 24
Peak memory 203952 kb
Host smart-01aa667e-5fb9-41ae-9968-4610cd1d2619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048565010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2048565010
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2859543830
Short name T1089
Test name
Test status
Simulation time 15520083 ps
CPU time 0.8 seconds
Started Jul 12 06:42:39 PM PDT 24
Finished Jul 12 06:42:44 PM PDT 24
Peak memory 204292 kb
Host smart-fa931555-3941-451f-944f-691a4a3732d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859543830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2859543830
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1800056670
Short name T1132
Test name
Test status
Simulation time 60295511 ps
CPU time 1.83 seconds
Started Jul 12 06:42:18 PM PDT 24
Finished Jul 12 06:42:24 PM PDT 24
Peak memory 216532 kb
Host smart-d969ca3d-9cba-412b-bb8d-0c79b517ad6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800056670 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1800056670
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.925747266
Short name T1115
Test name
Test status
Simulation time 52984633 ps
CPU time 1.49 seconds
Started Jul 12 06:42:20 PM PDT 24
Finished Jul 12 06:42:24 PM PDT 24
Peak memory 207352 kb
Host smart-028fdb46-fcbc-4d85-be8e-6d03eb7ef017
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925747266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.925747266
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2195899265
Short name T1034
Test name
Test status
Simulation time 15963766 ps
CPU time 0.74 seconds
Started Jul 12 06:42:20 PM PDT 24
Finished Jul 12 06:42:25 PM PDT 24
Peak memory 204344 kb
Host smart-3bc6724d-37b7-4118-9ece-77d4fe127afd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195899265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
195899265
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1028131903
Short name T1049
Test name
Test status
Simulation time 621817388 ps
CPU time 3.83 seconds
Started Jul 12 06:42:18 PM PDT 24
Finished Jul 12 06:42:25 PM PDT 24
Peak memory 215516 kb
Host smart-8166980f-598d-4f03-bd98-0fab0b875930
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028131903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1028131903
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1770732137
Short name T1134
Test name
Test status
Simulation time 228915551 ps
CPU time 4.98 seconds
Started Jul 12 06:42:19 PM PDT 24
Finished Jul 12 06:42:27 PM PDT 24
Peak memory 215756 kb
Host smart-b0affc63-5a41-4bf3-9b42-c7fafd6f7c31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770732137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
770732137
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3576755820
Short name T1070
Test name
Test status
Simulation time 2623932844 ps
CPU time 13.9 seconds
Started Jul 12 06:42:23 PM PDT 24
Finished Jul 12 06:42:42 PM PDT 24
Peak memory 215916 kb
Host smart-00b171b8-6d82-425d-bb96-d8e11be123aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576755820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3576755820
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2884348084
Short name T1093
Test name
Test status
Simulation time 83545564 ps
CPU time 1.77 seconds
Started Jul 12 06:42:18 PM PDT 24
Finished Jul 12 06:42:24 PM PDT 24
Peak memory 215604 kb
Host smart-a4608b54-be8e-4164-80e2-f94745ab3cb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884348084 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2884348084
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.822389069
Short name T147
Test name
Test status
Simulation time 18546202 ps
CPU time 1.23 seconds
Started Jul 12 06:42:21 PM PDT 24
Finished Jul 12 06:42:26 PM PDT 24
Peak memory 215520 kb
Host smart-92a56449-7fe9-4648-abe1-4e1e211f14ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822389069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.822389069
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1823149960
Short name T1142
Test name
Test status
Simulation time 18500808 ps
CPU time 0.69 seconds
Started Jul 12 06:42:32 PM PDT 24
Finished Jul 12 06:42:35 PM PDT 24
Peak memory 203988 kb
Host smart-d9c4463a-e816-417d-89d4-3d3ed9620f77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823149960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
823149960
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2853792368
Short name T1129
Test name
Test status
Simulation time 231268878 ps
CPU time 3.61 seconds
Started Jul 12 06:42:23 PM PDT 24
Finished Jul 12 06:42:31 PM PDT 24
Peak memory 207336 kb
Host smart-c9f5ab72-44fc-4a85-9cd6-bd27aa80c6e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853792368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2853792368
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2646756141
Short name T111
Test name
Test status
Simulation time 64291893 ps
CPU time 1.95 seconds
Started Jul 12 06:42:22 PM PDT 24
Finished Jul 12 06:42:29 PM PDT 24
Peak memory 215816 kb
Host smart-8f5269aa-61ed-45ef-bc7a-6518dacc500e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646756141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
646756141
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2009557616
Short name T184
Test name
Test status
Simulation time 1893770181 ps
CPU time 7.16 seconds
Started Jul 12 06:42:32 PM PDT 24
Finished Jul 12 06:42:40 PM PDT 24
Peak memory 215664 kb
Host smart-44324b5a-0713-4711-b7a2-86bdf04b88e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009557616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2009557616
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3930997218
Short name T1114
Test name
Test status
Simulation time 601163176 ps
CPU time 1.87 seconds
Started Jul 12 06:42:21 PM PDT 24
Finished Jul 12 06:42:27 PM PDT 24
Peak memory 215616 kb
Host smart-c4b2eefd-07f5-44ae-8de8-deff39ed0df7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930997218 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3930997218
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2162066856
Short name T127
Test name
Test status
Simulation time 92344173 ps
CPU time 2.42 seconds
Started Jul 12 06:42:23 PM PDT 24
Finished Jul 12 06:42:29 PM PDT 24
Peak memory 207368 kb
Host smart-66e80772-b842-4522-b80d-3c11f1247638
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162066856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
162066856
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.347846573
Short name T1056
Test name
Test status
Simulation time 56128285 ps
CPU time 0.76 seconds
Started Jul 12 06:42:24 PM PDT 24
Finished Jul 12 06:42:29 PM PDT 24
Peak memory 204352 kb
Host smart-9ce8d053-e362-4f64-8ba8-52724fe77631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347846573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.347846573
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2827960902
Short name T1094
Test name
Test status
Simulation time 229727515 ps
CPU time 1.85 seconds
Started Jul 12 06:42:20 PM PDT 24
Finished Jul 12 06:42:26 PM PDT 24
Peak memory 207292 kb
Host smart-9791f3fd-3e25-4754-a738-64226d3dc92f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827960902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2827960902
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3802938310
Short name T1098
Test name
Test status
Simulation time 204617085 ps
CPU time 1.73 seconds
Started Jul 12 06:42:27 PM PDT 24
Finished Jul 12 06:42:32 PM PDT 24
Peak memory 216788 kb
Host smart-6fb0e0d0-939c-4919-922b-e77ed86797c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802938310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
802938310
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.277718984
Short name T182
Test name
Test status
Simulation time 2149474517 ps
CPU time 13.3 seconds
Started Jul 12 06:42:23 PM PDT 24
Finished Jul 12 06:42:41 PM PDT 24
Peak memory 215960 kb
Host smart-a17d5a86-b172-4ade-bff8-e0e9e590339d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277718984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.277718984
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2694193563
Short name T1077
Test name
Test status
Simulation time 74908476 ps
CPU time 2.54 seconds
Started Jul 12 06:42:22 PM PDT 24
Finished Jul 12 06:42:29 PM PDT 24
Peak memory 217304 kb
Host smart-b6f7f768-681b-43f4-b3c7-a7f29bef2707
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694193563 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2694193563
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2602995634
Short name T1080
Test name
Test status
Simulation time 20258494 ps
CPU time 1.44 seconds
Started Jul 12 06:42:22 PM PDT 24
Finished Jul 12 06:42:28 PM PDT 24
Peak memory 207360 kb
Host smart-813c6560-eecc-48d3-b798-565aa65294d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602995634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
602995634
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3597983439
Short name T1106
Test name
Test status
Simulation time 16609731 ps
CPU time 0.74 seconds
Started Jul 12 06:42:26 PM PDT 24
Finished Jul 12 06:42:30 PM PDT 24
Peak memory 204028 kb
Host smart-f8cc2aa9-4c60-42de-97f4-f6ec03a81d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597983439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
597983439
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.621317298
Short name T1045
Test name
Test status
Simulation time 108106787 ps
CPU time 1.78 seconds
Started Jul 12 06:42:23 PM PDT 24
Finished Jul 12 06:42:29 PM PDT 24
Peak memory 216136 kb
Host smart-16229929-f7cb-4778-885e-0e5e7fd03f27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621317298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.621317298
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1783241083
Short name T99
Test name
Test status
Simulation time 172185392 ps
CPU time 2.63 seconds
Started Jul 12 06:42:29 PM PDT 24
Finished Jul 12 06:42:34 PM PDT 24
Peak memory 216776 kb
Host smart-c712b0f0-9e6a-45d0-b65f-cf16049f48b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783241083 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1783241083
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1991895393
Short name T128
Test name
Test status
Simulation time 637384769 ps
CPU time 2.05 seconds
Started Jul 12 06:42:19 PM PDT 24
Finished Jul 12 06:42:25 PM PDT 24
Peak memory 207368 kb
Host smart-646c0492-a450-4624-a74c-2e98ce569977
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991895393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
991895393
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.654219100
Short name T1048
Test name
Test status
Simulation time 81134920 ps
CPU time 0.75 seconds
Started Jul 12 06:42:22 PM PDT 24
Finished Jul 12 06:42:27 PM PDT 24
Peak memory 204304 kb
Host smart-a8445424-1c00-49f2-a6c0-ec05d616ec22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654219100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.654219100
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2930208246
Short name T144
Test name
Test status
Simulation time 109161147 ps
CPU time 2.84 seconds
Started Jul 12 06:42:21 PM PDT 24
Finished Jul 12 06:42:28 PM PDT 24
Peak memory 215532 kb
Host smart-17c81226-bf11-4944-ae42-83e19a1f45b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930208246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2930208246
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3712478882
Short name T1110
Test name
Test status
Simulation time 85709341 ps
CPU time 2.16 seconds
Started Jul 12 06:42:23 PM PDT 24
Finished Jul 12 06:42:30 PM PDT 24
Peak memory 215708 kb
Host smart-0125f4f4-a594-40a3-a5c0-fa48ac1390d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712478882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
712478882
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.316998570
Short name T102
Test name
Test status
Simulation time 290133636 ps
CPU time 18.82 seconds
Started Jul 12 06:42:20 PM PDT 24
Finished Jul 12 06:42:44 PM PDT 24
Peak memory 215516 kb
Host smart-30738844-1193-4302-92ff-6b10bc1cfb18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316998570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.316998570
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3802092921
Short name T594
Test name
Test status
Simulation time 112343057 ps
CPU time 2.17 seconds
Started Jul 12 06:21:38 PM PDT 24
Finished Jul 12 06:21:41 PM PDT 24
Peak memory 225528 kb
Host smart-a2651e5f-999d-495a-93b9-5c187b5db3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802092921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3802092921
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2094699178
Short name T704
Test name
Test status
Simulation time 27228715 ps
CPU time 0.75 seconds
Started Jul 12 06:21:27 PM PDT 24
Finished Jul 12 06:21:29 PM PDT 24
Peak memory 207428 kb
Host smart-bf181f97-9638-48b2-975d-a090ee330487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094699178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2094699178
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2535150798
Short name T40
Test name
Test status
Simulation time 25643851153 ps
CPU time 112.32 seconds
Started Jul 12 06:21:46 PM PDT 24
Finished Jul 12 06:23:39 PM PDT 24
Peak memory 240068 kb
Host smart-d63b97fe-0cbf-438e-986e-cfadcef2521c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535150798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2535150798
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2706990490
Short name T133
Test name
Test status
Simulation time 22407891907 ps
CPU time 106.26 seconds
Started Jul 12 06:21:43 PM PDT 24
Finished Jul 12 06:23:30 PM PDT 24
Peak memory 250396 kb
Host smart-d441dfe5-891f-4fe6-ba0c-a6aeaf96a954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706990490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2706990490
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.703132166
Short name T36
Test name
Test status
Simulation time 63108065301 ps
CPU time 304.35 seconds
Started Jul 12 06:21:47 PM PDT 24
Finished Jul 12 06:26:53 PM PDT 24
Peak memory 254136 kb
Host smart-44b13e64-f2c1-41f7-bbd2-9aff363f7d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703132166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
703132166
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3243670604
Short name T987
Test name
Test status
Simulation time 11582150462 ps
CPU time 68.78 seconds
Started Jul 12 06:21:39 PM PDT 24
Finished Jul 12 06:22:49 PM PDT 24
Peak memory 235196 kb
Host smart-5d561cf8-14be-448e-8598-4226c96f43fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243670604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3243670604
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2532794080
Short name T364
Test name
Test status
Simulation time 987401071 ps
CPU time 4.83 seconds
Started Jul 12 06:21:34 PM PDT 24
Finished Jul 12 06:21:39 PM PDT 24
Peak memory 233648 kb
Host smart-99ec8be4-8ed3-475b-9af0-d1a6455741cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532794080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2532794080
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.250945451
Short name T805
Test name
Test status
Simulation time 96127967 ps
CPU time 2.36 seconds
Started Jul 12 06:21:34 PM PDT 24
Finished Jul 12 06:21:37 PM PDT 24
Peak memory 224812 kb
Host smart-cf495a56-7c4a-4776-b1bc-583895769854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250945451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.250945451
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2219397181
Short name T644
Test name
Test status
Simulation time 63256012 ps
CPU time 1.02 seconds
Started Jul 12 06:21:27 PM PDT 24
Finished Jul 12 06:21:28 PM PDT 24
Peak memory 217656 kb
Host smart-267b0384-d042-4dbf-a3a0-837e05077667
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219397181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2219397181
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2044134277
Short name T667
Test name
Test status
Simulation time 4697022523 ps
CPU time 15.31 seconds
Started Jul 12 06:21:32 PM PDT 24
Finished Jul 12 06:21:48 PM PDT 24
Peak memory 225692 kb
Host smart-44a4d871-f762-416f-91d7-63103c711234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044134277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2044134277
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2850110047
Short name T261
Test name
Test status
Simulation time 1391820130 ps
CPU time 6.37 seconds
Started Jul 12 06:21:26 PM PDT 24
Finished Jul 12 06:21:33 PM PDT 24
Peak memory 233732 kb
Host smart-8ee77358-a278-4c50-b26e-d837f3c4eaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850110047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2850110047
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1378094806
Short name T1023
Test name
Test status
Simulation time 177445789 ps
CPU time 4.49 seconds
Started Jul 12 06:21:43 PM PDT 24
Finished Jul 12 06:21:48 PM PDT 24
Peak memory 221336 kb
Host smart-0f21c79f-ce00-4739-a8ec-e2e468339e48
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1378094806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1378094806
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3632789284
Short name T68
Test name
Test status
Simulation time 1097183751 ps
CPU time 1.09 seconds
Started Jul 12 06:21:46 PM PDT 24
Finished Jul 12 06:21:48 PM PDT 24
Peak memory 236736 kb
Host smart-8277366a-75c8-4106-95f1-21495e550e40
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632789284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3632789284
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3053027554
Short name T192
Test name
Test status
Simulation time 5734137251 ps
CPU time 72.17 seconds
Started Jul 12 06:21:48 PM PDT 24
Finished Jul 12 06:23:01 PM PDT 24
Peak memory 258544 kb
Host smart-f4075a65-c604-4924-8707-350c2ed58a73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053027554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3053027554
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3222242836
Short name T719
Test name
Test status
Simulation time 15636791149 ps
CPU time 23.56 seconds
Started Jul 12 06:21:26 PM PDT 24
Finished Jul 12 06:21:50 PM PDT 24
Peak memory 217576 kb
Host smart-2c5bb216-a231-4890-9614-1413ae227a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222242836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3222242836
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3744824060
Short name T354
Test name
Test status
Simulation time 6765481564 ps
CPU time 2.12 seconds
Started Jul 12 06:21:26 PM PDT 24
Finished Jul 12 06:21:28 PM PDT 24
Peak memory 209044 kb
Host smart-13beb2a8-eaec-4214-8f57-05d17889ee37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744824060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3744824060
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2619177049
Short name T525
Test name
Test status
Simulation time 68602620 ps
CPU time 1.88 seconds
Started Jul 12 06:21:26 PM PDT 24
Finished Jul 12 06:21:29 PM PDT 24
Peak memory 209128 kb
Host smart-7d619205-4afc-45e2-a94b-4c54bdd69447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619177049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2619177049
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2561278711
Short name T770
Test name
Test status
Simulation time 235886067 ps
CPU time 0.87 seconds
Started Jul 12 06:21:26 PM PDT 24
Finished Jul 12 06:21:28 PM PDT 24
Peak memory 207384 kb
Host smart-25175685-0e68-497e-9c16-8ec39c0f30cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561278711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2561278711
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2208339415
Short name T27
Test name
Test status
Simulation time 221537418 ps
CPU time 2.46 seconds
Started Jul 12 06:21:33 PM PDT 24
Finished Jul 12 06:21:36 PM PDT 24
Peak memory 225572 kb
Host smart-0cf434de-95f1-4e65-8d04-feaf7b840c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208339415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2208339415
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1893174926
Short name T367
Test name
Test status
Simulation time 38933312 ps
CPU time 0.68 seconds
Started Jul 12 06:22:07 PM PDT 24
Finished Jul 12 06:22:08 PM PDT 24
Peak memory 206348 kb
Host smart-d7de5917-331a-4806-989e-5a105a8259d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893174926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
893174926
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.405656124
Short name T675
Test name
Test status
Simulation time 3674612857 ps
CPU time 11.7 seconds
Started Jul 12 06:21:56 PM PDT 24
Finished Jul 12 06:22:09 PM PDT 24
Peak memory 225684 kb
Host smart-14ce68c3-a3d1-4c5f-9205-5cbeb32387da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405656124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.405656124
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.472811305
Short name T984
Test name
Test status
Simulation time 15362503 ps
CPU time 0.77 seconds
Started Jul 12 06:21:54 PM PDT 24
Finished Jul 12 06:21:55 PM PDT 24
Peak memory 206476 kb
Host smart-c3a0d49b-6be4-44ff-a460-a926093c1364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472811305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.472811305
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3406390690
Short name T672
Test name
Test status
Simulation time 86789468 ps
CPU time 0.73 seconds
Started Jul 12 06:22:03 PM PDT 24
Finished Jul 12 06:22:04 PM PDT 24
Peak memory 216900 kb
Host smart-1cc2ed5a-fbd4-49c4-b1c2-8017b6cf3e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406390690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3406390690
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2103926814
Short name T209
Test name
Test status
Simulation time 147271037935 ps
CPU time 206.2 seconds
Started Jul 12 06:22:05 PM PDT 24
Finished Jul 12 06:25:31 PM PDT 24
Peak memory 273104 kb
Host smart-b5877978-b7a8-43b7-b2bc-6599521ebb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103926814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2103926814
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3754584269
Short name T409
Test name
Test status
Simulation time 9605199772 ps
CPU time 38.4 seconds
Started Jul 12 06:22:06 PM PDT 24
Finished Jul 12 06:22:45 PM PDT 24
Peak memory 241648 kb
Host smart-5b6464cd-82bf-4b30-92f4-2b8e8a10f568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754584269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3754584269
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4061914379
Short name T587
Test name
Test status
Simulation time 3996075677 ps
CPU time 11.37 seconds
Started Jul 12 06:22:04 PM PDT 24
Finished Jul 12 06:22:16 PM PDT 24
Peak memory 235972 kb
Host smart-c3f7ff00-9887-4847-838a-dda6aa0b57de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061914379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4061914379
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2842532991
Short name T604
Test name
Test status
Simulation time 28133805313 ps
CPU time 50.88 seconds
Started Jul 12 06:22:04 PM PDT 24
Finished Jul 12 06:22:56 PM PDT 24
Peak memory 250252 kb
Host smart-34ad8b8f-6df9-4228-876a-19e9c63ce8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842532991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2842532991
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3741388544
Short name T59
Test name
Test status
Simulation time 529391757 ps
CPU time 4.75 seconds
Started Jul 12 06:22:02 PM PDT 24
Finished Jul 12 06:22:07 PM PDT 24
Peak memory 233792 kb
Host smart-51f80955-fbe2-42a4-95c6-45f058bfaebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741388544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3741388544
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1773170158
Short name T687
Test name
Test status
Simulation time 3613027479 ps
CPU time 29.2 seconds
Started Jul 12 06:21:59 PM PDT 24
Finished Jul 12 06:22:29 PM PDT 24
Peak memory 251188 kb
Host smart-d65a81b2-7508-4446-a9a5-3f5204f1519c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773170158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1773170158
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2130382679
Short name T703
Test name
Test status
Simulation time 25093893 ps
CPU time 1.04 seconds
Started Jul 12 06:21:57 PM PDT 24
Finished Jul 12 06:21:58 PM PDT 24
Peak memory 217644 kb
Host smart-b68dc8f4-1782-41f2-a9f3-dfa75069e68f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130382679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2130382679
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4294546889
Short name T435
Test name
Test status
Simulation time 13000137152 ps
CPU time 9.45 seconds
Started Jul 12 06:21:58 PM PDT 24
Finished Jul 12 06:22:09 PM PDT 24
Peak memory 225656 kb
Host smart-aae1b648-a931-4431-975b-2a16cadddab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294546889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4294546889
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1075394777
Short name T221
Test name
Test status
Simulation time 39288350500 ps
CPU time 27.31 seconds
Started Jul 12 06:21:59 PM PDT 24
Finished Jul 12 06:22:27 PM PDT 24
Peak memory 225680 kb
Host smart-53230234-c440-4dbb-81fb-887a710da9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075394777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1075394777
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4205448734
Short name T801
Test name
Test status
Simulation time 868869202 ps
CPU time 6.07 seconds
Started Jul 12 06:22:02 PM PDT 24
Finished Jul 12 06:22:09 PM PDT 24
Peak memory 222864 kb
Host smart-f8025d63-dac3-4f56-86ea-9f5fdd6608aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4205448734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4205448734
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1736452573
Short name T326
Test name
Test status
Simulation time 10822387 ps
CPU time 0.69 seconds
Started Jul 12 06:21:56 PM PDT 24
Finished Jul 12 06:21:58 PM PDT 24
Peak memory 206636 kb
Host smart-19a120d4-4258-42c0-b687-0e2a5eefbae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736452573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1736452573
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3292443604
Short name T522
Test name
Test status
Simulation time 2008556275 ps
CPU time 5.2 seconds
Started Jul 12 06:21:51 PM PDT 24
Finished Jul 12 06:21:57 PM PDT 24
Peak memory 217320 kb
Host smart-7e32b5c5-76f8-40dc-8e3c-ebe1e932f16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292443604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3292443604
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1720740322
Short name T774
Test name
Test status
Simulation time 42393503 ps
CPU time 1.09 seconds
Started Jul 12 06:22:03 PM PDT 24
Finished Jul 12 06:22:04 PM PDT 24
Peak memory 208948 kb
Host smart-35d7a2f1-0b05-4e31-96e0-7f4021c199d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720740322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1720740322
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3230231943
Short name T690
Test name
Test status
Simulation time 84711000 ps
CPU time 0.9 seconds
Started Jul 12 06:21:59 PM PDT 24
Finished Jul 12 06:22:00 PM PDT 24
Peak memory 207964 kb
Host smart-b93d9790-76c5-4cb3-bcb9-d50d4a4410ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230231943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3230231943
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2980664273
Short name T862
Test name
Test status
Simulation time 17123246590 ps
CPU time 28.71 seconds
Started Jul 12 06:21:59 PM PDT 24
Finished Jul 12 06:22:28 PM PDT 24
Peak memory 250284 kb
Host smart-0ce92c63-b93f-4966-9b97-67b0fc7ed0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980664273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2980664273
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.66431646
Short name T863
Test name
Test status
Simulation time 19305313 ps
CPU time 0.74 seconds
Started Jul 12 06:23:58 PM PDT 24
Finished Jul 12 06:23:59 PM PDT 24
Peak memory 206364 kb
Host smart-c0dad609-b951-485d-8452-769339829a80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66431646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.66431646
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.826848760
Short name T789
Test name
Test status
Simulation time 280345471 ps
CPU time 2.19 seconds
Started Jul 12 06:23:56 PM PDT 24
Finished Jul 12 06:23:59 PM PDT 24
Peak memory 225556 kb
Host smart-e9010b6e-9baf-49a8-aae9-e70fcb2e6ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826848760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.826848760
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1782654018
Short name T721
Test name
Test status
Simulation time 16466411 ps
CPU time 0.75 seconds
Started Jul 12 06:23:56 PM PDT 24
Finished Jul 12 06:23:58 PM PDT 24
Peak memory 206488 kb
Host smart-da25210e-2b5c-421c-9294-0a5859129034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782654018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1782654018
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1362867472
Short name T214
Test name
Test status
Simulation time 14317333903 ps
CPU time 123.17 seconds
Started Jul 12 06:24:00 PM PDT 24
Finished Jul 12 06:26:04 PM PDT 24
Peak memory 250420 kb
Host smart-9f373044-abfb-479c-acc7-2a6d344fae52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362867472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1362867472
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1640763796
Short name T204
Test name
Test status
Simulation time 10933264050 ps
CPU time 71.34 seconds
Started Jul 12 06:23:58 PM PDT 24
Finished Jul 12 06:25:10 PM PDT 24
Peak memory 241388 kb
Host smart-9d188775-c018-4030-a538-53e68da3303d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640763796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1640763796
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2530711172
Short name T445
Test name
Test status
Simulation time 94569153 ps
CPU time 2.55 seconds
Started Jul 12 06:23:55 PM PDT 24
Finished Jul 12 06:23:58 PM PDT 24
Peak memory 233764 kb
Host smart-4572b06f-440e-461f-9eb4-679b04f84d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530711172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2530711172
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2099979046
Short name T1027
Test name
Test status
Simulation time 65466958310 ps
CPU time 149.93 seconds
Started Jul 12 06:23:57 PM PDT 24
Finished Jul 12 06:26:28 PM PDT 24
Peak memory 264384 kb
Host smart-61c3bd87-4a1b-4a96-ba01-4d30488ca582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099979046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2099979046
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1863200228
Short name T251
Test name
Test status
Simulation time 298832234 ps
CPU time 4.75 seconds
Started Jul 12 06:23:56 PM PDT 24
Finished Jul 12 06:24:01 PM PDT 24
Peak memory 233684 kb
Host smart-9bdfab63-7f10-4b06-bd9b-d30bc04f7129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863200228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1863200228
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1413794252
Short name T262
Test name
Test status
Simulation time 1016855634 ps
CPU time 10.53 seconds
Started Jul 12 06:23:55 PM PDT 24
Finished Jul 12 06:24:07 PM PDT 24
Peak memory 225472 kb
Host smart-b18df740-8cb7-45b0-ac26-b7b0c9d81686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413794252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1413794252
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1003155243
Short name T955
Test name
Test status
Simulation time 2755737619 ps
CPU time 4.29 seconds
Started Jul 12 06:23:58 PM PDT 24
Finished Jul 12 06:24:04 PM PDT 24
Peak memory 233844 kb
Host smart-101a9824-d082-4fb9-be19-a9f73bac0fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003155243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1003155243
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2326082436
Short name T335
Test name
Test status
Simulation time 31058689 ps
CPU time 2.59 seconds
Started Jul 12 06:23:52 PM PDT 24
Finished Jul 12 06:23:55 PM PDT 24
Peak memory 233508 kb
Host smart-35d59d70-83b5-40a7-97e7-3556a51594fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326082436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2326082436
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3659000544
Short name T640
Test name
Test status
Simulation time 3660280328 ps
CPU time 11.88 seconds
Started Jul 12 06:23:57 PM PDT 24
Finished Jul 12 06:24:09 PM PDT 24
Peak memory 224100 kb
Host smart-a554336a-b169-4a4d-997e-3a2141680578
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3659000544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3659000544
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2510066878
Short name T988
Test name
Test status
Simulation time 4426604834 ps
CPU time 23.94 seconds
Started Jul 12 06:23:51 PM PDT 24
Finished Jul 12 06:24:15 PM PDT 24
Peak memory 217500 kb
Host smart-72ab898b-e5be-4707-b5f3-56634f30d940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510066878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2510066878
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1710196239
Short name T547
Test name
Test status
Simulation time 1426746705 ps
CPU time 6.13 seconds
Started Jul 12 06:23:52 PM PDT 24
Finished Jul 12 06:23:59 PM PDT 24
Peak memory 217364 kb
Host smart-87b22506-b29f-4c5f-86dd-036bb5b0ad8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710196239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1710196239
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.830074981
Short name T610
Test name
Test status
Simulation time 19427794 ps
CPU time 0.82 seconds
Started Jul 12 06:23:51 PM PDT 24
Finished Jul 12 06:23:53 PM PDT 24
Peak memory 206876 kb
Host smart-de8f6d04-c201-44c4-8ffd-6a1ede3384dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830074981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.830074981
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2725896498
Short name T969
Test name
Test status
Simulation time 206616082 ps
CPU time 0.77 seconds
Started Jul 12 06:23:51 PM PDT 24
Finished Jul 12 06:23:52 PM PDT 24
Peak memory 206952 kb
Host smart-13267613-d7cd-4597-a176-df20a98cf556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725896498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2725896498
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.984597434
Short name T475
Test name
Test status
Simulation time 22139335565 ps
CPU time 19.42 seconds
Started Jul 12 06:23:55 PM PDT 24
Finished Jul 12 06:24:16 PM PDT 24
Peak memory 233836 kb
Host smart-154e3d66-50b8-4d18-b8ce-a5c255b6597f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984597434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.984597434
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3340578979
Short name T528
Test name
Test status
Simulation time 32762931 ps
CPU time 0.7 seconds
Started Jul 12 06:24:07 PM PDT 24
Finished Jul 12 06:24:09 PM PDT 24
Peak memory 205792 kb
Host smart-18679362-7e33-499f-a1c5-d9f07aa67489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340578979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3340578979
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.4291111653
Short name T921
Test name
Test status
Simulation time 508691974 ps
CPU time 3.02 seconds
Started Jul 12 06:24:08 PM PDT 24
Finished Jul 12 06:24:12 PM PDT 24
Peak memory 225484 kb
Host smart-b94ea02e-1d17-4284-a875-7107979c0f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291111653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4291111653
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.403363882
Short name T540
Test name
Test status
Simulation time 21093273 ps
CPU time 0.85 seconds
Started Jul 12 06:24:03 PM PDT 24
Finished Jul 12 06:24:05 PM PDT 24
Peak memory 207472 kb
Host smart-dc174293-14c6-4702-9fb0-d94b06c05633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403363882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.403363882
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1711070711
Short name T233
Test name
Test status
Simulation time 8997408399 ps
CPU time 79.76 seconds
Started Jul 12 06:24:07 PM PDT 24
Finished Jul 12 06:25:27 PM PDT 24
Peak memory 256280 kb
Host smart-07f253fc-62de-4f3c-8d1e-96b1630fcf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711070711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1711070711
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1331461204
Short name T479
Test name
Test status
Simulation time 4456085291 ps
CPU time 61.29 seconds
Started Jul 12 06:24:07 PM PDT 24
Finished Jul 12 06:25:09 PM PDT 24
Peak memory 235016 kb
Host smart-ba1a67cf-23ac-4ccd-af51-ef62697e61da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331461204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1331461204
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2009147886
Short name T309
Test name
Test status
Simulation time 1743050277 ps
CPU time 22.13 seconds
Started Jul 12 06:24:08 PM PDT 24
Finished Jul 12 06:24:31 PM PDT 24
Peak memory 233728 kb
Host smart-d51f52be-b13b-4304-b21d-85ec775bdc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009147886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2009147886
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2158237882
Short name T971
Test name
Test status
Simulation time 11742906030 ps
CPU time 100.11 seconds
Started Jul 12 06:24:07 PM PDT 24
Finished Jul 12 06:25:48 PM PDT 24
Peak memory 250408 kb
Host smart-4f5871c5-9b86-43fa-9e07-1be024b7f7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158237882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2158237882
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.4091907728
Short name T847
Test name
Test status
Simulation time 298377557 ps
CPU time 4.31 seconds
Started Jul 12 06:24:08 PM PDT 24
Finished Jul 12 06:24:13 PM PDT 24
Peak memory 225512 kb
Host smart-eb7bf12b-fb2f-44d1-8ce5-936369d22abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091907728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.4091907728
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.279084097
Short name T732
Test name
Test status
Simulation time 120483964 ps
CPU time 1.05 seconds
Started Jul 12 06:24:01 PM PDT 24
Finished Jul 12 06:24:03 PM PDT 24
Peak memory 217604 kb
Host smart-42cf54eb-4972-475d-889d-93f4ed984496
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279084097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.279084097
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2458358314
Short name T648
Test name
Test status
Simulation time 6129020708 ps
CPU time 9.36 seconds
Started Jul 12 06:24:01 PM PDT 24
Finished Jul 12 06:24:11 PM PDT 24
Peak memory 225600 kb
Host smart-d91cb163-3768-4238-9cfc-b0020a2fb8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458358314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2458358314
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3327696348
Short name T240
Test name
Test status
Simulation time 5143748610 ps
CPU time 7.78 seconds
Started Jul 12 06:24:03 PM PDT 24
Finished Jul 12 06:24:11 PM PDT 24
Peak memory 242100 kb
Host smart-1526f256-1b99-475a-9cb6-9adb9f094652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327696348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3327696348
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1793402093
Short name T152
Test name
Test status
Simulation time 477115125 ps
CPU time 4.59 seconds
Started Jul 12 06:24:07 PM PDT 24
Finished Jul 12 06:24:13 PM PDT 24
Peak memory 223340 kb
Host smart-4cff075e-9639-41f6-874f-787e14290586
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1793402093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1793402093
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.769758365
Short name T845
Test name
Test status
Simulation time 74506933 ps
CPU time 1.03 seconds
Started Jul 12 06:24:07 PM PDT 24
Finished Jul 12 06:24:09 PM PDT 24
Peak memory 208724 kb
Host smart-be0a2097-4db5-4206-a6e6-0c016edaa0c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769758365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.769758365
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1591100813
Short name T747
Test name
Test status
Simulation time 9905967796 ps
CPU time 26.86 seconds
Started Jul 12 06:24:03 PM PDT 24
Finished Jul 12 06:24:30 PM PDT 24
Peak memory 217456 kb
Host smart-97a92473-70e0-4b48-965a-fd2003b00b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591100813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1591100813
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3077317137
Short name T841
Test name
Test status
Simulation time 9340800219 ps
CPU time 26.32 seconds
Started Jul 12 06:24:01 PM PDT 24
Finished Jul 12 06:24:28 PM PDT 24
Peak memory 217408 kb
Host smart-2623356b-4f5f-4bcc-8c81-66e8bf172e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077317137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3077317137
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.471707305
Short name T531
Test name
Test status
Simulation time 77753626 ps
CPU time 1.07 seconds
Started Jul 12 06:24:02 PM PDT 24
Finished Jul 12 06:24:04 PM PDT 24
Peak memory 208832 kb
Host smart-212a25b2-08aa-48ab-86e8-7f3e05542127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471707305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.471707305
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2225825220
Short name T386
Test name
Test status
Simulation time 52861697 ps
CPU time 0.91 seconds
Started Jul 12 06:24:04 PM PDT 24
Finished Jul 12 06:24:06 PM PDT 24
Peak memory 207960 kb
Host smart-219d42e4-0376-41e2-b099-a46bc39c1bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225825220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2225825220
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1933117629
Short name T579
Test name
Test status
Simulation time 211980436 ps
CPU time 2.49 seconds
Started Jul 12 06:24:07 PM PDT 24
Finished Jul 12 06:24:10 PM PDT 24
Peak memory 225560 kb
Host smart-f3ab1091-1bd7-4b65-92a9-c0cdbd725e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933117629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1933117629
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1373064045
Short name T887
Test name
Test status
Simulation time 12699772 ps
CPU time 0.72 seconds
Started Jul 12 06:24:19 PM PDT 24
Finished Jul 12 06:24:21 PM PDT 24
Peak memory 206356 kb
Host smart-cc81eaba-0d15-43f9-b794-1d952dd7dce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373064045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1373064045
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2948406700
Short name T434
Test name
Test status
Simulation time 12487998480 ps
CPU time 9.51 seconds
Started Jul 12 06:24:18 PM PDT 24
Finished Jul 12 06:24:29 PM PDT 24
Peak memory 225604 kb
Host smart-eba8df4e-1442-42b1-a77d-f40a4e265037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948406700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2948406700
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1081624088
Short name T684
Test name
Test status
Simulation time 14575232 ps
CPU time 0.76 seconds
Started Jul 12 06:24:12 PM PDT 24
Finished Jul 12 06:24:14 PM PDT 24
Peak memory 206768 kb
Host smart-92c6ea36-47c7-4176-ba88-1f8a4bb93804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081624088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1081624088
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3853496779
Short name T710
Test name
Test status
Simulation time 41609501907 ps
CPU time 87.57 seconds
Started Jul 12 06:24:18 PM PDT 24
Finished Jul 12 06:25:45 PM PDT 24
Peak memory 255496 kb
Host smart-91512fd1-cce8-4533-aaa3-c8e1f628d9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853496779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3853496779
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3847972068
Short name T839
Test name
Test status
Simulation time 28947976232 ps
CPU time 220.81 seconds
Started Jul 12 06:24:18 PM PDT 24
Finished Jul 12 06:28:00 PM PDT 24
Peak memory 252424 kb
Host smart-e260860f-934d-4296-a2db-9121940d6d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847972068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3847972068
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3036665129
Short name T889
Test name
Test status
Simulation time 732752540 ps
CPU time 17.56 seconds
Started Jul 12 06:24:19 PM PDT 24
Finished Jul 12 06:24:38 PM PDT 24
Peak memory 233688 kb
Host smart-c485438c-0bcb-4e7b-ac8b-f236da776824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036665129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3036665129
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.941439085
Short name T96
Test name
Test status
Simulation time 22096926619 ps
CPU time 67.6 seconds
Started Jul 12 06:24:20 PM PDT 24
Finished Jul 12 06:25:28 PM PDT 24
Peak memory 251288 kb
Host smart-bc5b0f55-103a-4a12-90b1-58767248603d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941439085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.941439085
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.453285412
Short name T746
Test name
Test status
Simulation time 378392763 ps
CPU time 2.88 seconds
Started Jul 12 06:24:11 PM PDT 24
Finished Jul 12 06:24:16 PM PDT 24
Peak memory 233764 kb
Host smart-7617b19a-a7bb-4b6c-b4b0-250117e632ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453285412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.453285412
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3774810932
Short name T880
Test name
Test status
Simulation time 12454649905 ps
CPU time 33.22 seconds
Started Jul 12 06:24:18 PM PDT 24
Finished Jul 12 06:24:53 PM PDT 24
Peak memory 233852 kb
Host smart-eae36bf2-63e3-4917-be84-9b2062397b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774810932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3774810932
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.593658657
Short name T483
Test name
Test status
Simulation time 16380576 ps
CPU time 1.08 seconds
Started Jul 12 06:24:12 PM PDT 24
Finished Jul 12 06:24:14 PM PDT 24
Peak memory 217636 kb
Host smart-ee57adb8-727a-41a8-a478-5654b8ab60c8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593658657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.593658657
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.80552013
Short name T210
Test name
Test status
Simulation time 9971376466 ps
CPU time 14.03 seconds
Started Jul 12 06:24:11 PM PDT 24
Finished Jul 12 06:24:25 PM PDT 24
Peak memory 233852 kb
Host smart-d872a0f7-8509-4e49-a58c-219134c2efa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80552013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.80552013
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3797324232
Short name T273
Test name
Test status
Simulation time 511995805 ps
CPU time 5.54 seconds
Started Jul 12 06:24:13 PM PDT 24
Finished Jul 12 06:24:19 PM PDT 24
Peak memory 233696 kb
Host smart-96030699-8b03-4357-8df2-9ad8c389cafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797324232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3797324232
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1478049018
Short name T920
Test name
Test status
Simulation time 544399820 ps
CPU time 4.37 seconds
Started Jul 12 06:24:16 PM PDT 24
Finished Jul 12 06:24:21 PM PDT 24
Peak memory 224028 kb
Host smart-abfb4ef8-d525-4649-8a2d-d5c432f8439e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1478049018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1478049018
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3324489649
Short name T904
Test name
Test status
Simulation time 10466890849 ps
CPU time 128.04 seconds
Started Jul 12 06:24:18 PM PDT 24
Finished Jul 12 06:26:27 PM PDT 24
Peak memory 256016 kb
Host smart-27e3d938-be5f-43e8-a13c-a21f3d05f107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324489649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3324489649
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2753718576
Short name T615
Test name
Test status
Simulation time 5680797155 ps
CPU time 28.66 seconds
Started Jul 12 06:24:12 PM PDT 24
Finished Jul 12 06:24:42 PM PDT 24
Peak memory 222036 kb
Host smart-37b255b3-25f3-487f-aeb9-7c5d1ccedf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753718576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2753718576
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1700480886
Short name T506
Test name
Test status
Simulation time 1010968102 ps
CPU time 3.72 seconds
Started Jul 12 06:24:11 PM PDT 24
Finished Jul 12 06:24:17 PM PDT 24
Peak memory 217240 kb
Host smart-0cb68c3e-0300-49e3-b54c-968dca4ac6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700480886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1700480886
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3263041768
Short name T519
Test name
Test status
Simulation time 87674013 ps
CPU time 1.53 seconds
Started Jul 12 06:24:12 PM PDT 24
Finished Jul 12 06:24:15 PM PDT 24
Peak memory 217336 kb
Host smart-114f61c5-d230-4b73-a16b-8a163abd795e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263041768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3263041768
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3065552712
Short name T438
Test name
Test status
Simulation time 72747696 ps
CPU time 0.92 seconds
Started Jul 12 06:24:12 PM PDT 24
Finished Jul 12 06:24:14 PM PDT 24
Peak memory 206936 kb
Host smart-a22f4b68-e0ae-42a3-8298-7f7bb2bd8739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065552712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3065552712
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.4161817016
Short name T492
Test name
Test status
Simulation time 937728877 ps
CPU time 3.02 seconds
Started Jul 12 06:24:19 PM PDT 24
Finished Jul 12 06:24:23 PM PDT 24
Peak memory 225480 kb
Host smart-a80f8957-d2af-4be4-a19a-1a4c19c9eb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161817016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.4161817016
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1021609304
Short name T7
Test name
Test status
Simulation time 35987165 ps
CPU time 0.76 seconds
Started Jul 12 06:24:25 PM PDT 24
Finished Jul 12 06:24:26 PM PDT 24
Peak memory 206696 kb
Host smart-b7cfd7a4-11f8-498f-99fb-33f76ff290c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021609304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1021609304
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.4248391141
Short name T730
Test name
Test status
Simulation time 107146624 ps
CPU time 2.73 seconds
Started Jul 12 06:24:26 PM PDT 24
Finished Jul 12 06:24:29 PM PDT 24
Peak memory 233600 kb
Host smart-4e2dcde8-d306-4b1b-b3dc-4ffa61b8734a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248391141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4248391141
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2236147099
Short name T768
Test name
Test status
Simulation time 19813483 ps
CPU time 0.79 seconds
Started Jul 12 06:24:20 PM PDT 24
Finished Jul 12 06:24:22 PM PDT 24
Peak memory 207488 kb
Host smart-2f1ac684-6fa3-44ca-bd8d-325472a02138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236147099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2236147099
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3131515113
Short name T864
Test name
Test status
Simulation time 46259805490 ps
CPU time 81.05 seconds
Started Jul 12 06:24:24 PM PDT 24
Finished Jul 12 06:25:45 PM PDT 24
Peak memory 250232 kb
Host smart-2cafb305-6306-4b8c-93c3-6ad7cdb4c4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131515113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3131515113
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.900995863
Short name T263
Test name
Test status
Simulation time 14758077245 ps
CPU time 120.69 seconds
Started Jul 12 06:24:24 PM PDT 24
Finished Jul 12 06:26:25 PM PDT 24
Peak memory 257432 kb
Host smart-e63524c1-2fd5-471b-98d7-4151849d30d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900995863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.900995863
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.346056638
Short name T132
Test name
Test status
Simulation time 126759607500 ps
CPU time 288.06 seconds
Started Jul 12 06:24:26 PM PDT 24
Finished Jul 12 06:29:15 PM PDT 24
Peak memory 257760 kb
Host smart-0a102952-589d-4e83-bda6-36a69992b9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346056638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.346056638
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3007577265
Short name T353
Test name
Test status
Simulation time 5418039832 ps
CPU time 24.49 seconds
Started Jul 12 06:24:28 PM PDT 24
Finished Jul 12 06:24:53 PM PDT 24
Peak memory 239512 kb
Host smart-914082f3-6966-4331-8f7d-0dbd64128a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007577265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3007577265
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.475548012
Short name T977
Test name
Test status
Simulation time 60208988 ps
CPU time 0.83 seconds
Started Jul 12 06:24:27 PM PDT 24
Finished Jul 12 06:24:28 PM PDT 24
Peak memory 216900 kb
Host smart-00fb2de5-b663-427b-bc34-06f3f638c3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475548012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.475548012
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2092680607
Short name T666
Test name
Test status
Simulation time 1672892827 ps
CPU time 5.12 seconds
Started Jul 12 06:24:24 PM PDT 24
Finished Jul 12 06:24:30 PM PDT 24
Peak memory 225464 kb
Host smart-7aad7967-2b06-42c9-be10-9a7bcd6ed52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092680607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2092680607
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1534874862
Short name T384
Test name
Test status
Simulation time 4446939501 ps
CPU time 19.13 seconds
Started Jul 12 06:24:25 PM PDT 24
Finished Jul 12 06:24:45 PM PDT 24
Peak memory 241852 kb
Host smart-1db6c992-c53a-47a7-a0ae-66e20b21f703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534874862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1534874862
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1457484843
Short name T803
Test name
Test status
Simulation time 92183871 ps
CPU time 1.02 seconds
Started Jul 12 06:24:18 PM PDT 24
Finished Jul 12 06:24:20 PM PDT 24
Peak memory 217620 kb
Host smart-50923f41-b578-4cd3-9085-007f3b1ad571
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457484843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1457484843
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1901001834
Short name T932
Test name
Test status
Simulation time 212790769 ps
CPU time 3.61 seconds
Started Jul 12 06:24:27 PM PDT 24
Finished Jul 12 06:24:31 PM PDT 24
Peak memory 233668 kb
Host smart-52acb360-aa7d-486f-bd00-852c08b4fec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901001834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1901001834
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3121098310
Short name T272
Test name
Test status
Simulation time 727338020 ps
CPU time 3.93 seconds
Started Jul 12 06:24:24 PM PDT 24
Finished Jul 12 06:24:29 PM PDT 24
Peak memory 225512 kb
Host smart-e135231e-58fd-4494-9cc5-0d5b7d077acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121098310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3121098310
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2220658428
Short name T668
Test name
Test status
Simulation time 985630371 ps
CPU time 6.93 seconds
Started Jul 12 06:24:26 PM PDT 24
Finished Jul 12 06:24:34 PM PDT 24
Peak memory 223088 kb
Host smart-b6dbe129-2b4d-4916-ac5c-839e5f8dfd34
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2220658428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2220658428
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3015213201
Short name T162
Test name
Test status
Simulation time 3230979461 ps
CPU time 83.92 seconds
Started Jul 12 06:24:27 PM PDT 24
Finished Jul 12 06:25:51 PM PDT 24
Peak memory 252276 kb
Host smart-7b174e38-ff16-492b-b1f2-3fe53e5fb3af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015213201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3015213201
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1730232040
Short name T922
Test name
Test status
Simulation time 4021365936 ps
CPU time 12.81 seconds
Started Jul 12 06:24:19 PM PDT 24
Finished Jul 12 06:24:33 PM PDT 24
Peak memory 220852 kb
Host smart-d2f18a46-4489-475a-bc0e-4e3e26a85459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730232040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1730232040
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1177562010
Short name T654
Test name
Test status
Simulation time 5277375617 ps
CPU time 18.68 seconds
Started Jul 12 06:24:21 PM PDT 24
Finished Jul 12 06:24:40 PM PDT 24
Peak memory 217424 kb
Host smart-5641a661-4ec3-43aa-8585-7fad3f1f08fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177562010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1177562010
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.70814025
Short name T634
Test name
Test status
Simulation time 143138783 ps
CPU time 1.24 seconds
Started Jul 12 06:24:18 PM PDT 24
Finished Jul 12 06:24:20 PM PDT 24
Peak memory 208084 kb
Host smart-de3f165d-d053-4d35-a739-fc53d0ac02f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70814025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.70814025
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1833139740
Short name T901
Test name
Test status
Simulation time 35111731 ps
CPU time 0.78 seconds
Started Jul 12 06:24:19 PM PDT 24
Finished Jul 12 06:24:20 PM PDT 24
Peak memory 206940 kb
Host smart-3b7d93ba-98a7-4f33-8bbf-87a1a94a8b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833139740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1833139740
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.843829622
Short name T400
Test name
Test status
Simulation time 4535666145 ps
CPU time 12.75 seconds
Started Jul 12 06:26:41 PM PDT 24
Finished Jul 12 06:26:55 PM PDT 24
Peak memory 240996 kb
Host smart-16d139eb-3705-4c24-a588-fd2cc44d43e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843829622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.843829622
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3231514949
Short name T953
Test name
Test status
Simulation time 14279599 ps
CPU time 0.73 seconds
Started Jul 12 06:24:38 PM PDT 24
Finished Jul 12 06:24:39 PM PDT 24
Peak memory 205756 kb
Host smart-a9bee8a8-80c2-4404-afb4-4259616d5bee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231514949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3231514949
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3608407296
Short name T742
Test name
Test status
Simulation time 304098278 ps
CPU time 2.84 seconds
Started Jul 12 06:24:34 PM PDT 24
Finished Jul 12 06:24:37 PM PDT 24
Peak memory 225572 kb
Host smart-6b164057-eef9-4910-ae30-2860048d18a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608407296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3608407296
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2779975341
Short name T962
Test name
Test status
Simulation time 60110170 ps
CPU time 0.75 seconds
Started Jul 12 06:24:31 PM PDT 24
Finished Jul 12 06:24:33 PM PDT 24
Peak memory 206436 kb
Host smart-960ba330-ecc1-497e-8756-3cd474589c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779975341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2779975341
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2507372878
Short name T673
Test name
Test status
Simulation time 15783726778 ps
CPU time 97.54 seconds
Started Jul 12 06:24:30 PM PDT 24
Finished Jul 12 06:26:09 PM PDT 24
Peak memory 240660 kb
Host smart-a9ac01af-ef2d-47d3-9335-a2bfb3abae03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507372878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2507372878
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1782037742
Short name T215
Test name
Test status
Simulation time 2957005000 ps
CPU time 66.63 seconds
Started Jul 12 06:24:30 PM PDT 24
Finished Jul 12 06:25:38 PM PDT 24
Peak memory 254196 kb
Host smart-355c4076-a7d5-4919-8cf8-8c1069d6890c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782037742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1782037742
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2150466682
Short name T1029
Test name
Test status
Simulation time 311561683 ps
CPU time 8.91 seconds
Started Jul 12 06:24:34 PM PDT 24
Finished Jul 12 06:24:44 PM PDT 24
Peak memory 233732 kb
Host smart-4b13e114-aa18-483a-80b5-7be2bbaabe8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150466682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2150466682
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2063121729
Short name T873
Test name
Test status
Simulation time 2609455414 ps
CPU time 36.83 seconds
Started Jul 12 06:24:33 PM PDT 24
Finished Jul 12 06:25:11 PM PDT 24
Peak memory 242060 kb
Host smart-837ed770-8b1d-4d75-ab20-66539e0f30c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063121729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2063121729
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.904329486
Short name T994
Test name
Test status
Simulation time 4876093462 ps
CPU time 18 seconds
Started Jul 12 06:24:30 PM PDT 24
Finished Jul 12 06:24:49 PM PDT 24
Peak memory 233864 kb
Host smart-44429dc0-ff13-4bce-a65e-6cf6bcb53a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904329486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.904329486
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3789757106
Short name T414
Test name
Test status
Simulation time 234943993 ps
CPU time 6.04 seconds
Started Jul 12 06:24:30 PM PDT 24
Finished Jul 12 06:24:37 PM PDT 24
Peak memory 233784 kb
Host smart-260447e5-99ef-489c-bf4d-5dce3e13e3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789757106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3789757106
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2039666043
Short name T549
Test name
Test status
Simulation time 58212042 ps
CPU time 1.06 seconds
Started Jul 12 06:24:28 PM PDT 24
Finished Jul 12 06:24:30 PM PDT 24
Peak memory 218920 kb
Host smart-a7c3e0bd-bbd6-47c5-b27c-d28a1933463b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039666043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2039666043
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1876535132
Short name T635
Test name
Test status
Simulation time 140796536 ps
CPU time 2.19 seconds
Started Jul 12 06:24:31 PM PDT 24
Finished Jul 12 06:24:34 PM PDT 24
Peak memory 225264 kb
Host smart-9ef6a022-ebde-476e-97b2-243d3dd1a19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876535132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1876535132
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.4093858072
Short name T508
Test name
Test status
Simulation time 9534237829 ps
CPU time 28.09 seconds
Started Jul 12 06:24:31 PM PDT 24
Finished Jul 12 06:25:00 PM PDT 24
Peak memory 241548 kb
Host smart-d0112c10-a586-4385-ae7d-152822350077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093858072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.4093858072
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4077306305
Short name T465
Test name
Test status
Simulation time 150861898 ps
CPU time 3.6 seconds
Started Jul 12 06:24:29 PM PDT 24
Finished Jul 12 06:24:34 PM PDT 24
Peak memory 221388 kb
Host smart-c74806e6-4365-436e-931c-d131b36b5236
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4077306305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4077306305
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3720849416
Short name T443
Test name
Test status
Simulation time 24093305300 ps
CPU time 30.25 seconds
Started Jul 12 06:24:29 PM PDT 24
Finished Jul 12 06:25:00 PM PDT 24
Peak memory 217512 kb
Host smart-cf99c66b-2362-41e5-8d4a-23cc59ddccdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720849416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3720849416
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3276321326
Short name T577
Test name
Test status
Simulation time 266729477 ps
CPU time 1.04 seconds
Started Jul 12 06:24:30 PM PDT 24
Finished Jul 12 06:24:32 PM PDT 24
Peak memory 208044 kb
Host smart-2b952a9a-ef9b-499a-bad1-5500baab858b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276321326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3276321326
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1121827416
Short name T639
Test name
Test status
Simulation time 437070651 ps
CPU time 2.1 seconds
Started Jul 12 06:24:33 PM PDT 24
Finished Jul 12 06:24:36 PM PDT 24
Peak memory 217296 kb
Host smart-a00fee16-bc54-48f1-a252-a6a9d0d15e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121827416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1121827416
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3667352699
Short name T480
Test name
Test status
Simulation time 118847001 ps
CPU time 0.77 seconds
Started Jul 12 06:24:29 PM PDT 24
Finished Jul 12 06:24:31 PM PDT 24
Peak memory 206940 kb
Host smart-fe5124ed-ad2e-47db-a5cf-76c68eef8f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667352699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3667352699
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.695036083
Short name T1031
Test name
Test status
Simulation time 33675831 ps
CPU time 2.13 seconds
Started Jul 12 06:24:33 PM PDT 24
Finished Jul 12 06:24:35 PM PDT 24
Peak memory 225540 kb
Host smart-e912f745-f0f4-4356-8391-7add3b53f839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695036083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.695036083
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2057076856
Short name T351
Test name
Test status
Simulation time 26034323 ps
CPU time 0.74 seconds
Started Jul 12 06:24:55 PM PDT 24
Finished Jul 12 06:24:56 PM PDT 24
Peak memory 205748 kb
Host smart-7327f49f-5370-4f16-876e-c82cd9c22227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057076856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2057076856
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.541402815
Short name T1001
Test name
Test status
Simulation time 323288127 ps
CPU time 3.06 seconds
Started Jul 12 06:24:45 PM PDT 24
Finished Jul 12 06:24:49 PM PDT 24
Peak memory 225604 kb
Host smart-7962eb91-0b26-422a-80ca-321482fcd603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541402815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.541402815
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.320460309
Short name T431
Test name
Test status
Simulation time 55137186 ps
CPU time 0.81 seconds
Started Jul 12 06:24:36 PM PDT 24
Finished Jul 12 06:24:38 PM PDT 24
Peak memory 207752 kb
Host smart-c250554d-f710-4ef7-9990-c2fe49ac30ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320460309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.320460309
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1644979316
Short name T270
Test name
Test status
Simulation time 28793366665 ps
CPU time 194.07 seconds
Started Jul 12 06:24:43 PM PDT 24
Finished Jul 12 06:27:59 PM PDT 24
Peak memory 250372 kb
Host smart-5d19d341-d463-48f2-814c-8defd3174d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644979316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1644979316
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.599211361
Short name T284
Test name
Test status
Simulation time 106615295690 ps
CPU time 861.15 seconds
Started Jul 12 06:24:43 PM PDT 24
Finished Jul 12 06:39:05 PM PDT 24
Peak memory 268968 kb
Host smart-a0df7276-1a64-4e95-b47a-5bd8a3970ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599211361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.599211361
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2608788985
Short name T625
Test name
Test status
Simulation time 14410350166 ps
CPU time 45.42 seconds
Started Jul 12 06:24:56 PM PDT 24
Finished Jul 12 06:25:43 PM PDT 24
Peak memory 242136 kb
Host smart-f81f8717-4d2a-45b9-bac8-78c833ef0469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608788985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2608788985
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.525696036
Short name T308
Test name
Test status
Simulation time 677157467 ps
CPU time 6.45 seconds
Started Jul 12 06:24:43 PM PDT 24
Finished Jul 12 06:24:51 PM PDT 24
Peak memory 225560 kb
Host smart-2cd35d9c-6c0c-4343-869b-cf5c1d480ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525696036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.525696036
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3613688068
Short name T662
Test name
Test status
Simulation time 28294200398 ps
CPU time 146.85 seconds
Started Jul 12 06:24:43 PM PDT 24
Finished Jul 12 06:27:12 PM PDT 24
Peak memory 250508 kb
Host smart-28e16352-f3a9-47cb-ac1c-949d0b91f814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613688068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3613688068
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3620347658
Short name T954
Test name
Test status
Simulation time 419685052 ps
CPU time 6.81 seconds
Started Jul 12 06:24:41 PM PDT 24
Finished Jul 12 06:24:48 PM PDT 24
Peak memory 233752 kb
Host smart-6d8b57df-c090-49de-b9c5-c8d58087ebe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620347658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3620347658
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.149529737
Short name T940
Test name
Test status
Simulation time 8522898144 ps
CPU time 118.32 seconds
Started Jul 12 06:24:43 PM PDT 24
Finished Jul 12 06:26:43 PM PDT 24
Peak memory 225728 kb
Host smart-627884df-9a81-4053-b6b5-f104270f7380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149529737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.149529737
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2353276744
Short name T795
Test name
Test status
Simulation time 108956186 ps
CPU time 1.12 seconds
Started Jul 12 06:24:36 PM PDT 24
Finished Jul 12 06:24:37 PM PDT 24
Peak memory 217632 kb
Host smart-5c9df255-f022-4223-b3fd-1af7af641b39
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353276744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2353276744
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2378171066
Short name T565
Test name
Test status
Simulation time 5615689449 ps
CPU time 6.78 seconds
Started Jul 12 06:24:37 PM PDT 24
Finished Jul 12 06:24:44 PM PDT 24
Peak memory 225652 kb
Host smart-816048ac-6a3b-4ecc-b8af-2c1c23065c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378171066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2378171066
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3650515221
Short name T216
Test name
Test status
Simulation time 2149870621 ps
CPU time 5.29 seconds
Started Jul 12 06:24:38 PM PDT 24
Finished Jul 12 06:24:44 PM PDT 24
Peak memory 225684 kb
Host smart-7cf7e47b-8415-4d72-b86d-4f7ec44969e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650515221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3650515221
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2081710741
Short name T416
Test name
Test status
Simulation time 1093437827 ps
CPU time 5.62 seconds
Started Jul 12 06:24:42 PM PDT 24
Finished Jul 12 06:24:49 PM PDT 24
Peak memory 223960 kb
Host smart-e43186d2-4149-43ac-b8e0-9aae2dda3265
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2081710741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2081710741
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2003375671
Short name T491
Test name
Test status
Simulation time 6907066390 ps
CPU time 27.03 seconds
Started Jul 12 06:24:35 PM PDT 24
Finished Jul 12 06:25:02 PM PDT 24
Peak memory 217508 kb
Host smart-3d26a654-9f14-41b0-86c2-7b505419c636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003375671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2003375671
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2676006990
Short name T822
Test name
Test status
Simulation time 22326831696 ps
CPU time 12.53 seconds
Started Jul 12 06:24:39 PM PDT 24
Finished Jul 12 06:24:51 PM PDT 24
Peak memory 217464 kb
Host smart-ac8278b1-7a2e-4728-9b5d-8720c3b8f451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676006990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2676006990
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1027607386
Short name T499
Test name
Test status
Simulation time 74353770 ps
CPU time 4.13 seconds
Started Jul 12 06:24:34 PM PDT 24
Finished Jul 12 06:24:39 PM PDT 24
Peak memory 217352 kb
Host smart-39d99dea-8dba-4ee2-a652-f6dd6d017502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027607386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1027607386
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1583356776
Short name T561
Test name
Test status
Simulation time 24824997 ps
CPU time 0.78 seconds
Started Jul 12 06:24:36 PM PDT 24
Finished Jul 12 06:24:37 PM PDT 24
Peak memory 206956 kb
Host smart-2da39267-1fb2-4a8f-9563-0e88037f96c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583356776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1583356776
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.725517473
Short name T596
Test name
Test status
Simulation time 29904862222 ps
CPU time 26.81 seconds
Started Jul 12 06:24:44 PM PDT 24
Finished Jul 12 06:25:12 PM PDT 24
Peak memory 233924 kb
Host smart-6822a372-211d-40d6-9e4f-0062c81c0ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725517473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.725517473
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1504050375
Short name T562
Test name
Test status
Simulation time 40209839 ps
CPU time 0.74 seconds
Started Jul 12 06:24:55 PM PDT 24
Finished Jul 12 06:24:58 PM PDT 24
Peak memory 206320 kb
Host smart-760c0307-f427-4420-bb2a-d6913d3b0bb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504050375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1504050375
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3891040095
Short name T60
Test name
Test status
Simulation time 2448208113 ps
CPU time 11.4 seconds
Started Jul 12 06:24:48 PM PDT 24
Finished Jul 12 06:25:00 PM PDT 24
Peak memory 233904 kb
Host smart-49c2b2bf-a9c7-4705-99b8-0c99776a0e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891040095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3891040095
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.192468099
Short name T592
Test name
Test status
Simulation time 33092519 ps
CPU time 0.77 seconds
Started Jul 12 06:24:46 PM PDT 24
Finished Jul 12 06:24:48 PM PDT 24
Peak memory 207500 kb
Host smart-132058a0-ccfa-4c94-8bc4-872f1cbe2b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192468099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.192468099
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2903630319
Short name T657
Test name
Test status
Simulation time 9008425598 ps
CPU time 62.31 seconds
Started Jul 12 06:25:03 PM PDT 24
Finished Jul 12 06:26:06 PM PDT 24
Peak memory 258420 kb
Host smart-d50c08b3-01ee-413e-948f-a857d34fb959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903630319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2903630319
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.692808808
Short name T800
Test name
Test status
Simulation time 15164682404 ps
CPU time 63.94 seconds
Started Jul 12 06:24:55 PM PDT 24
Finished Jul 12 06:26:01 PM PDT 24
Peak memory 250368 kb
Host smart-3efe498e-c855-492f-8ea9-12bc4cb86b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692808808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.692808808
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3062073272
Short name T238
Test name
Test status
Simulation time 5796308397 ps
CPU time 25.3 seconds
Started Jul 12 06:24:51 PM PDT 24
Finished Jul 12 06:25:17 PM PDT 24
Peak memory 242084 kb
Host smart-a694adcd-989c-40d4-8326-5755001f2d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062073272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3062073272
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.4273274007
Short name T205
Test name
Test status
Simulation time 3459545624 ps
CPU time 62.3 seconds
Started Jul 12 06:24:55 PM PDT 24
Finished Jul 12 06:25:59 PM PDT 24
Peak memory 250228 kb
Host smart-7c69762e-d20d-451e-a9fa-520d5d2f2542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273274007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.4273274007
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.914514082
Short name T548
Test name
Test status
Simulation time 8030141203 ps
CPU time 16.94 seconds
Started Jul 12 06:24:56 PM PDT 24
Finished Jul 12 06:25:14 PM PDT 24
Peak memory 225668 kb
Host smart-9ac95409-59c5-4283-8f69-533115108772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914514082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.914514082
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1634028371
Short name T895
Test name
Test status
Simulation time 926159669 ps
CPU time 6.28 seconds
Started Jul 12 06:24:48 PM PDT 24
Finished Jul 12 06:24:55 PM PDT 24
Peak memory 240440 kb
Host smart-bf19f98b-c2f3-4ba7-aeb5-7b25b12f033a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634028371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1634028371
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1119940955
Short name T773
Test name
Test status
Simulation time 110713842 ps
CPU time 1.02 seconds
Started Jul 12 06:24:55 PM PDT 24
Finished Jul 12 06:24:57 PM PDT 24
Peak memory 218944 kb
Host smart-8a2104da-1eae-4f3b-bc0d-8a16b5a90e02
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119940955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1119940955
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2081261064
Short name T759
Test name
Test status
Simulation time 189404979 ps
CPU time 2.48 seconds
Started Jul 12 06:24:48 PM PDT 24
Finished Jul 12 06:24:52 PM PDT 24
Peak memory 225504 kb
Host smart-3042aa3c-9cc8-4a2b-a30b-7f7774527e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081261064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2081261064
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.766833464
Short name T243
Test name
Test status
Simulation time 652176560 ps
CPU time 6.18 seconds
Started Jul 12 06:24:49 PM PDT 24
Finished Jul 12 06:24:56 PM PDT 24
Peak memory 225556 kb
Host smart-f02f049e-3f07-47d3-9b20-e4faddc9d54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766833464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.766833464
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1389583386
Short name T464
Test name
Test status
Simulation time 235384097 ps
CPU time 6.06 seconds
Started Jul 12 06:25:02 PM PDT 24
Finished Jul 12 06:25:09 PM PDT 24
Peak memory 219816 kb
Host smart-d9112128-3451-4e5a-8c69-a6d83e86b824
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1389583386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1389583386
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.649317928
Short name T22
Test name
Test status
Simulation time 12049762081 ps
CPU time 147.5 seconds
Started Jul 12 06:25:02 PM PDT 24
Finished Jul 12 06:27:30 PM PDT 24
Peak memory 266208 kb
Host smart-6803fecd-1b78-40d3-a13d-0640b5c43c81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649317928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.649317928
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3382070855
Short name T171
Test name
Test status
Simulation time 43507230 ps
CPU time 0.71 seconds
Started Jul 12 06:24:56 PM PDT 24
Finished Jul 12 06:24:58 PM PDT 24
Peak memory 206640 kb
Host smart-f7198a3c-33a8-4342-b0a8-c96cf5809221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382070855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3382070855
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.889687030
Short name T373
Test name
Test status
Simulation time 774753039 ps
CPU time 3.68 seconds
Started Jul 12 06:24:55 PM PDT 24
Finished Jul 12 06:25:00 PM PDT 24
Peak memory 217328 kb
Host smart-32fb7c0b-a39e-48da-aa13-689937152b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889687030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.889687030
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.62324489
Short name T724
Test name
Test status
Simulation time 1154339537 ps
CPU time 2.06 seconds
Started Jul 12 06:24:48 PM PDT 24
Finished Jul 12 06:24:51 PM PDT 24
Peak memory 217360 kb
Host smart-4d76ef33-0de5-48bd-b360-72dcfa9d4f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62324489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.62324489
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.90792278
Short name T885
Test name
Test status
Simulation time 36547663 ps
CPU time 0.77 seconds
Started Jul 12 06:24:48 PM PDT 24
Finished Jul 12 06:24:50 PM PDT 24
Peak memory 206920 kb
Host smart-8127476e-ba66-4185-b272-da03d73ac2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90792278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.90792278
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3473001707
Short name T603
Test name
Test status
Simulation time 85968467 ps
CPU time 2.67 seconds
Started Jul 12 06:24:51 PM PDT 24
Finished Jul 12 06:24:54 PM PDT 24
Peak memory 233780 kb
Host smart-d8bc00a8-0567-4028-92f3-905c58af85e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473001707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3473001707
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2911535626
Short name T324
Test name
Test status
Simulation time 21564273 ps
CPU time 0.76 seconds
Started Jul 12 06:25:12 PM PDT 24
Finished Jul 12 06:25:14 PM PDT 24
Peak memory 206840 kb
Host smart-6030b510-cf34-4566-88ec-16257a991e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911535626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2911535626
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3637476411
Short name T685
Test name
Test status
Simulation time 35748816 ps
CPU time 2.39 seconds
Started Jul 12 06:25:03 PM PDT 24
Finished Jul 12 06:25:06 PM PDT 24
Peak memory 233704 kb
Host smart-e9e801a4-e682-4aa4-8f33-8a569bed8fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637476411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3637476411
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.508681543
Short name T772
Test name
Test status
Simulation time 56932826 ps
CPU time 0.79 seconds
Started Jul 12 06:24:57 PM PDT 24
Finished Jul 12 06:24:59 PM PDT 24
Peak memory 207812 kb
Host smart-94a63ce9-bf9b-457a-a6b0-741f715f529d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508681543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.508681543
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.354079203
Short name T394
Test name
Test status
Simulation time 69189726 ps
CPU time 0.76 seconds
Started Jul 12 06:25:02 PM PDT 24
Finished Jul 12 06:25:04 PM PDT 24
Peak memory 216896 kb
Host smart-58ea906f-676f-4b6f-bae6-ba452d6ba3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354079203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.354079203
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2335341473
Short name T651
Test name
Test status
Simulation time 57328565151 ps
CPU time 308.11 seconds
Started Jul 12 06:25:07 PM PDT 24
Finished Jul 12 06:30:16 PM PDT 24
Peak memory 250356 kb
Host smart-4dc8ca22-cf22-446c-9dcc-e587e58421a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335341473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2335341473
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2624249600
Short name T678
Test name
Test status
Simulation time 2704472636 ps
CPU time 35.36 seconds
Started Jul 12 06:25:11 PM PDT 24
Finished Jul 12 06:25:48 PM PDT 24
Peak memory 250284 kb
Host smart-c0397281-5587-4719-9178-76edca2fa975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624249600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2624249600
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.4212996050
Short name T619
Test name
Test status
Simulation time 18993491491 ps
CPU time 63.21 seconds
Started Jul 12 06:25:03 PM PDT 24
Finished Jul 12 06:26:07 PM PDT 24
Peak memory 233760 kb
Host smart-03927eb2-3962-4955-b9b7-297c5b3302b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212996050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.4212996050
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1880907091
Short name T418
Test name
Test status
Simulation time 7049598774 ps
CPU time 46.57 seconds
Started Jul 12 06:25:04 PM PDT 24
Finished Jul 12 06:25:51 PM PDT 24
Peak memory 252788 kb
Host smart-422542db-5a62-487d-b4cb-399194a16848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880907091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1880907091
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1928451483
Short name T248
Test name
Test status
Simulation time 857711366 ps
CPU time 6.08 seconds
Started Jul 12 06:25:03 PM PDT 24
Finished Jul 12 06:25:10 PM PDT 24
Peak memory 233772 kb
Host smart-21adae6b-c452-47d4-a143-dd3e3c29d1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928451483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1928451483
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.329139636
Short name T471
Test name
Test status
Simulation time 2257072614 ps
CPU time 18.74 seconds
Started Jul 12 06:25:02 PM PDT 24
Finished Jul 12 06:25:22 PM PDT 24
Peak memory 233872 kb
Host smart-d19bdc11-0ac0-4a5b-b89f-e2411fbee42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329139636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.329139636
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.535575
Short name T965
Test name
Test status
Simulation time 34789695 ps
CPU time 1.11 seconds
Started Jul 12 06:24:56 PM PDT 24
Finished Jul 12 06:24:59 PM PDT 24
Peak memory 217584 kb
Host smart-7b79a20c-a328-4088-8db0-ca98e3f94c14
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_
SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.spi_device_mem_parity.535575
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.73613070
Short name T806
Test name
Test status
Simulation time 429806533 ps
CPU time 3.95 seconds
Started Jul 12 06:25:04 PM PDT 24
Finished Jul 12 06:25:08 PM PDT 24
Peak memory 225508 kb
Host smart-2723f136-273a-477c-863d-1cf75453a08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73613070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.73613070
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1341650560
Short name T572
Test name
Test status
Simulation time 4483719961 ps
CPU time 12.33 seconds
Started Jul 12 06:25:02 PM PDT 24
Finished Jul 12 06:25:16 PM PDT 24
Peak memory 238212 kb
Host smart-cf105e91-1d00-4886-8e32-1520fe75b709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341650560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1341650560
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2426512622
Short name T520
Test name
Test status
Simulation time 376384126 ps
CPU time 3.76 seconds
Started Jul 12 06:25:03 PM PDT 24
Finished Jul 12 06:25:08 PM PDT 24
Peak memory 220424 kb
Host smart-24142f19-2a15-4274-ab54-1dd9c580b5f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2426512622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2426512622
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1495201003
Short name T312
Test name
Test status
Simulation time 11843673285 ps
CPU time 28.66 seconds
Started Jul 12 06:24:57 PM PDT 24
Finished Jul 12 06:25:27 PM PDT 24
Peak memory 217748 kb
Host smart-5cd519b9-c8fb-4280-91af-3d6b6d9501e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495201003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1495201003
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3099254164
Short name T390
Test name
Test status
Simulation time 1336481493 ps
CPU time 5.43 seconds
Started Jul 12 06:24:57 PM PDT 24
Finished Jul 12 06:25:04 PM PDT 24
Peak memory 217372 kb
Host smart-f68ee8a4-ac64-4baf-99a6-3dda8e123637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099254164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3099254164
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2855135633
Short name T533
Test name
Test status
Simulation time 178193637 ps
CPU time 1.2 seconds
Started Jul 12 06:25:03 PM PDT 24
Finished Jul 12 06:25:05 PM PDT 24
Peak memory 208932 kb
Host smart-fdd57d36-edac-4e8b-a543-edd3840b7702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855135633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2855135633
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.462331687
Short name T936
Test name
Test status
Simulation time 12065580 ps
CPU time 0.71 seconds
Started Jul 12 06:25:30 PM PDT 24
Finished Jul 12 06:25:31 PM PDT 24
Peak memory 206896 kb
Host smart-61826b94-1b49-4012-b114-c548a8a2bcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462331687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.462331687
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.502085602
Short name T487
Test name
Test status
Simulation time 2026553389 ps
CPU time 8.4 seconds
Started Jul 12 06:25:01 PM PDT 24
Finished Jul 12 06:25:10 PM PDT 24
Peak memory 225520 kb
Host smart-00fa9752-1f05-4407-bed0-cade5c90a8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502085602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.502085602
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1304030008
Short name T680
Test name
Test status
Simulation time 142875072 ps
CPU time 0.71 seconds
Started Jul 12 06:25:18 PM PDT 24
Finished Jul 12 06:25:20 PM PDT 24
Peak memory 206336 kb
Host smart-28bb0c92-57e4-4fd2-a2b0-953e77a9e843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304030008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1304030008
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2331133675
Short name T702
Test name
Test status
Simulation time 33363055 ps
CPU time 2.51 seconds
Started Jul 12 06:25:17 PM PDT 24
Finished Jul 12 06:25:21 PM PDT 24
Peak memory 233432 kb
Host smart-58467a62-f04b-4f23-aa53-803222a4233f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331133675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2331133675
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.105825032
Short name T458
Test name
Test status
Simulation time 47427281 ps
CPU time 0.78 seconds
Started Jul 12 06:25:10 PM PDT 24
Finished Jul 12 06:25:12 PM PDT 24
Peak memory 207460 kb
Host smart-881c5597-5aed-43e8-99fe-8164d8f56c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105825032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.105825032
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.848322621
Short name T923
Test name
Test status
Simulation time 29194596651 ps
CPU time 218.66 seconds
Started Jul 12 06:25:18 PM PDT 24
Finished Jul 12 06:28:58 PM PDT 24
Peak memory 255680 kb
Host smart-df4c115c-e7a8-4d07-ad5e-bf328fc84ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848322621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.848322621
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1478337896
Short name T857
Test name
Test status
Simulation time 30647456394 ps
CPU time 90.77 seconds
Started Jul 12 06:25:15 PM PDT 24
Finished Jul 12 06:26:49 PM PDT 24
Peak memory 252280 kb
Host smart-14260090-2570-4176-ac17-5414edf49610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478337896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1478337896
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.614366022
Short name T861
Test name
Test status
Simulation time 44881249245 ps
CPU time 166.79 seconds
Started Jul 12 06:25:17 PM PDT 24
Finished Jul 12 06:28:06 PM PDT 24
Peak memory 252356 kb
Host smart-fd073007-d75b-46d3-9ee9-f4440057c8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614366022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.614366022
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3107278233
Short name T566
Test name
Test status
Simulation time 470151673 ps
CPU time 7.49 seconds
Started Jul 12 06:25:10 PM PDT 24
Finished Jul 12 06:25:18 PM PDT 24
Peak memory 233720 kb
Host smart-efd04d7a-61a1-4f54-92e3-7c13da6986bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107278233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3107278233
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.349205751
Short name T266
Test name
Test status
Simulation time 14885100834 ps
CPU time 65.05 seconds
Started Jul 12 06:25:13 PM PDT 24
Finished Jul 12 06:26:18 PM PDT 24
Peak memory 238528 kb
Host smart-7061839a-97ba-42de-9016-b418354d12f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349205751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.349205751
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2914472554
Short name T467
Test name
Test status
Simulation time 310791848 ps
CPU time 1.12 seconds
Started Jul 12 06:25:09 PM PDT 24
Finished Jul 12 06:25:11 PM PDT 24
Peak memory 217632 kb
Host smart-6dde714d-1bcd-4b06-b3cb-e0384b266565
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914472554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2914472554
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3280291488
Short name T544
Test name
Test status
Simulation time 683900240 ps
CPU time 4.27 seconds
Started Jul 12 06:25:10 PM PDT 24
Finished Jul 12 06:25:15 PM PDT 24
Peak memory 225572 kb
Host smart-9205a6d0-3d6c-42a4-bc14-1e6daf7779de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280291488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3280291488
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2568815825
Short name T451
Test name
Test status
Simulation time 896044906 ps
CPU time 6.23 seconds
Started Jul 12 06:25:09 PM PDT 24
Finished Jul 12 06:25:16 PM PDT 24
Peak memory 225580 kb
Host smart-7070465c-8975-4fb4-af5b-b5f8d96c5e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568815825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2568815825
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3455053651
Short name T727
Test name
Test status
Simulation time 1349146888 ps
CPU time 15.83 seconds
Started Jul 12 06:25:16 PM PDT 24
Finished Jul 12 06:25:34 PM PDT 24
Peak memory 220708 kb
Host smart-5c933f27-bbb9-4056-a53c-f71baa4074e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3455053651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3455053651
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2999994642
Short name T142
Test name
Test status
Simulation time 17747872148 ps
CPU time 96.84 seconds
Started Jul 12 06:25:20 PM PDT 24
Finished Jul 12 06:26:58 PM PDT 24
Peak memory 254572 kb
Host smart-e8a9d59f-1abb-41d9-9983-f1a9511c50d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999994642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2999994642
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3134833826
Short name T559
Test name
Test status
Simulation time 12832200603 ps
CPU time 25.1 seconds
Started Jul 12 06:25:08 PM PDT 24
Finished Jul 12 06:25:33 PM PDT 24
Peak memory 217712 kb
Host smart-c3e0c88a-5e7f-4e1d-99c2-e9dcf4994f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134833826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3134833826
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.4284889540
Short name T692
Test name
Test status
Simulation time 4478325865 ps
CPU time 13.33 seconds
Started Jul 12 06:25:09 PM PDT 24
Finished Jul 12 06:25:24 PM PDT 24
Peak memory 217472 kb
Host smart-1c4a035f-b224-4d93-b0c3-a9a4f6f65630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284889540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4284889540
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3639886613
Short name T931
Test name
Test status
Simulation time 62271897 ps
CPU time 0.73 seconds
Started Jul 12 06:25:07 PM PDT 24
Finished Jul 12 06:25:09 PM PDT 24
Peak memory 206936 kb
Host smart-df97ce76-b90a-48e5-b363-c063fd9dfc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639886613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3639886613
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2615244071
Short name T713
Test name
Test status
Simulation time 139292310 ps
CPU time 1.12 seconds
Started Jul 12 06:25:13 PM PDT 24
Finished Jul 12 06:25:15 PM PDT 24
Peak memory 207944 kb
Host smart-0cdd26fc-ef9a-4eab-882e-d83ceabc8873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615244071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2615244071
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2240335777
Short name T187
Test name
Test status
Simulation time 1192352017 ps
CPU time 5.71 seconds
Started Jul 12 06:25:10 PM PDT 24
Finished Jul 12 06:25:16 PM PDT 24
Peak memory 225528 kb
Host smart-aa61569c-8e65-42dc-b75e-2a74f3073a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240335777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2240335777
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2160301006
Short name T972
Test name
Test status
Simulation time 20930317 ps
CPU time 0.74 seconds
Started Jul 12 06:25:31 PM PDT 24
Finished Jul 12 06:25:33 PM PDT 24
Peak memory 206380 kb
Host smart-6f3a3c9f-3a76-4bc5-a0c4-afced78f47f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160301006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2160301006
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.230704970
Short name T439
Test name
Test status
Simulation time 69425494 ps
CPU time 2.65 seconds
Started Jul 12 06:25:24 PM PDT 24
Finished Jul 12 06:25:27 PM PDT 24
Peak memory 233660 kb
Host smart-3b4d0568-c5e7-4027-82db-b77df7195d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230704970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.230704970
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.4288539711
Short name T381
Test name
Test status
Simulation time 115527215 ps
CPU time 0.71 seconds
Started Jul 12 06:25:15 PM PDT 24
Finished Jul 12 06:25:17 PM PDT 24
Peak memory 206464 kb
Host smart-05b047c2-080d-42a1-882a-161877d20abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288539711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4288539711
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.284340510
Short name T686
Test name
Test status
Simulation time 3783349483 ps
CPU time 79.66 seconds
Started Jul 12 06:25:30 PM PDT 24
Finished Jul 12 06:26:51 PM PDT 24
Peak memory 258572 kb
Host smart-62d53806-dd4f-41a5-be0c-0c38ecf973cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284340510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.284340510
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.599199097
Short name T757
Test name
Test status
Simulation time 7412326924 ps
CPU time 39.77 seconds
Started Jul 12 06:25:29 PM PDT 24
Finished Jul 12 06:26:09 PM PDT 24
Peak memory 225732 kb
Host smart-6a91f725-a414-4dd6-885b-7fc237a9bdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599199097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.599199097
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.4267141705
Short name T411
Test name
Test status
Simulation time 1287730568 ps
CPU time 4.98 seconds
Started Jul 12 06:25:22 PM PDT 24
Finished Jul 12 06:25:28 PM PDT 24
Peak memory 225544 kb
Host smart-eb2fb052-5bc7-470e-ad9a-a76ac907be7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267141705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4267141705
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1933330446
Short name T1014
Test name
Test status
Simulation time 14575033518 ps
CPU time 48.51 seconds
Started Jul 12 06:25:25 PM PDT 24
Finished Jul 12 06:26:15 PM PDT 24
Peak memory 267228 kb
Host smart-1598da52-8d28-46b8-ba91-78e4c1f75181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933330446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1933330446
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1159244550
Short name T222
Test name
Test status
Simulation time 924090752 ps
CPU time 8.57 seconds
Started Jul 12 06:25:24 PM PDT 24
Finished Jul 12 06:25:34 PM PDT 24
Peak memory 225520 kb
Host smart-b983fa2e-38c2-44fc-8e7a-74dba3fa1630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159244550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1159244550
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3759113633
Short name T212
Test name
Test status
Simulation time 349882641 ps
CPU time 8.16 seconds
Started Jul 12 06:25:23 PM PDT 24
Finished Jul 12 06:25:32 PM PDT 24
Peak memory 234820 kb
Host smart-f68adedd-80bb-4224-a795-cb1b47db136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759113633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3759113633
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3507152467
Short name T38
Test name
Test status
Simulation time 109110054 ps
CPU time 1.09 seconds
Started Jul 12 06:25:14 PM PDT 24
Finished Jul 12 06:25:17 PM PDT 24
Peak memory 217632 kb
Host smart-36d561ac-48f3-4b38-bc3a-c63c446f1f64
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507152467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3507152467
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3927981789
Short name T339
Test name
Test status
Simulation time 114278755 ps
CPU time 2.57 seconds
Started Jul 12 06:25:14 PM PDT 24
Finished Jul 12 06:25:18 PM PDT 24
Peak memory 224908 kb
Host smart-31e4362b-db2a-4871-91ed-b04892d4964e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927981789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3927981789
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.4234420054
Short name T8
Test name
Test status
Simulation time 1766207479 ps
CPU time 9.79 seconds
Started Jul 12 06:25:15 PM PDT 24
Finished Jul 12 06:25:27 PM PDT 24
Peak memory 225572 kb
Host smart-ae8f9f88-a10a-4e22-93d6-9c04351d8acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234420054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.4234420054
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1658406472
Short name T1011
Test name
Test status
Simulation time 328024801 ps
CPU time 3.75 seconds
Started Jul 12 06:25:24 PM PDT 24
Finished Jul 12 06:25:28 PM PDT 24
Peak memory 223904 kb
Host smart-2be0e2f5-27c0-4c66-adf2-7c5efb5767b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1658406472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1658406472
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.702306308
Short name T876
Test name
Test status
Simulation time 60949803468 ps
CPU time 136.67 seconds
Started Jul 12 06:25:30 PM PDT 24
Finished Jul 12 06:27:48 PM PDT 24
Peak memory 256416 kb
Host smart-8b536ffd-5475-41a6-8042-7db11b56a373
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702306308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.702306308
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.256803401
Short name T754
Test name
Test status
Simulation time 6236515592 ps
CPU time 38.97 seconds
Started Jul 12 06:25:18 PM PDT 24
Finished Jul 12 06:25:59 PM PDT 24
Peak memory 217512 kb
Host smart-6c45bfd5-660a-449b-8984-7d63073804f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256803401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.256803401
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2721568251
Short name T485
Test name
Test status
Simulation time 118279281 ps
CPU time 1.21 seconds
Started Jul 12 06:25:21 PM PDT 24
Finished Jul 12 06:25:23 PM PDT 24
Peak memory 208800 kb
Host smart-032dad3b-1e4f-45f1-ac35-2265cdf83ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721568251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2721568251
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3812443406
Short name T437
Test name
Test status
Simulation time 99117649 ps
CPU time 1.69 seconds
Started Jul 12 06:25:17 PM PDT 24
Finished Jul 12 06:25:21 PM PDT 24
Peak memory 217300 kb
Host smart-d7471c2b-3d8f-4f06-9808-dc8867cf1821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812443406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3812443406
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.919238088
Short name T775
Test name
Test status
Simulation time 53419630 ps
CPU time 0.91 seconds
Started Jul 12 06:25:20 PM PDT 24
Finished Jul 12 06:25:22 PM PDT 24
Peak memory 206828 kb
Host smart-a3658d1c-e953-4487-895b-526aac2fccb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919238088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.919238088
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1958005435
Short name T276
Test name
Test status
Simulation time 761265814 ps
CPU time 8.44 seconds
Started Jul 12 06:25:25 PM PDT 24
Finished Jul 12 06:25:35 PM PDT 24
Peak memory 233664 kb
Host smart-598cfe7e-097c-4fc5-8877-2af75d0a56b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958005435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1958005435
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2300403624
Short name T626
Test name
Test status
Simulation time 42173955 ps
CPU time 0.72 seconds
Started Jul 12 06:22:21 PM PDT 24
Finished Jul 12 06:22:22 PM PDT 24
Peak memory 206268 kb
Host smart-b6c1ec78-7803-4cf0-a06b-89bc1c9e58df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300403624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
300403624
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.4150980755
Short name T808
Test name
Test status
Simulation time 32599107 ps
CPU time 2.65 seconds
Started Jul 12 06:22:14 PM PDT 24
Finished Jul 12 06:22:18 PM PDT 24
Peak memory 233512 kb
Host smart-d80cede5-c7b8-4f5b-b822-3c822333f743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150980755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.4150980755
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2732378479
Short name T653
Test name
Test status
Simulation time 109284776 ps
CPU time 0.75 seconds
Started Jul 12 06:22:03 PM PDT 24
Finished Jul 12 06:22:05 PM PDT 24
Peak memory 206468 kb
Host smart-5b96d1ed-9989-4eaa-941e-cb8ee28d439a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732378479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2732378479
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2532651506
Short name T301
Test name
Test status
Simulation time 28460339642 ps
CPU time 52.95 seconds
Started Jul 12 06:22:14 PM PDT 24
Finished Jul 12 06:23:08 PM PDT 24
Peak memory 248684 kb
Host smart-6acbc769-382e-4838-bf73-29e05e23fce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532651506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2532651506
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3846674406
Short name T211
Test name
Test status
Simulation time 9771414371 ps
CPU time 83.13 seconds
Started Jul 12 06:22:16 PM PDT 24
Finished Jul 12 06:23:40 PM PDT 24
Peak memory 252444 kb
Host smart-c2de495b-6392-4db2-9ebd-643081ba21e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846674406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3846674406
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1872623608
Short name T892
Test name
Test status
Simulation time 5176722043 ps
CPU time 14.29 seconds
Started Jul 12 06:22:14 PM PDT 24
Finished Jul 12 06:22:29 PM PDT 24
Peak memory 218788 kb
Host smart-79b6bcc9-0fd0-4f2c-beab-207c6bf39a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872623608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1872623608
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3548108679
Short name T758
Test name
Test status
Simulation time 38825112705 ps
CPU time 20.82 seconds
Started Jul 12 06:22:14 PM PDT 24
Finished Jul 12 06:22:36 PM PDT 24
Peak memory 225656 kb
Host smart-eb6ba209-25b0-40b8-9875-dee9b5b69201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548108679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3548108679
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1301244270
Short name T951
Test name
Test status
Simulation time 36654127 ps
CPU time 0.75 seconds
Started Jul 12 06:22:14 PM PDT 24
Finished Jul 12 06:22:15 PM PDT 24
Peak memory 216912 kb
Host smart-f4ee2558-c29b-4266-b4d6-ccace25c95ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301244270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1301244270
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2572229550
Short name T460
Test name
Test status
Simulation time 4331260462 ps
CPU time 8.54 seconds
Started Jul 12 06:22:13 PM PDT 24
Finished Jul 12 06:22:22 PM PDT 24
Peak memory 225660 kb
Host smart-780b88bf-96b4-4005-af71-40e285d4a7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572229550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2572229550
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2705315167
Short name T97
Test name
Test status
Simulation time 11677787757 ps
CPU time 27.14 seconds
Started Jul 12 06:22:14 PM PDT 24
Finished Jul 12 06:22:42 PM PDT 24
Peak memory 233892 kb
Host smart-e959abbd-c148-466b-9bb9-590e4c77f206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705315167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2705315167
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2539431128
Short name T919
Test name
Test status
Simulation time 196820200 ps
CPU time 1.11 seconds
Started Jul 12 06:22:09 PM PDT 24
Finished Jul 12 06:22:10 PM PDT 24
Peak memory 217656 kb
Host smart-6bf2f22c-c8e4-49f6-bbf5-887d72ed90e3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539431128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2539431128
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1109298423
Short name T275
Test name
Test status
Simulation time 356053962 ps
CPU time 3.67 seconds
Started Jul 12 06:22:16 PM PDT 24
Finished Jul 12 06:22:20 PM PDT 24
Peak memory 233688 kb
Host smart-95cf10a1-eecc-4307-8f8f-e82e08fdba40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109298423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1109298423
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.47220749
Short name T532
Test name
Test status
Simulation time 6276971717 ps
CPU time 6.67 seconds
Started Jul 12 06:22:08 PM PDT 24
Finished Jul 12 06:22:15 PM PDT 24
Peak memory 233816 kb
Host smart-a5c34707-445a-43db-9730-7f3a3d92a501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47220749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.47220749
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1005211370
Short name T669
Test name
Test status
Simulation time 29974142986 ps
CPU time 21.43 seconds
Started Jul 12 06:22:14 PM PDT 24
Finished Jul 12 06:22:36 PM PDT 24
Peak memory 223348 kb
Host smart-30ecca28-39de-4326-b903-72a9905cb719
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1005211370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1005211370
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1793861202
Short name T70
Test name
Test status
Simulation time 942737104 ps
CPU time 1.08 seconds
Started Jul 12 06:22:18 PM PDT 24
Finished Jul 12 06:22:20 PM PDT 24
Peak memory 236392 kb
Host smart-5b7135f5-1a47-48c7-957e-dbedc75f99d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793861202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1793861202
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3844615286
Short name T77
Test name
Test status
Simulation time 7362581079 ps
CPU time 33.46 seconds
Started Jul 12 06:22:18 PM PDT 24
Finished Jul 12 06:22:52 PM PDT 24
Peak memory 242096 kb
Host smart-1064a0a2-bbd0-4364-a5fa-23778dbaf881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844615286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3844615286
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2667932286
Short name T57
Test name
Test status
Simulation time 368291405 ps
CPU time 0.73 seconds
Started Jul 12 06:22:09 PM PDT 24
Finished Jul 12 06:22:10 PM PDT 24
Peak memory 206896 kb
Host smart-cc19ef24-fd16-495c-8915-2a22c64de78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667932286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2667932286
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3046903195
Short name T473
Test name
Test status
Simulation time 3567715796 ps
CPU time 4.62 seconds
Started Jul 12 06:22:10 PM PDT 24
Finished Jul 12 06:22:15 PM PDT 24
Peak memory 217472 kb
Host smart-3b2a1eb6-0cf6-4206-95e3-b12be4a0ecb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046903195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3046903195
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3591816473
Short name T415
Test name
Test status
Simulation time 50405003 ps
CPU time 0.69 seconds
Started Jul 12 06:22:09 PM PDT 24
Finished Jul 12 06:22:10 PM PDT 24
Peak memory 206540 kb
Host smart-452be82a-db2a-4843-9b7c-88b1c770d01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591816473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3591816473
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2718738029
Short name T401
Test name
Test status
Simulation time 247475104 ps
CPU time 0.93 seconds
Started Jul 12 06:22:10 PM PDT 24
Finished Jul 12 06:22:12 PM PDT 24
Peak memory 207276 kb
Host smart-9d2d8346-1b77-4b30-86f9-1c3859dc9794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718738029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2718738029
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2951790574
Short name T784
Test name
Test status
Simulation time 31216089762 ps
CPU time 23.66 seconds
Started Jul 12 06:22:15 PM PDT 24
Finished Jul 12 06:22:39 PM PDT 24
Peak memory 231332 kb
Host smart-fad1ac74-6eba-4dc2-a095-3d68c45022a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951790574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2951790574
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.4087634480
Short name T842
Test name
Test status
Simulation time 17439405 ps
CPU time 0.71 seconds
Started Jul 12 06:25:37 PM PDT 24
Finished Jul 12 06:25:38 PM PDT 24
Peak memory 206724 kb
Host smart-d109c676-fa9c-44d2-8d61-ac4224d354fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087634480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
4087634480
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3067709849
Short name T341
Test name
Test status
Simulation time 31841400 ps
CPU time 2.51 seconds
Started Jul 12 06:25:30 PM PDT 24
Finished Jul 12 06:25:34 PM PDT 24
Peak memory 233476 kb
Host smart-ae0beaac-16e7-472c-9524-40f08b696d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067709849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3067709849
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1561155910
Short name T886
Test name
Test status
Simulation time 51186703 ps
CPU time 0.76 seconds
Started Jul 12 06:25:29 PM PDT 24
Finished Jul 12 06:25:31 PM PDT 24
Peak memory 206804 kb
Host smart-7e9b5ca8-4bb7-4015-942a-a454a6111477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561155910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1561155910
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1736680653
Short name T769
Test name
Test status
Simulation time 101356197641 ps
CPU time 66.91 seconds
Started Jul 12 06:25:37 PM PDT 24
Finished Jul 12 06:26:44 PM PDT 24
Peak memory 252028 kb
Host smart-c392592a-fef7-470b-b1f9-ffbf3ec2a774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736680653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1736680653
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1705482540
Short name T751
Test name
Test status
Simulation time 55555144259 ps
CPU time 112.26 seconds
Started Jul 12 06:25:37 PM PDT 24
Finished Jul 12 06:27:30 PM PDT 24
Peak memory 250392 kb
Host smart-6c981412-5b0a-4725-85ad-cf063fb32a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705482540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1705482540
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2345054415
Short name T511
Test name
Test status
Simulation time 37655627015 ps
CPU time 62.61 seconds
Started Jul 12 06:25:39 PM PDT 24
Finished Jul 12 06:26:43 PM PDT 24
Peak memory 224616 kb
Host smart-57ee712d-c1f0-4ba0-85ef-79799fb23deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345054415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2345054415
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1961026895
Short name T960
Test name
Test status
Simulation time 513462208 ps
CPU time 11.48 seconds
Started Jul 12 06:25:37 PM PDT 24
Finished Jul 12 06:25:49 PM PDT 24
Peak memory 234784 kb
Host smart-d7789135-e3ed-4e40-ab6d-ab643941b82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961026895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1961026895
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1659460615
Short name T952
Test name
Test status
Simulation time 53873385149 ps
CPU time 42.01 seconds
Started Jul 12 06:25:38 PM PDT 24
Finished Jul 12 06:26:21 PM PDT 24
Peak memory 242088 kb
Host smart-fd1657ce-e312-4cda-a96e-8f8ff5638aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659460615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1659460615
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1366848227
Short name T237
Test name
Test status
Simulation time 635661242 ps
CPU time 5.21 seconds
Started Jul 12 06:25:30 PM PDT 24
Finished Jul 12 06:25:36 PM PDT 24
Peak memory 233704 kb
Host smart-1a0ab503-1f0f-4129-a02f-8576cf8308f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366848227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1366848227
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1532556426
Short name T976
Test name
Test status
Simulation time 1250554923 ps
CPU time 20.22 seconds
Started Jul 12 06:25:30 PM PDT 24
Finished Jul 12 06:25:52 PM PDT 24
Peak memory 251172 kb
Host smart-134249c5-92e1-4359-af24-dc0dd4dd6c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532556426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1532556426
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.4128284115
Short name T700
Test name
Test status
Simulation time 1104933288 ps
CPU time 7.39 seconds
Started Jul 12 06:25:29 PM PDT 24
Finished Jul 12 06:25:37 PM PDT 24
Peak memory 241524 kb
Host smart-04e75b52-1220-4567-a731-9591e8654c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128284115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.4128284115
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3087354679
Short name T53
Test name
Test status
Simulation time 1952767629 ps
CPU time 8.6 seconds
Started Jul 12 06:25:32 PM PDT 24
Finished Jul 12 06:25:41 PM PDT 24
Peak memory 233692 kb
Host smart-745be548-3715-455a-b06e-1ce72be5ba34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087354679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3087354679
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1596696938
Short name T423
Test name
Test status
Simulation time 4947146303 ps
CPU time 10.08 seconds
Started Jul 12 06:25:37 PM PDT 24
Finished Jul 12 06:25:48 PM PDT 24
Peak memory 222328 kb
Host smart-30e38002-d529-4b18-bf16-5be8699b4682
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1596696938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1596696938
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.4053671321
Short name T201
Test name
Test status
Simulation time 29531173714 ps
CPU time 98.37 seconds
Started Jul 12 06:25:39 PM PDT 24
Finished Jul 12 06:27:18 PM PDT 24
Peak memory 255068 kb
Host smart-db20f0c3-d7bc-4178-9724-0c32ee2b0031
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053671321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.4053671321
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.317424787
Short name T474
Test name
Test status
Simulation time 3685194040 ps
CPU time 19.31 seconds
Started Jul 12 06:26:04 PM PDT 24
Finished Jul 12 06:26:24 PM PDT 24
Peak memory 217460 kb
Host smart-2b0556c7-3620-46f1-923f-14b057d0c940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317424787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.317424787
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2584016327
Short name T618
Test name
Test status
Simulation time 24912296466 ps
CPU time 8.01 seconds
Started Jul 12 06:25:29 PM PDT 24
Finished Jul 12 06:25:38 PM PDT 24
Peak memory 217420 kb
Host smart-87423b44-1e63-4510-a2b6-2854f0bb25e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584016327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2584016327
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3808285220
Short name T630
Test name
Test status
Simulation time 30424876 ps
CPU time 1.26 seconds
Started Jul 12 06:25:29 PM PDT 24
Finished Jul 12 06:25:31 PM PDT 24
Peak memory 208952 kb
Host smart-f85bb7a7-bf7b-4a73-89ca-079dc8e399df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808285220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3808285220
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.17631745
Short name T733
Test name
Test status
Simulation time 71729931 ps
CPU time 0.91 seconds
Started Jul 12 06:25:31 PM PDT 24
Finished Jul 12 06:25:33 PM PDT 24
Peak memory 206960 kb
Host smart-61ff3477-7626-4872-9468-ef4981604f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17631745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.17631745
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.533759841
Short name T560
Test name
Test status
Simulation time 28197786252 ps
CPU time 20.99 seconds
Started Jul 12 06:25:30 PM PDT 24
Finished Jul 12 06:25:52 PM PDT 24
Peak memory 233844 kb
Host smart-0bb6e7e9-ece2-49aa-89f2-3e78ee8d3d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533759841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.533759841
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2948274294
Short name T30
Test name
Test status
Simulation time 12529402 ps
CPU time 0.76 seconds
Started Jul 12 06:25:45 PM PDT 24
Finished Jul 12 06:25:47 PM PDT 24
Peak memory 205800 kb
Host smart-a48b4153-a7c5-4104-b718-56a73a6ca6d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948274294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2948274294
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3770726366
Short name T882
Test name
Test status
Simulation time 533778365 ps
CPU time 2.94 seconds
Started Jul 12 06:25:46 PM PDT 24
Finished Jul 12 06:25:50 PM PDT 24
Peak memory 233724 kb
Host smart-f5ab557c-cd38-4f07-8003-bc7e327c0354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770726366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3770726366
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.659118528
Short name T790
Test name
Test status
Simulation time 17974869 ps
CPU time 0.76 seconds
Started Jul 12 06:25:39 PM PDT 24
Finished Jul 12 06:25:40 PM PDT 24
Peak memory 207828 kb
Host smart-fe7edc00-947b-4fa4-ac23-883ab6a7ed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659118528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.659118528
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3399743843
Short name T219
Test name
Test status
Simulation time 75323363899 ps
CPU time 153.11 seconds
Started Jul 12 06:25:46 PM PDT 24
Finished Jul 12 06:28:21 PM PDT 24
Peak memory 271448 kb
Host smart-9d26819e-8bc9-4e7d-a17d-5855888827e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399743843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3399743843
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.193621453
Short name T225
Test name
Test status
Simulation time 28729594756 ps
CPU time 313.18 seconds
Started Jul 12 06:25:49 PM PDT 24
Finished Jul 12 06:31:03 PM PDT 24
Peak memory 257460 kb
Host smart-6a3e763f-74bb-4436-8b88-eff1c9f134cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193621453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.193621453
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2533457986
Short name T446
Test name
Test status
Simulation time 62917455991 ps
CPU time 293.78 seconds
Started Jul 12 06:25:47 PM PDT 24
Finished Jul 12 06:30:42 PM PDT 24
Peak memory 266760 kb
Host smart-821bea2d-ca62-47fa-be66-9bede2c8bdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533457986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2533457986
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3848173303
Short name T93
Test name
Test status
Simulation time 110635935 ps
CPU time 2.85 seconds
Started Jul 12 06:25:45 PM PDT 24
Finished Jul 12 06:25:49 PM PDT 24
Peak memory 233748 kb
Host smart-f827b7e4-247f-4dbb-9d8e-282607bbfbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848173303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3848173303
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.262634694
Short name T924
Test name
Test status
Simulation time 58868610535 ps
CPU time 102.04 seconds
Started Jul 12 06:25:45 PM PDT 24
Finished Jul 12 06:27:29 PM PDT 24
Peak memory 250288 kb
Host smart-c944b576-70ff-491c-9a51-e277fbd63242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262634694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.262634694
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2908183135
Short name T396
Test name
Test status
Simulation time 2524332579 ps
CPU time 4.21 seconds
Started Jul 12 06:25:38 PM PDT 24
Finished Jul 12 06:25:43 PM PDT 24
Peak memory 229192 kb
Host smart-5419a666-e835-4294-9271-267e1cce0026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908183135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2908183135
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3777814290
Short name T274
Test name
Test status
Simulation time 13910495727 ps
CPU time 37.75 seconds
Started Jul 12 06:25:38 PM PDT 24
Finished Jul 12 06:26:17 PM PDT 24
Peak memory 251600 kb
Host smart-df69ac8b-12ef-4c0f-8bae-78438bd49f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777814290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3777814290
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2318695220
Short name T29
Test name
Test status
Simulation time 714759873 ps
CPU time 4.28 seconds
Started Jul 12 06:25:38 PM PDT 24
Finished Jul 12 06:25:43 PM PDT 24
Peak memory 225524 kb
Host smart-c7ffc319-c418-4537-a077-1f6b89482b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318695220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2318695220
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1043478805
Short name T392
Test name
Test status
Simulation time 193676949 ps
CPU time 2.55 seconds
Started Jul 12 06:25:38 PM PDT 24
Finished Jul 12 06:25:41 PM PDT 24
Peak memory 225504 kb
Host smart-5ccea8a8-a58f-4b26-98c5-7fc7106b616c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043478805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1043478805
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3245023227
Short name T4
Test name
Test status
Simulation time 232691682 ps
CPU time 5.08 seconds
Started Jul 12 06:25:47 PM PDT 24
Finished Jul 12 06:25:53 PM PDT 24
Peak memory 224112 kb
Host smart-2d7d55e1-e485-4f25-abe3-ef31d4cfe947
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3245023227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3245023227
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2015330447
Short name T967
Test name
Test status
Simulation time 82250576465 ps
CPU time 320.09 seconds
Started Jul 12 06:25:51 PM PDT 24
Finished Jul 12 06:31:12 PM PDT 24
Peak memory 283224 kb
Host smart-aeeda419-3bb7-471f-ba88-59d8dc47ad39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015330447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2015330447
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.420000959
Short name T884
Test name
Test status
Simulation time 247996569 ps
CPU time 4.37 seconds
Started Jul 12 06:25:37 PM PDT 24
Finished Jul 12 06:25:42 PM PDT 24
Peak memory 217292 kb
Host smart-76293664-50d8-4504-9733-47428374e7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420000959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.420000959
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3980911063
Short name T740
Test name
Test status
Simulation time 7879084547 ps
CPU time 6.5 seconds
Started Jul 12 06:25:36 PM PDT 24
Finished Jul 12 06:25:43 PM PDT 24
Peak memory 217448 kb
Host smart-f5ddbce8-5ce9-4e3d-a798-5f42c90e7e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980911063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3980911063
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3683173674
Short name T598
Test name
Test status
Simulation time 134840062 ps
CPU time 1.89 seconds
Started Jul 12 06:25:40 PM PDT 24
Finished Jul 12 06:25:42 PM PDT 24
Peak memory 217380 kb
Host smart-c33b2768-3cc9-4d4a-a249-6c664e6c9241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683173674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3683173674
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.929601828
Short name T894
Test name
Test status
Simulation time 124341234 ps
CPU time 0.7 seconds
Started Jul 12 06:25:37 PM PDT 24
Finished Jul 12 06:25:38 PM PDT 24
Peak memory 206904 kb
Host smart-f8bb18c4-6b76-4d87-875f-31e745470163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929601828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.929601828
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.4118233707
Short name T432
Test name
Test status
Simulation time 87050153 ps
CPU time 3.06 seconds
Started Jul 12 06:25:45 PM PDT 24
Finished Jul 12 06:25:49 PM PDT 24
Peak memory 233776 kb
Host smart-2fdc0991-b83a-4b37-b13b-67e25d1d895d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118233707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4118233707
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3370980469
Short name T631
Test name
Test status
Simulation time 20329370 ps
CPU time 0.74 seconds
Started Jul 12 06:25:55 PM PDT 24
Finished Jul 12 06:25:57 PM PDT 24
Peak memory 206476 kb
Host smart-82a7ae20-3611-4b29-b4e8-1ddce3dbcfc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370980469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3370980469
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2555719629
Short name T897
Test name
Test status
Simulation time 173161804 ps
CPU time 3.89 seconds
Started Jul 12 06:25:52 PM PDT 24
Finished Jul 12 06:25:57 PM PDT 24
Peak memory 233724 kb
Host smart-60aede96-10dd-4dae-94fe-4f3cd1ad52d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555719629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2555719629
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1452766535
Short name T782
Test name
Test status
Simulation time 42606637 ps
CPU time 0.77 seconds
Started Jul 12 06:25:51 PM PDT 24
Finished Jul 12 06:25:53 PM PDT 24
Peak memory 207508 kb
Host smart-579ea1c7-e512-4ebb-902d-e1955932646f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452766535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1452766535
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.754466890
Short name T250
Test name
Test status
Simulation time 60778233788 ps
CPU time 115.23 seconds
Started Jul 12 06:25:52 PM PDT 24
Finished Jul 12 06:27:48 PM PDT 24
Peak memory 242088 kb
Host smart-071125ff-bdbe-493b-ada2-708265d31bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754466890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.754466890
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.810042651
Short name T231
Test name
Test status
Simulation time 7411380032 ps
CPU time 57.87 seconds
Started Jul 12 06:25:51 PM PDT 24
Finished Jul 12 06:26:49 PM PDT 24
Peak memory 253648 kb
Host smart-77733cd2-041c-4af4-bb2d-a8ce677fcf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810042651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.810042651
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.899721848
Short name T72
Test name
Test status
Simulation time 71617225129 ps
CPU time 160.83 seconds
Started Jul 12 06:25:55 PM PDT 24
Finished Jul 12 06:28:37 PM PDT 24
Peak memory 233996 kb
Host smart-348e5766-4870-4071-a44c-e136697668a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899721848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.899721848
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.690888532
Short name T905
Test name
Test status
Simulation time 286605391 ps
CPU time 5.6 seconds
Started Jul 12 06:25:54 PM PDT 24
Finished Jul 12 06:26:01 PM PDT 24
Peak memory 240440 kb
Host smart-a7c2efe3-8c43-46b4-9064-b47793b26119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690888532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.690888532
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1305226188
Short name T433
Test name
Test status
Simulation time 39113823736 ps
CPU time 139.66 seconds
Started Jul 12 06:25:53 PM PDT 24
Finished Jul 12 06:28:14 PM PDT 24
Peak memory 250264 kb
Host smart-44d8abde-2cdd-47a1-b211-295e845397c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305226188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1305226188
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1198515354
Short name T802
Test name
Test status
Simulation time 44207748 ps
CPU time 2.46 seconds
Started Jul 12 06:25:53 PM PDT 24
Finished Jul 12 06:25:56 PM PDT 24
Peak memory 225532 kb
Host smart-f38852b1-f5f1-4d20-9aeb-446b0f4ac1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198515354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1198515354
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2486989268
Short name T821
Test name
Test status
Simulation time 14289004541 ps
CPU time 24.13 seconds
Started Jul 12 06:34:37 PM PDT 24
Finished Jul 12 06:35:03 PM PDT 24
Peak memory 225620 kb
Host smart-31e177be-3c45-48b8-b7ef-a734a8c8d53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486989268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2486989268
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.4149076759
Short name T453
Test name
Test status
Simulation time 14265365630 ps
CPU time 10.93 seconds
Started Jul 12 06:25:52 PM PDT 24
Finished Jul 12 06:26:04 PM PDT 24
Peak memory 225688 kb
Host smart-d623256d-3cd6-429d-bb64-01873e3acdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149076759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.4149076759
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.390762600
Short name T578
Test name
Test status
Simulation time 110913449 ps
CPU time 2.52 seconds
Started Jul 12 06:25:51 PM PDT 24
Finished Jul 12 06:25:55 PM PDT 24
Peak memory 233436 kb
Host smart-fa346671-3a70-489f-8416-1ad1a543f28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390762600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.390762600
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.183513929
Short name T834
Test name
Test status
Simulation time 4058227547 ps
CPU time 12.3 seconds
Started Jul 12 06:25:54 PM PDT 24
Finished Jul 12 06:26:08 PM PDT 24
Peak memory 220696 kb
Host smart-f4564c2a-cd6f-4f43-a6e1-4f54f38bc6b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=183513929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.183513929
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1945087410
Short name T403
Test name
Test status
Simulation time 1527756267 ps
CPU time 25.76 seconds
Started Jul 12 06:25:52 PM PDT 24
Finished Jul 12 06:26:19 PM PDT 24
Peak memory 217508 kb
Host smart-e4c620fa-e7f4-40d1-99b5-ff89056a66be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945087410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1945087410
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4273079248
Short name T991
Test name
Test status
Simulation time 2859124534 ps
CPU time 3.65 seconds
Started Jul 12 06:25:51 PM PDT 24
Finished Jul 12 06:25:56 PM PDT 24
Peak memory 217484 kb
Host smart-245dbd19-2c95-455c-82b7-44951f83cdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273079248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4273079248
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.15257600
Short name T534
Test name
Test status
Simulation time 96525771 ps
CPU time 1.35 seconds
Started Jul 12 06:25:53 PM PDT 24
Finished Jul 12 06:25:55 PM PDT 24
Peak memory 208900 kb
Host smart-2139b136-46ef-4e35-b645-00c2b8957022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15257600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.15257600
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2896667732
Short name T88
Test name
Test status
Simulation time 94646281 ps
CPU time 0.94 seconds
Started Jul 12 06:25:53 PM PDT 24
Finished Jul 12 06:25:55 PM PDT 24
Peak memory 206936 kb
Host smart-237fd616-cc2a-4ad1-9aad-597a18e6745a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896667732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2896667732
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.682393828
Short name T696
Test name
Test status
Simulation time 1172799402 ps
CPU time 8.83 seconds
Started Jul 12 06:25:52 PM PDT 24
Finished Jul 12 06:26:02 PM PDT 24
Peak memory 233712 kb
Host smart-926dd13c-68b3-4ab7-a3c7-d222e6dd0edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682393828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.682393828
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3007256967
Short name T883
Test name
Test status
Simulation time 30341496 ps
CPU time 0.73 seconds
Started Jul 12 06:26:05 PM PDT 24
Finished Jul 12 06:26:07 PM PDT 24
Peak memory 205608 kb
Host smart-eb29f43b-1338-4d26-85f2-77c820eaf36a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007256967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3007256967
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.440728086
Short name T717
Test name
Test status
Simulation time 572308522 ps
CPU time 5.39 seconds
Started Jul 12 06:25:59 PM PDT 24
Finished Jul 12 06:26:05 PM PDT 24
Peak memory 233736 kb
Host smart-50437ac0-c582-4713-b3aa-159eaa1a81a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440728086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.440728086
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1630616164
Short name T624
Test name
Test status
Simulation time 17563727 ps
CPU time 0.81 seconds
Started Jul 12 06:26:01 PM PDT 24
Finished Jul 12 06:26:03 PM PDT 24
Peak memory 206444 kb
Host smart-6837ef0d-0da3-4e47-a185-035945f39d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630616164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1630616164
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2761619946
Short name T763
Test name
Test status
Simulation time 18197030945 ps
CPU time 131.61 seconds
Started Jul 12 06:26:00 PM PDT 24
Finished Jul 12 06:28:13 PM PDT 24
Peak memory 258008 kb
Host smart-782f8501-9308-4fcf-9759-46eb67f9318a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761619946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2761619946
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.732249801
Short name T79
Test name
Test status
Simulation time 8095749920 ps
CPU time 72.79 seconds
Started Jul 12 06:26:04 PM PDT 24
Finished Jul 12 06:27:17 PM PDT 24
Peak memory 253576 kb
Host smart-106a7879-3c1c-42d5-9132-b49cc93e3abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732249801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.732249801
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4220102602
Short name T826
Test name
Test status
Simulation time 69247536086 ps
CPU time 100.51 seconds
Started Jul 12 06:26:08 PM PDT 24
Finished Jul 12 06:27:49 PM PDT 24
Peak memory 257684 kb
Host smart-5e5de0e2-43cb-4855-bd9b-e76868bc9272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220102602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4220102602
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.925124943
Short name T799
Test name
Test status
Simulation time 164900557 ps
CPU time 2.78 seconds
Started Jul 12 06:26:01 PM PDT 24
Finished Jul 12 06:26:05 PM PDT 24
Peak memory 233756 kb
Host smart-c320f219-e0a2-4e2f-82c1-9fbf6c5c909a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925124943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.925124943
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.209814280
Short name T982
Test name
Test status
Simulation time 10281957553 ps
CPU time 74.4 seconds
Started Jul 12 06:26:00 PM PDT 24
Finished Jul 12 06:27:16 PM PDT 24
Peak memory 250292 kb
Host smart-5290d6e7-09c6-4d51-80f3-4816a6591f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209814280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.209814280
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2889482030
Short name T906
Test name
Test status
Simulation time 3332164695 ps
CPU time 6.05 seconds
Started Jul 12 06:26:00 PM PDT 24
Finished Jul 12 06:26:08 PM PDT 24
Peak memory 233832 kb
Host smart-712eb0c5-348c-4b99-be47-e464e239f9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889482030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2889482030
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1019716685
Short name T509
Test name
Test status
Simulation time 1666981277 ps
CPU time 19.87 seconds
Started Jul 12 06:25:57 PM PDT 24
Finished Jul 12 06:26:18 PM PDT 24
Peak memory 233692 kb
Host smart-d42f2361-a7fd-4ab5-af49-e5600c32b7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019716685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1019716685
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3334725687
Short name T627
Test name
Test status
Simulation time 8944056214 ps
CPU time 12.43 seconds
Started Jul 12 06:25:59 PM PDT 24
Finished Jul 12 06:26:12 PM PDT 24
Peak memory 242060 kb
Host smart-46513a86-cf0b-4557-870e-aae389af9feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334725687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3334725687
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2969019450
Short name T442
Test name
Test status
Simulation time 2216539547 ps
CPU time 5.5 seconds
Started Jul 12 06:26:00 PM PDT 24
Finished Jul 12 06:26:07 PM PDT 24
Peak memory 225676 kb
Host smart-7aa7f175-459c-4e80-8af9-7d0d19b3e4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969019450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2969019450
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.511774026
Short name T583
Test name
Test status
Simulation time 997534078 ps
CPU time 9.48 seconds
Started Jul 12 06:26:04 PM PDT 24
Finished Jul 12 06:26:14 PM PDT 24
Peak memory 223204 kb
Host smart-e6c3efcc-e277-41fc-b40c-f97fa0967064
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=511774026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.511774026
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1312863993
Short name T51
Test name
Test status
Simulation time 32596385707 ps
CPU time 372.47 seconds
Started Jul 12 06:26:07 PM PDT 24
Finished Jul 12 06:32:20 PM PDT 24
Peak memory 275000 kb
Host smart-094ab722-2c15-4404-8bc8-9759fb87432e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312863993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1312863993
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.203749425
Short name T718
Test name
Test status
Simulation time 26617778992 ps
CPU time 20.41 seconds
Started Jul 12 06:26:05 PM PDT 24
Finished Jul 12 06:26:26 PM PDT 24
Peak memory 221480 kb
Host smart-08b4dfd0-0d45-48ff-95e7-2711b0787699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203749425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.203749425
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.235843689
Short name T858
Test name
Test status
Simulation time 924078428 ps
CPU time 3.66 seconds
Started Jul 12 06:26:00 PM PDT 24
Finished Jul 12 06:26:05 PM PDT 24
Peak memory 217304 kb
Host smart-a09df1a8-ce37-4036-a3ec-a72cb18d55e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235843689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.235843689
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2161243982
Short name T968
Test name
Test status
Simulation time 139278857 ps
CPU time 5.54 seconds
Started Jul 12 06:25:58 PM PDT 24
Finished Jul 12 06:26:04 PM PDT 24
Peak memory 217352 kb
Host smart-516b1395-7139-4b67-80e0-9796d550233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161243982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2161243982
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1737030394
Short name T397
Test name
Test status
Simulation time 23787391 ps
CPU time 0.81 seconds
Started Jul 12 06:26:04 PM PDT 24
Finished Jul 12 06:26:06 PM PDT 24
Peak memory 206960 kb
Host smart-021e8d91-4e46-4beb-ba88-c2b44e6f52c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737030394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1737030394
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.471278939
Short name T570
Test name
Test status
Simulation time 2776096000 ps
CPU time 12.52 seconds
Started Jul 12 06:26:02 PM PDT 24
Finished Jul 12 06:26:15 PM PDT 24
Peak memory 233824 kb
Host smart-cfb38918-850c-45dd-8357-45ec55c0a712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471278939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.471278939
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.683990952
Short name T365
Test name
Test status
Simulation time 19865875 ps
CPU time 0.71 seconds
Started Jul 12 06:26:13 PM PDT 24
Finished Jul 12 06:26:14 PM PDT 24
Peak memory 206704 kb
Host smart-4625ab9a-caa0-4a62-b058-860fab3f7d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683990952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.683990952
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3496032254
Short name T382
Test name
Test status
Simulation time 495001498 ps
CPU time 5.79 seconds
Started Jul 12 06:26:21 PM PDT 24
Finished Jul 12 06:26:29 PM PDT 24
Peak memory 233700 kb
Host smart-1d7f28d1-b4c3-472e-a631-e0c8df65cfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496032254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3496032254
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3413492230
Short name T358
Test name
Test status
Simulation time 31237195 ps
CPU time 0.81 seconds
Started Jul 12 06:26:10 PM PDT 24
Finished Jul 12 06:26:12 PM PDT 24
Peak memory 207460 kb
Host smart-50afe237-8e2d-4d0a-8da5-58a7c5fb7292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413492230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3413492230
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2880787898
Short name T47
Test name
Test status
Simulation time 80817946369 ps
CPU time 285.94 seconds
Started Jul 12 06:26:21 PM PDT 24
Finished Jul 12 06:31:10 PM PDT 24
Peak memory 252636 kb
Host smart-d5b043e1-593f-451c-bf0b-6bccc0383c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880787898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2880787898
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.126246760
Short name T1018
Test name
Test status
Simulation time 7970258169 ps
CPU time 55.13 seconds
Started Jul 12 06:26:19 PM PDT 24
Finished Jul 12 06:27:15 PM PDT 24
Peak memory 251428 kb
Host smart-9388946f-e10f-4b55-be45-eb1efe13513e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126246760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.126246760
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3295974577
Short name T542
Test name
Test status
Simulation time 10005885765 ps
CPU time 92.69 seconds
Started Jul 12 06:26:15 PM PDT 24
Finished Jul 12 06:27:49 PM PDT 24
Peak memory 250416 kb
Host smart-bb06213e-e88a-4797-bdcc-df7034461513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295974577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3295974577
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3791340145
Short name T1025
Test name
Test status
Simulation time 550339610 ps
CPU time 5.71 seconds
Started Jul 12 06:26:13 PM PDT 24
Finished Jul 12 06:26:19 PM PDT 24
Peak memory 225532 kb
Host smart-ab474981-5ca0-4a1e-984b-8b517c5d3ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791340145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3791340145
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.629068676
Short name T138
Test name
Test status
Simulation time 44408216167 ps
CPU time 217.66 seconds
Started Jul 12 06:26:14 PM PDT 24
Finished Jul 12 06:29:53 PM PDT 24
Peak memory 250260 kb
Host smart-7caef4ed-5015-4ee4-9fc6-0e7f981128c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629068676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.629068676
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.4255997509
Short name T462
Test name
Test status
Simulation time 420901580 ps
CPU time 3.52 seconds
Started Jul 12 06:26:05 PM PDT 24
Finished Jul 12 06:26:10 PM PDT 24
Peak memory 225512 kb
Host smart-81b69433-f1a5-4f91-80f1-7a8aff9d28bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255997509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4255997509
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.4235708700
Short name T593
Test name
Test status
Simulation time 2301033768 ps
CPU time 19.62 seconds
Started Jul 12 06:26:07 PM PDT 24
Finished Jul 12 06:26:27 PM PDT 24
Peak memory 233848 kb
Host smart-c0681bc7-c031-45ba-b256-2d1faa5a509e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235708700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.4235708700
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.691882519
Short name T694
Test name
Test status
Simulation time 3404042534 ps
CPU time 10.2 seconds
Started Jul 12 06:26:10 PM PDT 24
Finished Jul 12 06:26:21 PM PDT 24
Peak memory 233836 kb
Host smart-b14b0f5f-8b3d-4279-bc20-9038abaa6bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691882519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.691882519
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.307178581
Short name T674
Test name
Test status
Simulation time 140426235 ps
CPU time 2.78 seconds
Started Jul 12 06:26:05 PM PDT 24
Finished Jul 12 06:26:09 PM PDT 24
Peak memory 233716 kb
Host smart-ced988bd-82ca-484a-b948-17ac304d5816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307178581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.307178581
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3757560147
Short name T597
Test name
Test status
Simulation time 1020058271 ps
CPU time 11.29 seconds
Started Jul 12 06:26:14 PM PDT 24
Finished Jul 12 06:26:27 PM PDT 24
Peak memory 223300 kb
Host smart-cfa46447-5925-4430-b15d-f1642c8e0d74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3757560147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3757560147
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3055538532
Short name T387
Test name
Test status
Simulation time 3449559688 ps
CPU time 26.6 seconds
Started Jul 12 06:26:06 PM PDT 24
Finished Jul 12 06:26:33 PM PDT 24
Peak memory 217404 kb
Host smart-a156db57-5f89-4e74-80fd-d33e94b50e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055538532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3055538532
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1422068356
Short name T588
Test name
Test status
Simulation time 69932180462 ps
CPU time 19.7 seconds
Started Jul 12 06:26:06 PM PDT 24
Finished Jul 12 06:26:27 PM PDT 24
Peak memory 217444 kb
Host smart-5b04ef15-5042-4cc3-a272-48479e0552e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422068356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1422068356
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.4138495686
Short name T320
Test name
Test status
Simulation time 526911272 ps
CPU time 1.73 seconds
Started Jul 12 06:26:06 PM PDT 24
Finished Jul 12 06:26:09 PM PDT 24
Peak memory 217320 kb
Host smart-da11338d-d2d4-4e10-b382-c5d5c142afda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138495686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.4138495686
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3197067628
Short name T340
Test name
Test status
Simulation time 245994872 ps
CPU time 1.06 seconds
Started Jul 12 06:26:10 PM PDT 24
Finished Jul 12 06:26:12 PM PDT 24
Peak memory 207072 kb
Host smart-f11d5509-74b1-45ba-8918-5d76242db5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197067628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3197067628
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3636358033
Short name T239
Test name
Test status
Simulation time 7886768102 ps
CPU time 8.19 seconds
Started Jul 12 06:26:10 PM PDT 24
Finished Jul 12 06:26:20 PM PDT 24
Peak memory 225684 kb
Host smart-1f5d4813-aed5-4b70-9bad-80ea40468247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636358033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3636358033
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1248620239
Short name T877
Test name
Test status
Simulation time 23069083 ps
CPU time 0.72 seconds
Started Jul 12 06:26:22 PM PDT 24
Finished Jul 12 06:26:25 PM PDT 24
Peak memory 205728 kb
Host smart-8837e3d2-ce35-40c3-bfb1-9b54f74501c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248620239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1248620239
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3098085645
Short name T911
Test name
Test status
Simulation time 531450510 ps
CPU time 7.47 seconds
Started Jul 12 06:26:23 PM PDT 24
Finished Jul 12 06:26:33 PM PDT 24
Peak memory 225528 kb
Host smart-a34b6038-e8b3-4035-8287-6db1504f9482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098085645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3098085645
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3042762491
Short name T677
Test name
Test status
Simulation time 32209116 ps
CPU time 0.78 seconds
Started Jul 12 06:26:14 PM PDT 24
Finished Jul 12 06:26:15 PM PDT 24
Peak memory 206800 kb
Host smart-2f75bd33-4b9c-4947-8622-dd41d7a77bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042762491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3042762491
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2572498254
Short name T370
Test name
Test status
Simulation time 44292482 ps
CPU time 0.75 seconds
Started Jul 12 06:26:20 PM PDT 24
Finished Jul 12 06:26:22 PM PDT 24
Peak memory 216908 kb
Host smart-cfdb1b2a-7072-4230-a51d-6aa3c062d3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572498254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2572498254
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3806974622
Short name T218
Test name
Test status
Simulation time 6364664920 ps
CPU time 67.2 seconds
Started Jul 12 06:26:21 PM PDT 24
Finished Jul 12 06:27:31 PM PDT 24
Peak memory 255176 kb
Host smart-88d06355-a7d5-4b5b-aa9d-bcd8c31d9798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806974622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3806974622
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.917686627
Short name T907
Test name
Test status
Simulation time 19417745302 ps
CPU time 90.41 seconds
Started Jul 12 06:26:22 PM PDT 24
Finished Jul 12 06:27:56 PM PDT 24
Peak memory 257248 kb
Host smart-df52dce4-f899-48c1-9690-8bb3cfdac8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917686627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.917686627
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3815122690
Short name T148
Test name
Test status
Simulation time 128124032 ps
CPU time 3.81 seconds
Started Jul 12 06:26:21 PM PDT 24
Finished Jul 12 06:26:27 PM PDT 24
Peak memory 225508 kb
Host smart-95bd4195-6a55-49bb-9ebb-d8a63507f24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815122690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3815122690
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.196210382
Short name T835
Test name
Test status
Simulation time 19035279 ps
CPU time 0.78 seconds
Started Jul 12 06:26:23 PM PDT 24
Finished Jul 12 06:26:27 PM PDT 24
Peak memory 216880 kb
Host smart-4616950b-9a24-4944-9bf1-55cf5084cf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196210382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds
.196210382
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.4185040742
Short name T347
Test name
Test status
Simulation time 6364451090 ps
CPU time 15.76 seconds
Started Jul 12 06:26:15 PM PDT 24
Finished Jul 12 06:26:32 PM PDT 24
Peak memory 225656 kb
Host smart-68c3d553-9da6-4980-8f6a-b04c1609fb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185040742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.4185040742
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1370034584
Short name T246
Test name
Test status
Simulation time 12915985815 ps
CPU time 119.82 seconds
Started Jul 12 06:26:21 PM PDT 24
Finished Jul 12 06:28:23 PM PDT 24
Peak memory 252876 kb
Host smart-a8141253-8b80-47d0-9f0d-9e62c6fef4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370034584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1370034584
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1770249213
Short name T925
Test name
Test status
Simulation time 7122463014 ps
CPU time 22.41 seconds
Started Jul 12 06:26:12 PM PDT 24
Finished Jul 12 06:26:35 PM PDT 24
Peak memory 233792 kb
Host smart-a688f494-14d6-49a4-989c-4b253ea05146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770249213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1770249213
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3978561504
Short name T642
Test name
Test status
Simulation time 10867373061 ps
CPU time 29.85 seconds
Started Jul 12 06:26:15 PM PDT 24
Finished Jul 12 06:26:46 PM PDT 24
Peak memory 241232 kb
Host smart-6fc921bb-d840-4fec-b339-d6eecceff963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978561504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3978561504
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.525248395
Short name T793
Test name
Test status
Simulation time 5398718957 ps
CPU time 14.15 seconds
Started Jul 12 06:26:21 PM PDT 24
Finished Jul 12 06:26:37 PM PDT 24
Peak memory 223156 kb
Host smart-686b1d03-ca19-427c-bbe9-470405e429b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=525248395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.525248395
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.4142293962
Short name T15
Test name
Test status
Simulation time 129980698 ps
CPU time 0.91 seconds
Started Jul 12 06:26:22 PM PDT 24
Finished Jul 12 06:26:26 PM PDT 24
Peak memory 208520 kb
Host smart-84784f1b-2289-426f-a370-ede4fb041988
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142293962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.4142293962
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3865339604
Short name T33
Test name
Test status
Simulation time 26145459863 ps
CPU time 32.52 seconds
Started Jul 12 06:26:16 PM PDT 24
Finished Jul 12 06:26:49 PM PDT 24
Peak memory 217508 kb
Host smart-42033788-c569-41e2-b368-e45dd97a46bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865339604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3865339604
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1931136809
Short name T336
Test name
Test status
Simulation time 12275564 ps
CPU time 0.7 seconds
Started Jul 12 06:26:14 PM PDT 24
Finished Jul 12 06:26:15 PM PDT 24
Peak memory 206612 kb
Host smart-e1cb2f1b-2afc-4479-900a-2415f8e9cf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931136809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1931136809
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3328339165
Short name T71
Test name
Test status
Simulation time 96262022 ps
CPU time 1.3 seconds
Started Jul 12 06:26:15 PM PDT 24
Finished Jul 12 06:26:17 PM PDT 24
Peak memory 209156 kb
Host smart-c2dcd191-92e4-403c-a998-a39a5b46059b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328339165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3328339165
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1575586380
Short name T461
Test name
Test status
Simulation time 98059280 ps
CPU time 0.88 seconds
Started Jul 12 06:26:13 PM PDT 24
Finished Jul 12 06:26:14 PM PDT 24
Peak memory 206940 kb
Host smart-78f0f2a2-4d94-44b9-ba9b-27c3b4d4793a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575586380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1575586380
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2295139989
Short name T236
Test name
Test status
Simulation time 9513194223 ps
CPU time 27.8 seconds
Started Jul 12 06:26:21 PM PDT 24
Finished Jul 12 06:26:52 PM PDT 24
Peak memory 233872 kb
Host smart-10d9a3f4-cd47-4913-b75f-2b0f904b38d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295139989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2295139989
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1580440924
Short name T481
Test name
Test status
Simulation time 55117164 ps
CPU time 0.71 seconds
Started Jul 12 06:26:29 PM PDT 24
Finished Jul 12 06:26:31 PM PDT 24
Peak memory 206396 kb
Host smart-3c8acbec-8926-43d4-8750-3a45efc47df0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580440924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1580440924
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3575331522
Short name T854
Test name
Test status
Simulation time 166742697 ps
CPU time 4.09 seconds
Started Jul 12 06:26:27 PM PDT 24
Finished Jul 12 06:26:32 PM PDT 24
Peak memory 233760 kb
Host smart-660aaba3-e588-4c6e-9173-cc1d0336e224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575331522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3575331522
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2919604961
Short name T656
Test name
Test status
Simulation time 20563573 ps
CPU time 0.73 seconds
Started Jul 12 06:26:21 PM PDT 24
Finished Jul 12 06:26:25 PM PDT 24
Peak memory 206804 kb
Host smart-65e60eb6-28e0-4024-8b7b-5823b90121bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919604961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2919604961
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3878646105
Short name T297
Test name
Test status
Simulation time 59788698449 ps
CPU time 250.37 seconds
Started Jul 12 06:26:34 PM PDT 24
Finished Jul 12 06:30:45 PM PDT 24
Peak memory 273792 kb
Host smart-27e56b23-044f-4a4e-890e-0fe3e701d20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878646105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3878646105
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3426949799
Short name T288
Test name
Test status
Simulation time 5960668828 ps
CPU time 44.84 seconds
Started Jul 12 06:26:29 PM PDT 24
Finished Jul 12 06:27:15 PM PDT 24
Peak memory 250348 kb
Host smart-2327f45a-b56a-41f3-95f0-01188e4d5016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426949799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3426949799
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3765172929
Short name T502
Test name
Test status
Simulation time 2847195479 ps
CPU time 37.44 seconds
Started Jul 12 06:26:29 PM PDT 24
Finished Jul 12 06:27:08 PM PDT 24
Peak memory 244776 kb
Host smart-f54546e7-06ed-42d6-b023-13b412da6643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765172929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3765172929
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1257672887
Short name T422
Test name
Test status
Simulation time 87855350 ps
CPU time 3.18 seconds
Started Jul 12 06:26:29 PM PDT 24
Finished Jul 12 06:26:33 PM PDT 24
Peak memory 225576 kb
Host smart-b452963a-8dc2-442d-97c7-d7f3f37afe84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257672887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1257672887
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1848551260
Short name T866
Test name
Test status
Simulation time 343500815 ps
CPU time 5.53 seconds
Started Jul 12 06:26:30 PM PDT 24
Finished Jul 12 06:26:37 PM PDT 24
Peak memory 233716 kb
Host smart-4880cece-29be-45fb-a124-cbb97d697181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848551260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1848551260
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2465804125
Short name T573
Test name
Test status
Simulation time 306348087 ps
CPU time 6.89 seconds
Started Jul 12 06:26:30 PM PDT 24
Finished Jul 12 06:26:38 PM PDT 24
Peak memory 233688 kb
Host smart-a2e6ef8a-d1df-4950-b439-c95d0b770847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465804125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2465804125
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1636363216
Short name T349
Test name
Test status
Simulation time 84369838 ps
CPU time 2.38 seconds
Started Jul 12 06:26:28 PM PDT 24
Finished Jul 12 06:26:32 PM PDT 24
Peak memory 225540 kb
Host smart-3b855a0e-da50-40d7-b5c1-4f567904d6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636363216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1636363216
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.463255946
Short name T168
Test name
Test status
Simulation time 4951194052 ps
CPU time 14.78 seconds
Started Jul 12 06:26:24 PM PDT 24
Finished Jul 12 06:26:42 PM PDT 24
Peak memory 233872 kb
Host smart-4075a758-7331-4ae1-9df7-69eed0a4ec3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463255946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.463255946
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3233652926
Short name T776
Test name
Test status
Simulation time 291801358 ps
CPU time 4.31 seconds
Started Jul 12 06:26:30 PM PDT 24
Finished Jul 12 06:26:36 PM PDT 24
Peak memory 224120 kb
Host smart-4bc0c11e-0992-40e5-8092-b250b96e3197
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3233652926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3233652926
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3184154068
Short name T165
Test name
Test status
Simulation time 362789875657 ps
CPU time 946.71 seconds
Started Jul 12 06:26:32 PM PDT 24
Finished Jul 12 06:42:21 PM PDT 24
Peak memory 271572 kb
Host smart-efc1c928-8622-480e-81e6-37feef6017c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184154068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3184154068
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.4023722707
Short name T399
Test name
Test status
Simulation time 19791475 ps
CPU time 0.7 seconds
Started Jul 12 06:26:22 PM PDT 24
Finished Jul 12 06:26:25 PM PDT 24
Peak memory 206524 kb
Host smart-1c88a891-500a-467f-a07c-948f4954b138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023722707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.4023722707
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.541661303
Short name T417
Test name
Test status
Simulation time 55792245 ps
CPU time 0.89 seconds
Started Jul 12 06:26:22 PM PDT 24
Finished Jul 12 06:26:25 PM PDT 24
Peak memory 206936 kb
Host smart-02f489fd-97bd-4f3f-befe-53b3a9ffdd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541661303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.541661303
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1341612265
Short name T743
Test name
Test status
Simulation time 587838652 ps
CPU time 7.5 seconds
Started Jul 12 06:26:29 PM PDT 24
Finished Jul 12 06:26:38 PM PDT 24
Peak memory 234676 kb
Host smart-8cabc8c1-2e84-473b-87ee-6306afd8c281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341612265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1341612265
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1646539940
Short name T878
Test name
Test status
Simulation time 25707893 ps
CPU time 0.74 seconds
Started Jul 12 06:26:45 PM PDT 24
Finished Jul 12 06:26:46 PM PDT 24
Peak memory 205780 kb
Host smart-358b66e0-1f56-4186-85fd-c00811235903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646539940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1646539940
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.178698680
Short name T809
Test name
Test status
Simulation time 241723419 ps
CPU time 3.16 seconds
Started Jul 12 06:26:39 PM PDT 24
Finished Jul 12 06:26:43 PM PDT 24
Peak memory 225524 kb
Host smart-648567b2-c1e4-4824-863e-ea11ac0764d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178698680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.178698680
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.525297552
Short name T939
Test name
Test status
Simulation time 132512151 ps
CPU time 0.75 seconds
Started Jul 12 06:26:30 PM PDT 24
Finished Jul 12 06:26:32 PM PDT 24
Peak memory 206464 kb
Host smart-d21acadd-f376-4253-a1fa-6742ac7fd29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525297552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.525297552
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3809135462
Short name T860
Test name
Test status
Simulation time 52537795448 ps
CPU time 175.46 seconds
Started Jul 12 06:26:36 PM PDT 24
Finished Jul 12 06:29:32 PM PDT 24
Peak memory 251288 kb
Host smart-b4d68a83-b35e-499f-8d66-9c68a2b9637b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809135462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3809135462
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2551064491
Short name T213
Test name
Test status
Simulation time 3752223561 ps
CPU time 92.94 seconds
Started Jul 12 06:26:36 PM PDT 24
Finished Jul 12 06:28:10 PM PDT 24
Peak memory 267808 kb
Host smart-2d6c5a0f-b613-404a-a094-0a6a10657cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551064491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2551064491
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3417731757
Short name T571
Test name
Test status
Simulation time 6499237511 ps
CPU time 25.31 seconds
Started Jul 12 06:26:44 PM PDT 24
Finished Jul 12 06:27:10 PM PDT 24
Peak memory 239360 kb
Host smart-bc42327c-0ba8-4b5a-b9d2-2f50582010ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417731757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3417731757
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3606261686
Short name T153
Test name
Test status
Simulation time 130400927 ps
CPU time 5.55 seconds
Started Jul 12 06:26:36 PM PDT 24
Finished Jul 12 06:26:43 PM PDT 24
Peak memory 222384 kb
Host smart-787ed063-3461-49a5-8a05-41d6dc4c1c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606261686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3606261686
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3267396256
Short name T1016
Test name
Test status
Simulation time 28248919994 ps
CPU time 206.95 seconds
Started Jul 12 06:26:36 PM PDT 24
Finished Jul 12 06:30:05 PM PDT 24
Peak memory 258348 kb
Host smart-e74c1da4-4372-433e-9ed0-aba80a30aa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267396256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3267396256
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.180005020
Short name T693
Test name
Test status
Simulation time 5066573337 ps
CPU time 10.63 seconds
Started Jul 12 06:26:37 PM PDT 24
Finished Jul 12 06:26:49 PM PDT 24
Peak memory 233980 kb
Host smart-9333d18f-d95b-438f-bd2b-b7a95be5c962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180005020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.180005020
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2951114644
Short name T638
Test name
Test status
Simulation time 2585023583 ps
CPU time 13.99 seconds
Started Jul 12 06:26:38 PM PDT 24
Finished Jul 12 06:26:53 PM PDT 24
Peak memory 225644 kb
Host smart-bede8b6e-b626-4247-a89e-ca6e8408a4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951114644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2951114644
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3284179503
Short name T699
Test name
Test status
Simulation time 1300753483 ps
CPU time 4.11 seconds
Started Jul 12 06:26:37 PM PDT 24
Finished Jul 12 06:26:43 PM PDT 24
Peak memory 225528 kb
Host smart-a0d77ee1-ef61-46ad-a415-380d672eb0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284179503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3284179503
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1443064508
Short name T419
Test name
Test status
Simulation time 2389975851 ps
CPU time 9.67 seconds
Started Jul 12 06:26:39 PM PDT 24
Finished Jul 12 06:26:50 PM PDT 24
Peak memory 225588 kb
Host smart-bf7be21e-fb5e-456c-a549-11f8cb57d4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443064508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1443064508
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3233916760
Short name T670
Test name
Test status
Simulation time 522272224 ps
CPU time 6.51 seconds
Started Jul 12 06:26:36 PM PDT 24
Finished Jul 12 06:26:44 PM PDT 24
Peak memory 219852 kb
Host smart-2ac45c59-0884-4f7e-9b85-af0f792ae2cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3233916760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3233916760
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3623378030
Short name T139
Test name
Test status
Simulation time 1944978025 ps
CPU time 34.46 seconds
Started Jul 12 06:26:44 PM PDT 24
Finished Jul 12 06:27:20 PM PDT 24
Peak memory 233916 kb
Host smart-38772ac9-c8e6-4c58-b758-b2fe24ed14dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623378030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3623378030
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.925695005
Short name T318
Test name
Test status
Simulation time 1795012407 ps
CPU time 22.1 seconds
Started Jul 12 06:26:38 PM PDT 24
Finished Jul 12 06:27:02 PM PDT 24
Peak memory 217444 kb
Host smart-5c251e42-9356-4a90-8b55-3de62ca9d020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925695005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.925695005
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3884806812
Short name T767
Test name
Test status
Simulation time 5619585623 ps
CPU time 4.51 seconds
Started Jul 12 06:26:29 PM PDT 24
Finished Jul 12 06:26:35 PM PDT 24
Peak memory 217480 kb
Host smart-6d362e18-50f6-4573-bc45-7b6105632f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884806812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3884806812
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.590275874
Short name T660
Test name
Test status
Simulation time 12625361 ps
CPU time 0.71 seconds
Started Jul 12 06:26:35 PM PDT 24
Finished Jul 12 06:26:37 PM PDT 24
Peak memory 206504 kb
Host smart-0329e289-2b06-4b8e-9d56-e207b8919614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590275874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.590275874
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3539451316
Short name T708
Test name
Test status
Simulation time 146205608 ps
CPU time 1.05 seconds
Started Jul 12 06:26:39 PM PDT 24
Finished Jul 12 06:26:41 PM PDT 24
Peak memory 206872 kb
Host smart-5108166d-6dfc-40e1-b5dd-d3e1fba448ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539451316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3539451316
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1244205321
Short name T56
Test name
Test status
Simulation time 11262163903 ps
CPU time 34.39 seconds
Started Jul 12 06:26:37 PM PDT 24
Finished Jul 12 06:27:12 PM PDT 24
Peak memory 225464 kb
Host smart-91dbccfd-9a1a-4356-9c60-2988e0a80a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244205321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1244205321
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.980241901
Short name T898
Test name
Test status
Simulation time 36998786 ps
CPU time 0.72 seconds
Started Jul 12 06:26:49 PM PDT 24
Finished Jul 12 06:26:50 PM PDT 24
Peak memory 205760 kb
Host smart-01c5d3bd-59e1-44f0-be37-3237a617d1bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980241901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.980241901
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.4118385944
Short name T169
Test name
Test status
Simulation time 3513075169 ps
CPU time 13.51 seconds
Started Jul 12 06:26:43 PM PDT 24
Finished Jul 12 06:26:57 PM PDT 24
Peak memory 233900 kb
Host smart-afbf2358-5162-4e2e-a29b-85a90eb82104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118385944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.4118385944
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.836199008
Short name T726
Test name
Test status
Simulation time 15839017 ps
CPU time 0.81 seconds
Started Jul 12 06:26:41 PM PDT 24
Finished Jul 12 06:26:43 PM PDT 24
Peak memory 206468 kb
Host smart-4c3ff672-f522-4cee-a16b-f9d8c9841134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836199008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.836199008
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2402684885
Short name T197
Test name
Test status
Simulation time 13252224491 ps
CPU time 85.47 seconds
Started Jul 12 06:26:50 PM PDT 24
Finished Jul 12 06:28:17 PM PDT 24
Peak memory 235832 kb
Host smart-4d6a24d2-f791-4008-bdf7-01bbc5d2bb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402684885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2402684885
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1936589002
Short name T286
Test name
Test status
Simulation time 5702194015 ps
CPU time 47.32 seconds
Started Jul 12 06:26:51 PM PDT 24
Finished Jul 12 06:27:40 PM PDT 24
Peak memory 233920 kb
Host smart-c77538ad-dea6-49a2-aa43-357320446363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936589002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1936589002
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.724235164
Short name T744
Test name
Test status
Simulation time 2327981269 ps
CPU time 33.86 seconds
Started Jul 12 06:26:50 PM PDT 24
Finished Jul 12 06:27:25 PM PDT 24
Peak memory 225740 kb
Host smart-c2f94efe-76e0-4697-9479-fd3cddadd74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724235164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.724235164
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2832584553
Short name T676
Test name
Test status
Simulation time 56383646 ps
CPU time 3.11 seconds
Started Jul 12 06:26:43 PM PDT 24
Finished Jul 12 06:26:48 PM PDT 24
Peak memory 233764 kb
Host smart-89a13ad6-6d12-48a5-acaf-d3f589f44aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832584553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2832584553
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1987271504
Short name T737
Test name
Test status
Simulation time 5388113066 ps
CPU time 67.43 seconds
Started Jul 12 06:26:51 PM PDT 24
Finished Jul 12 06:28:00 PM PDT 24
Peak memory 264568 kb
Host smart-c7218f42-67b2-44b8-b148-cf6f53d436f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987271504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1987271504
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2072839857
Short name T966
Test name
Test status
Simulation time 549989463 ps
CPU time 4.25 seconds
Started Jul 12 06:26:43 PM PDT 24
Finished Jul 12 06:26:48 PM PDT 24
Peak memory 233800 kb
Host smart-cf2af9f3-67a1-4f41-8eaa-ecc880a41665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072839857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2072839857
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.4157001231
Short name T828
Test name
Test status
Simulation time 13726084041 ps
CPU time 121.93 seconds
Started Jul 12 06:26:45 PM PDT 24
Finished Jul 12 06:28:47 PM PDT 24
Peak memory 233908 kb
Host smart-3f2aa0e1-7737-406b-a466-dfe7fb88bb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157001231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4157001231
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.192612252
Short name T691
Test name
Test status
Simulation time 23402321730 ps
CPU time 12.54 seconds
Started Jul 12 06:26:42 PM PDT 24
Finished Jul 12 06:26:56 PM PDT 24
Peak memory 225624 kb
Host smart-01cc78dc-e4e0-4ef0-8d78-7a3dc4776e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192612252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.192612252
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4010537864
Short name T241
Test name
Test status
Simulation time 5069672426 ps
CPU time 5.92 seconds
Started Jul 12 06:26:44 PM PDT 24
Finished Jul 12 06:26:51 PM PDT 24
Peak memory 233876 kb
Host smart-f40130ce-e491-407d-abfe-91b73490b2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010537864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4010537864
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.191648217
Short name T43
Test name
Test status
Simulation time 2296080340 ps
CPU time 5.27 seconds
Started Jul 12 06:26:53 PM PDT 24
Finished Jul 12 06:26:59 PM PDT 24
Peak memory 221608 kb
Host smart-19c926cd-a3d6-4fda-b45c-a286d8f91f91
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=191648217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.191648217
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3069859782
Short name T18
Test name
Test status
Simulation time 27683461881 ps
CPU time 251.07 seconds
Started Jul 12 06:26:50 PM PDT 24
Finished Jul 12 06:31:02 PM PDT 24
Peak memory 268212 kb
Host smart-30257675-2935-4d2e-be0d-ff135c7a41fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069859782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3069859782
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.521409617
Short name T575
Test name
Test status
Simulation time 5638327692 ps
CPU time 36.12 seconds
Started Jul 12 06:26:43 PM PDT 24
Finished Jul 12 06:27:20 PM PDT 24
Peak memory 221252 kb
Host smart-7cc17860-cf57-420e-a74e-cdfc43993b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521409617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.521409617
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4151248754
Short name T84
Test name
Test status
Simulation time 1686860417 ps
CPU time 6.21 seconds
Started Jul 12 06:26:41 PM PDT 24
Finished Jul 12 06:26:49 PM PDT 24
Peak memory 217348 kb
Host smart-1960a779-2fd0-416f-b8fa-382889b99ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151248754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4151248754
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2858732771
Short name T928
Test name
Test status
Simulation time 18869326 ps
CPU time 0.88 seconds
Started Jul 12 06:26:41 PM PDT 24
Finished Jul 12 06:26:43 PM PDT 24
Peak memory 207956 kb
Host smart-31c3e834-9943-4187-afa6-3c659071cfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858732771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2858732771
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.115974965
Short name T1004
Test name
Test status
Simulation time 19919035 ps
CPU time 0.74 seconds
Started Jul 12 06:26:39 PM PDT 24
Finished Jul 12 06:26:41 PM PDT 24
Peak memory 206964 kb
Host smart-a1808ebc-93dd-4363-a9db-07dabc7122c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115974965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.115974965
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2078843137
Short name T551
Test name
Test status
Simulation time 1217517921 ps
CPU time 3.89 seconds
Started Jul 12 06:26:42 PM PDT 24
Finished Jul 12 06:26:47 PM PDT 24
Peak memory 225472 kb
Host smart-747a2ff1-067a-402f-874f-4176ee8a8c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078843137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2078843137
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.958027631
Short name T956
Test name
Test status
Simulation time 102185486 ps
CPU time 0.72 seconds
Started Jul 12 06:26:59 PM PDT 24
Finished Jul 12 06:27:01 PM PDT 24
Peak memory 206708 kb
Host smart-d57913b6-cd44-4d37-b593-c5ab6a6cfd66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958027631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.958027631
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.116886389
Short name T267
Test name
Test status
Simulation time 372605906 ps
CPU time 6.12 seconds
Started Jul 12 06:26:58 PM PDT 24
Finished Jul 12 06:27:06 PM PDT 24
Peak memory 225560 kb
Host smart-e9f2f434-7f0d-46c3-87b2-1adf75a1bf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116886389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.116886389
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2120950190
Short name T338
Test name
Test status
Simulation time 87116572 ps
CPU time 0.77 seconds
Started Jul 12 06:26:51 PM PDT 24
Finished Jul 12 06:26:54 PM PDT 24
Peak memory 206456 kb
Host smart-0c1cbdb8-2092-4b3f-9f50-6e4f6232539d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120950190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2120950190
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1989194162
Short name T749
Test name
Test status
Simulation time 62765807341 ps
CPU time 453.24 seconds
Started Jul 12 06:26:57 PM PDT 24
Finished Jul 12 06:34:31 PM PDT 24
Peak memory 269124 kb
Host smart-7e9f6da8-3aa0-4041-9a84-a96a0a620d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989194162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1989194162
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.468293498
Short name T455
Test name
Test status
Simulation time 4350930721 ps
CPU time 55.66 seconds
Started Jul 12 06:26:58 PM PDT 24
Finished Jul 12 06:27:55 PM PDT 24
Peak memory 253472 kb
Host smart-cf83035a-ce46-49f9-924e-41aa58a49d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468293498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.468293498
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1998979680
Short name T50
Test name
Test status
Simulation time 32856646441 ps
CPU time 183.94 seconds
Started Jul 12 06:26:59 PM PDT 24
Finished Jul 12 06:30:04 PM PDT 24
Peak memory 263444 kb
Host smart-72e1b432-24fd-4374-9469-2bde3458f0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998979680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1998979680
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3817300611
Short name T580
Test name
Test status
Simulation time 200451223 ps
CPU time 3.26 seconds
Started Jul 12 06:26:58 PM PDT 24
Finished Jul 12 06:27:02 PM PDT 24
Peak memory 233752 kb
Host smart-d0e9eaac-82a4-4d50-9221-ffb64cec09f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817300611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3817300611
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.1821600967
Short name T436
Test name
Test status
Simulation time 1610528107 ps
CPU time 16.11 seconds
Started Jul 12 06:26:59 PM PDT 24
Finished Jul 12 06:27:16 PM PDT 24
Peak memory 241960 kb
Host smart-c2b327d8-92e9-44c9-ab7c-f0f1d4dd40ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821600967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.1821600967
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3054958660
Short name T1002
Test name
Test status
Simulation time 161525517 ps
CPU time 2.77 seconds
Started Jul 12 06:26:49 PM PDT 24
Finished Jul 12 06:26:53 PM PDT 24
Peak memory 225564 kb
Host smart-32a57fb0-bb41-4b7e-9386-fb419e603631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054958660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3054958660
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1581333548
Short name T539
Test name
Test status
Simulation time 104300705 ps
CPU time 2.37 seconds
Started Jul 12 06:26:51 PM PDT 24
Finished Jul 12 06:26:55 PM PDT 24
Peak memory 224140 kb
Host smart-d23ecae9-5d8a-4558-b573-85d0126f371c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581333548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1581333548
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2689375391
Short name T1
Test name
Test status
Simulation time 2004219030 ps
CPU time 9.83 seconds
Started Jul 12 06:26:52 PM PDT 24
Finished Jul 12 06:27:03 PM PDT 24
Peak memory 240968 kb
Host smart-e4474af0-ebb4-41cc-bf2a-e3db30eb8e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689375391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2689375391
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.300769049
Short name T825
Test name
Test status
Simulation time 257669146 ps
CPU time 3.28 seconds
Started Jul 12 06:26:51 PM PDT 24
Finished Jul 12 06:26:55 PM PDT 24
Peak memory 225532 kb
Host smart-7934b965-e77c-4c7d-9070-9a48e6fa7278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300769049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.300769049
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1690789597
Short name T621
Test name
Test status
Simulation time 12164972521 ps
CPU time 11.88 seconds
Started Jul 12 06:26:58 PM PDT 24
Finished Jul 12 06:27:12 PM PDT 24
Peak memory 221508 kb
Host smart-f2ffa3ac-1550-4c89-8c3a-0f92f1e08d9e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1690789597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1690789597
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1617252949
Short name T649
Test name
Test status
Simulation time 2606378059 ps
CPU time 53.26 seconds
Started Jul 12 06:26:59 PM PDT 24
Finished Jul 12 06:27:53 PM PDT 24
Peak memory 250424 kb
Host smart-1787bef0-02be-4b42-9634-30dc19b05d37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617252949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1617252949
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3551350244
Short name T454
Test name
Test status
Simulation time 2838608437 ps
CPU time 12.55 seconds
Started Jul 12 06:26:51 PM PDT 24
Finished Jul 12 06:27:05 PM PDT 24
Peak memory 217448 kb
Host smart-a14be30c-2bcf-4fa3-b608-f453577b4c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551350244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3551350244
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.762901376
Short name T490
Test name
Test status
Simulation time 1698048641 ps
CPU time 5 seconds
Started Jul 12 06:26:50 PM PDT 24
Finished Jul 12 06:26:56 PM PDT 24
Peak memory 217368 kb
Host smart-07127be3-e741-43a8-bfeb-3c0e8f0a03e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762901376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.762901376
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1624465960
Short name T846
Test name
Test status
Simulation time 53262467 ps
CPU time 0.94 seconds
Started Jul 12 06:26:51 PM PDT 24
Finished Jul 12 06:26:53 PM PDT 24
Peak memory 208216 kb
Host smart-9b6be7cd-eea3-44ee-b9b5-b30baafa7bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624465960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1624465960
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.4037117312
Short name T344
Test name
Test status
Simulation time 161720042 ps
CPU time 0.9 seconds
Started Jul 12 06:26:53 PM PDT 24
Finished Jul 12 06:26:55 PM PDT 24
Peak memory 207072 kb
Host smart-b004fe64-eb1a-45ed-a573-bd23a1d636e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037117312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.4037117312
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1623677944
Short name T11
Test name
Test status
Simulation time 4792691436 ps
CPU time 10.86 seconds
Started Jul 12 06:26:57 PM PDT 24
Finished Jul 12 06:27:09 PM PDT 24
Peak memory 233828 kb
Host smart-54abfe48-7d84-48da-9e5f-b9f77bc11b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623677944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1623677944
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4061333036
Short name T859
Test name
Test status
Simulation time 24051275 ps
CPU time 0.74 seconds
Started Jul 12 06:22:41 PM PDT 24
Finished Jul 12 06:22:42 PM PDT 24
Peak memory 206340 kb
Host smart-bb35d91f-5c93-4d02-ac23-1aba51b55a43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061333036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
061333036
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.4268569806
Short name T735
Test name
Test status
Simulation time 477846988 ps
CPU time 2.55 seconds
Started Jul 12 06:22:33 PM PDT 24
Finished Jul 12 06:22:37 PM PDT 24
Peak memory 225604 kb
Host smart-ba976bc6-f3a7-40a6-8ef3-c5900c5bbd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268569806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.4268569806
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1910299990
Short name T830
Test name
Test status
Simulation time 102239385 ps
CPU time 0.77 seconds
Started Jul 12 06:22:19 PM PDT 24
Finished Jul 12 06:22:21 PM PDT 24
Peak memory 207508 kb
Host smart-bbf7cdb2-faef-46f7-8dff-e8f90cd77f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910299990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1910299990
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.395651966
Short name T55
Test name
Test status
Simulation time 5111430014 ps
CPU time 69.11 seconds
Started Jul 12 06:22:33 PM PDT 24
Finished Jul 12 06:23:43 PM PDT 24
Peak memory 258560 kb
Host smart-145f1d3f-1c7b-4c7b-9091-c93cb21b2813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395651966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.395651966
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.787430153
Short name T628
Test name
Test status
Simulation time 1666083197 ps
CPU time 38.88 seconds
Started Jul 12 06:22:39 PM PDT 24
Finished Jul 12 06:23:18 PM PDT 24
Peak memory 251324 kb
Host smart-d679e7de-73f3-4b9f-858b-975aea9b3967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787430153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
787430153
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3922266839
Short name T818
Test name
Test status
Simulation time 5152049866 ps
CPU time 19.45 seconds
Started Jul 12 06:22:33 PM PDT 24
Finished Jul 12 06:22:53 PM PDT 24
Peak memory 242032 kb
Host smart-f671e29d-2268-495d-a4a3-270091276e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922266839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3922266839
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.595459566
Short name T985
Test name
Test status
Simulation time 673665137 ps
CPU time 14.41 seconds
Started Jul 12 06:22:34 PM PDT 24
Finished Jul 12 06:22:49 PM PDT 24
Peak memory 241944 kb
Host smart-9c0e41ed-a7b0-4b8a-b1af-595d1c3c3b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595459566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
595459566
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1972442136
Short name T470
Test name
Test status
Simulation time 2471178999 ps
CPU time 5.24 seconds
Started Jul 12 06:22:34 PM PDT 24
Finished Jul 12 06:22:40 PM PDT 24
Peak memory 225580 kb
Host smart-f4fb6047-fe4d-495c-a78b-614feb41eb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972442136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1972442136
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2230173906
Short name T420
Test name
Test status
Simulation time 818868775 ps
CPU time 18.27 seconds
Started Jul 12 06:22:34 PM PDT 24
Finished Jul 12 06:22:54 PM PDT 24
Peak memory 250152 kb
Host smart-ba72cf92-5613-463a-979c-acc81dfd71fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230173906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2230173906
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3311059738
Short name T484
Test name
Test status
Simulation time 17350470 ps
CPU time 1.13 seconds
Started Jul 12 06:22:23 PM PDT 24
Finished Jul 12 06:22:24 PM PDT 24
Peak memory 217588 kb
Host smart-6949516b-2d52-47a3-b9e5-b77a68066f77
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311059738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3311059738
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2579444781
Short name T302
Test name
Test status
Simulation time 20816152845 ps
CPU time 19.16 seconds
Started Jul 12 06:22:25 PM PDT 24
Finished Jul 12 06:22:45 PM PDT 24
Peak memory 225632 kb
Host smart-d8fd6b83-33df-4bbf-abbc-cb726b3c02fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579444781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2579444781
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1916877337
Short name T698
Test name
Test status
Simulation time 51507596792 ps
CPU time 16.53 seconds
Started Jul 12 06:22:23 PM PDT 24
Finished Jul 12 06:22:40 PM PDT 24
Peak memory 225632 kb
Host smart-46f583c6-c571-4d57-9d63-50a4dcbcdcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916877337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1916877337
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.212171850
Short name T942
Test name
Test status
Simulation time 287607491 ps
CPU time 3.77 seconds
Started Jul 12 06:22:35 PM PDT 24
Finished Jul 12 06:22:40 PM PDT 24
Peak memory 223612 kb
Host smart-902cc94c-894e-489d-8f80-589c77a21f62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=212171850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.212171850
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.520351122
Short name T67
Test name
Test status
Simulation time 87392417 ps
CPU time 1.1 seconds
Started Jul 12 06:22:39 PM PDT 24
Finished Jul 12 06:22:40 PM PDT 24
Peak memory 236360 kb
Host smart-eaad8028-6d38-4d4f-9846-8fe64921b051
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520351122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.520351122
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2245275988
Short name T167
Test name
Test status
Simulation time 3386656554 ps
CPU time 64.19 seconds
Started Jul 12 06:22:39 PM PDT 24
Finished Jul 12 06:23:43 PM PDT 24
Peak memory 253476 kb
Host smart-ae5d2dc8-8ad6-49e0-9432-a8c5de05425d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245275988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2245275988
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.443929867
Short name T816
Test name
Test status
Simulation time 17438513419 ps
CPU time 24.87 seconds
Started Jul 12 06:22:23 PM PDT 24
Finished Jul 12 06:22:49 PM PDT 24
Peak memory 217468 kb
Host smart-d6733475-516c-41b6-8a4c-770c39d4f4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443929867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.443929867
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2343015800
Short name T333
Test name
Test status
Simulation time 987040856 ps
CPU time 1.62 seconds
Started Jul 12 06:22:25 PM PDT 24
Finished Jul 12 06:22:27 PM PDT 24
Peak memory 208920 kb
Host smart-0ebf749f-2d1a-4d91-a4b5-23e68563d831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343015800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2343015800
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1362555132
Short name T369
Test name
Test status
Simulation time 730140379 ps
CPU time 1.07 seconds
Started Jul 12 06:22:24 PM PDT 24
Finished Jul 12 06:22:25 PM PDT 24
Peak memory 207968 kb
Host smart-dbda145d-5695-42e7-9819-303090f4ef68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362555132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1362555132
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1560198218
Short name T585
Test name
Test status
Simulation time 37338018 ps
CPU time 0.71 seconds
Started Jul 12 06:22:25 PM PDT 24
Finished Jul 12 06:22:26 PM PDT 24
Peak memory 206516 kb
Host smart-c6c1ded3-319a-4f0b-8767-6179acd5d34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560198218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1560198218
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.4063138424
Short name T999
Test name
Test status
Simulation time 3047909514 ps
CPU time 14.73 seconds
Started Jul 12 06:22:35 PM PDT 24
Finished Jul 12 06:22:51 PM PDT 24
Peak memory 233864 kb
Host smart-2013add7-6dde-4df7-867f-b7ab7fae049a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063138424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.4063138424
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1314828479
Short name T706
Test name
Test status
Simulation time 37220294 ps
CPU time 0.69 seconds
Started Jul 12 06:27:06 PM PDT 24
Finished Jul 12 06:27:08 PM PDT 24
Peak memory 206364 kb
Host smart-5fa7947d-4fef-406d-8027-87d3c825d6da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314828479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1314828479
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3617559196
Short name T817
Test name
Test status
Simulation time 627252541 ps
CPU time 5.07 seconds
Started Jul 12 06:27:05 PM PDT 24
Finished Jul 12 06:27:11 PM PDT 24
Peak memory 233712 kb
Host smart-97e3f956-91fb-42aa-b6c6-fd11ac8475c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617559196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3617559196
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3293124829
Short name T796
Test name
Test status
Simulation time 21847369 ps
CPU time 0.79 seconds
Started Jul 12 06:26:59 PM PDT 24
Finished Jul 12 06:27:01 PM PDT 24
Peak memory 207496 kb
Host smart-5b5ba9ae-3fd1-42ce-9509-e67b4d972fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293124829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3293124829
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.4142997372
Short name T736
Test name
Test status
Simulation time 28555550555 ps
CPU time 219.85 seconds
Started Jul 12 06:27:04 PM PDT 24
Finished Jul 12 06:30:44 PM PDT 24
Peak memory 257960 kb
Host smart-5e41cb4a-50d4-4a37-8caa-a5b9aa2d7582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142997372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.4142997372
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.216389481
Short name T995
Test name
Test status
Simulation time 16502197890 ps
CPU time 79.01 seconds
Started Jul 12 06:27:10 PM PDT 24
Finished Jul 12 06:28:31 PM PDT 24
Peak memory 249788 kb
Host smart-33b1301e-1953-4ae3-8ceb-4b3611f2685e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216389481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.216389481
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2374186220
Short name T317
Test name
Test status
Simulation time 10046971733 ps
CPU time 85.91 seconds
Started Jul 12 06:27:06 PM PDT 24
Finished Jul 12 06:28:33 PM PDT 24
Peak memory 250392 kb
Host smart-ed950133-5bae-4e0e-b52b-71204601a58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374186220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2374186220
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.594901942
Short name T602
Test name
Test status
Simulation time 37850221 ps
CPU time 2.54 seconds
Started Jul 12 06:27:10 PM PDT 24
Finished Jul 12 06:27:15 PM PDT 24
Peak memory 225036 kb
Host smart-369e7fd1-32a5-4a68-85c9-7e19dfae2b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594901942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.594901942
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2532106943
Short name T295
Test name
Test status
Simulation time 110950087754 ps
CPU time 173.52 seconds
Started Jul 12 06:27:07 PM PDT 24
Finished Jul 12 06:30:02 PM PDT 24
Peak memory 241788 kb
Host smart-47df95ad-5611-4604-8916-1c7afdb05c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532106943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2532106943
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3669310517
Short name T224
Test name
Test status
Simulation time 1540735148 ps
CPU time 7.68 seconds
Started Jul 12 06:26:59 PM PDT 24
Finished Jul 12 06:27:08 PM PDT 24
Peak memory 233736 kb
Host smart-ad53ee6c-468f-4218-abea-a2ffe26c1ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669310517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3669310517
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1933673532
Short name T407
Test name
Test status
Simulation time 572060427 ps
CPU time 7.88 seconds
Started Jul 12 06:27:05 PM PDT 24
Finished Jul 12 06:27:14 PM PDT 24
Peak memory 237432 kb
Host smart-88a2767b-ddf5-476c-baa9-9a978674bd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933673532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1933673532
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2938464456
Short name T289
Test name
Test status
Simulation time 4875142441 ps
CPU time 9.1 seconds
Started Jul 12 06:26:57 PM PDT 24
Finished Jul 12 06:27:08 PM PDT 24
Peak memory 225672 kb
Host smart-998265b2-6d2c-4489-aaa9-0981ee455553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938464456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2938464456
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2729715453
Short name T501
Test name
Test status
Simulation time 17096493816 ps
CPU time 44.63 seconds
Started Jul 12 06:27:00 PM PDT 24
Finished Jul 12 06:27:46 PM PDT 24
Peak memory 250208 kb
Host smart-0f054060-f1a4-4a3d-adbc-2eadb780db79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729715453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2729715453
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2327296383
Short name T917
Test name
Test status
Simulation time 798193534 ps
CPU time 7.39 seconds
Started Jul 12 06:27:04 PM PDT 24
Finished Jul 12 06:27:12 PM PDT 24
Peak memory 223096 kb
Host smart-7defcc7d-349d-4741-a0db-625d6ea67260
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2327296383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2327296383
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1436962611
Short name T131
Test name
Test status
Simulation time 88047946661 ps
CPU time 251.6 seconds
Started Jul 12 06:27:05 PM PDT 24
Finished Jul 12 06:31:18 PM PDT 24
Peak memory 274764 kb
Host smart-fdfcd94b-04a4-4be6-903d-a7f8fd905e0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436962611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1436962611
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.4069889406
Short name T316
Test name
Test status
Simulation time 13954687470 ps
CPU time 18.32 seconds
Started Jul 12 06:26:57 PM PDT 24
Finished Jul 12 06:27:16 PM PDT 24
Peak memory 217488 kb
Host smart-60639b84-5130-49ab-a782-0570004ea1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069889406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4069889406
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.565848154
Short name T1021
Test name
Test status
Simulation time 2696531723 ps
CPU time 5.62 seconds
Started Jul 12 06:26:58 PM PDT 24
Finished Jul 12 06:27:04 PM PDT 24
Peak memory 217396 kb
Host smart-818960c0-ad3b-42e4-9a65-b631a82c0f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565848154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.565848154
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.610928348
Short name T391
Test name
Test status
Simulation time 43872602 ps
CPU time 0.71 seconds
Started Jul 12 06:27:01 PM PDT 24
Finished Jul 12 06:27:02 PM PDT 24
Peak memory 206680 kb
Host smart-e77246e5-f33b-45a2-8d9b-19a0feaab51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610928348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.610928348
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1494984184
Short name T536
Test name
Test status
Simulation time 55244746 ps
CPU time 0.69 seconds
Started Jul 12 06:26:58 PM PDT 24
Finished Jul 12 06:26:59 PM PDT 24
Peak memory 206540 kb
Host smart-d5769b6a-f7c5-4241-a828-ace9b120819b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494984184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1494984184
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.4221927731
Short name T1017
Test name
Test status
Simulation time 488412487 ps
CPU time 6.36 seconds
Started Jul 12 06:27:10 PM PDT 24
Finished Jul 12 06:27:17 PM PDT 24
Peak memory 235888 kb
Host smart-871168e3-2867-4fd4-bd0b-e431a2d6bd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221927731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.4221927731
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.142665899
Short name T496
Test name
Test status
Simulation time 13244912 ps
CPU time 0.78 seconds
Started Jul 12 06:27:15 PM PDT 24
Finished Jul 12 06:27:18 PM PDT 24
Peak memory 206712 kb
Host smart-8e1ee689-3b61-40e0-a922-cdc4a7aed873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142665899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.142665899
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3458073511
Short name T664
Test name
Test status
Simulation time 6947154623 ps
CPU time 7.16 seconds
Started Jul 12 06:27:14 PM PDT 24
Finished Jul 12 06:27:24 PM PDT 24
Peak memory 225620 kb
Host smart-8aa59411-2ba4-4c90-8bee-2b764339dc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458073511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3458073511
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2970626150
Short name T346
Test name
Test status
Simulation time 51088957 ps
CPU time 0.74 seconds
Started Jul 12 06:27:06 PM PDT 24
Finished Jul 12 06:27:08 PM PDT 24
Peak memory 207488 kb
Host smart-9d347704-1981-4e1e-be07-f57301fcec84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970626150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2970626150
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2563674560
Short name T174
Test name
Test status
Simulation time 192318842627 ps
CPU time 275.69 seconds
Started Jul 12 06:27:13 PM PDT 24
Finished Jul 12 06:31:51 PM PDT 24
Peak memory 251208 kb
Host smart-9c6afdaf-718f-4ffd-bddf-725497fb57ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563674560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2563674560
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1128827882
Short name T282
Test name
Test status
Simulation time 53633467435 ps
CPU time 136.55 seconds
Started Jul 12 06:27:13 PM PDT 24
Finished Jul 12 06:29:32 PM PDT 24
Peak memory 245284 kb
Host smart-91ccfa62-2da4-42b7-a612-616e82b77ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128827882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1128827882
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1609953088
Short name T299
Test name
Test status
Simulation time 38760366623 ps
CPU time 380.89 seconds
Started Jul 12 06:27:13 PM PDT 24
Finished Jul 12 06:33:35 PM PDT 24
Peak memory 251020 kb
Host smart-0a6f73dd-330b-4860-affb-38e1cfe41e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609953088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1609953088
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1979711202
Short name T78
Test name
Test status
Simulation time 5338189497 ps
CPU time 14.61 seconds
Started Jul 12 06:27:19 PM PDT 24
Finished Jul 12 06:27:35 PM PDT 24
Peak memory 233856 kb
Host smart-c6a4ec4d-41ab-4ef7-b392-7a7aac0f65c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979711202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1979711202
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.145192501
Short name T918
Test name
Test status
Simulation time 105140089442 ps
CPU time 165.93 seconds
Started Jul 12 06:27:14 PM PDT 24
Finished Jul 12 06:30:02 PM PDT 24
Peak memory 250720 kb
Host smart-c476842f-359a-46ad-a364-f3676bd7d7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145192501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.145192501
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2361810171
Short name T1013
Test name
Test status
Simulation time 166547768 ps
CPU time 2.07 seconds
Started Jul 12 06:27:06 PM PDT 24
Finished Jul 12 06:27:09 PM PDT 24
Peak memory 233476 kb
Host smart-019cd0bc-052c-422e-b5cb-b0e0a6356a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361810171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2361810171
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2967723789
Short name T503
Test name
Test status
Simulation time 12695954118 ps
CPU time 16.83 seconds
Started Jul 12 06:27:14 PM PDT 24
Finished Jul 12 06:27:34 PM PDT 24
Peak memory 239480 kb
Host smart-f9a6807a-c5fc-432d-a5a9-67f0105a8e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967723789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2967723789
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3415927439
Short name T853
Test name
Test status
Simulation time 143411297 ps
CPU time 2.26 seconds
Started Jul 12 06:27:05 PM PDT 24
Finished Jul 12 06:27:08 PM PDT 24
Peak memory 223924 kb
Host smart-c0f9f3c3-a687-49f3-8c34-883ba9589ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415927439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3415927439
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1217203490
Short name T791
Test name
Test status
Simulation time 38340726370 ps
CPU time 31.02 seconds
Started Jul 12 06:27:05 PM PDT 24
Finished Jul 12 06:27:37 PM PDT 24
Peak memory 225680 kb
Host smart-da981211-eab9-45b1-8c68-528690043986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217203490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1217203490
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2638484045
Short name T827
Test name
Test status
Simulation time 2472365742 ps
CPU time 8.2 seconds
Started Jul 12 06:27:13 PM PDT 24
Finished Jul 12 06:27:24 PM PDT 24
Peak memory 222720 kb
Host smart-fbc58a99-3851-4bf4-8cc0-c04c7583922a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2638484045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2638484045
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1713447551
Short name T195
Test name
Test status
Simulation time 231775495601 ps
CPU time 558.24 seconds
Started Jul 12 06:27:14 PM PDT 24
Finished Jul 12 06:36:35 PM PDT 24
Peak memory 265552 kb
Host smart-a669ba58-16ac-46d7-9d6e-697f941be191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713447551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1713447551
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.844761046
Short name T844
Test name
Test status
Simulation time 2429616609 ps
CPU time 12.56 seconds
Started Jul 12 06:27:06 PM PDT 24
Finished Jul 12 06:27:19 PM PDT 24
Peak memory 217528 kb
Host smart-cb9a2589-e423-4b65-9385-b342eaa89084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844761046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.844761046
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2148344902
Short name T86
Test name
Test status
Simulation time 4992735782 ps
CPU time 16.9 seconds
Started Jul 12 06:27:05 PM PDT 24
Finished Jul 12 06:27:22 PM PDT 24
Peak memory 217436 kb
Host smart-7d9631aa-8a60-4255-94b3-7daae5146af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148344902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2148344902
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1573105602
Short name T646
Test name
Test status
Simulation time 241006201 ps
CPU time 1.45 seconds
Started Jul 12 06:27:07 PM PDT 24
Finished Jul 12 06:27:10 PM PDT 24
Peak memory 217348 kb
Host smart-b68006d0-7c77-460a-be58-821b87afd671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573105602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1573105602
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3331628175
Short name T359
Test name
Test status
Simulation time 29412430 ps
CPU time 0.82 seconds
Started Jul 12 06:27:06 PM PDT 24
Finished Jul 12 06:27:08 PM PDT 24
Peak memory 206952 kb
Host smart-03ada71f-28f2-4d3e-9e29-7b9e5fb5e0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331628175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3331628175
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2743182164
Short name T990
Test name
Test status
Simulation time 618744562 ps
CPU time 5.01 seconds
Started Jul 12 06:27:14 PM PDT 24
Finished Jul 12 06:27:21 PM PDT 24
Peak memory 225492 kb
Host smart-feaaa94d-6da1-457a-b252-933483b02f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743182164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2743182164
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3808003111
Short name T529
Test name
Test status
Simulation time 11090682 ps
CPU time 0.71 seconds
Started Jul 12 06:27:20 PM PDT 24
Finished Jul 12 06:27:22 PM PDT 24
Peak memory 205740 kb
Host smart-11974431-6613-432a-b9a0-960d63356344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808003111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3808003111
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1389307450
Short name T934
Test name
Test status
Simulation time 236535733 ps
CPU time 5.06 seconds
Started Jul 12 06:27:21 PM PDT 24
Finished Jul 12 06:27:27 PM PDT 24
Peak memory 233716 kb
Host smart-3d9fe321-b9ed-44e2-96a3-a265fc700f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389307450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1389307450
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2404055648
Short name T441
Test name
Test status
Simulation time 14734881 ps
CPU time 0.8 seconds
Started Jul 12 06:27:13 PM PDT 24
Finished Jul 12 06:27:16 PM PDT 24
Peak memory 207844 kb
Host smart-1cd1ee8d-d25e-49fa-a6b0-4d59d7a5217e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404055648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2404055648
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3577566837
Short name T259
Test name
Test status
Simulation time 9048951658 ps
CPU time 115.43 seconds
Started Jul 12 06:27:22 PM PDT 24
Finished Jul 12 06:29:19 PM PDT 24
Peak memory 270616 kb
Host smart-e5099765-bce7-492a-86ca-69955f81ba27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577566837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3577566837
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2565360340
Short name T1020
Test name
Test status
Simulation time 3545234739 ps
CPU time 65.61 seconds
Started Jul 12 06:27:22 PM PDT 24
Finished Jul 12 06:28:29 PM PDT 24
Peak memory 250100 kb
Host smart-0d96838a-7940-4adf-b69c-f75b65f6c462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565360340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2565360340
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1872861057
Short name T283
Test name
Test status
Simulation time 91861648794 ps
CPU time 183.2 seconds
Started Jul 12 06:27:20 PM PDT 24
Finished Jul 12 06:30:25 PM PDT 24
Peak memory 271884 kb
Host smart-9fe0b57d-4ae9-4c64-ba40-6ec656e37ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872861057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1872861057
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2836217633
Short name T332
Test name
Test status
Simulation time 442061760 ps
CPU time 2.57 seconds
Started Jul 12 06:27:19 PM PDT 24
Finished Jul 12 06:27:23 PM PDT 24
Peak memory 219792 kb
Host smart-66841535-0b4e-4c82-8378-1ae6cac09fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836217633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2836217633
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2036435968
Short name T478
Test name
Test status
Simulation time 7989335294 ps
CPU time 35.38 seconds
Started Jul 12 06:27:21 PM PDT 24
Finished Jul 12 06:27:58 PM PDT 24
Peak memory 250312 kb
Host smart-661461f7-0ad4-4122-9ea9-e4700a7ef72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036435968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2036435968
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2620708806
Short name T633
Test name
Test status
Simulation time 2305786377 ps
CPU time 12.96 seconds
Started Jul 12 06:27:19 PM PDT 24
Finished Jul 12 06:27:33 PM PDT 24
Peak memory 225636 kb
Host smart-58f27cc8-b41e-4783-907b-a648d16e92ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620708806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2620708806
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.442122583
Short name T1012
Test name
Test status
Simulation time 8531346005 ps
CPU time 27.96 seconds
Started Jul 12 06:27:19 PM PDT 24
Finished Jul 12 06:27:48 PM PDT 24
Peak memory 241160 kb
Host smart-48e303d8-d168-4708-b947-cc9790c859ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442122583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.442122583
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.609312776
Short name T194
Test name
Test status
Simulation time 44499456344 ps
CPU time 9.42 seconds
Started Jul 12 06:27:13 PM PDT 24
Finished Jul 12 06:27:26 PM PDT 24
Peak memory 225640 kb
Host smart-39321803-25bf-4bc0-9da0-4c9383284377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609312776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.609312776
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.147418008
Short name T253
Test name
Test status
Simulation time 416720716 ps
CPU time 6.12 seconds
Started Jul 12 06:27:13 PM PDT 24
Finished Jul 12 06:27:22 PM PDT 24
Peak memory 233676 kb
Host smart-21932616-9095-4b39-86d3-0bcc803fcb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147418008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.147418008
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4089275112
Short name T620
Test name
Test status
Simulation time 1696072512 ps
CPU time 9.74 seconds
Started Jul 12 06:27:20 PM PDT 24
Finished Jul 12 06:27:31 PM PDT 24
Peak memory 222640 kb
Host smart-721e981d-201e-422c-9ab2-80754633b2c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4089275112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4089275112
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2862570693
Short name T14
Test name
Test status
Simulation time 26906963351 ps
CPU time 38.42 seconds
Started Jul 12 06:27:21 PM PDT 24
Finished Jul 12 06:28:02 PM PDT 24
Peak memory 225764 kb
Host smart-5f16650e-5014-4299-8e98-141b1a1a1c8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862570693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2862570693
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2115983688
Short name T537
Test name
Test status
Simulation time 794198983 ps
CPU time 6.09 seconds
Started Jul 12 06:27:13 PM PDT 24
Finished Jul 12 06:27:22 PM PDT 24
Peak memory 217300 kb
Host smart-185486dd-e907-4ffe-a154-bbacf4b16d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115983688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2115983688
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1064664218
Short name T848
Test name
Test status
Simulation time 3982413647 ps
CPU time 11.87 seconds
Started Jul 12 06:27:15 PM PDT 24
Finished Jul 12 06:27:29 PM PDT 24
Peak memory 217464 kb
Host smart-820e7dd8-5321-4b5a-9903-b99a9a240a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064664218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1064664218
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1499394070
Short name T556
Test name
Test status
Simulation time 131635473 ps
CPU time 1.08 seconds
Started Jul 12 06:27:12 PM PDT 24
Finished Jul 12 06:27:15 PM PDT 24
Peak memory 207968 kb
Host smart-24f391f3-8549-4d47-8dca-9d184cf01be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499394070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1499394070
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1803868671
Short name T24
Test name
Test status
Simulation time 27294789 ps
CPU time 0.73 seconds
Started Jul 12 06:27:13 PM PDT 24
Finished Jul 12 06:27:17 PM PDT 24
Peak memory 206952 kb
Host smart-87f663a5-6153-41c7-9d7a-ba5abf618e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803868671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1803868671
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3646209439
Short name T910
Test name
Test status
Simulation time 237163148 ps
CPU time 2.35 seconds
Started Jul 12 06:27:20 PM PDT 24
Finished Jul 12 06:27:24 PM PDT 24
Peak memory 228644 kb
Host smart-f0625b25-d91e-4752-99dc-c061981ad43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646209439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3646209439
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2443668520
Short name T683
Test name
Test status
Simulation time 10392232 ps
CPU time 0.7 seconds
Started Jul 12 06:27:28 PM PDT 24
Finished Jul 12 06:27:31 PM PDT 24
Peak memory 205780 kb
Host smart-6e23451f-7120-45b8-8cd8-212e3f3af7d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443668520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2443668520
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2635328873
Short name T190
Test name
Test status
Simulation time 243812112 ps
CPU time 4.71 seconds
Started Jul 12 06:27:26 PM PDT 24
Finished Jul 12 06:27:32 PM PDT 24
Peak memory 225504 kb
Host smart-3e9b72a6-9764-4718-8f5b-f0b21cd09260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635328873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2635328873
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1361499557
Short name T1000
Test name
Test status
Simulation time 58540538 ps
CPU time 0.76 seconds
Started Jul 12 06:27:20 PM PDT 24
Finished Jul 12 06:27:23 PM PDT 24
Peak memory 207484 kb
Host smart-8a5334f9-d640-48f8-b098-b0f5d45ece99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361499557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1361499557
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.4141251609
Short name T228
Test name
Test status
Simulation time 986296085 ps
CPU time 18.97 seconds
Started Jul 12 06:27:26 PM PDT 24
Finished Jul 12 06:27:47 PM PDT 24
Peak memory 250340 kb
Host smart-47013b1c-5822-4164-922f-0ede690fe2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141251609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.4141251609
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3550542901
Short name T315
Test name
Test status
Simulation time 255911248233 ps
CPU time 199.37 seconds
Started Jul 12 06:27:29 PM PDT 24
Finished Jul 12 06:30:50 PM PDT 24
Peak memory 268596 kb
Host smart-d8835f47-bd47-45a3-b5bf-f32c747283c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550542901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3550542901
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1015343084
Short name T957
Test name
Test status
Simulation time 12219786322 ps
CPU time 80.74 seconds
Started Jul 12 06:27:27 PM PDT 24
Finished Jul 12 06:28:49 PM PDT 24
Peak memory 258564 kb
Host smart-d9433ac5-c414-4481-b156-8884da3f303c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015343084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1015343084
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2398053341
Short name T731
Test name
Test status
Simulation time 8039239926 ps
CPU time 28.29 seconds
Started Jul 12 06:27:30 PM PDT 24
Finished Jul 12 06:28:00 PM PDT 24
Peak memory 240372 kb
Host smart-6824f352-46d1-4761-b58a-82a80e6c2448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398053341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2398053341
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.801950015
Short name T611
Test name
Test status
Simulation time 4614395033 ps
CPU time 27.86 seconds
Started Jul 12 06:27:29 PM PDT 24
Finished Jul 12 06:27:59 PM PDT 24
Peak memory 257384 kb
Host smart-e0784643-1132-4f8e-b321-26c7506e77cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801950015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.801950015
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1678178696
Short name T235
Test name
Test status
Simulation time 343248612 ps
CPU time 5.25 seconds
Started Jul 12 06:27:21 PM PDT 24
Finished Jul 12 06:27:27 PM PDT 24
Peak memory 233700 kb
Host smart-bd57edb7-358b-408f-9ef0-c7545858fca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678178696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1678178696
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2251148478
Short name T265
Test name
Test status
Simulation time 45749710917 ps
CPU time 92.36 seconds
Started Jul 12 06:27:28 PM PDT 24
Finished Jul 12 06:29:01 PM PDT 24
Peak memory 241968 kb
Host smart-28feeda0-155b-4732-b4a8-293a6a0f0f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251148478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2251148478
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.168139140
Short name T515
Test name
Test status
Simulation time 1198857428 ps
CPU time 5.56 seconds
Started Jul 12 06:27:22 PM PDT 24
Finished Jul 12 06:27:29 PM PDT 24
Peak memory 237308 kb
Host smart-a38e81e0-5d7f-4d3b-91a5-8a9deb6c9e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168139140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.168139140
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1659980640
Short name T981
Test name
Test status
Simulation time 168845235 ps
CPU time 2.52 seconds
Started Jul 12 06:27:20 PM PDT 24
Finished Jul 12 06:27:24 PM PDT 24
Peak memory 233464 kb
Host smart-38029715-7c01-4211-a327-686c79de821d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659980640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1659980640
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2306838420
Short name T452
Test name
Test status
Simulation time 174951322 ps
CPU time 4.45 seconds
Started Jul 12 06:27:27 PM PDT 24
Finished Jul 12 06:27:32 PM PDT 24
Peak memory 219784 kb
Host smart-e276f41d-c811-4554-865b-0d41d5a499e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2306838420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2306838420
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2193882905
Short name T523
Test name
Test status
Simulation time 117175443960 ps
CPU time 285.25 seconds
Started Jul 12 06:27:30 PM PDT 24
Finished Jul 12 06:32:17 PM PDT 24
Peak memory 258616 kb
Host smart-86790c15-469a-4954-9ad7-bbf5a97b60c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193882905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2193882905
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3386098834
Short name T313
Test name
Test status
Simulation time 3557939465 ps
CPU time 10.85 seconds
Started Jul 12 06:27:22 PM PDT 24
Finished Jul 12 06:27:34 PM PDT 24
Peak memory 221308 kb
Host smart-2ad78583-0e4b-4a93-a783-590122e2e046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386098834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3386098834
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3737656893
Short name T375
Test name
Test status
Simulation time 834994436 ps
CPU time 2.52 seconds
Started Jul 12 06:27:21 PM PDT 24
Finished Jul 12 06:27:24 PM PDT 24
Peak memory 217288 kb
Host smart-a3f04b65-ac28-4af3-a6ac-a44c4c7c3c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737656893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3737656893
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.4011256592
Short name T323
Test name
Test status
Simulation time 55806802 ps
CPU time 1.19 seconds
Started Jul 12 06:27:23 PM PDT 24
Finished Jul 12 06:27:26 PM PDT 24
Peak memory 217340 kb
Host smart-f903cc3a-19a1-464b-8a6c-0d274350c8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011256592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.4011256592
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3390257356
Short name T576
Test name
Test status
Simulation time 69129007 ps
CPU time 0.75 seconds
Started Jul 12 06:27:21 PM PDT 24
Finished Jul 12 06:27:24 PM PDT 24
Peak memory 206944 kb
Host smart-38371ba2-9f31-48e0-b5e8-85c9fd7ee5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390257356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3390257356
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.4152970738
Short name T616
Test name
Test status
Simulation time 165008259 ps
CPU time 3.31 seconds
Started Jul 12 06:27:29 PM PDT 24
Finished Jul 12 06:27:34 PM PDT 24
Peak memory 225492 kb
Host smart-e23e5c62-7267-4739-96f9-a41ff8ff7120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152970738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.4152970738
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2334579725
Short name T599
Test name
Test status
Simulation time 38186612 ps
CPU time 0.74 seconds
Started Jul 12 06:27:32 PM PDT 24
Finished Jul 12 06:27:34 PM PDT 24
Peak memory 206684 kb
Host smart-f1e17236-d7c8-4d05-ab31-4f888db74712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334579725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2334579725
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1049093037
Short name T787
Test name
Test status
Simulation time 33523019 ps
CPU time 2.03 seconds
Started Jul 12 06:27:36 PM PDT 24
Finished Jul 12 06:27:39 PM PDT 24
Peak memory 225512 kb
Host smart-b882d7c3-603a-4111-b0ee-7fffce8c8c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049093037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1049093037
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3296434930
Short name T815
Test name
Test status
Simulation time 81780338 ps
CPU time 0.78 seconds
Started Jul 12 06:27:27 PM PDT 24
Finished Jul 12 06:27:29 PM PDT 24
Peak memory 207476 kb
Host smart-543759f9-4d99-4da6-8466-781a9f5a37b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296434930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3296434930
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1127058953
Short name T1003
Test name
Test status
Simulation time 84142353051 ps
CPU time 171.38 seconds
Started Jul 12 06:27:34 PM PDT 24
Finished Jul 12 06:30:27 PM PDT 24
Peak memory 256608 kb
Host smart-eeb25689-efc4-404c-9320-de610f7ab63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127058953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1127058953
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.4233229508
Short name T388
Test name
Test status
Simulation time 12014483584 ps
CPU time 16.97 seconds
Started Jul 12 06:27:38 PM PDT 24
Finished Jul 12 06:27:56 PM PDT 24
Peak memory 218648 kb
Host smart-c1f22a35-16ce-49b1-8d1d-65d56eb6af2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233229508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.4233229508
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3669910029
Short name T872
Test name
Test status
Simulation time 18249924865 ps
CPU time 80.24 seconds
Started Jul 12 06:27:33 PM PDT 24
Finished Jul 12 06:28:54 PM PDT 24
Peak memory 265420 kb
Host smart-b6ff83a2-2722-4fd5-ae92-bcfc47f69bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669910029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3669910029
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1170165999
Short name T820
Test name
Test status
Simulation time 1081873098 ps
CPU time 6.16 seconds
Started Jul 12 06:27:34 PM PDT 24
Finished Jul 12 06:27:42 PM PDT 24
Peak memory 225564 kb
Host smart-3c862136-25df-4b32-a8a2-4fb5c674690f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170165999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1170165999
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3935006316
Short name T91
Test name
Test status
Simulation time 6379355100 ps
CPU time 14.08 seconds
Started Jul 12 06:27:35 PM PDT 24
Finished Jul 12 06:27:51 PM PDT 24
Peak memory 225624 kb
Host smart-7eafd35c-aaf8-4414-9761-07a78c7f255e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935006316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3935006316
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1809195530
Short name T135
Test name
Test status
Simulation time 333850581 ps
CPU time 4.32 seconds
Started Jul 12 06:27:33 PM PDT 24
Finished Jul 12 06:27:39 PM PDT 24
Peak memory 233712 kb
Host smart-3a2f40ff-cce8-4960-ad6f-258afe2ae8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809195530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1809195530
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1869509812
Short name T249
Test name
Test status
Simulation time 767412777 ps
CPU time 3.93 seconds
Started Jul 12 06:27:34 PM PDT 24
Finished Jul 12 06:27:39 PM PDT 24
Peak memory 225456 kb
Host smart-ec1ea9a4-5eaf-46a3-8acb-58b156947c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869509812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1869509812
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3184706844
Short name T665
Test name
Test status
Simulation time 5206757324 ps
CPU time 7.85 seconds
Started Jul 12 06:27:40 PM PDT 24
Finished Jul 12 06:27:49 PM PDT 24
Peak memory 223696 kb
Host smart-cefb5487-b4ce-40be-be35-bcfabbe79561
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3184706844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3184706844
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.4261742093
Short name T961
Test name
Test status
Simulation time 17050791584 ps
CPU time 19.64 seconds
Started Jul 12 06:27:28 PM PDT 24
Finished Jul 12 06:27:49 PM PDT 24
Peak memory 217424 kb
Host smart-3a6ec4e2-bd78-40f2-9d0c-6c8fa6aa11b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261742093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.4261742093
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1951867304
Short name T974
Test name
Test status
Simulation time 2955697788 ps
CPU time 3.44 seconds
Started Jul 12 06:27:28 PM PDT 24
Finished Jul 12 06:27:33 PM PDT 24
Peak memory 217420 kb
Host smart-26996d98-2bb2-4812-a8c1-3554702941d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951867304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1951867304
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3912540897
Short name T512
Test name
Test status
Simulation time 13219137 ps
CPU time 0.75 seconds
Started Jul 12 06:27:29 PM PDT 24
Finished Jul 12 06:27:32 PM PDT 24
Peak memory 206944 kb
Host smart-5d43dcef-34d6-4408-8300-39116001f545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912540897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3912540897
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.453902767
Short name T695
Test name
Test status
Simulation time 205788148 ps
CPU time 0.77 seconds
Started Jul 12 06:27:28 PM PDT 24
Finished Jul 12 06:27:30 PM PDT 24
Peak memory 206884 kb
Host smart-15763e94-a10f-48fd-94c4-162be00e1cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453902767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.453902767
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2329633027
Short name T254
Test name
Test status
Simulation time 805585411 ps
CPU time 6.05 seconds
Started Jul 12 06:27:36 PM PDT 24
Finished Jul 12 06:27:43 PM PDT 24
Peak memory 237672 kb
Host smart-e92e7d77-e00d-4969-8b5d-82509156690e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329633027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2329633027
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2093377137
Short name T1024
Test name
Test status
Simulation time 14546908 ps
CPU time 0.7 seconds
Started Jul 12 06:27:49 PM PDT 24
Finished Jul 12 06:27:51 PM PDT 24
Peak memory 206360 kb
Host smart-6eaab698-54e5-4853-b282-d083ed62e897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093377137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2093377137
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3519085358
Short name T632
Test name
Test status
Simulation time 1892000528 ps
CPU time 17.42 seconds
Started Jul 12 06:27:39 PM PDT 24
Finished Jul 12 06:27:58 PM PDT 24
Peak memory 225556 kb
Host smart-8c179901-d5af-4be1-912e-f911369dcddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519085358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3519085358
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2871535343
Short name T824
Test name
Test status
Simulation time 40770397 ps
CPU time 0.78 seconds
Started Jul 12 06:27:35 PM PDT 24
Finished Jul 12 06:27:37 PM PDT 24
Peak memory 206784 kb
Host smart-3b072d49-6af5-4178-8754-59a3465fc165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871535343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2871535343
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1722734397
Short name T296
Test name
Test status
Simulation time 22833192247 ps
CPU time 108.28 seconds
Started Jul 12 06:27:41 PM PDT 24
Finished Jul 12 06:29:31 PM PDT 24
Peak memory 256336 kb
Host smart-00f1c01c-0d38-4b5e-a851-706e2a1ce0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722734397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1722734397
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3769217386
Short name T268
Test name
Test status
Simulation time 3557950340 ps
CPU time 84.29 seconds
Started Jul 12 06:27:41 PM PDT 24
Finished Jul 12 06:29:07 PM PDT 24
Peak memory 264992 kb
Host smart-c3b60fb1-c911-4cce-b59b-3c5ef02ff772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769217386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3769217386
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2067142150
Short name T659
Test name
Test status
Simulation time 9854001052 ps
CPU time 87.43 seconds
Started Jul 12 06:27:42 PM PDT 24
Finished Jul 12 06:29:11 PM PDT 24
Peak memory 240712 kb
Host smart-6b34e1e4-2752-482e-ac3c-80d2a1dee60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067142150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2067142150
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3656666189
Short name T1030
Test name
Test status
Simulation time 1003195569 ps
CPU time 16.2 seconds
Started Jul 12 06:27:43 PM PDT 24
Finished Jul 12 06:28:01 PM PDT 24
Peak memory 241736 kb
Host smart-17d5ed35-191f-4fe4-9d1d-ca7f19209d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656666189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3656666189
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.4025196168
Short name T973
Test name
Test status
Simulation time 17004077979 ps
CPU time 59.65 seconds
Started Jul 12 06:27:43 PM PDT 24
Finished Jul 12 06:28:44 PM PDT 24
Peak memory 254204 kb
Host smart-cd95736e-5fea-44dd-b376-b525b13fc6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025196168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.4025196168
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1586969472
Short name T327
Test name
Test status
Simulation time 699159871 ps
CPU time 10.92 seconds
Started Jul 12 06:27:52 PM PDT 24
Finished Jul 12 06:28:04 PM PDT 24
Peak memory 225464 kb
Host smart-597fff93-3c1a-402b-be96-5d98a04ac15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586969472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1586969472
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3815079212
Short name T1008
Test name
Test status
Simulation time 32743733 ps
CPU time 2.46 seconds
Started Jul 12 06:27:40 PM PDT 24
Finished Jul 12 06:27:44 PM PDT 24
Peak memory 233488 kb
Host smart-d2abb2d9-4aa5-467c-a61d-58049f9330c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815079212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3815079212
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.715695758
Short name T2
Test name
Test status
Simulation time 9900937830 ps
CPU time 11.17 seconds
Started Jul 12 06:27:41 PM PDT 24
Finished Jul 12 06:27:54 PM PDT 24
Peak memory 240656 kb
Host smart-2fc6d535-919e-4231-98d8-b34dfe37dadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715695758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.715695758
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1112539735
Short name T404
Test name
Test status
Simulation time 11531418130 ps
CPU time 11.42 seconds
Started Jul 12 06:27:42 PM PDT 24
Finished Jul 12 06:27:55 PM PDT 24
Peak memory 225716 kb
Host smart-aff34dcb-e5b8-48a0-b915-e85ea3e7466d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112539735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1112539735
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1172412728
Short name T992
Test name
Test status
Simulation time 3239440667 ps
CPU time 17.09 seconds
Started Jul 12 06:27:43 PM PDT 24
Finished Jul 12 06:28:02 PM PDT 24
Peak memory 223220 kb
Host smart-21780ad3-3756-4d95-af38-2078d7e59836
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1172412728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1172412728
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3832138472
Short name T963
Test name
Test status
Simulation time 54528008 ps
CPU time 1.06 seconds
Started Jul 12 06:27:42 PM PDT 24
Finished Jul 12 06:27:44 PM PDT 24
Peak memory 208048 kb
Host smart-34bc50a9-5f23-4880-88a6-8ceb7ec4713a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832138472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3832138472
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.70792163
Short name T655
Test name
Test status
Simulation time 28122744 ps
CPU time 0.72 seconds
Started Jul 12 06:27:47 PM PDT 24
Finished Jul 12 06:27:48 PM PDT 24
Peak memory 206612 kb
Host smart-81322c36-8faa-4e13-961d-bff5c45a3025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70792163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.70792163
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.434645830
Short name T393
Test name
Test status
Simulation time 2249222552 ps
CPU time 10.58 seconds
Started Jul 12 06:27:36 PM PDT 24
Finished Jul 12 06:27:48 PM PDT 24
Peak memory 217448 kb
Host smart-0ccd775e-ec31-4d2b-94bd-1c3a7727dd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434645830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.434645830
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1848152663
Short name T363
Test name
Test status
Simulation time 87930630 ps
CPU time 2.1 seconds
Started Jul 12 06:27:43 PM PDT 24
Finished Jul 12 06:27:47 PM PDT 24
Peak memory 217488 kb
Host smart-83426649-db6b-4dda-a8b5-326c13675c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848152663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1848152663
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.585552810
Short name T930
Test name
Test status
Simulation time 46707618 ps
CPU time 0.81 seconds
Started Jul 12 06:27:42 PM PDT 24
Finished Jul 12 06:27:44 PM PDT 24
Peak memory 206948 kb
Host smart-3bfb175c-e91b-47d6-819c-0117f21081a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585552810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.585552810
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.702469048
Short name T486
Test name
Test status
Simulation time 303646255 ps
CPU time 3.81 seconds
Started Jul 12 06:27:43 PM PDT 24
Finished Jul 12 06:27:48 PM PDT 24
Peak memory 225520 kb
Host smart-f05bd78b-352b-438d-9309-d81b0b63311d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702469048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.702469048
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3660597350
Short name T380
Test name
Test status
Simulation time 64195151 ps
CPU time 0.76 seconds
Started Jul 12 06:27:59 PM PDT 24
Finished Jul 12 06:28:03 PM PDT 24
Peak memory 206372 kb
Host smart-bd3c2e23-f0d5-4704-b6f2-26f1e766d4b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660597350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3660597350
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3786469670
Short name T778
Test name
Test status
Simulation time 264325087 ps
CPU time 2.81 seconds
Started Jul 12 06:27:51 PM PDT 24
Finished Jul 12 06:27:55 PM PDT 24
Peak memory 225520 kb
Host smart-d87f47f4-f02b-4c73-87a6-57a11d82bda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786469670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3786469670
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1381019750
Short name T348
Test name
Test status
Simulation time 41298125 ps
CPU time 0.77 seconds
Started Jul 12 06:27:49 PM PDT 24
Finished Jul 12 06:27:51 PM PDT 24
Peak memory 207488 kb
Host smart-7db07300-79fe-4535-821d-54cbda26763b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381019750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1381019750
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1138744696
Short name T554
Test name
Test status
Simulation time 649927470 ps
CPU time 11.43 seconds
Started Jul 12 06:27:56 PM PDT 24
Finished Jul 12 06:28:09 PM PDT 24
Peak memory 235116 kb
Host smart-6bcbfa54-e3ad-4fd0-9175-4cbd77d20da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138744696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1138744696
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2424526464
Short name T902
Test name
Test status
Simulation time 271292129788 ps
CPU time 562.48 seconds
Started Jul 12 06:27:50 PM PDT 24
Finished Jul 12 06:37:14 PM PDT 24
Peak memory 270860 kb
Host smart-57d92f36-b531-43fb-91b1-e24a277addaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424526464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2424526464
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2630846024
Short name T314
Test name
Test status
Simulation time 1452377157 ps
CPU time 10.98 seconds
Started Jul 12 06:27:51 PM PDT 24
Finished Jul 12 06:28:04 PM PDT 24
Peak memory 218700 kb
Host smart-313cebaf-ef2d-429a-bcfe-d5e5b6422016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630846024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2630846024
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3714164684
Short name T723
Test name
Test status
Simulation time 12934630292 ps
CPU time 24.61 seconds
Started Jul 12 06:27:50 PM PDT 24
Finished Jul 12 06:28:16 PM PDT 24
Peak memory 233904 kb
Host smart-ad5099e4-6b22-49ff-a3fb-0c4f754fc352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714164684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3714164684
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.4116296570
Short name T136
Test name
Test status
Simulation time 1025669141 ps
CPU time 6.13 seconds
Started Jul 12 06:27:48 PM PDT 24
Finished Jul 12 06:27:56 PM PDT 24
Peak memory 233764 kb
Host smart-0dfad26c-2982-45e9-8368-0a458200ea2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116296570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.4116296570
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.976284965
Short name T1010
Test name
Test status
Simulation time 525041848 ps
CPU time 3.45 seconds
Started Jul 12 06:27:56 PM PDT 24
Finished Jul 12 06:28:01 PM PDT 24
Peak memory 225512 kb
Host smart-b8d226c0-6630-411b-ab5b-fb27a6918de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976284965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.976284965
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.478388454
Short name T6
Test name
Test status
Simulation time 227711804 ps
CPU time 3.2 seconds
Started Jul 12 06:27:56 PM PDT 24
Finished Jul 12 06:28:01 PM PDT 24
Peak memory 225556 kb
Host smart-aa18f78c-cf4c-44f1-a75c-b62d0a94bafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478388454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.478388454
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1661682209
Short name T865
Test name
Test status
Simulation time 622660873 ps
CPU time 3.06 seconds
Started Jul 12 06:27:51 PM PDT 24
Finished Jul 12 06:27:56 PM PDT 24
Peak memory 225496 kb
Host smart-d2458b1d-4797-4e62-b0f1-1cf480ca265d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661682209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1661682209
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3599067235
Short name T42
Test name
Test status
Simulation time 547252334 ps
CPU time 5.11 seconds
Started Jul 12 06:27:49 PM PDT 24
Finished Jul 12 06:27:56 PM PDT 24
Peak memory 220924 kb
Host smart-29bbc299-9079-4121-bc9a-8a25c8f56212
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3599067235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3599067235
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1866050337
Short name T989
Test name
Test status
Simulation time 15228174461 ps
CPU time 191.53 seconds
Started Jul 12 06:27:59 PM PDT 24
Finished Jul 12 06:31:14 PM PDT 24
Peak memory 250420 kb
Host smart-4f434219-0351-4e1d-bd78-adb0f988f784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866050337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1866050337
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2855758201
Short name T137
Test name
Test status
Simulation time 3870806560 ps
CPU time 32.78 seconds
Started Jul 12 06:27:50 PM PDT 24
Finished Jul 12 06:28:24 PM PDT 24
Peak memory 217412 kb
Host smart-f953ba5d-8cda-458c-a87a-84b9eb953cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855758201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2855758201
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3460799115
Short name T716
Test name
Test status
Simulation time 7035359483 ps
CPU time 4.45 seconds
Started Jul 12 06:27:48 PM PDT 24
Finished Jul 12 06:27:54 PM PDT 24
Peak memory 217448 kb
Host smart-b45b14d3-c81e-48cb-a87d-9ba26ac89571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460799115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3460799115
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2357789493
Short name T545
Test name
Test status
Simulation time 156449037 ps
CPU time 1.6 seconds
Started Jul 12 06:27:50 PM PDT 24
Finished Jul 12 06:27:54 PM PDT 24
Peak memory 208952 kb
Host smart-59413d48-5123-4a69-90f0-6f2d9299606c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357789493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2357789493
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2174378106
Short name T915
Test name
Test status
Simulation time 68015860 ps
CPU time 0.84 seconds
Started Jul 12 06:27:50 PM PDT 24
Finished Jul 12 06:27:53 PM PDT 24
Peak memory 207184 kb
Host smart-389db403-d4b7-42b4-bcf9-2a8545a40da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174378106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2174378106
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1483268397
Short name T682
Test name
Test status
Simulation time 242895272 ps
CPU time 3.41 seconds
Started Jul 12 06:27:50 PM PDT 24
Finished Jul 12 06:27:55 PM PDT 24
Peak memory 233704 kb
Host smart-566a262e-dbd6-4cfd-89fe-206387c6e531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483268397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1483268397
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1098559528
Short name T762
Test name
Test status
Simulation time 37723087 ps
CPU time 0.69 seconds
Started Jul 12 06:27:57 PM PDT 24
Finished Jul 12 06:27:59 PM PDT 24
Peak memory 206344 kb
Host smart-92ae7527-69e1-40b5-9ae7-64aae13878bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098559528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1098559528
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.4112360940
Short name T360
Test name
Test status
Simulation time 142327753 ps
CPU time 2.47 seconds
Started Jul 12 06:28:00 PM PDT 24
Finished Jul 12 06:28:06 PM PDT 24
Peak memory 233436 kb
Host smart-bf5bcd6f-9a1c-4508-be7e-b2da0c6fdaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112360940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.4112360940
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2961271940
Short name T413
Test name
Test status
Simulation time 41111729 ps
CPU time 0.76 seconds
Started Jul 12 06:27:59 PM PDT 24
Finished Jul 12 06:28:03 PM PDT 24
Peak memory 207500 kb
Host smart-1ff7aadd-fdde-43b3-ac8a-71407acc0939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961271940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2961271940
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2593403379
Short name T890
Test name
Test status
Simulation time 26810644348 ps
CPU time 187.73 seconds
Started Jul 12 06:27:58 PM PDT 24
Finished Jul 12 06:31:08 PM PDT 24
Peak memory 253368 kb
Host smart-9dd11ecc-8e81-4ec5-bba0-273f2eabba35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593403379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2593403379
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1915278042
Short name T260
Test name
Test status
Simulation time 17024436627 ps
CPU time 136.11 seconds
Started Jul 12 06:27:59 PM PDT 24
Finished Jul 12 06:30:19 PM PDT 24
Peak memory 253056 kb
Host smart-f8f77975-04f9-4c21-9b5d-69c5b9ee3caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915278042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1915278042
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1565020765
Short name T232
Test name
Test status
Simulation time 26707104349 ps
CPU time 115.79 seconds
Started Jul 12 06:27:58 PM PDT 24
Finished Jul 12 06:29:57 PM PDT 24
Peak memory 256660 kb
Host smart-129c9564-b3ed-4173-a1c2-6b81af13c1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565020765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1565020765
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3033749044
Short name T304
Test name
Test status
Simulation time 1118307005 ps
CPU time 8.42 seconds
Started Jul 12 06:27:58 PM PDT 24
Finished Jul 12 06:28:10 PM PDT 24
Peak memory 233740 kb
Host smart-79e42d02-2fab-4f7e-a911-e67d3f401d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033749044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3033749044
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2063185189
Short name T185
Test name
Test status
Simulation time 51650625897 ps
CPU time 137.45 seconds
Started Jul 12 06:27:59 PM PDT 24
Finished Jul 12 06:30:20 PM PDT 24
Peak memory 258464 kb
Host smart-54345413-1455-4738-96d0-05d0fea09e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063185189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2063185189
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3489476258
Short name T681
Test name
Test status
Simulation time 5269307702 ps
CPU time 7.86 seconds
Started Jul 12 06:28:01 PM PDT 24
Finished Jul 12 06:28:12 PM PDT 24
Peak memory 225632 kb
Host smart-806eae7b-6a9a-4b85-b170-371c3d1f38ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489476258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3489476258
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3774879935
Short name T643
Test name
Test status
Simulation time 6691143066 ps
CPU time 14.93 seconds
Started Jul 12 06:27:58 PM PDT 24
Finished Jul 12 06:28:15 PM PDT 24
Peak memory 233876 kb
Host smart-23b1ca4a-1814-40a6-a469-c6a57fcb3073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774879935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3774879935
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2566837256
Short name T426
Test name
Test status
Simulation time 2805157784 ps
CPU time 8.18 seconds
Started Jul 12 06:27:59 PM PDT 24
Finished Jul 12 06:28:11 PM PDT 24
Peak memory 233896 kb
Host smart-11b1de30-c796-4eda-95f2-6a2f36dc3101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566837256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2566837256
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2594320294
Short name T869
Test name
Test status
Simulation time 8304556911 ps
CPU time 9.91 seconds
Started Jul 12 06:27:56 PM PDT 24
Finished Jul 12 06:28:07 PM PDT 24
Peak memory 233824 kb
Host smart-7acd85b2-b0ec-4e05-b63a-4515d21a8051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594320294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2594320294
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.795400577
Short name T494
Test name
Test status
Simulation time 696574201 ps
CPU time 10.31 seconds
Started Jul 12 06:27:58 PM PDT 24
Finished Jul 12 06:28:11 PM PDT 24
Peak memory 221360 kb
Host smart-92e0aabb-ac16-42cc-8127-e54eef2ae961
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=795400577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.795400577
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1523410539
Short name T163
Test name
Test status
Simulation time 44844109 ps
CPU time 0.95 seconds
Started Jul 12 06:28:00 PM PDT 24
Finished Jul 12 06:28:04 PM PDT 24
Peak memory 207556 kb
Host smart-b6eb7fbe-5ae9-463e-a66c-92f0dd12f6ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523410539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1523410539
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3135853243
Short name T546
Test name
Test status
Simulation time 3040478613 ps
CPU time 25.4 seconds
Started Jul 12 06:27:58 PM PDT 24
Finished Jul 12 06:28:26 PM PDT 24
Peak memory 217500 kb
Host smart-5089cc38-aece-4afc-836a-86365dbb0ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135853243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3135853243
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3917409024
Short name T729
Test name
Test status
Simulation time 5473508332 ps
CPU time 14.59 seconds
Started Jul 12 06:27:59 PM PDT 24
Finished Jul 12 06:28:17 PM PDT 24
Peak memory 217516 kb
Host smart-4989f0f5-c5f8-4329-b2c1-50429c3fe3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917409024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3917409024
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2875527348
Short name T527
Test name
Test status
Simulation time 197732319 ps
CPU time 1.98 seconds
Started Jul 12 06:27:59 PM PDT 24
Finished Jul 12 06:28:05 PM PDT 24
Peak memory 217320 kb
Host smart-428a9bcd-0d48-43a8-91d8-168b3010433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875527348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2875527348
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2469030080
Short name T355
Test name
Test status
Simulation time 23762938 ps
CPU time 0.82 seconds
Started Jul 12 06:27:59 PM PDT 24
Finished Jul 12 06:28:03 PM PDT 24
Peak memory 206964 kb
Host smart-5dcfc135-b655-46ec-a007-ae422d30ffe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469030080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2469030080
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3404033389
Short name T832
Test name
Test status
Simulation time 521807036 ps
CPU time 6.83 seconds
Started Jul 12 06:27:57 PM PDT 24
Finished Jul 12 06:28:06 PM PDT 24
Peak memory 233716 kb
Host smart-bb2d5864-4bfc-474d-8906-c06cdbdf059c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404033389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3404033389
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3589659630
Short name T569
Test name
Test status
Simulation time 42037740 ps
CPU time 0.72 seconds
Started Jul 12 06:28:03 PM PDT 24
Finished Jul 12 06:28:06 PM PDT 24
Peak memory 206352 kb
Host smart-5ad0f79d-a353-49a4-b421-409ca891c4e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589659630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3589659630
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3547807421
Short name T188
Test name
Test status
Simulation time 504328307 ps
CPU time 8.28 seconds
Started Jul 12 06:28:07 PM PDT 24
Finished Jul 12 06:28:17 PM PDT 24
Peak memory 233748 kb
Host smart-bad61ce7-8546-42a3-b194-32f6b947d310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547807421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3547807421
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3435260691
Short name T371
Test name
Test status
Simulation time 42625553 ps
CPU time 0.76 seconds
Started Jul 12 06:28:06 PM PDT 24
Finished Jul 12 06:28:08 PM PDT 24
Peak memory 206456 kb
Host smart-2a290df7-7ac6-4c4e-b433-0dda48e8e357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435260691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3435260691
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2622690004
Short name T601
Test name
Test status
Simulation time 29852997722 ps
CPU time 108.96 seconds
Started Jul 12 06:28:06 PM PDT 24
Finished Jul 12 06:29:57 PM PDT 24
Peak memory 250224 kb
Host smart-bc0f4963-534b-45cc-82c2-1ea9c75ea8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622690004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2622690004
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3051788318
Short name T500
Test name
Test status
Simulation time 12210076487 ps
CPU time 90.67 seconds
Started Jul 12 06:28:07 PM PDT 24
Finished Jul 12 06:29:40 PM PDT 24
Peak memory 258576 kb
Host smart-bbefea1a-0712-48ae-88e1-04208bbfee04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051788318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3051788318
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2470569329
Short name T150
Test name
Test status
Simulation time 4320024933 ps
CPU time 73.91 seconds
Started Jul 12 06:28:04 PM PDT 24
Finished Jul 12 06:29:20 PM PDT 24
Peak memory 250556 kb
Host smart-2165cdb5-060e-4dbf-9720-aa841e7e174d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470569329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2470569329
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1881639784
Short name T804
Test name
Test status
Simulation time 186348654 ps
CPU time 5.43 seconds
Started Jul 12 06:28:07 PM PDT 24
Finished Jul 12 06:28:14 PM PDT 24
Peak memory 233752 kb
Host smart-94b35360-2965-43aa-8638-b6021a1d3cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881639784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1881639784
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3050362405
Short name T269
Test name
Test status
Simulation time 1885858426 ps
CPU time 11.53 seconds
Started Jul 12 06:28:05 PM PDT 24
Finished Jul 12 06:28:18 PM PDT 24
Peak memory 233692 kb
Host smart-51a85b5a-d676-49cd-b747-56a99b298c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050362405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3050362405
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.593881321
Short name T510
Test name
Test status
Simulation time 513311904 ps
CPU time 11.76 seconds
Started Jul 12 06:28:03 PM PDT 24
Finished Jul 12 06:28:17 PM PDT 24
Peak memory 250116 kb
Host smart-48c8d25f-cfce-4b88-a0a6-284911e0a2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593881321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.593881321
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1856298886
Short name T903
Test name
Test status
Simulation time 281407045 ps
CPU time 2.33 seconds
Started Jul 12 06:28:04 PM PDT 24
Finished Jul 12 06:28:08 PM PDT 24
Peak memory 224148 kb
Host smart-bcac2a1a-a7f5-4910-b47f-2d415b33cf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856298886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1856298886
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1731424008
Short name T563
Test name
Test status
Simulation time 3790300957 ps
CPU time 10.4 seconds
Started Jul 12 06:28:07 PM PDT 24
Finished Jul 12 06:28:20 PM PDT 24
Peak memory 220288 kb
Host smart-f28d7b46-770a-46cd-9cbe-a114c39a4852
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1731424008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1731424008
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2579746039
Short name T745
Test name
Test status
Simulation time 17267477003 ps
CPU time 55.47 seconds
Started Jul 12 06:28:04 PM PDT 24
Finished Jul 12 06:29:02 PM PDT 24
Peak memory 250396 kb
Host smart-5d6d7c5b-045e-44f9-96b5-4b35edfbb878
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579746039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2579746039
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.567176338
Short name T361
Test name
Test status
Simulation time 1985532459 ps
CPU time 3.94 seconds
Started Jul 12 06:28:05 PM PDT 24
Finished Jul 12 06:28:11 PM PDT 24
Peak memory 217328 kb
Host smart-64288f87-dfb2-4239-b2e0-3203d339aaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567176338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.567176338
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3608214378
Short name T852
Test name
Test status
Simulation time 35162709662 ps
CPU time 18.87 seconds
Started Jul 12 06:28:08 PM PDT 24
Finished Jul 12 06:28:28 PM PDT 24
Peak memory 217512 kb
Host smart-4b3f2e16-d759-4062-a28b-0f4985f08fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608214378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3608214378
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.815475429
Short name T586
Test name
Test status
Simulation time 11072664 ps
CPU time 0.72 seconds
Started Jul 12 06:28:04 PM PDT 24
Finished Jul 12 06:28:07 PM PDT 24
Peak memory 206492 kb
Host smart-77bdb4a5-82c8-47e4-ae4d-63dfa19a03f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815475429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.815475429
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3147867639
Short name T771
Test name
Test status
Simulation time 99114030 ps
CPU time 0.83 seconds
Started Jul 12 06:28:05 PM PDT 24
Finished Jul 12 06:28:08 PM PDT 24
Peak memory 206872 kb
Host smart-2bfbcc4c-b83b-4540-8767-84ad2bb0bb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147867639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3147867639
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.712975898
Short name T609
Test name
Test status
Simulation time 20473445785 ps
CPU time 16.08 seconds
Started Jul 12 06:28:04 PM PDT 24
Finished Jul 12 06:28:22 PM PDT 24
Peak memory 225680 kb
Host smart-53a13731-ba93-41ee-aa8c-60b5eb64e729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712975898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.712975898
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1281914101
Short name T783
Test name
Test status
Simulation time 24557354 ps
CPU time 0.74 seconds
Started Jul 12 06:28:12 PM PDT 24
Finished Jul 12 06:28:14 PM PDT 24
Peak memory 206284 kb
Host smart-21db76e8-3511-4635-8d9f-5dee338a9135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281914101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1281914101
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.279321878
Short name T738
Test name
Test status
Simulation time 1349647464 ps
CPU time 3.99 seconds
Started Jul 12 06:28:12 PM PDT 24
Finished Jul 12 06:28:17 PM PDT 24
Peak memory 233784 kb
Host smart-9c11e25c-eae8-4798-a7cc-1d70c3ee6d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279321878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.279321878
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3974716912
Short name T728
Test name
Test status
Simulation time 21616154 ps
CPU time 0.76 seconds
Started Jul 12 06:28:06 PM PDT 24
Finished Jul 12 06:28:09 PM PDT 24
Peak memory 207440 kb
Host smart-09f89711-447f-4b0c-b07b-96454ff8116e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974716912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3974716912
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3649009632
Short name T516
Test name
Test status
Simulation time 30433915676 ps
CPU time 55.68 seconds
Started Jul 12 06:28:11 PM PDT 24
Finished Jul 12 06:29:08 PM PDT 24
Peak memory 239276 kb
Host smart-cb75bbe7-7127-445a-8e63-7edd1ff1198d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649009632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3649009632
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2956663237
Short name T555
Test name
Test status
Simulation time 330117429 ps
CPU time 4.34 seconds
Started Jul 12 06:28:14 PM PDT 24
Finished Jul 12 06:28:20 PM PDT 24
Peak memory 218720 kb
Host smart-f0abae1e-631b-487c-9404-bece14c0303c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956663237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2956663237
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2640423305
Short name T658
Test name
Test status
Simulation time 27140274191 ps
CPU time 241.25 seconds
Started Jul 12 06:28:15 PM PDT 24
Finished Jul 12 06:32:18 PM PDT 24
Peak memory 256180 kb
Host smart-1b723320-06d8-400f-b9cc-32167da942f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640423305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2640423305
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1874002761
Short name T950
Test name
Test status
Simulation time 3397446976 ps
CPU time 15.92 seconds
Started Jul 12 06:28:14 PM PDT 24
Finished Jul 12 06:28:32 PM PDT 24
Peak memory 238000 kb
Host smart-b7b9efbf-4a68-41b8-87ae-8dad6bc864c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874002761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1874002761
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.935769066
Short name T279
Test name
Test status
Simulation time 25869544791 ps
CPU time 227.82 seconds
Started Jul 12 06:28:13 PM PDT 24
Finished Jul 12 06:32:02 PM PDT 24
Peak memory 266652 kb
Host smart-28526015-75a0-4721-81d8-a19746fab374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935769066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.935769066
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.8344328
Short name T115
Test name
Test status
Simulation time 2181552601 ps
CPU time 5.1 seconds
Started Jul 12 06:28:14 PM PDT 24
Finished Jul 12 06:28:20 PM PDT 24
Peak memory 233884 kb
Host smart-a8ed320a-c559-40cc-916d-f57e0dc9fbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8344328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.8344328
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.368676037
Short name T538
Test name
Test status
Simulation time 9489774123 ps
CPU time 35.12 seconds
Started Jul 12 06:28:13 PM PDT 24
Finished Jul 12 06:28:49 PM PDT 24
Peak memory 234876 kb
Host smart-2cfdaa0e-29c5-4251-a41e-27980e86b549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368676037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.368676037
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1627835052
Short name T607
Test name
Test status
Simulation time 4342945079 ps
CPU time 13.9 seconds
Started Jul 12 06:28:14 PM PDT 24
Finished Jul 12 06:28:29 PM PDT 24
Peak memory 233892 kb
Host smart-871911de-7555-4702-8056-eaa333cf9a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627835052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1627835052
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2312889369
Short name T92
Test name
Test status
Simulation time 6120856138 ps
CPU time 19.21 seconds
Started Jul 12 06:28:12 PM PDT 24
Finished Jul 12 06:28:32 PM PDT 24
Peak memory 240876 kb
Host smart-4a894825-7249-4749-87d6-79a927eb2fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312889369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2312889369
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1763140087
Short name T913
Test name
Test status
Simulation time 231148256 ps
CPU time 5.45 seconds
Started Jul 12 06:28:12 PM PDT 24
Finished Jul 12 06:28:18 PM PDT 24
Peak memory 223880 kb
Host smart-140aeec4-105b-42f5-a55c-a8b941c2d3b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1763140087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1763140087
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2691197669
Short name T164
Test name
Test status
Simulation time 13864273607 ps
CPU time 154.58 seconds
Started Jul 12 06:28:14 PM PDT 24
Finished Jul 12 06:30:50 PM PDT 24
Peak memory 250324 kb
Host smart-7437ab76-162a-4c91-8308-f154a97b1bb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691197669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2691197669
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3951412087
Short name T498
Test name
Test status
Simulation time 5113985592 ps
CPU time 27.69 seconds
Started Jul 12 06:28:06 PM PDT 24
Finished Jul 12 06:28:36 PM PDT 24
Peak memory 217460 kb
Host smart-4470a93d-18dd-4daa-8707-d952de539151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951412087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3951412087
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.963712714
Short name T707
Test name
Test status
Simulation time 393168655 ps
CPU time 2.11 seconds
Started Jul 12 06:28:08 PM PDT 24
Finished Jul 12 06:28:12 PM PDT 24
Peak memory 217096 kb
Host smart-303f805f-bef3-4fc0-91f3-f03f11231ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963712714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.963712714
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.843618752
Short name T715
Test name
Test status
Simulation time 165654405 ps
CPU time 1.34 seconds
Started Jul 12 06:28:13 PM PDT 24
Finished Jul 12 06:28:16 PM PDT 24
Peak memory 217380 kb
Host smart-3225f4ea-f59d-4a03-95ed-b573126278bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843618752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.843618752
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.4078389982
Short name T964
Test name
Test status
Simulation time 25905540 ps
CPU time 0.77 seconds
Started Jul 12 06:28:13 PM PDT 24
Finished Jul 12 06:28:15 PM PDT 24
Peak memory 206944 kb
Host smart-8d7fba34-130a-461a-93d1-b4a97ea5c46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078389982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.4078389982
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3311138957
Short name T247
Test name
Test status
Simulation time 2225704771 ps
CPU time 9.87 seconds
Started Jul 12 06:28:14 PM PDT 24
Finished Jul 12 06:28:26 PM PDT 24
Peak memory 233812 kb
Host smart-97165b2d-0484-4dbd-8cd4-617daf76d4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311138957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3311138957
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2878992792
Short name T997
Test name
Test status
Simulation time 44568373 ps
CPU time 0.69 seconds
Started Jul 12 06:22:50 PM PDT 24
Finished Jul 12 06:22:53 PM PDT 24
Peak memory 206372 kb
Host smart-4ff21dfb-9a47-47a8-8a70-8b0b64e8f1c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878992792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
878992792
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.496015468
Short name T74
Test name
Test status
Simulation time 737021003 ps
CPU time 3.87 seconds
Started Jul 12 06:22:50 PM PDT 24
Finished Jul 12 06:22:56 PM PDT 24
Peak memory 233720 kb
Host smart-d213897f-5205-4607-b9b4-6e10718c8ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496015468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.496015468
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2204909471
Short name T28
Test name
Test status
Simulation time 46288190 ps
CPU time 0.78 seconds
Started Jul 12 06:22:41 PM PDT 24
Finished Jul 12 06:22:43 PM PDT 24
Peak memory 207800 kb
Host smart-307f0c8f-c228-469d-9231-e94bd0604536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204909471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2204909471
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3455877066
Short name T200
Test name
Test status
Simulation time 60367626313 ps
CPU time 408.31 seconds
Started Jul 12 06:22:49 PM PDT 24
Finished Jul 12 06:29:38 PM PDT 24
Peak memory 266536 kb
Host smart-4e8ee440-dae6-4e02-ba72-69d365007737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455877066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3455877066
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2716271229
Short name T927
Test name
Test status
Simulation time 1752081604 ps
CPU time 28.24 seconds
Started Jul 12 06:22:51 PM PDT 24
Finished Jul 12 06:23:21 PM PDT 24
Peak memory 250236 kb
Host smart-5baaf6ac-858f-4246-aab7-ff625a9a2c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716271229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2716271229
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2435960449
Short name T875
Test name
Test status
Simulation time 13994409270 ps
CPU time 134.31 seconds
Started Jul 12 06:22:53 PM PDT 24
Finished Jul 12 06:25:08 PM PDT 24
Peak memory 252932 kb
Host smart-ca1d4971-a54f-4e54-b2e1-d56ae3876863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435960449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2435960449
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3814214903
Short name T899
Test name
Test status
Simulation time 624813725 ps
CPU time 6.99 seconds
Started Jul 12 06:26:21 PM PDT 24
Finished Jul 12 06:26:31 PM PDT 24
Peak memory 229692 kb
Host smart-e87566a9-3ccb-4efe-98c1-407bf130f176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814214903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3814214903
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.858685431
Short name T983
Test name
Test status
Simulation time 23360319635 ps
CPU time 64.58 seconds
Started Jul 12 06:22:45 PM PDT 24
Finished Jul 12 06:23:51 PM PDT 24
Peak memory 250264 kb
Host smart-c84629be-6104-4a1e-84a5-936b0c6120ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858685431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
858685431
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2781705185
Short name T807
Test name
Test status
Simulation time 13271484597 ps
CPU time 18.97 seconds
Started Jul 12 06:22:45 PM PDT 24
Finished Jul 12 06:23:05 PM PDT 24
Peak memory 233876 kb
Host smart-489b7d9c-dae3-490a-a781-cb9c432f0fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781705185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2781705185
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3036006303
Short name T463
Test name
Test status
Simulation time 1714557898 ps
CPU time 18.75 seconds
Started Jul 12 06:22:44 PM PDT 24
Finished Jul 12 06:23:03 PM PDT 24
Peak memory 233776 kb
Host smart-74e7f385-c45e-4d29-ac54-abb5d857f8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036006303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3036006303
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3639114286
Short name T810
Test name
Test status
Simulation time 42449913 ps
CPU time 1.06 seconds
Started Jul 12 06:22:42 PM PDT 24
Finished Jul 12 06:22:44 PM PDT 24
Peak memory 218940 kb
Host smart-f328607c-2604-432a-9924-c78b0f578f1f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639114286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3639114286
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.53559603
Short name T220
Test name
Test status
Simulation time 169949349465 ps
CPU time 25.29 seconds
Started Jul 12 06:22:50 PM PDT 24
Finished Jul 12 06:23:18 PM PDT 24
Peak memory 225580 kb
Host smart-4dec1b36-9bd1-49ec-9948-1c53cb07a8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53559603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.53559603
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2682513015
Short name T867
Test name
Test status
Simulation time 23663645954 ps
CPU time 17.21 seconds
Started Jul 12 06:22:50 PM PDT 24
Finished Jul 12 06:23:10 PM PDT 24
Peak memory 241660 kb
Host smart-da6a706e-5254-43fa-9636-7ceffff09928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682513015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2682513015
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.179094543
Short name T151
Test name
Test status
Simulation time 307831934 ps
CPU time 5.25 seconds
Started Jul 12 06:22:44 PM PDT 24
Finished Jul 12 06:22:50 PM PDT 24
Peak memory 224052 kb
Host smart-e37b4feb-1a19-4192-88c0-450c0507b3b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=179094543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.179094543
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2696157361
Short name T69
Test name
Test status
Simulation time 65922270 ps
CPU time 0.92 seconds
Started Jul 12 06:22:47 PM PDT 24
Finished Jul 12 06:22:49 PM PDT 24
Peak memory 236316 kb
Host smart-9985e88a-8199-4f68-98da-ba9456e316b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696157361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2696157361
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1638787977
Short name T814
Test name
Test status
Simulation time 452983106812 ps
CPU time 291.51 seconds
Started Jul 12 06:22:48 PM PDT 24
Finished Jul 12 06:27:41 PM PDT 24
Peak memory 256412 kb
Host smart-fcc3ade0-9b6a-4840-bf5e-3a5c92ccf183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638787977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1638787977
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2754055671
Short name T385
Test name
Test status
Simulation time 7070838150 ps
CPU time 23.91 seconds
Started Jul 12 06:22:41 PM PDT 24
Finished Jul 12 06:23:05 PM PDT 24
Peak memory 217468 kb
Host smart-5738f82c-9160-4942-b3c3-2cb6dad41dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754055671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2754055671
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2153595929
Short name T493
Test name
Test status
Simulation time 9806365465 ps
CPU time 27.96 seconds
Started Jul 12 06:22:38 PM PDT 24
Finished Jul 12 06:23:07 PM PDT 24
Peak memory 217484 kb
Host smart-2a439b03-52a7-42a6-acf8-4b64b00e1935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153595929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2153595929
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3689449418
Short name T9
Test name
Test status
Simulation time 143511399 ps
CPU time 1.99 seconds
Started Jul 12 06:22:50 PM PDT 24
Finished Jul 12 06:22:55 PM PDT 24
Peak memory 217268 kb
Host smart-46ff6b4b-4231-4a11-bd72-ce074e3c87d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689449418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3689449418
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1070814263
Short name T357
Test name
Test status
Simulation time 64807036 ps
CPU time 0.76 seconds
Started Jul 12 06:22:49 PM PDT 24
Finished Jul 12 06:22:52 PM PDT 24
Peak memory 206880 kb
Host smart-82d83b53-337f-48e7-b08d-54d9049086a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070814263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1070814263
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2166496883
Short name T62
Test name
Test status
Simulation time 1282499371 ps
CPU time 11.03 seconds
Started Jul 12 06:22:44 PM PDT 24
Finished Jul 12 06:22:55 PM PDT 24
Peak memory 241868 kb
Host smart-556b66a5-5a6b-4fbd-bc99-e4b942c34cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166496883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2166496883
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.247457933
Short name T993
Test name
Test status
Simulation time 11900897 ps
CPU time 0.72 seconds
Started Jul 12 06:28:26 PM PDT 24
Finished Jul 12 06:28:28 PM PDT 24
Peak memory 206360 kb
Host smart-9e6d049f-f2d2-4c84-80b9-26ee90119dd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247457933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.247457933
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2637668552
Short name T837
Test name
Test status
Simulation time 1806295722 ps
CPU time 21.19 seconds
Started Jul 12 06:28:19 PM PDT 24
Finished Jul 12 06:28:41 PM PDT 24
Peak memory 225516 kb
Host smart-59365bfa-abb5-4ae8-8885-a44d2cbe6d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637668552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2637668552
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4059301224
Short name T329
Test name
Test status
Simulation time 25631511 ps
CPU time 0.78 seconds
Started Jul 12 06:28:14 PM PDT 24
Finished Jul 12 06:28:16 PM PDT 24
Peak memory 207812 kb
Host smart-84928680-8fbc-4f2e-857d-befb0417d830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059301224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4059301224
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1095583897
Short name T714
Test name
Test status
Simulation time 5806829578 ps
CPU time 58.87 seconds
Started Jul 12 06:28:21 PM PDT 24
Finished Jul 12 06:29:21 PM PDT 24
Peak memory 250408 kb
Host smart-6546c433-8219-4287-b817-48913c877266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095583897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1095583897
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.66464572
Short name T605
Test name
Test status
Simulation time 5019924361 ps
CPU time 77.78 seconds
Started Jul 12 06:28:27 PM PDT 24
Finished Jul 12 06:29:45 PM PDT 24
Peak memory 254376 kb
Host smart-e6905e2d-2b6f-4018-931f-753094a8ebaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66464572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.66464572
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.688637559
Short name T574
Test name
Test status
Simulation time 965429247 ps
CPU time 10.86 seconds
Started Jul 12 06:28:21 PM PDT 24
Finished Jul 12 06:28:32 PM PDT 24
Peak memory 233792 kb
Host smart-c2374372-3f23-4b8f-8370-8b630e995d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688637559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.688637559
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.762425256
Short name T766
Test name
Test status
Simulation time 151045007 ps
CPU time 3.36 seconds
Started Jul 12 06:28:19 PM PDT 24
Finished Jul 12 06:28:23 PM PDT 24
Peak memory 225540 kb
Host smart-2b390004-622a-44b3-aaad-faabbf86670a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762425256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.762425256
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3471925568
Short name T202
Test name
Test status
Simulation time 5109392762 ps
CPU time 12.33 seconds
Started Jul 12 06:28:21 PM PDT 24
Finished Jul 12 06:28:34 PM PDT 24
Peak memory 225656 kb
Host smart-de28fbd9-4c33-4624-b4b6-7e03ea915669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471925568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3471925568
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1253163700
Short name T207
Test name
Test status
Simulation time 1033736001 ps
CPU time 7.94 seconds
Started Jul 12 06:28:20 PM PDT 24
Finished Jul 12 06:28:29 PM PDT 24
Peak memory 233748 kb
Host smart-18eee8f2-25d7-46bc-98c6-f8967ca8b2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253163700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1253163700
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1703422795
Short name T647
Test name
Test status
Simulation time 255175084 ps
CPU time 2.04 seconds
Started Jul 12 06:28:13 PM PDT 24
Finished Jul 12 06:28:16 PM PDT 24
Peak memory 225024 kb
Host smart-a2021e72-830a-4fa4-8b40-c3c2354f1695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703422795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1703422795
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4254813556
Short name T760
Test name
Test status
Simulation time 413053884 ps
CPU time 7.99 seconds
Started Jul 12 06:28:22 PM PDT 24
Finished Jul 12 06:28:31 PM PDT 24
Peak memory 223016 kb
Host smart-f784fdfb-13a7-4270-bb72-9d09b2acfec6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4254813556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4254813556
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3071505451
Short name T1007
Test name
Test status
Simulation time 261938864 ps
CPU time 1.09 seconds
Started Jul 12 06:28:28 PM PDT 24
Finished Jul 12 06:28:30 PM PDT 24
Peak memory 208028 kb
Host smart-c1b5a194-3334-4bb8-9c63-3c199890e8a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071505451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3071505451
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1342516016
Short name T378
Test name
Test status
Simulation time 11726159 ps
CPU time 0.71 seconds
Started Jul 12 06:28:13 PM PDT 24
Finished Jul 12 06:28:15 PM PDT 24
Peak memory 206612 kb
Host smart-f42d9d99-c4c1-41c8-92fa-37aa4ce61aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342516016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1342516016
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.4228839659
Short name T362
Test name
Test status
Simulation time 17820650 ps
CPU time 0.72 seconds
Started Jul 12 06:28:14 PM PDT 24
Finished Jul 12 06:28:16 PM PDT 24
Peak memory 206632 kb
Host smart-b7358149-0785-4356-b888-29a262fff0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228839659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.4228839659
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.13485026
Short name T722
Test name
Test status
Simulation time 662356007 ps
CPU time 2.95 seconds
Started Jul 12 06:28:12 PM PDT 24
Finished Jul 12 06:28:16 PM PDT 24
Peak memory 217348 kb
Host smart-9b824e9e-7deb-4a94-bad4-92cc3fd0da85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13485026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.13485026
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1500960415
Short name T505
Test name
Test status
Simulation time 85583106 ps
CPU time 0.91 seconds
Started Jul 12 06:28:12 PM PDT 24
Finished Jul 12 06:28:14 PM PDT 24
Peak memory 207976 kb
Host smart-212dedfa-c14d-4f3b-87af-8a228413979f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500960415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1500960415
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2857591691
Short name T457
Test name
Test status
Simulation time 54826078636 ps
CPU time 22.91 seconds
Started Jul 12 06:28:20 PM PDT 24
Finished Jul 12 06:28:43 PM PDT 24
Peak memory 240488 kb
Host smart-71ca8795-0d63-4acd-aaa4-ef337a7e06ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857591691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2857591691
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.4257862094
Short name T372
Test name
Test status
Simulation time 35537315 ps
CPU time 0.74 seconds
Started Jul 12 06:28:36 PM PDT 24
Finished Jul 12 06:28:37 PM PDT 24
Peak memory 205804 kb
Host smart-278afeaf-e999-4456-aa0e-d46febc07387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257862094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4257862094
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3486012292
Short name T1006
Test name
Test status
Simulation time 62222329 ps
CPU time 2.4 seconds
Started Jul 12 06:28:27 PM PDT 24
Finished Jul 12 06:28:30 PM PDT 24
Peak memory 233456 kb
Host smart-a8a0ee65-ab25-4bb6-a2fc-140f20cbc649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486012292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3486012292
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3416901208
Short name T330
Test name
Test status
Simulation time 13580375 ps
CPU time 0.82 seconds
Started Jul 12 06:28:27 PM PDT 24
Finished Jul 12 06:28:29 PM PDT 24
Peak memory 207844 kb
Host smart-4c092771-bd7d-4bd4-a7e9-90e36fc0e91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416901208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3416901208
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.532997039
Short name T856
Test name
Test status
Simulation time 51746984066 ps
CPU time 85.98 seconds
Started Jul 12 06:28:26 PM PDT 24
Finished Jul 12 06:29:52 PM PDT 24
Peak memory 250436 kb
Host smart-24f37b46-76ae-4a41-ad3c-a9c03e223a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532997039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.532997039
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2386776874
Short name T623
Test name
Test status
Simulation time 50373164322 ps
CPU time 243.38 seconds
Started Jul 12 06:28:34 PM PDT 24
Finished Jul 12 06:32:38 PM PDT 24
Peak memory 250460 kb
Host smart-00a608bc-5beb-42b5-8873-644d284aeeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386776874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2386776874
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3035646321
Short name T281
Test name
Test status
Simulation time 80422170340 ps
CPU time 763.36 seconds
Started Jul 12 06:28:36 PM PDT 24
Finished Jul 12 06:41:20 PM PDT 24
Peak memory 261280 kb
Host smart-51481c1d-f264-4bfa-8e43-0795b83364b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035646321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3035646321
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.490691412
Short name T663
Test name
Test status
Simulation time 99372515 ps
CPU time 3.79 seconds
Started Jul 12 06:28:28 PM PDT 24
Finished Jul 12 06:28:33 PM PDT 24
Peak memory 233672 kb
Host smart-42e64167-2371-44d7-b534-113448e5e3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490691412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.490691412
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2998833991
Short name T94
Test name
Test status
Simulation time 36151496706 ps
CPU time 58.83 seconds
Started Jul 12 06:28:27 PM PDT 24
Finished Jul 12 06:29:26 PM PDT 24
Peak memory 241352 kb
Host smart-c29eacc5-6f62-459c-9875-a033d30bde52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998833991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2998833991
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3760755244
Short name T456
Test name
Test status
Simulation time 1546373853 ps
CPU time 15.25 seconds
Started Jul 12 06:28:28 PM PDT 24
Finished Jul 12 06:28:44 PM PDT 24
Peak memory 231012 kb
Host smart-214521ef-b9e2-4f0c-8e84-0364e3b37420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760755244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3760755244
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.168735743
Short name T705
Test name
Test status
Simulation time 138485531 ps
CPU time 5.33 seconds
Started Jul 12 06:28:27 PM PDT 24
Finished Jul 12 06:28:33 PM PDT 24
Peak memory 225528 kb
Host smart-d36deb13-972b-4699-b03f-92cf4f3f165c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168735743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.168735743
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.4117539222
Short name T896
Test name
Test status
Simulation time 420264005 ps
CPU time 4.26 seconds
Started Jul 12 06:28:29 PM PDT 24
Finished Jul 12 06:28:34 PM PDT 24
Peak memory 233788 kb
Host smart-d9f3215c-a659-4746-b805-76888a3699c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117539222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.4117539222
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.515322150
Short name T812
Test name
Test status
Simulation time 4018952047 ps
CPU time 6.88 seconds
Started Jul 12 06:28:26 PM PDT 24
Finished Jul 12 06:28:34 PM PDT 24
Peak memory 225620 kb
Host smart-d9045515-407f-43da-b804-c5f02d495966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515322150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.515322150
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.209556766
Short name T477
Test name
Test status
Simulation time 4459303695 ps
CPU time 12.97 seconds
Started Jul 12 06:28:28 PM PDT 24
Finished Jul 12 06:28:42 PM PDT 24
Peak memory 221668 kb
Host smart-fe37d823-3fae-4b90-9c58-edaa7d8d7419
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=209556766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.209556766
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3094778356
Short name T447
Test name
Test status
Simulation time 10392060186 ps
CPU time 57.92 seconds
Started Jul 12 06:28:29 PM PDT 24
Finished Jul 12 06:29:27 PM PDT 24
Peak memory 217488 kb
Host smart-9c108341-f91e-49f1-834a-3c52991a4dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094778356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3094778356
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.179243188
Short name T564
Test name
Test status
Simulation time 1745979689 ps
CPU time 7.96 seconds
Started Jul 12 06:28:27 PM PDT 24
Finished Jul 12 06:28:37 PM PDT 24
Peak memory 217304 kb
Host smart-2950f481-7154-4f8f-9e2e-65173e6abf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179243188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.179243188
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2301110064
Short name T49
Test name
Test status
Simulation time 28643743 ps
CPU time 0.84 seconds
Started Jul 12 06:28:27 PM PDT 24
Finished Jul 12 06:28:28 PM PDT 24
Peak memory 207968 kb
Host smart-2c3cc84f-57f6-41a4-8ddf-653be327a84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301110064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2301110064
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3183848784
Short name T641
Test name
Test status
Simulation time 38393291 ps
CPU time 0.79 seconds
Started Jul 12 06:28:28 PM PDT 24
Finished Jul 12 06:28:30 PM PDT 24
Peak memory 206928 kb
Host smart-315ef7e5-fdd6-4a3d-bf3f-4ccf61252093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183848784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3183848784
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1153108388
Short name T765
Test name
Test status
Simulation time 2486391940 ps
CPU time 11.54 seconds
Started Jul 12 06:28:29 PM PDT 24
Finished Jul 12 06:28:42 PM PDT 24
Peak memory 225704 kb
Host smart-82b806cf-ce3f-4e19-afce-261dca6b3ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153108388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1153108388
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.499089457
Short name T65
Test name
Test status
Simulation time 49847366 ps
CPU time 0.74 seconds
Started Jul 12 06:28:40 PM PDT 24
Finished Jul 12 06:28:41 PM PDT 24
Peak memory 206376 kb
Host smart-470ecd3e-7c5d-4c35-bfe2-d389777b9f07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499089457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.499089457
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.278217411
Short name T1015
Test name
Test status
Simulation time 3758281526 ps
CPU time 7.33 seconds
Started Jul 12 06:28:35 PM PDT 24
Finished Jul 12 06:28:43 PM PDT 24
Peak memory 225696 kb
Host smart-e75fab54-4501-47fd-b209-16f4846ee2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278217411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.278217411
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2768239275
Short name T328
Test name
Test status
Simulation time 15778612 ps
CPU time 0.77 seconds
Started Jul 12 06:28:33 PM PDT 24
Finished Jul 12 06:28:35 PM PDT 24
Peak memory 207492 kb
Host smart-62976b98-28c1-44c7-8d8e-5dc9aeb4370d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768239275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2768239275
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.165525222
Short name T172
Test name
Test status
Simulation time 208885276839 ps
CPU time 197.62 seconds
Started Jul 12 06:28:42 PM PDT 24
Finished Jul 12 06:32:01 PM PDT 24
Peak memory 257416 kb
Host smart-b02cc681-5625-4425-94a6-c971c67140d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165525222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.165525222
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2835809401
Short name T739
Test name
Test status
Simulation time 10583029092 ps
CPU time 100.24 seconds
Started Jul 12 06:28:41 PM PDT 24
Finished Jul 12 06:30:22 PM PDT 24
Peak memory 258556 kb
Host smart-454c2ef1-0066-490c-89bf-8e3c81f48643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835809401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2835809401
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1349692649
Short name T294
Test name
Test status
Simulation time 14225876200 ps
CPU time 229.39 seconds
Started Jul 12 06:28:41 PM PDT 24
Finished Jul 12 06:32:31 PM PDT 24
Peak memory 266488 kb
Host smart-de70ca32-a6a8-4458-b74c-d3a18feab505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349692649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1349692649
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1401018035
Short name T444
Test name
Test status
Simulation time 1638801089 ps
CPU time 6.92 seconds
Started Jul 12 06:28:34 PM PDT 24
Finished Jul 12 06:28:41 PM PDT 24
Peak memory 225544 kb
Host smart-d00b08f0-fdcf-471a-9c1c-1dd01ff07185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401018035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1401018035
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.34050343
Short name T958
Test name
Test status
Simulation time 56941800754 ps
CPU time 113.94 seconds
Started Jul 12 06:28:35 PM PDT 24
Finished Jul 12 06:30:30 PM PDT 24
Peak memory 254396 kb
Host smart-4a36fadc-90c4-4d33-a2df-3b3fe58c476f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34050343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.34050343
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3153251091
Short name T833
Test name
Test status
Simulation time 99940048 ps
CPU time 2.18 seconds
Started Jul 12 06:28:35 PM PDT 24
Finished Jul 12 06:28:37 PM PDT 24
Peak memory 223960 kb
Host smart-722e8827-b599-4535-aad5-63c31c890d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153251091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3153251091
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2339734292
Short name T948
Test name
Test status
Simulation time 1386787246 ps
CPU time 14.2 seconds
Started Jul 12 06:28:34 PM PDT 24
Finished Jul 12 06:28:49 PM PDT 24
Peak memory 225516 kb
Host smart-ed279c87-74c6-41f0-a98a-fcf916d02a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339734292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2339734292
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3163476234
Short name T944
Test name
Test status
Simulation time 19308000616 ps
CPU time 8.42 seconds
Started Jul 12 06:28:35 PM PDT 24
Finished Jul 12 06:28:45 PM PDT 24
Peak memory 235712 kb
Host smart-344676f6-1e85-4e1e-823c-caf224807a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163476234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3163476234
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3228184852
Short name T242
Test name
Test status
Simulation time 1176657103 ps
CPU time 2.68 seconds
Started Jul 12 06:28:35 PM PDT 24
Finished Jul 12 06:28:38 PM PDT 24
Peak memory 225508 kb
Host smart-0637e97f-fbe1-474b-9c66-84cafb115ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228184852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3228184852
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3127059162
Short name T476
Test name
Test status
Simulation time 462454225 ps
CPU time 4.96 seconds
Started Jul 12 06:28:35 PM PDT 24
Finished Jul 12 06:28:41 PM PDT 24
Peak memory 220844 kb
Host smart-020c7cb7-1449-4339-9d22-a1f3bc0bdfe2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3127059162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3127059162
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1689670073
Short name T949
Test name
Test status
Simulation time 8641156104 ps
CPU time 154.26 seconds
Started Jul 12 06:28:44 PM PDT 24
Finished Jul 12 06:31:20 PM PDT 24
Peak memory 273536 kb
Host smart-ff4b1b64-0657-4e25-9ad4-335f1bc415aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689670073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1689670073
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1809508494
Short name T376
Test name
Test status
Simulation time 167694597 ps
CPU time 2.17 seconds
Started Jul 12 06:28:37 PM PDT 24
Finished Jul 12 06:28:40 PM PDT 24
Peak memory 217360 kb
Host smart-73b7ee9e-0695-4efa-b523-e29f049c22b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809508494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1809508494
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2858843292
Short name T688
Test name
Test status
Simulation time 27941334938 ps
CPU time 6.89 seconds
Started Jul 12 06:28:37 PM PDT 24
Finished Jul 12 06:28:44 PM PDT 24
Peak memory 217460 kb
Host smart-b83e2893-907a-408a-b13d-150fd47015b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858843292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2858843292
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.724906264
Short name T440
Test name
Test status
Simulation time 62454615 ps
CPU time 1.33 seconds
Started Jul 12 06:28:36 PM PDT 24
Finished Jul 12 06:28:38 PM PDT 24
Peak memory 217316 kb
Host smart-9f9e312c-dd57-4a0f-b27b-6a04ef5dc350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724906264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.724906264
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2232340124
Short name T617
Test name
Test status
Simulation time 53288415 ps
CPU time 0.73 seconds
Started Jul 12 06:28:34 PM PDT 24
Finished Jul 12 06:28:35 PM PDT 24
Peak memory 206764 kb
Host smart-f65d46ff-63f0-4891-a32e-0112b3eb5e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232340124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2232340124
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3909310561
Short name T595
Test name
Test status
Simulation time 2425681625 ps
CPU time 4.37 seconds
Started Jul 12 06:28:37 PM PDT 24
Finished Jul 12 06:28:42 PM PDT 24
Peak memory 225836 kb
Host smart-65288609-71ce-4a55-93cb-bc3e387d829d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909310561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3909310561
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.207779123
Short name T608
Test name
Test status
Simulation time 102026078 ps
CPU time 0.73 seconds
Started Jul 12 06:29:26 PM PDT 24
Finished Jul 12 06:29:28 PM PDT 24
Peak memory 206344 kb
Host smart-a8dc831d-116e-463c-b73b-9c2e3d446e00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207779123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.207779123
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1925801313
Short name T606
Test name
Test status
Simulation time 3153775426 ps
CPU time 10 seconds
Started Jul 12 06:28:44 PM PDT 24
Finished Jul 12 06:28:56 PM PDT 24
Peak memory 225656 kb
Host smart-093334f7-5ac2-420f-968a-47332979bbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925801313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1925801313
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.691865236
Short name T450
Test name
Test status
Simulation time 19555469 ps
CPU time 0.78 seconds
Started Jul 12 06:28:43 PM PDT 24
Finished Jul 12 06:28:46 PM PDT 24
Peak memory 207500 kb
Host smart-eb1e6081-6847-4558-9801-43b3b62a7da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691865236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.691865236
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.4170400680
Short name T781
Test name
Test status
Simulation time 17324048175 ps
CPU time 124.85 seconds
Started Jul 12 06:28:43 PM PDT 24
Finished Jul 12 06:30:49 PM PDT 24
Peak memory 254448 kb
Host smart-4f157f28-43bd-4ab6-a643-9c5a360f505e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170400680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.4170400680
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2357106614
Short name T402
Test name
Test status
Simulation time 3591593784 ps
CPU time 30.44 seconds
Started Jul 12 06:28:42 PM PDT 24
Finished Jul 12 06:29:14 PM PDT 24
Peak memory 242184 kb
Host smart-86645ac7-8469-4c1a-9a8c-7d128f2f5c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357106614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2357106614
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.238430133
Short name T193
Test name
Test status
Simulation time 3817815005 ps
CPU time 94.93 seconds
Started Jul 12 06:28:41 PM PDT 24
Finished Jul 12 06:30:18 PM PDT 24
Peak memory 258576 kb
Host smart-40e2737e-a287-43b3-9650-8db51583efee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238430133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.238430133
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.171041456
Short name T311
Test name
Test status
Simulation time 2715285969 ps
CPU time 46.41 seconds
Started Jul 12 06:28:43 PM PDT 24
Finished Jul 12 06:29:31 PM PDT 24
Peak memory 233896 kb
Host smart-554320ba-d02b-4ced-a665-050ecf81acf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171041456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.171041456
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2180568118
Short name T64
Test name
Test status
Simulation time 1866420232 ps
CPU time 32.3 seconds
Started Jul 12 06:28:41 PM PDT 24
Finished Jul 12 06:29:14 PM PDT 24
Peak memory 250832 kb
Host smart-6b7f523f-792c-4df3-81ff-c667f2b5c3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180568118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2180568118
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2813553659
Short name T379
Test name
Test status
Simulation time 4487862158 ps
CPU time 9.36 seconds
Started Jul 12 06:28:42 PM PDT 24
Finished Jul 12 06:28:53 PM PDT 24
Peak memory 225636 kb
Host smart-9bf21c7a-8e02-4a51-b1f4-604b19bce1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813553659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2813553659
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.4163494060
Short name T497
Test name
Test status
Simulation time 19492623991 ps
CPU time 49.58 seconds
Started Jul 12 06:28:42 PM PDT 24
Finished Jul 12 06:29:33 PM PDT 24
Peak memory 233860 kb
Host smart-f68f8836-7416-4cdb-98b2-baac69fbaa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163494060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4163494060
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1448015750
Short name T255
Test name
Test status
Simulation time 3082749307 ps
CPU time 10.66 seconds
Started Jul 12 06:28:44 PM PDT 24
Finished Jul 12 06:28:56 PM PDT 24
Peak memory 233892 kb
Host smart-757b7ae8-c9ff-47d8-b306-72a432c4be40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448015750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1448015750
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2933838096
Short name T567
Test name
Test status
Simulation time 34861163 ps
CPU time 2.43 seconds
Started Jul 12 06:28:43 PM PDT 24
Finished Jul 12 06:28:48 PM PDT 24
Peak memory 233456 kb
Host smart-5c70953b-c9fa-4b04-9875-edd7bcb8be1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933838096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2933838096
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.265217051
Short name T472
Test name
Test status
Simulation time 387892736 ps
CPU time 6.33 seconds
Started Jul 12 06:28:42 PM PDT 24
Finished Jul 12 06:28:49 PM PDT 24
Peak memory 224016 kb
Host smart-5a721462-e10b-41dd-8f94-318ae099c1f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=265217051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.265217051
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3680475934
Short name T321
Test name
Test status
Simulation time 110788372610 ps
CPU time 41.56 seconds
Started Jul 12 06:28:44 PM PDT 24
Finished Jul 12 06:29:27 PM PDT 24
Peak memory 217488 kb
Host smart-35a7f51d-b582-440f-a162-5d6803074e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680475934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3680475934
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.899429415
Short name T383
Test name
Test status
Simulation time 7904212665 ps
CPU time 3.07 seconds
Started Jul 12 06:28:42 PM PDT 24
Finished Jul 12 06:28:46 PM PDT 24
Peak memory 217268 kb
Host smart-21c6253b-f498-4ef4-9844-a84375f950a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899429415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.899429415
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1209761552
Short name T325
Test name
Test status
Simulation time 25044188 ps
CPU time 1.01 seconds
Started Jul 12 06:28:42 PM PDT 24
Finished Jul 12 06:28:45 PM PDT 24
Peak memory 208312 kb
Host smart-d58491b3-e62c-4ad2-8e93-10175a0c032c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209761552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1209761552
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.327442949
Short name T514
Test name
Test status
Simulation time 34795383 ps
CPU time 0.85 seconds
Started Jul 12 06:28:44 PM PDT 24
Finished Jul 12 06:28:46 PM PDT 24
Peak memory 206976 kb
Host smart-375f0aec-f360-421a-8c5d-b797b42ef8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327442949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.327442949
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.62810714
Short name T206
Test name
Test status
Simulation time 2408165523 ps
CPU time 6.14 seconds
Started Jul 12 06:28:43 PM PDT 24
Finished Jul 12 06:28:51 PM PDT 24
Peak memory 233852 kb
Host smart-115cc43e-90cf-4891-aad5-18e1cda4d00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62810714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.62810714
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.628535353
Short name T334
Test name
Test status
Simulation time 47547014 ps
CPU time 0.71 seconds
Started Jul 12 06:28:50 PM PDT 24
Finished Jul 12 06:28:51 PM PDT 24
Peak memory 206388 kb
Host smart-3e1ec7b6-eacb-4f6f-97b8-68974ef573f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628535353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.628535353
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1005972795
Short name T786
Test name
Test status
Simulation time 1094457415 ps
CPU time 9.91 seconds
Started Jul 12 06:28:50 PM PDT 24
Finished Jul 12 06:29:01 PM PDT 24
Peak memory 233744 kb
Host smart-f7b1ac1d-1da3-4c52-86f7-114ec484dd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005972795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1005972795
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.670484515
Short name T429
Test name
Test status
Simulation time 36048313 ps
CPU time 0.78 seconds
Started Jul 12 06:28:51 PM PDT 24
Finished Jul 12 06:28:52 PM PDT 24
Peak memory 207472 kb
Host smart-edbbf1c6-294d-4279-b812-817dd45d6486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670484515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.670484515
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1725453716
Short name T661
Test name
Test status
Simulation time 2915746646 ps
CPU time 26.45 seconds
Started Jul 12 06:28:50 PM PDT 24
Finished Jul 12 06:29:18 PM PDT 24
Peak memory 236188 kb
Host smart-04afa7e0-5af7-430c-9ac9-f89f556e6513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725453716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1725453716
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3933012282
Short name T256
Test name
Test status
Simulation time 11322167238 ps
CPU time 148.53 seconds
Started Jul 12 06:28:49 PM PDT 24
Finished Jul 12 06:31:18 PM PDT 24
Peak memory 255848 kb
Host smart-d2703907-dcd0-487f-b756-a27ca6893b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933012282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3933012282
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4110912178
Short name T777
Test name
Test status
Simulation time 69343500298 ps
CPU time 244.39 seconds
Started Jul 12 06:28:48 PM PDT 24
Finished Jul 12 06:32:54 PM PDT 24
Peak memory 266636 kb
Host smart-d7498dbc-56db-440e-8aff-ab2ef89a7908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110912178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4110912178
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1098173615
Short name T337
Test name
Test status
Simulation time 500920951 ps
CPU time 3.33 seconds
Started Jul 12 06:28:52 PM PDT 24
Finished Jul 12 06:28:56 PM PDT 24
Peak memory 225484 kb
Host smart-c044cf7c-9f50-4b4e-af2a-a5c2f3d85709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098173615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1098173615
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1527140979
Short name T303
Test name
Test status
Simulation time 208780509857 ps
CPU time 377.79 seconds
Started Jul 12 06:28:55 PM PDT 24
Finished Jul 12 06:35:14 PM PDT 24
Peak memory 265060 kb
Host smart-080614a7-0de1-4767-9ebd-b371c28e78b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527140979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1527140979
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1636024666
Short name T277
Test name
Test status
Simulation time 437693193 ps
CPU time 8.33 seconds
Started Jul 12 06:28:48 PM PDT 24
Finished Jul 12 06:28:58 PM PDT 24
Peak memory 225520 kb
Host smart-6e62e631-de16-4334-a99c-faa638604910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636024666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1636024666
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.4121074143
Short name T868
Test name
Test status
Simulation time 4518026077 ps
CPU time 15.8 seconds
Started Jul 12 06:28:49 PM PDT 24
Finished Jul 12 06:29:05 PM PDT 24
Peak memory 228308 kb
Host smart-b88863ad-5976-415a-96e6-415bb65d46f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121074143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.4121074143
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2787346691
Short name T711
Test name
Test status
Simulation time 871602128 ps
CPU time 5.61 seconds
Started Jul 12 06:28:52 PM PDT 24
Finished Jul 12 06:28:58 PM PDT 24
Peak memory 225460 kb
Host smart-3c9279f2-e7d7-43fe-8c89-8acf6c0cbcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787346691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2787346691
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1503667170
Short name T943
Test name
Test status
Simulation time 5245912372 ps
CPU time 10.61 seconds
Started Jul 12 06:28:51 PM PDT 24
Finished Jul 12 06:29:02 PM PDT 24
Peak memory 233860 kb
Host smart-c031b9ad-4355-4a95-a788-585623d89dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503667170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1503667170
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3409539074
Short name T689
Test name
Test status
Simulation time 1825290436 ps
CPU time 6.34 seconds
Started Jul 12 06:28:49 PM PDT 24
Finished Jul 12 06:28:56 PM PDT 24
Peak memory 221544 kb
Host smart-a434ad19-7d52-47ed-8ac0-3db5a953d61e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3409539074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3409539074
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1611418160
Short name T292
Test name
Test status
Simulation time 114641544494 ps
CPU time 393.22 seconds
Started Jul 12 06:28:50 PM PDT 24
Finished Jul 12 06:35:24 PM PDT 24
Peak memory 250428 kb
Host smart-c3767bde-559c-467f-9b84-5f56eb2da1e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611418160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1611418160
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2076693043
Short name T408
Test name
Test status
Simulation time 19322430072 ps
CPU time 48.75 seconds
Started Jul 12 06:28:54 PM PDT 24
Finished Jul 12 06:29:43 PM PDT 24
Peak memory 217512 kb
Host smart-2f1f9683-b5c9-488c-b279-8160debe056c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076693043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2076693043
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1675663713
Short name T87
Test name
Test status
Simulation time 644784674 ps
CPU time 3.79 seconds
Started Jul 12 06:28:50 PM PDT 24
Finished Jul 12 06:28:54 PM PDT 24
Peak memory 217316 kb
Host smart-cbfa400d-38b4-4e58-9660-ffe791f7fb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675663713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1675663713
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.4249173458
Short name T342
Test name
Test status
Simulation time 190957272 ps
CPU time 3.06 seconds
Started Jul 12 06:28:49 PM PDT 24
Finished Jul 12 06:28:53 PM PDT 24
Peak memory 217396 kb
Host smart-5dd0faa6-9701-4505-9312-7c90783e2908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249173458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.4249173458
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.896703361
Short name T513
Test name
Test status
Simulation time 10302658 ps
CPU time 0.69 seconds
Started Jul 12 06:28:49 PM PDT 24
Finished Jul 12 06:28:50 PM PDT 24
Peak memory 206504 kb
Host smart-f14e9839-decc-48b6-a00e-cb610cded727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896703361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.896703361
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2809001693
Short name T244
Test name
Test status
Simulation time 13539054922 ps
CPU time 12.09 seconds
Started Jul 12 06:28:50 PM PDT 24
Finished Jul 12 06:29:03 PM PDT 24
Peak memory 233852 kb
Host smart-53c9cee4-75fd-4d48-9ba1-4a75d9971441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809001693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2809001693
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1323880698
Short name T697
Test name
Test status
Simulation time 32836410 ps
CPU time 0.78 seconds
Started Jul 12 06:28:57 PM PDT 24
Finished Jul 12 06:28:59 PM PDT 24
Peak memory 206556 kb
Host smart-5d764112-5783-4c7a-89fc-39cce74d3105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323880698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1323880698
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2945767312
Short name T543
Test name
Test status
Simulation time 315397151 ps
CPU time 2.23 seconds
Started Jul 12 06:28:59 PM PDT 24
Finished Jul 12 06:29:02 PM PDT 24
Peak memory 225560 kb
Host smart-a181bf18-d5bf-499a-91b6-f1bf7df02352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945767312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2945767312
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.869605411
Short name T552
Test name
Test status
Simulation time 25039735 ps
CPU time 0.82 seconds
Started Jul 12 06:28:50 PM PDT 24
Finished Jul 12 06:28:52 PM PDT 24
Peak memory 207500 kb
Host smart-cba90ecc-5d12-4bb0-b933-03de0e6e2b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869605411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.869605411
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2682478731
Short name T23
Test name
Test status
Simulation time 29941677678 ps
CPU time 106.64 seconds
Started Jul 12 06:28:56 PM PDT 24
Finished Jul 12 06:30:44 PM PDT 24
Peak memory 254532 kb
Host smart-bd903bbc-126e-450c-8f18-f5793e0536ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682478731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2682478731
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.923779140
Short name T524
Test name
Test status
Simulation time 8152464867 ps
CPU time 86.79 seconds
Started Jul 12 06:28:55 PM PDT 24
Finished Jul 12 06:30:23 PM PDT 24
Peak memory 250356 kb
Host smart-c475affa-6aca-4677-ad01-a21990bd87a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923779140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.923779140
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2005557772
Short name T35
Test name
Test status
Simulation time 84852661097 ps
CPU time 451.92 seconds
Started Jul 12 06:28:59 PM PDT 24
Finished Jul 12 06:36:32 PM PDT 24
Peak memory 253148 kb
Host smart-6f531f2a-9f54-40a8-b5c6-12e6f2798858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005557772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2005557772
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1084290249
Short name T448
Test name
Test status
Simulation time 763824745 ps
CPU time 5.14 seconds
Started Jul 12 06:28:56 PM PDT 24
Finished Jul 12 06:29:03 PM PDT 24
Peak memory 233736 kb
Host smart-a8405ff0-7145-4017-9dab-c6d68f6c8e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084290249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1084290249
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2473928537
Short name T1009
Test name
Test status
Simulation time 16579496371 ps
CPU time 108.95 seconds
Started Jul 12 06:28:55 PM PDT 24
Finished Jul 12 06:30:45 PM PDT 24
Peak memory 266620 kb
Host smart-6d1eca3e-0d27-4749-9e94-9d4782e9b047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473928537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2473928537
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.308845127
Short name T264
Test name
Test status
Simulation time 160078273 ps
CPU time 2.91 seconds
Started Jul 12 06:28:57 PM PDT 24
Finished Jul 12 06:29:01 PM PDT 24
Peak memory 219800 kb
Host smart-c5be60e7-457b-440b-977e-51e76002a8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308845127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.308845127
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1100128977
Short name T748
Test name
Test status
Simulation time 23003319753 ps
CPU time 56.25 seconds
Started Jul 12 06:28:57 PM PDT 24
Finished Jul 12 06:29:55 PM PDT 24
Peak memory 241412 kb
Host smart-93037290-bbf4-4486-963f-d435b47ba591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100128977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1100128977
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3024801094
Short name T507
Test name
Test status
Simulation time 2102425742 ps
CPU time 9.61 seconds
Started Jul 12 06:28:56 PM PDT 24
Finished Jul 12 06:29:07 PM PDT 24
Peak memory 233692 kb
Host smart-a7b707d0-0398-46a0-a6b7-be6b53ed3d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024801094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3024801094
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2002576800
Short name T998
Test name
Test status
Simulation time 3667724861 ps
CPU time 9.73 seconds
Started Jul 12 06:28:56 PM PDT 24
Finished Jul 12 06:29:07 PM PDT 24
Peak memory 233904 kb
Host smart-abef12e3-cb01-42f9-9d8f-4bd0709414e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002576800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2002576800
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2524847228
Short name T469
Test name
Test status
Simulation time 631230262 ps
CPU time 8.59 seconds
Started Jul 12 06:28:57 PM PDT 24
Finished Jul 12 06:29:07 PM PDT 24
Peak memory 221112 kb
Host smart-93130501-df0f-4885-943d-17956c16d5e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2524847228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2524847228
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.4001207899
Short name T166
Test name
Test status
Simulation time 541303143645 ps
CPU time 1178.87 seconds
Started Jul 12 06:28:57 PM PDT 24
Finished Jul 12 06:48:38 PM PDT 24
Peak memory 274464 kb
Host smart-d2f65bb1-43ff-4eaa-a64b-fc4531a6afad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001207899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.4001207899
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.253825724
Short name T753
Test name
Test status
Simulation time 7224073904 ps
CPU time 10.6 seconds
Started Jul 12 06:29:00 PM PDT 24
Finished Jul 12 06:29:11 PM PDT 24
Peak memory 218672 kb
Host smart-789e27b2-a249-4118-ba38-4261e1d4eb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253825724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.253825724
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2975758415
Short name T893
Test name
Test status
Simulation time 955692795 ps
CPU time 2.07 seconds
Started Jul 12 06:28:50 PM PDT 24
Finished Jul 12 06:28:53 PM PDT 24
Peak memory 208892 kb
Host smart-3503f0a1-75db-4e14-a20c-70beda9e26df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975758415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2975758415
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2201309416
Short name T1022
Test name
Test status
Simulation time 31432903 ps
CPU time 1.02 seconds
Started Jul 12 06:28:56 PM PDT 24
Finished Jul 12 06:28:59 PM PDT 24
Peak memory 207972 kb
Host smart-9d6b8acd-e559-4abe-a1a4-89812d4ff420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201309416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2201309416
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3704908825
Short name T345
Test name
Test status
Simulation time 26027866 ps
CPU time 0.81 seconds
Started Jul 12 06:28:56 PM PDT 24
Finished Jul 12 06:28:58 PM PDT 24
Peak memory 206956 kb
Host smart-08dbe9ef-52bb-4374-9a3f-2b97842be673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704908825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3704908825
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.970859509
Short name T614
Test name
Test status
Simulation time 1300132989 ps
CPU time 6.29 seconds
Started Jul 12 06:28:57 PM PDT 24
Finished Jul 12 06:29:05 PM PDT 24
Peak memory 233788 kb
Host smart-9e194860-289b-4104-bca7-2f8e0a9d16b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970859509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.970859509
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2800271483
Short name T752
Test name
Test status
Simulation time 20674324 ps
CPU time 0.75 seconds
Started Jul 12 06:29:15 PM PDT 24
Finished Jul 12 06:29:17 PM PDT 24
Peak memory 205788 kb
Host smart-b3069a17-3e40-4baf-a5de-5a349436fb58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800271483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2800271483
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1291541582
Short name T829
Test name
Test status
Simulation time 116995953 ps
CPU time 2.83 seconds
Started Jul 12 06:29:05 PM PDT 24
Finished Jul 12 06:29:09 PM PDT 24
Peak memory 225524 kb
Host smart-05fbfbc8-bc36-4fe3-95da-3d39d25d4a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291541582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1291541582
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.4289057027
Short name T679
Test name
Test status
Simulation time 20307956 ps
CPU time 0.79 seconds
Started Jul 12 06:28:57 PM PDT 24
Finished Jul 12 06:28:59 PM PDT 24
Peak memory 207488 kb
Host smart-4b64afce-12ea-4084-8726-4fc04930350c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289057027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.4289057027
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.178866409
Short name T227
Test name
Test status
Simulation time 108402520173 ps
CPU time 236.68 seconds
Started Jul 12 06:29:05 PM PDT 24
Finished Jul 12 06:33:03 PM PDT 24
Peak memory 266660 kb
Host smart-8a5f0659-781a-44a7-a563-8a2f114af99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178866409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.178866409
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.944006009
Short name T1028
Test name
Test status
Simulation time 60691990459 ps
CPU time 300.28 seconds
Started Jul 12 06:29:04 PM PDT 24
Finished Jul 12 06:34:05 PM PDT 24
Peak memory 256388 kb
Host smart-e775cf00-b559-4a9e-b585-ea68a113b928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944006009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.944006009
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2695292700
Short name T764
Test name
Test status
Simulation time 112452382508 ps
CPU time 304.92 seconds
Started Jul 12 06:29:05 PM PDT 24
Finished Jul 12 06:34:11 PM PDT 24
Peak memory 266308 kb
Host smart-003d9c83-7a2f-4c57-9858-dcf0c3d2199b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695292700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2695292700
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2821606534
Short name T916
Test name
Test status
Simulation time 7035904232 ps
CPU time 31.56 seconds
Started Jul 12 06:29:04 PM PDT 24
Finished Jul 12 06:29:36 PM PDT 24
Peak memory 233816 kb
Host smart-a0cc3d4d-9297-4b55-bc87-9d49e71a46e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821606534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2821606534
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.871827788
Short name T198
Test name
Test status
Simulation time 10498411863 ps
CPU time 77.89 seconds
Started Jul 12 06:29:05 PM PDT 24
Finished Jul 12 06:30:23 PM PDT 24
Peak memory 254000 kb
Host smart-6c4fc92b-87df-421d-a637-f4ad1d663155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871827788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.871827788
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3049535414
Short name T843
Test name
Test status
Simulation time 13671677908 ps
CPU time 45.22 seconds
Started Jul 12 06:28:57 PM PDT 24
Finished Jul 12 06:29:44 PM PDT 24
Peak memory 225564 kb
Host smart-77a3bda1-95b7-4a61-834b-121cc055a1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049535414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3049535414
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3944352291
Short name T217
Test name
Test status
Simulation time 567859847 ps
CPU time 10.41 seconds
Started Jul 12 06:28:56 PM PDT 24
Finished Jul 12 06:29:08 PM PDT 24
Peak memory 233672 kb
Host smart-d51ab32c-3cd6-499f-864a-721c825892bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944352291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3944352291
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3491019375
Short name T741
Test name
Test status
Simulation time 289115837 ps
CPU time 3.3 seconds
Started Jul 12 06:28:56 PM PDT 24
Finished Jul 12 06:29:01 PM PDT 24
Peak memory 233684 kb
Host smart-5731f336-1c68-44a4-abc7-3898de7707e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491019375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3491019375
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3404884558
Short name T230
Test name
Test status
Simulation time 222254240 ps
CPU time 5.21 seconds
Started Jul 12 06:28:56 PM PDT 24
Finished Jul 12 06:29:02 PM PDT 24
Peak memory 233672 kb
Host smart-6754aa39-9879-4523-bc0f-42b29d54aac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404884558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3404884558
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1475870977
Short name T761
Test name
Test status
Simulation time 625013278 ps
CPU time 6.26 seconds
Started Jul 12 06:29:05 PM PDT 24
Finished Jul 12 06:29:12 PM PDT 24
Peak memory 220168 kb
Host smart-9423478e-edfb-4f31-a512-90ead12101db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1475870977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1475870977
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4232873533
Short name T16
Test name
Test status
Simulation time 7153818052 ps
CPU time 68.76 seconds
Started Jul 12 06:29:15 PM PDT 24
Finished Jul 12 06:30:25 PM PDT 24
Peak memory 250424 kb
Host smart-93f61fe0-6920-4269-8a4b-35c6498fb0b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232873533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4232873533
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2579546328
Short name T622
Test name
Test status
Simulation time 29788565 ps
CPU time 0.73 seconds
Started Jul 12 06:28:55 PM PDT 24
Finished Jul 12 06:28:57 PM PDT 24
Peak memory 206620 kb
Host smart-d5b987ba-96bb-4f1e-a112-41e708d394be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579546328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2579546328
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2574108358
Short name T482
Test name
Test status
Simulation time 381759781 ps
CPU time 3.02 seconds
Started Jul 12 06:39:11 PM PDT 24
Finished Jul 12 06:39:18 PM PDT 24
Peak memory 217312 kb
Host smart-47232390-f8d4-4dfa-b636-ae86bc7929ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574108358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2574108358
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1993444157
Short name T584
Test name
Test status
Simulation time 133086200 ps
CPU time 1.22 seconds
Started Jul 12 06:28:56 PM PDT 24
Finished Jul 12 06:28:59 PM PDT 24
Peak memory 217144 kb
Host smart-8c7a6ef7-2c75-46b2-919f-b4cf446627bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993444157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1993444157
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3542836083
Short name T959
Test name
Test status
Simulation time 191547350 ps
CPU time 0.91 seconds
Started Jul 12 06:28:56 PM PDT 24
Finished Jul 12 06:28:59 PM PDT 24
Peak memory 207972 kb
Host smart-2e432a8d-68ee-47d2-a020-851412771370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542836083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3542836083
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1052623656
Short name T63
Test name
Test status
Simulation time 4806890361 ps
CPU time 10.36 seconds
Started Jul 12 06:29:05 PM PDT 24
Finished Jul 12 06:29:16 PM PDT 24
Peak memory 233840 kb
Host smart-08d6f052-0585-4ac4-a5a1-e2354fa05088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052623656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1052623656
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1852758413
Short name T73
Test name
Test status
Simulation time 23165705 ps
CPU time 0.73 seconds
Started Jul 12 06:29:14 PM PDT 24
Finished Jul 12 06:29:15 PM PDT 24
Peak memory 206352 kb
Host smart-5f9f8fe5-20e4-4190-95c1-9d4aae9a0054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852758413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1852758413
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2736939160
Short name T377
Test name
Test status
Simulation time 48420571 ps
CPU time 2.66 seconds
Started Jul 12 06:29:12 PM PDT 24
Finished Jul 12 06:29:15 PM PDT 24
Peak memory 233416 kb
Host smart-e3ea4a51-1263-4a62-a1cf-52229825352e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736939160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2736939160
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3907204453
Short name T425
Test name
Test status
Simulation time 49966956 ps
CPU time 0.78 seconds
Started Jul 12 06:29:14 PM PDT 24
Finished Jul 12 06:29:16 PM PDT 24
Peak memory 207812 kb
Host smart-dcf5e5b7-5995-4d2b-be4f-9f76124cb916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907204453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3907204453
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2525660996
Short name T734
Test name
Test status
Simulation time 9122051201 ps
CPU time 66.08 seconds
Started Jul 12 06:29:13 PM PDT 24
Finished Jul 12 06:30:20 PM PDT 24
Peak memory 252808 kb
Host smart-7c0ca646-7ce0-4f38-9963-1e0c1f628ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525660996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2525660996
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1327364951
Short name T938
Test name
Test status
Simulation time 4473584996 ps
CPU time 50.33 seconds
Started Jul 12 06:29:13 PM PDT 24
Finished Jul 12 06:30:04 PM PDT 24
Peak memory 250456 kb
Host smart-9b0818b1-ba8b-494b-b702-c7edf1304309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327364951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1327364951
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3361169270
Short name T300
Test name
Test status
Simulation time 46741435370 ps
CPU time 204.71 seconds
Started Jul 12 06:29:13 PM PDT 24
Finished Jul 12 06:32:39 PM PDT 24
Peak memory 256508 kb
Host smart-632e601f-2c0b-40df-95c9-b7c47a8b14ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361169270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3361169270
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3983973820
Short name T785
Test name
Test status
Simulation time 239220149 ps
CPU time 3.73 seconds
Started Jul 12 06:29:15 PM PDT 24
Finished Jul 12 06:29:19 PM PDT 24
Peak memory 219936 kb
Host smart-e28ec087-8587-4f1f-bb9b-53ea22a34170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983973820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3983973820
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.261635313
Short name T175
Test name
Test status
Simulation time 9244906574 ps
CPU time 68.76 seconds
Started Jul 12 06:29:14 PM PDT 24
Finished Jul 12 06:30:24 PM PDT 24
Peak memory 242060 kb
Host smart-f82d6b15-df2c-428e-8eee-395bbddee789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261635313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.261635313
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3810271867
Short name T780
Test name
Test status
Simulation time 441728767 ps
CPU time 6.46 seconds
Started Jul 12 06:29:12 PM PDT 24
Finished Jul 12 06:29:19 PM PDT 24
Peak memory 225512 kb
Host smart-5ed11a02-2d0c-4d41-8d66-b5f9cd887219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810271867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3810271867
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1888860563
Short name T553
Test name
Test status
Simulation time 3530567945 ps
CPU time 23.3 seconds
Started Jul 12 06:29:15 PM PDT 24
Finished Jul 12 06:29:39 PM PDT 24
Peak memory 233780 kb
Host smart-2f13e4c7-f269-4a38-94cf-7edecf393add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888860563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1888860563
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1778427532
Short name T636
Test name
Test status
Simulation time 741921912 ps
CPU time 3.83 seconds
Started Jul 12 06:29:15 PM PDT 24
Finished Jul 12 06:29:20 PM PDT 24
Peak memory 233744 kb
Host smart-7f5fd9a3-6615-4e9b-8499-429b956ed316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778427532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1778427532
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3035530174
Short name T870
Test name
Test status
Simulation time 499142306 ps
CPU time 7.45 seconds
Started Jul 12 06:29:15 PM PDT 24
Finished Jul 12 06:29:23 PM PDT 24
Peak memory 220284 kb
Host smart-88698113-cd9c-4351-a218-fe1baeddd9f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3035530174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3035530174
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.4125788226
Short name T134
Test name
Test status
Simulation time 96819132875 ps
CPU time 900.44 seconds
Started Jul 12 06:29:15 PM PDT 24
Finished Jul 12 06:44:17 PM PDT 24
Peak memory 267548 kb
Host smart-25698b97-5a1a-4b3b-97d9-240b0e6f31ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125788226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.4125788226
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.597325313
Short name T466
Test name
Test status
Simulation time 1733187021 ps
CPU time 25.11 seconds
Started Jul 12 06:29:14 PM PDT 24
Finished Jul 12 06:29:40 PM PDT 24
Peak memory 217476 kb
Host smart-b0b1ee6f-86d2-4304-b46d-cceada1a8095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597325313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.597325313
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.197088932
Short name T412
Test name
Test status
Simulation time 21020811714 ps
CPU time 8.64 seconds
Started Jul 12 06:29:12 PM PDT 24
Finished Jul 12 06:29:21 PM PDT 24
Peak memory 217540 kb
Host smart-e33acaa2-7476-4219-b721-7d01e8363ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197088932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.197088932
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.39500273
Short name T797
Test name
Test status
Simulation time 118501897 ps
CPU time 1.04 seconds
Started Jul 12 06:29:13 PM PDT 24
Finished Jul 12 06:29:15 PM PDT 24
Peak memory 207960 kb
Host smart-d9398352-6d20-4f35-8814-78ece2d5eec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39500273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.39500273
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.830552609
Short name T459
Test name
Test status
Simulation time 16985410 ps
CPU time 0.72 seconds
Started Jul 12 06:29:15 PM PDT 24
Finished Jul 12 06:29:17 PM PDT 24
Peak memory 206936 kb
Host smart-81e351e1-cea7-4c55-b525-6cfa0f4eeb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830552609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.830552609
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.4162956117
Short name T926
Test name
Test status
Simulation time 9977197741 ps
CPU time 9.28 seconds
Started Jul 12 06:29:13 PM PDT 24
Finished Jul 12 06:29:23 PM PDT 24
Peak memory 225680 kb
Host smart-aea17036-e9c7-4f1d-86e5-51ee367acf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162956117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4162956117
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1011940022
Short name T645
Test name
Test status
Simulation time 38773243 ps
CPU time 0.73 seconds
Started Jul 12 06:29:21 PM PDT 24
Finished Jul 12 06:29:23 PM PDT 24
Peak memory 206380 kb
Host smart-104bc659-40da-4998-b8f0-3b1a6dc6b1fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011940022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1011940022
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1075910932
Short name T95
Test name
Test status
Simulation time 6236541627 ps
CPU time 15.65 seconds
Started Jul 12 06:29:21 PM PDT 24
Finished Jul 12 06:29:38 PM PDT 24
Peak memory 225636 kb
Host smart-e5e2c1eb-fef3-4162-a918-32310a310d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075910932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1075910932
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3942613103
Short name T582
Test name
Test status
Simulation time 18450607 ps
CPU time 0.83 seconds
Started Jul 12 06:29:15 PM PDT 24
Finished Jul 12 06:29:16 PM PDT 24
Peak memory 207488 kb
Host smart-ba7bc818-8c53-4f66-86f5-c3caba0ff9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942613103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3942613103
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.176003503
Short name T935
Test name
Test status
Simulation time 12828713519 ps
CPU time 96.03 seconds
Started Jul 12 06:29:22 PM PDT 24
Finished Jul 12 06:30:59 PM PDT 24
Peak memory 241536 kb
Host smart-584bb8ba-2bbd-48ea-9b7f-739329dfb1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176003503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.176003503
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3286708558
Short name T823
Test name
Test status
Simulation time 8623883630 ps
CPU time 149.87 seconds
Started Jul 12 06:29:21 PM PDT 24
Finished Jul 12 06:31:53 PM PDT 24
Peak memory 265236 kb
Host smart-29fa8d18-07df-4f17-87d9-d9663c35321b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286708558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3286708558
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1613619389
Short name T975
Test name
Test status
Simulation time 15220716815 ps
CPU time 125.72 seconds
Started Jul 12 06:29:22 PM PDT 24
Finished Jul 12 06:31:29 PM PDT 24
Peak memory 250408 kb
Host smart-c99b1e9e-d58b-47df-8c85-96ee7ae286dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613619389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1613619389
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1689574009
Short name T908
Test name
Test status
Simulation time 673274696 ps
CPU time 6.94 seconds
Started Jul 12 06:29:21 PM PDT 24
Finished Jul 12 06:29:30 PM PDT 24
Peak memory 236704 kb
Host smart-f86e715f-1bbd-4874-a723-b67fda0e7c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689574009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1689574009
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2924338044
Short name T521
Test name
Test status
Simulation time 18864838021 ps
CPU time 137.43 seconds
Started Jul 12 06:29:21 PM PDT 24
Finished Jul 12 06:31:40 PM PDT 24
Peak memory 256476 kb
Host smart-1da88cbf-d473-4f0b-8121-1b6b44b6b8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924338044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2924338044
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2397588585
Short name T855
Test name
Test status
Simulation time 477231988 ps
CPU time 7.6 seconds
Started Jul 12 06:29:21 PM PDT 24
Finished Jul 12 06:29:30 PM PDT 24
Peak memory 233728 kb
Host smart-6b3cdc49-b895-425f-81c2-99fd62579ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397588585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2397588585
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2891385531
Short name T946
Test name
Test status
Simulation time 248710707 ps
CPU time 5.46 seconds
Started Jul 12 06:29:21 PM PDT 24
Finished Jul 12 06:29:28 PM PDT 24
Peak memory 233700 kb
Host smart-b0177a93-95bb-4f38-baf5-4fa01074d4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891385531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2891385531
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2264942585
Short name T831
Test name
Test status
Simulation time 140702127 ps
CPU time 2.54 seconds
Started Jul 12 06:29:21 PM PDT 24
Finished Jul 12 06:29:26 PM PDT 24
Peak memory 225564 kb
Host smart-544d17a8-d04e-4f15-ba8c-c8aa0d1120f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264942585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2264942585
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.202012865
Short name T245
Test name
Test status
Simulation time 2041760236 ps
CPU time 10.08 seconds
Started Jul 12 06:29:22 PM PDT 24
Finished Jul 12 06:29:34 PM PDT 24
Peak memory 241880 kb
Host smart-a50d0def-a64e-4528-8c24-db1726cbb26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202012865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.202012865
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3849756779
Short name T650
Test name
Test status
Simulation time 4307356684 ps
CPU time 8.44 seconds
Started Jul 12 06:29:20 PM PDT 24
Finished Jul 12 06:29:30 PM PDT 24
Peak memory 224224 kb
Host smart-88853f0b-a41a-4e55-8f9c-9104c38d6899
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3849756779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3849756779
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.394058477
Short name T141
Test name
Test status
Simulation time 50173540110 ps
CPU time 550.1 seconds
Started Jul 12 06:29:21 PM PDT 24
Finished Jul 12 06:38:32 PM PDT 24
Peak memory 283192 kb
Host smart-c659b0ef-dd79-4ddb-ae65-2caabbd71c02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394058477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.394058477
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2881526104
Short name T85
Test name
Test status
Simulation time 600148878 ps
CPU time 3.56 seconds
Started Jul 12 06:29:13 PM PDT 24
Finished Jul 12 06:29:17 PM PDT 24
Peak memory 217400 kb
Host smart-7aa3041a-58d1-4f50-bf8c-d95b6abdf500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881526104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2881526104
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2440525256
Short name T637
Test name
Test status
Simulation time 641402698 ps
CPU time 2.39 seconds
Started Jul 12 06:29:12 PM PDT 24
Finished Jul 12 06:29:16 PM PDT 24
Peak memory 208868 kb
Host smart-c323d6a3-4960-4916-b60e-b5f68d5f3dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440525256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2440525256
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3845488116
Short name T518
Test name
Test status
Simulation time 185840234 ps
CPU time 2.04 seconds
Started Jul 12 06:29:13 PM PDT 24
Finished Jul 12 06:29:16 PM PDT 24
Peak memory 217320 kb
Host smart-c798ff48-a224-4354-b55e-164434936846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845488116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3845488116
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3735656298
Short name T61
Test name
Test status
Simulation time 90398353 ps
CPU time 0.71 seconds
Started Jul 12 06:29:13 PM PDT 24
Finished Jul 12 06:29:14 PM PDT 24
Peak memory 206764 kb
Host smart-2e5aebd6-7097-4c14-9057-da3809ab20d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735656298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3735656298
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1551444471
Short name T794
Test name
Test status
Simulation time 329575361 ps
CPU time 4.62 seconds
Started Jul 12 06:29:22 PM PDT 24
Finished Jul 12 06:29:28 PM PDT 24
Peak memory 233720 kb
Host smart-d6f15bef-1180-46f0-ab6b-4e4b7e192d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551444471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1551444471
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3856640478
Short name T933
Test name
Test status
Simulation time 50880550 ps
CPU time 0.71 seconds
Started Jul 12 06:29:29 PM PDT 24
Finished Jul 12 06:29:30 PM PDT 24
Peak memory 205788 kb
Host smart-c4265dad-b887-4148-abba-cd42e6ce2191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856640478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3856640478
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.193948229
Short name T912
Test name
Test status
Simulation time 120814267 ps
CPU time 2.9 seconds
Started Jul 12 06:29:30 PM PDT 24
Finished Jul 12 06:29:34 PM PDT 24
Peak memory 225532 kb
Host smart-a3544a90-982c-445c-8267-11db8717eedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193948229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.193948229
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3165630358
Short name T331
Test name
Test status
Simulation time 17981901 ps
CPU time 0.77 seconds
Started Jul 12 06:29:20 PM PDT 24
Finished Jul 12 06:29:21 PM PDT 24
Peak memory 206444 kb
Host smart-0cbd4eb0-f2eb-4c07-8d57-537a67b2c453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165630358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3165630358
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2080023286
Short name T406
Test name
Test status
Simulation time 36921543450 ps
CPU time 64.39 seconds
Started Jul 12 06:29:28 PM PDT 24
Finished Jul 12 06:30:33 PM PDT 24
Peak memory 237256 kb
Host smart-1c59cd77-45da-41dd-b9ff-3312dc37a141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080023286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2080023286
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.155072071
Short name T947
Test name
Test status
Simulation time 13975094499 ps
CPU time 116.28 seconds
Started Jul 12 06:29:30 PM PDT 24
Finished Jul 12 06:31:27 PM PDT 24
Peak memory 251416 kb
Host smart-71d3871c-5a9f-4efa-a2d8-ea6ff29c79e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155072071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.155072071
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.466846341
Short name T343
Test name
Test status
Simulation time 1132265274 ps
CPU time 23.04 seconds
Started Jul 12 06:29:30 PM PDT 24
Finished Jul 12 06:29:54 PM PDT 24
Peak memory 250120 kb
Host smart-0937bd0c-25d3-442c-8e53-74f10ba9a6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466846341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.466846341
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.51866291
Short name T881
Test name
Test status
Simulation time 332115405 ps
CPU time 4.6 seconds
Started Jul 12 06:29:27 PM PDT 24
Finished Jul 12 06:29:33 PM PDT 24
Peak memory 233736 kb
Host smart-be66de39-20ae-48a1-81f3-131865fb3aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51866291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.51866291
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.621510616
Short name T589
Test name
Test status
Simulation time 14566838693 ps
CPU time 32.63 seconds
Started Jul 12 06:29:31 PM PDT 24
Finished Jul 12 06:30:05 PM PDT 24
Peak memory 250108 kb
Host smart-50a9fce2-6c27-43b5-9824-4070990d2695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621510616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.621510616
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1756218006
Short name T970
Test name
Test status
Simulation time 5381582337 ps
CPU time 11.79 seconds
Started Jul 12 06:29:22 PM PDT 24
Finished Jul 12 06:29:36 PM PDT 24
Peak memory 233828 kb
Host smart-bcd24acc-489e-471f-a547-05bab27642c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756218006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1756218006
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1875156035
Short name T629
Test name
Test status
Simulation time 2502809175 ps
CPU time 16.33 seconds
Started Jul 12 06:29:29 PM PDT 24
Finished Jul 12 06:29:46 PM PDT 24
Peak memory 239820 kb
Host smart-e686d1d7-76cb-42a7-befd-ce474300cd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875156035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1875156035
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3753032848
Short name T258
Test name
Test status
Simulation time 3794016480 ps
CPU time 11.43 seconds
Started Jul 12 06:29:22 PM PDT 24
Finished Jul 12 06:29:35 PM PDT 24
Peak memory 240644 kb
Host smart-de7f7a36-65b2-4bf4-b026-ed187d3fd06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753032848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3753032848
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2661524506
Short name T849
Test name
Test status
Simulation time 3856794617 ps
CPU time 10.79 seconds
Started Jul 12 06:29:21 PM PDT 24
Finished Jul 12 06:29:34 PM PDT 24
Peak memory 234056 kb
Host smart-a3628a8a-7304-44a3-882f-67eaac3c74f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661524506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2661524506
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2744351171
Short name T526
Test name
Test status
Simulation time 359483108 ps
CPU time 4.84 seconds
Started Jul 12 06:29:29 PM PDT 24
Finished Jul 12 06:29:34 PM PDT 24
Peak memory 221380 kb
Host smart-56d8accb-f577-46d1-9b84-06ecc9e1f6af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2744351171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2744351171
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2189757540
Short name T430
Test name
Test status
Simulation time 8305677819 ps
CPU time 33.42 seconds
Started Jul 12 06:29:28 PM PDT 24
Finished Jul 12 06:30:02 PM PDT 24
Peak memory 225700 kb
Host smart-8b369b7d-f869-433b-b2c2-6ec98eac99fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189757540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2189757540
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3305001337
Short name T701
Test name
Test status
Simulation time 18505592810 ps
CPU time 20.37 seconds
Started Jul 12 06:29:23 PM PDT 24
Finished Jul 12 06:29:45 PM PDT 24
Peak memory 217508 kb
Host smart-9202c783-8ec7-427a-8500-71752eb63e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305001337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3305001337
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.331375177
Short name T374
Test name
Test status
Simulation time 315426500 ps
CPU time 1.44 seconds
Started Jul 12 06:29:20 PM PDT 24
Finished Jul 12 06:29:23 PM PDT 24
Peak memory 208892 kb
Host smart-7b6b1b19-73ca-4494-a074-7e86cb267b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331375177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.331375177
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3398631521
Short name T1005
Test name
Test status
Simulation time 332846379 ps
CPU time 1.55 seconds
Started Jul 12 06:29:23 PM PDT 24
Finished Jul 12 06:29:26 PM PDT 24
Peak memory 217328 kb
Host smart-b5e87e6e-1546-4e21-8d80-0eaa59e904ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398631521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3398631521
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3367347716
Short name T366
Test name
Test status
Simulation time 72231649 ps
CPU time 0.91 seconds
Started Jul 12 06:29:19 PM PDT 24
Finished Jul 12 06:29:21 PM PDT 24
Peak memory 206948 kb
Host smart-ac15fade-04af-476a-b9e6-a31775620168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367347716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3367347716
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2641987525
Short name T750
Test name
Test status
Simulation time 1540460709 ps
CPU time 6.03 seconds
Started Jul 12 06:29:30 PM PDT 24
Finished Jul 12 06:29:37 PM PDT 24
Peak memory 233668 kb
Host smart-9edb1632-a279-4daa-be73-58160450e6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641987525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2641987525
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3654088522
Short name T779
Test name
Test status
Simulation time 13409950 ps
CPU time 0.74 seconds
Started Jul 12 06:23:08 PM PDT 24
Finished Jul 12 06:23:09 PM PDT 24
Peak memory 206360 kb
Host smart-3d55e8de-324c-448e-a35c-ad4f3505b832
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654088522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
654088522
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.631618072
Short name T590
Test name
Test status
Simulation time 36906594 ps
CPU time 2.74 seconds
Started Jul 12 06:23:02 PM PDT 24
Finished Jul 12 06:23:06 PM PDT 24
Peak memory 233732 kb
Host smart-52d6d7c8-89dd-43fc-acfd-99ecd5f37b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631618072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.631618072
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.4088647077
Short name T755
Test name
Test status
Simulation time 49139059 ps
CPU time 0.77 seconds
Started Jul 12 06:22:48 PM PDT 24
Finished Jul 12 06:22:51 PM PDT 24
Peak memory 206456 kb
Host smart-bc2cbe81-d890-4705-9a50-12a36d19eb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088647077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.4088647077
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1039720451
Short name T226
Test name
Test status
Simulation time 8103162069 ps
CPU time 29.95 seconds
Started Jul 12 06:23:11 PM PDT 24
Finished Jul 12 06:23:43 PM PDT 24
Peak memory 225620 kb
Host smart-618226c9-b25c-4214-a615-3b032db553e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039720451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1039720451
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2170549098
Short name T298
Test name
Test status
Simulation time 15059045827 ps
CPU time 39.29 seconds
Started Jul 12 06:23:02 PM PDT 24
Finished Jul 12 06:23:41 PM PDT 24
Peak memory 238348 kb
Host smart-35a13a7d-00be-4dda-a725-eb8f5077b56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170549098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2170549098
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2793822347
Short name T914
Test name
Test status
Simulation time 25207965144 ps
CPU time 251.96 seconds
Started Jul 12 06:23:00 PM PDT 24
Finished Jul 12 06:27:13 PM PDT 24
Peak memory 250400 kb
Host smart-5de512a7-ec80-4fef-98f9-02fdff79e6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793822347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2793822347
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1945581415
Short name T756
Test name
Test status
Simulation time 5247803212 ps
CPU time 16.1 seconds
Started Jul 12 06:23:12 PM PDT 24
Finished Jul 12 06:23:29 PM PDT 24
Peak memory 238936 kb
Host smart-dafe802d-720e-4272-9ff2-8b1ca89fb795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945581415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1945581415
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1554912488
Short name T557
Test name
Test status
Simulation time 696735396 ps
CPU time 7.65 seconds
Started Jul 12 06:23:01 PM PDT 24
Finished Jul 12 06:23:09 PM PDT 24
Peak memory 233800 kb
Host smart-87f2f041-09a4-4800-a3cc-5545bd53a584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554912488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1554912488
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1561286878
Short name T140
Test name
Test status
Simulation time 26973537520 ps
CPU time 49.63 seconds
Started Jul 12 06:23:12 PM PDT 24
Finished Jul 12 06:24:03 PM PDT 24
Peak memory 225672 kb
Host smart-193b96cd-361b-472c-88a0-d9dfeb645128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561286878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1561286878
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3181859892
Short name T37
Test name
Test status
Simulation time 45799298 ps
CPU time 1.02 seconds
Started Jul 12 06:22:56 PM PDT 24
Finished Jul 12 06:22:58 PM PDT 24
Peak memory 217652 kb
Host smart-ca7accd1-0524-4186-8b01-28a287e01400
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181859892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3181859892
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3564918391
Short name T568
Test name
Test status
Simulation time 490611775 ps
CPU time 3.78 seconds
Started Jul 12 06:22:55 PM PDT 24
Finished Jul 12 06:23:00 PM PDT 24
Peak memory 233700 kb
Host smart-0cce948d-dc1f-4286-8378-2bcac42dae32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564918391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3564918391
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1645500988
Short name T252
Test name
Test status
Simulation time 39470405921 ps
CPU time 10.9 seconds
Started Jul 12 06:22:56 PM PDT 24
Finished Jul 12 06:23:08 PM PDT 24
Peak memory 228268 kb
Host smart-1d7294a0-e2e0-4e54-8b96-251e87664d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645500988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1645500988
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1653952303
Short name T798
Test name
Test status
Simulation time 946073212 ps
CPU time 5.3 seconds
Started Jul 12 06:23:02 PM PDT 24
Finished Jul 12 06:23:08 PM PDT 24
Peak memory 223676 kb
Host smart-a2eecc76-c750-4972-ae28-5186e07f3f8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1653952303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1653952303
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3464733098
Short name T709
Test name
Test status
Simulation time 5301552145 ps
CPU time 30.51 seconds
Started Jul 12 06:23:06 PM PDT 24
Finished Jul 12 06:23:37 PM PDT 24
Peak memory 217480 kb
Host smart-41e4d11e-d091-43df-99f0-7f817e89a0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464733098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3464733098
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.241687450
Short name T819
Test name
Test status
Simulation time 23151173756 ps
CPU time 16.05 seconds
Started Jul 12 06:22:57 PM PDT 24
Finished Jul 12 06:23:14 PM PDT 24
Peak memory 217432 kb
Host smart-51680584-4e13-49d9-876a-5ec752184b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241687450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.241687450
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1179936649
Short name T389
Test name
Test status
Simulation time 71407421 ps
CPU time 1.99 seconds
Started Jul 12 06:22:57 PM PDT 24
Finished Jul 12 06:22:59 PM PDT 24
Peak memory 217324 kb
Host smart-cc52c026-8c1b-4e80-a386-2c7fef3c42a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179936649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1179936649
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2543213551
Short name T929
Test name
Test status
Simulation time 119903862 ps
CPU time 1.01 seconds
Started Jul 12 06:22:55 PM PDT 24
Finished Jul 12 06:22:57 PM PDT 24
Peak memory 206896 kb
Host smart-9efd4dee-59b8-4408-8dae-a50fc90a82da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543213551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2543213551
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2263519957
Short name T996
Test name
Test status
Simulation time 34554182093 ps
CPU time 31.02 seconds
Started Jul 12 06:23:11 PM PDT 24
Finished Jul 12 06:23:44 PM PDT 24
Peak memory 233748 kb
Host smart-5480e732-4274-4da3-a3fe-d13f2bb59389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263519957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2263519957
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2007847698
Short name T600
Test name
Test status
Simulation time 36335801 ps
CPU time 0.75 seconds
Started Jul 12 06:23:19 PM PDT 24
Finished Jul 12 06:23:21 PM PDT 24
Peak memory 206352 kb
Host smart-8e6ddd17-e0c8-458d-8e05-0d7baa20fc61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007847698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
007847698
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2035180964
Short name T937
Test name
Test status
Simulation time 113514267 ps
CPU time 2.38 seconds
Started Jul 12 06:23:18 PM PDT 24
Finished Jul 12 06:23:21 PM PDT 24
Peak memory 233772 kb
Host smart-88afdd2c-4ca0-4b0b-b452-78f4b0584e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035180964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2035180964
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3926598162
Short name T352
Test name
Test status
Simulation time 42401462 ps
CPU time 0.78 seconds
Started Jul 12 06:23:08 PM PDT 24
Finished Jul 12 06:23:09 PM PDT 24
Peak memory 207504 kb
Host smart-9d0dfee7-0780-4308-ad6b-d32544b97f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926598162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3926598162
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1920969014
Short name T900
Test name
Test status
Simulation time 38478835 ps
CPU time 0.8 seconds
Started Jul 12 06:23:17 PM PDT 24
Finished Jul 12 06:23:18 PM PDT 24
Peak memory 216864 kb
Host smart-3f306fe3-e672-47f5-9f16-4386085f0edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920969014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1920969014
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.924598014
Short name T48
Test name
Test status
Simulation time 8770447261 ps
CPU time 88.52 seconds
Started Jul 12 06:23:17 PM PDT 24
Finished Jul 12 06:24:47 PM PDT 24
Peak memory 239768 kb
Host smart-c394c536-ce8a-4e73-99b5-6b491c123c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924598014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.924598014
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3481067886
Short name T203
Test name
Test status
Simulation time 59614678914 ps
CPU time 142.56 seconds
Started Jul 12 06:23:17 PM PDT 24
Finished Jul 12 06:25:40 PM PDT 24
Peak memory 250408 kb
Host smart-3548aee1-1183-44ac-b623-ee68111e5d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481067886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3481067886
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1331246155
Short name T307
Test name
Test status
Simulation time 21311650204 ps
CPU time 48.51 seconds
Started Jul 12 06:23:18 PM PDT 24
Finished Jul 12 06:24:08 PM PDT 24
Peak memory 233864 kb
Host smart-335a1e7f-6224-46b4-a8c2-cba1f69b5da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331246155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1331246155
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3911018731
Short name T1026
Test name
Test status
Simulation time 14818224 ps
CPU time 0.76 seconds
Started Jul 12 06:23:18 PM PDT 24
Finished Jul 12 06:23:19 PM PDT 24
Peak memory 216896 kb
Host smart-6a481b2a-ac9b-4685-96eb-4694bc6ade40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911018731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3911018731
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2027915212
Short name T840
Test name
Test status
Simulation time 159805834 ps
CPU time 3.57 seconds
Started Jul 12 06:23:12 PM PDT 24
Finished Jul 12 06:23:17 PM PDT 24
Peak memory 225580 kb
Host smart-58185984-3674-412f-996c-dddc5202b58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027915212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2027915212
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1196698901
Short name T208
Test name
Test status
Simulation time 9274701503 ps
CPU time 77.44 seconds
Started Jul 12 06:23:16 PM PDT 24
Finished Jul 12 06:24:34 PM PDT 24
Peak memory 233852 kb
Host smart-91a72e92-b171-49ed-af7a-6443d5a096d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196698901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1196698901
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2408828222
Short name T405
Test name
Test status
Simulation time 17456252 ps
CPU time 1.02 seconds
Started Jul 12 06:23:06 PM PDT 24
Finished Jul 12 06:23:08 PM PDT 24
Peak memory 217644 kb
Host smart-e440d735-694e-4321-9f68-5e5b7649b661
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408828222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2408828222
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1915152142
Short name T792
Test name
Test status
Simulation time 20903080340 ps
CPU time 15.35 seconds
Started Jul 12 06:23:12 PM PDT 24
Finished Jul 12 06:23:28 PM PDT 24
Peak memory 233812 kb
Host smart-6dc87580-34ee-406c-810b-277c6a977609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915152142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1915152142
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3587295081
Short name T395
Test name
Test status
Simulation time 688297537 ps
CPU time 7.22 seconds
Started Jul 12 06:23:11 PM PDT 24
Finished Jul 12 06:23:20 PM PDT 24
Peak memory 241812 kb
Host smart-40c10d69-d296-4fbe-8048-3f2282586f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587295081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3587295081
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1217048205
Short name T428
Test name
Test status
Simulation time 398949036 ps
CPU time 4.96 seconds
Started Jul 12 06:23:16 PM PDT 24
Finished Jul 12 06:23:22 PM PDT 24
Peak memory 223420 kb
Host smart-5a9cc62b-8552-4e25-8aaa-18565986fcb6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1217048205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1217048205
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1196118588
Short name T813
Test name
Test status
Simulation time 5515228068 ps
CPU time 79.35 seconds
Started Jul 12 06:23:18 PM PDT 24
Finished Jul 12 06:24:38 PM PDT 24
Peak memory 258300 kb
Host smart-cd0964dd-1783-4428-887a-54dff735e3c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196118588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1196118588
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3683767241
Short name T13
Test name
Test status
Simulation time 17707802829 ps
CPU time 30.19 seconds
Started Jul 12 06:23:10 PM PDT 24
Finished Jul 12 06:23:41 PM PDT 24
Peak memory 217544 kb
Host smart-09318560-c19e-45b9-a39f-44bbdb80d6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683767241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3683767241
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3720254100
Short name T89
Test name
Test status
Simulation time 1393419896 ps
CPU time 4.46 seconds
Started Jul 12 06:23:06 PM PDT 24
Finished Jul 12 06:23:11 PM PDT 24
Peak memory 217276 kb
Host smart-399eca08-c9d9-408a-ae34-2166021c1185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720254100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3720254100
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1711802740
Short name T25
Test name
Test status
Simulation time 68734428 ps
CPU time 2.25 seconds
Started Jul 12 06:23:12 PM PDT 24
Finished Jul 12 06:23:16 PM PDT 24
Peak memory 217360 kb
Host smart-a1ab1545-cea6-4d5f-aace-adf83cf16bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711802740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1711802740
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3670127041
Short name T504
Test name
Test status
Simulation time 39669776 ps
CPU time 0.76 seconds
Started Jul 12 06:23:09 PM PDT 24
Finished Jul 12 06:23:10 PM PDT 24
Peak memory 206908 kb
Host smart-1730f9a0-cf37-4e62-8cf1-a9e700e7cece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670127041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3670127041
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.338838249
Short name T271
Test name
Test status
Simulation time 3112138441 ps
CPU time 12.16 seconds
Started Jul 12 06:23:18 PM PDT 24
Finished Jul 12 06:23:31 PM PDT 24
Peak memory 233864 kb
Host smart-1e8cbbb4-c853-413c-900b-6b5b9e57ea88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338838249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.338838249
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3228708312
Short name T558
Test name
Test status
Simulation time 17090886 ps
CPU time 0.72 seconds
Started Jul 12 06:23:26 PM PDT 24
Finished Jul 12 06:23:28 PM PDT 24
Peak memory 206396 kb
Host smart-375d62e4-046c-488e-bb90-5fcf9579fa93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228708312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
228708312
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1107128122
Short name T891
Test name
Test status
Simulation time 705616314 ps
CPU time 3.91 seconds
Started Jul 12 06:23:28 PM PDT 24
Finished Jul 12 06:23:33 PM PDT 24
Peak memory 233744 kb
Host smart-da6674a0-7be3-4a58-87f4-f67ceb428747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107128122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1107128122
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1448385214
Short name T410
Test name
Test status
Simulation time 42912990 ps
CPU time 0.78 seconds
Started Jul 12 06:23:23 PM PDT 24
Finished Jul 12 06:23:25 PM PDT 24
Peak memory 207500 kb
Host smart-ab14930b-d67d-4502-8a6c-6e05130f06d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448385214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1448385214
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3341656669
Short name T581
Test name
Test status
Simulation time 21704703823 ps
CPU time 79.22 seconds
Started Jul 12 06:23:27 PM PDT 24
Finished Jul 12 06:24:48 PM PDT 24
Peak memory 256076 kb
Host smart-ed5e4bc3-19e6-4bdf-97df-567876168942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341656669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3341656669
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1597469639
Short name T196
Test name
Test status
Simulation time 908705506775 ps
CPU time 453.32 seconds
Started Jul 12 06:23:30 PM PDT 24
Finished Jul 12 06:31:04 PM PDT 24
Peak memory 267632 kb
Host smart-ae907574-f09b-439b-b6ac-0802e11496ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597469639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1597469639
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1179233887
Short name T229
Test name
Test status
Simulation time 2730278378 ps
CPU time 57.87 seconds
Started Jul 12 06:23:28 PM PDT 24
Finished Jul 12 06:24:27 PM PDT 24
Peak memory 258564 kb
Host smart-d92ff9d7-1bae-4659-ae99-03fc9fc2fcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179233887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1179233887
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2725152457
Short name T310
Test name
Test status
Simulation time 32793521426 ps
CPU time 22.07 seconds
Started Jul 12 06:23:27 PM PDT 24
Finished Jul 12 06:23:50 PM PDT 24
Peak memory 225656 kb
Host smart-678c8227-2c0d-49fd-a399-96a219d1aba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725152457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2725152457
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.975827107
Short name T468
Test name
Test status
Simulation time 4435430026 ps
CPU time 21.1 seconds
Started Jul 12 06:23:28 PM PDT 24
Finished Jul 12 06:23:51 PM PDT 24
Peak memory 254848 kb
Host smart-60089f17-965f-497f-a2c6-c82799a5d2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975827107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.
975827107
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3689846031
Short name T356
Test name
Test status
Simulation time 325151208 ps
CPU time 2.19 seconds
Started Jul 12 06:23:22 PM PDT 24
Finished Jul 12 06:23:24 PM PDT 24
Peak memory 225260 kb
Host smart-e09862a0-07ee-482d-a9e5-3929054333b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689846031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3689846031
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3241719296
Short name T535
Test name
Test status
Simulation time 9001872903 ps
CPU time 63.84 seconds
Started Jul 12 06:23:28 PM PDT 24
Finished Jul 12 06:24:33 PM PDT 24
Peak memory 241948 kb
Host smart-02c9b84d-b5e9-4b15-b630-efcfd0494cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241719296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3241719296
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.595077443
Short name T489
Test name
Test status
Simulation time 48936120 ps
CPU time 1.09 seconds
Started Jul 12 06:23:24 PM PDT 24
Finished Jul 12 06:23:26 PM PDT 24
Peak memory 217624 kb
Host smart-d616bf1b-1651-4f7a-a22c-ae34559a952f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595077443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.595077443
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2488770731
Short name T612
Test name
Test status
Simulation time 21529132801 ps
CPU time 12.77 seconds
Started Jul 12 06:23:23 PM PDT 24
Finished Jul 12 06:23:36 PM PDT 24
Peak memory 241596 kb
Host smart-76d9bca0-04f4-4868-ae96-c0449a03710f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488770731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2488770731
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3263042934
Short name T811
Test name
Test status
Simulation time 31069966 ps
CPU time 2.28 seconds
Started Jul 12 06:23:22 PM PDT 24
Finished Jul 12 06:23:25 PM PDT 24
Peak memory 224892 kb
Host smart-dd226da7-516b-4922-88b9-0080f8fcc89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263042934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3263042934
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3216221987
Short name T720
Test name
Test status
Simulation time 1897723791 ps
CPU time 12.11 seconds
Started Jul 12 06:23:27 PM PDT 24
Finished Jul 12 06:23:41 PM PDT 24
Peak memory 223648 kb
Host smart-419d105a-a1d8-4e45-b7e3-982289a27951
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3216221987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3216221987
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1236650340
Short name T424
Test name
Test status
Simulation time 1200773407 ps
CPU time 7.88 seconds
Started Jul 12 06:23:22 PM PDT 24
Finished Jul 12 06:23:30 PM PDT 24
Peak memory 217388 kb
Host smart-ee578637-1ed4-4673-a46c-f5b79561d778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236650340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1236650340
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3692159444
Short name T874
Test name
Test status
Simulation time 19223784570 ps
CPU time 15.37 seconds
Started Jul 12 06:23:23 PM PDT 24
Finished Jul 12 06:23:39 PM PDT 24
Peak memory 217444 kb
Host smart-4821f0ac-2552-4f6c-9883-5863c023eb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692159444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3692159444
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1311444725
Short name T712
Test name
Test status
Simulation time 93250941 ps
CPU time 1.53 seconds
Started Jul 12 06:23:25 PM PDT 24
Finished Jul 12 06:23:27 PM PDT 24
Peak memory 217304 kb
Host smart-659c08d9-af7b-4c11-b0bf-bd4aa9b3d300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311444725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1311444725
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2717112470
Short name T788
Test name
Test status
Simulation time 29794644 ps
CPU time 0.7 seconds
Started Jul 12 06:23:22 PM PDT 24
Finished Jul 12 06:23:23 PM PDT 24
Peak memory 206488 kb
Host smart-4cef8f58-230d-4723-a500-10adce644c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717112470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2717112470
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3274519658
Short name T223
Test name
Test status
Simulation time 5607074859 ps
CPU time 22.58 seconds
Started Jul 12 06:23:27 PM PDT 24
Finished Jul 12 06:23:52 PM PDT 24
Peak memory 233808 kb
Host smart-0484852c-592e-466f-b01c-1a920c54b16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274519658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3274519658
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2134145848
Short name T986
Test name
Test status
Simulation time 29501119 ps
CPU time 0.69 seconds
Started Jul 12 06:23:39 PM PDT 24
Finished Jul 12 06:23:41 PM PDT 24
Peak memory 206680 kb
Host smart-d9bda5cf-78f2-4271-bf3f-bc8b7edfddf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134145848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
134145848
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3437765075
Short name T495
Test name
Test status
Simulation time 795587606 ps
CPU time 5.15 seconds
Started Jul 12 06:23:33 PM PDT 24
Finished Jul 12 06:23:39 PM PDT 24
Peak memory 233732 kb
Host smart-13081a5f-26d6-404d-8bcd-42ef632a1b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437765075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3437765075
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3897496358
Short name T541
Test name
Test status
Simulation time 26667577 ps
CPU time 0.79 seconds
Started Jul 12 06:23:27 PM PDT 24
Finished Jul 12 06:23:29 PM PDT 24
Peak memory 207836 kb
Host smart-0c58d55c-d3e6-43c8-8cee-304a3cc709c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897496358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3897496358
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3532145920
Short name T290
Test name
Test status
Simulation time 7076668754 ps
CPU time 96.88 seconds
Started Jul 12 06:23:41 PM PDT 24
Finished Jul 12 06:25:19 PM PDT 24
Peak memory 255328 kb
Host smart-7105a564-74fc-4a2a-954d-18477dd661a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532145920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3532145920
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2274582583
Short name T287
Test name
Test status
Simulation time 9254050849 ps
CPU time 43.45 seconds
Started Jul 12 06:23:41 PM PDT 24
Finished Jul 12 06:24:25 PM PDT 24
Peak memory 252472 kb
Host smart-bafcb204-e88d-4275-a784-5209344b989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274582583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2274582583
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.895410987
Short name T1019
Test name
Test status
Simulation time 25208319635 ps
CPU time 8.33 seconds
Started Jul 12 06:23:39 PM PDT 24
Finished Jul 12 06:23:49 PM PDT 24
Peak memory 218888 kb
Host smart-826a3fee-e2a7-4fdf-b5a2-b3c679615044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895410987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
895410987
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1098146189
Short name T305
Test name
Test status
Simulation time 134089955 ps
CPU time 4.08 seconds
Started Jul 12 06:23:35 PM PDT 24
Finished Jul 12 06:23:40 PM PDT 24
Peak memory 233672 kb
Host smart-99807d0f-4a31-41aa-8354-74d87129e0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098146189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1098146189
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2502411414
Short name T945
Test name
Test status
Simulation time 133531734385 ps
CPU time 210.87 seconds
Started Jul 12 06:23:32 PM PDT 24
Finished Jul 12 06:27:04 PM PDT 24
Peak memory 252532 kb
Host smart-2ccc1aa8-1743-49b0-9f53-6bc1955a37c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502411414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2502411414
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2757689320
Short name T449
Test name
Test status
Simulation time 37591545 ps
CPU time 2.21 seconds
Started Jul 12 06:23:33 PM PDT 24
Finished Jul 12 06:23:36 PM PDT 24
Peak memory 224252 kb
Host smart-cbcce07e-724a-4113-a5fd-d2bda130ca04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757689320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2757689320
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.677067885
Short name T517
Test name
Test status
Simulation time 17333229934 ps
CPU time 43.82 seconds
Started Jul 12 06:23:35 PM PDT 24
Finished Jul 12 06:24:20 PM PDT 24
Peak memory 241976 kb
Host smart-c0fdd785-9801-475f-8510-b666bad93524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677067885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.677067885
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2237385937
Short name T591
Test name
Test status
Simulation time 56359592 ps
CPU time 1.05 seconds
Started Jul 12 06:23:27 PM PDT 24
Finished Jul 12 06:23:29 PM PDT 24
Peak memory 218872 kb
Host smart-d18ce14e-4d63-4baa-94f0-7dd1dfcf47df
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237385937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2237385937
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3798764000
Short name T671
Test name
Test status
Simulation time 41260636975 ps
CPU time 29.25 seconds
Started Jul 12 06:23:31 PM PDT 24
Finished Jul 12 06:24:01 PM PDT 24
Peak memory 252096 kb
Host smart-97ad63da-f124-4063-a156-e6d45f149643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798764000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3798764000
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1145624231
Short name T613
Test name
Test status
Simulation time 244565428 ps
CPU time 4.83 seconds
Started Jul 12 06:23:34 PM PDT 24
Finished Jul 12 06:23:39 PM PDT 24
Peak memory 225536 kb
Host smart-6c816977-22ff-4847-9208-a9ec45e2db7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145624231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1145624231
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3004510057
Short name T941
Test name
Test status
Simulation time 89027254 ps
CPU time 4.07 seconds
Started Jul 12 06:23:32 PM PDT 24
Finished Jul 12 06:23:37 PM PDT 24
Peak memory 223584 kb
Host smart-cd0f9c5a-9512-470c-808f-8475bd4300d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3004510057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3004510057
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3572887211
Short name T319
Test name
Test status
Simulation time 20221772030 ps
CPU time 29.28 seconds
Started Jul 12 06:23:27 PM PDT 24
Finished Jul 12 06:23:58 PM PDT 24
Peak memory 217488 kb
Host smart-d6b2c8af-ffb9-487a-a4fb-c6902384b1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572887211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3572887211
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3294130760
Short name T836
Test name
Test status
Simulation time 233440158 ps
CPU time 1.18 seconds
Started Jul 12 06:23:27 PM PDT 24
Finished Jul 12 06:23:29 PM PDT 24
Peak memory 207960 kb
Host smart-fbb6edd2-c6ed-4425-8074-6c530d51324c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294130760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3294130760
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3429685912
Short name T75
Test name
Test status
Simulation time 42976028 ps
CPU time 1.47 seconds
Started Jul 12 06:23:35 PM PDT 24
Finished Jul 12 06:23:37 PM PDT 24
Peak memory 217368 kb
Host smart-8bea11ec-c348-410c-84ed-fd9cbe72bb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429685912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3429685912
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.4247818717
Short name T350
Test name
Test status
Simulation time 122995358 ps
CPU time 0.82 seconds
Started Jul 12 06:23:33 PM PDT 24
Finished Jul 12 06:23:35 PM PDT 24
Peak memory 206924 kb
Host smart-c01ad74c-8402-4dc1-a9d8-0ccef84a6b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247818717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.4247818717
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3491170075
Short name T850
Test name
Test status
Simulation time 16382389487 ps
CPU time 33.91 seconds
Started Jul 12 06:23:32 PM PDT 24
Finished Jul 12 06:24:07 PM PDT 24
Peak memory 243856 kb
Host smart-2470149e-4c69-4cae-a1f9-0542d57986ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491170075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3491170075
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1392057405
Short name T909
Test name
Test status
Simulation time 31545917 ps
CPU time 0.75 seconds
Started Jul 12 06:23:49 PM PDT 24
Finished Jul 12 06:23:51 PM PDT 24
Peak memory 205760 kb
Host smart-6cdce7f9-2f07-4acc-af9d-1cac48099189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392057405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
392057405
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3751190187
Short name T652
Test name
Test status
Simulation time 104911986 ps
CPU time 4.08 seconds
Started Jul 12 06:23:44 PM PDT 24
Finished Jul 12 06:23:49 PM PDT 24
Peak memory 233716 kb
Host smart-e87a1650-0d94-4556-8662-0a7a38eda348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751190187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3751190187
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1307119208
Short name T488
Test name
Test status
Simulation time 79999227 ps
CPU time 0.81 seconds
Started Jul 12 06:23:42 PM PDT 24
Finished Jul 12 06:23:43 PM PDT 24
Peak memory 207824 kb
Host smart-388532d1-f412-4a7a-90aa-97fd1873fb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307119208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1307119208
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2417169415
Short name T888
Test name
Test status
Simulation time 13912415 ps
CPU time 0.76 seconds
Started Jul 12 06:23:46 PM PDT 24
Finished Jul 12 06:23:47 PM PDT 24
Peak memory 216912 kb
Host smart-6cbf10f1-fc7b-4cc8-b84d-f5811f5b1c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417169415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2417169415
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2499240448
Short name T530
Test name
Test status
Simulation time 112460716086 ps
CPU time 517.27 seconds
Started Jul 12 06:23:46 PM PDT 24
Finished Jul 12 06:32:24 PM PDT 24
Peak memory 266728 kb
Host smart-d51c1c57-f994-4f62-a96a-d4060a95a8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499240448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2499240448
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1103523335
Short name T980
Test name
Test status
Simulation time 966702336 ps
CPU time 3.55 seconds
Started Jul 12 06:23:46 PM PDT 24
Finished Jul 12 06:23:50 PM PDT 24
Peak memory 225580 kb
Host smart-6d11b277-1ca6-404d-913e-be40cd09eb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103523335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1103523335
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.229625065
Short name T725
Test name
Test status
Simulation time 85375179403 ps
CPU time 155.91 seconds
Started Jul 12 06:23:45 PM PDT 24
Finished Jul 12 06:26:21 PM PDT 24
Peak memory 253168 kb
Host smart-0faeaed5-1136-4d58-aadc-f6b9194649f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229625065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
229625065
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.779114622
Short name T550
Test name
Test status
Simulation time 265626847 ps
CPU time 4.02 seconds
Started Jul 12 06:23:43 PM PDT 24
Finished Jul 12 06:23:48 PM PDT 24
Peak memory 233720 kb
Host smart-b15928f1-aac3-4e1a-a696-1bcf9be3ae46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779114622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.779114622
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.459215831
Short name T5
Test name
Test status
Simulation time 8769584805 ps
CPU time 23.55 seconds
Started Jul 12 06:23:44 PM PDT 24
Finished Jul 12 06:24:08 PM PDT 24
Peak memory 252428 kb
Host smart-408c09ed-c71b-4e86-bb42-1c89cec8c6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459215831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.459215831
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3733956358
Short name T851
Test name
Test status
Simulation time 43542936 ps
CPU time 1.06 seconds
Started Jul 12 06:23:41 PM PDT 24
Finished Jul 12 06:23:43 PM PDT 24
Peak memory 217632 kb
Host smart-7e358b87-268d-43e9-bf52-d71de41a4a0d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733956358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3733956358
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.12541390
Short name T979
Test name
Test status
Simulation time 542073539 ps
CPU time 7.08 seconds
Started Jul 12 06:23:44 PM PDT 24
Finished Jul 12 06:23:52 PM PDT 24
Peak memory 233756 kb
Host smart-c7739d6c-b14e-4b0f-9bc1-09dace44923b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12541390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.12541390
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3397314722
Short name T398
Test name
Test status
Simulation time 1734171152 ps
CPU time 7.33 seconds
Started Jul 12 06:23:45 PM PDT 24
Finished Jul 12 06:23:53 PM PDT 24
Peak memory 225504 kb
Host smart-e7695bea-4b2a-4fdc-8d0c-0248b2eba22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397314722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3397314722
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3819417497
Short name T871
Test name
Test status
Simulation time 263515444 ps
CPU time 3.79 seconds
Started Jul 12 06:23:49 PM PDT 24
Finished Jul 12 06:23:53 PM PDT 24
Peak memory 223064 kb
Host smart-7b1a8ee6-f31b-4b28-98ac-d09a2c2636bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3819417497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3819417497
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3790032062
Short name T421
Test name
Test status
Simulation time 2328920242 ps
CPU time 10.8 seconds
Started Jul 12 06:23:40 PM PDT 24
Finished Jul 12 06:23:52 PM PDT 24
Peak memory 218736 kb
Host smart-3c6b7bb6-8d87-4896-aca3-c10a3eda56c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790032062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3790032062
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1107540657
Short name T838
Test name
Test status
Simulation time 389863501 ps
CPU time 2.33 seconds
Started Jul 12 06:23:38 PM PDT 24
Finished Jul 12 06:23:41 PM PDT 24
Peak memory 217144 kb
Host smart-70073136-9a68-497e-9866-b7a2dc867764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107540657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1107540657
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1853727865
Short name T879
Test name
Test status
Simulation time 18520856 ps
CPU time 0.78 seconds
Started Jul 12 06:23:46 PM PDT 24
Finished Jul 12 06:23:47 PM PDT 24
Peak memory 206956 kb
Host smart-27ecbb98-3cad-4506-abaa-3465d5a889a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853727865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1853727865
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3792348348
Short name T368
Test name
Test status
Simulation time 135783512 ps
CPU time 0.75 seconds
Started Jul 12 06:23:47 PM PDT 24
Finished Jul 12 06:23:48 PM PDT 24
Peak memory 206876 kb
Host smart-4b7f4752-5c45-4634-b772-d32e49b8edb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792348348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3792348348
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3794235935
Short name T3
Test name
Test status
Simulation time 60863587924 ps
CPU time 23.1 seconds
Started Jul 12 06:23:46 PM PDT 24
Finished Jul 12 06:24:10 PM PDT 24
Peak memory 249964 kb
Host smart-6a8b1323-29b6-47ea-977d-9047f65441fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794235935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3794235935
Directory /workspace/9.spi_device_upload/latest
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