Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2870980	1			T1	1196		T2	1		T3	1
all_values[1]	2870980	1			T1	1196		T2	1		T3	1
all_values[2]	2870980	1			T1	1196		T2	1		T3	1
all_values[3]	2870980	1			T1	1196		T2	1		T3	1
all_values[4]	2870980	1			T1	1196		T2	1		T3	1
all_values[5]	2870980	1			T1	1196		T2	1		T3	1
all_values[6]	2870980	1			T1	1196		T2	1		T3	1
all_values[7]	2870980	1			T1	1196		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22263195

1

T1

9568

T2

8

T3

8

auto[1]

704645

1

T9

38

T16

87

T18

86

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22939921

1

T1

9568

T2

8

T3

8

auto[1]

27919

1

T7

344

T9

23

T34

247

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2848759	1			T1	1196		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	12959	1			T7	200		T9	2		T34	95
all_values[0]	auto[1]	auto[0]	9018	1			T9	3		T16	10		T18	13
all_values[0]	auto[1]	auto[1]	244	1			T9	1		T16	7		T18	6
all_values[1]	auto[0]	auto[0]	2759184	1			T1	1196		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	8762	1			T7	129		T34	86		T35	64
all_values[1]	auto[1]	auto[0]	102732	1			T9	3		T16	5		T18	6
all_values[1]	auto[1]	auto[1]	302	1			T9	3		T16	5		T18	1
all_values[2]	auto[0]	auto[0]	2809269	1			T1	1196		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	3521	1			T7	15		T9	1		T34	66
all_values[2]	auto[1]	auto[0]	57938	1			T9	3		T16	3		T18	4
all_values[2]	auto[1]	auto[1]	252	1			T9	3		T16	4		T18	4
all_values[3]	auto[0]	auto[0]	2739632	1			T1	1196		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	189	1			T9	2		T16	1		T18	9
all_values[3]	auto[1]	auto[0]	130974	1			T9	4		T16	14		T18	2
all_values[3]	auto[1]	auto[1]	185	1			T9	1		T16	5		T18	2
all_values[4]	auto[0]	auto[0]	2815082	1			T1	1196		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	204	1			T9	2		T16	7		T18	4
all_values[4]	auto[1]	auto[0]	55516	1			T9	2		T16	4		T18	7
all_values[4]	auto[1]	auto[1]	178	1			T16	4		T18	5		T19	3
all_values[5]	auto[0]	auto[0]	2755860	1			T1	1196		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	170	1			T16	5		T18	3		T19	4
all_values[5]	auto[1]	auto[0]	114775	1			T9	4		T16	1		T18	10
all_values[5]	auto[1]	auto[1]	175	1			T9	2		T16	7		T18	2
all_values[6]	auto[0]	auto[0]	2713347	1			T1	1196		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	186	1			T9	3		T16	7		T18	5
all_values[6]	auto[1]	auto[0]	157226	1			T9	1		T16	3		T18	11
all_values[6]	auto[1]	auto[1]	221	1			T9	2		T16	4		T18	4
all_values[7]	auto[0]	auto[0]	2795873	1			T1	1196		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	198	1			T16	2		T18	1		T19	3
all_values[7]	auto[1]	auto[0]	74736	1			T9	5		T16	7		T18	6
all_values[7]	auto[1]	auto[1]	173	1			T9	1		T16	4		T18	3