Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36909	1			T1	551		T2	2		T5	6
auto[SpiFlashAddrCfg]	7767	1			T1	37		T2	2		T7	44
auto[SpiFlashAddr3b]	9705	1			T1	64		T5	4		T7	44
auto[SpiFlashAddr4b]	8209	1			T1	44		T5	2		T7	53

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35602

1

T1

339

T5

12

T7

154

auto[1]

26988

1

T1

357

T2

4

T7

160

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34357

1

T1

397

T2

2

T5

4

auto[1]

28233

1

T1

299

T2

2

T5

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41640	1			T1	567		T2	2		T5	8
values[1]	1251	1			T1	10		T7	6		T10	3
values[2]	1552	1			T1	4		T2	2		T5	2
values[3]	1645	1			T1	7		T7	8		T10	5
values[4]	1592	1			T1	1		T5	2		T7	11
values[5]	1494	1			T1	6		T7	13		T10	5
values[6]	1514	1			T1	12		T7	4		T10	1
values[7]	1480	1			T1	13		T7	13		T10	6
values[8]	10422	1			T1	76		T7	45		T10	25

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35713

1

T1

696

T2

4

T5

12

auto[1]

26877

1

T7

314

T11

173

T14

441

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

59256

1

T1

680

T2

4

T5

10

write

3334

1

T1

16

T5

2

T7

20

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20236

1

T1

136

T2

2

T5

2

valids[0x1]

42354

1

T1

560

T2

2

T5

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1660	1			T1	18		T2	2		T7	5
internal_process_ops[0x5a]	1678	1			T1	9		T7	10		T10	1
internal_process_ops[0x05]	22353	1			T1	444		T7	88		T10	4
internal_process_ops[0x35]	1687	1			T1	7		T7	9		T10	5
internal_process_ops[0x15]	1665	1			T1	9		T5	6		T7	12
internal_process_ops[0x03]	1098	1			T1	7		T7	1		T10	7
internal_process_ops[0x0b]	1113	1			T1	8		T5	2		T7	4
internal_process_ops[0x3b]	1120	1			T1	10		T7	2		T10	4
internal_process_ops[0x6b]	1143	1			T1	13		T7	2		T10	1
internal_process_ops[0xbb]	1152	1			T1	6		T2	2		T7	2
internal_process_ops[0xeb]	1148	1			T1	10		T7	3		T10	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60859

1

T1

689

T2

4

T5

12

auto[1]

1731

1

T1

7

T7

8

T10

14

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60146

1

T1

677

T2

4

T5

12

auto[1]

2444

1

T1

19

T7

17

T10

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12502

1

T1

263

T5

6

T10

39

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7362

1

T1

285

T2

2

T10

11

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2214

1

T1

17

T10

4

T50

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1985

1

T1

15

T2

2

T10

7

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2810

1

T1

32

T5

2

T10

9

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2542

1

T1

30

T10

12

T47

23

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2364

1

T1

21

T5

2

T10

9

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2144

1

T1

17

T10

14

T13

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

143

1

T10

1

T47

2

T34

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

138

1

T47

4

T34

1

T52

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

92

1

T47

1

T34

1

T51

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

105

1

T1

3

T10

4

T47

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

104

1

T47

3

T34

1

T164

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

108

1

T10

3

T47

2

T34

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

93

1

T1

2

T47

2

T134

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

101

1

T1

3

T13

2

T47

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

109

1

T1

1

T5

2

T12

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

108

1

T134

2

T80

1

T165

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

109

1

T1

1

T47

7

T51

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

120

1

T10

3

T47

5

T51

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

137

1

T1

5

T50

2

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

99

1

T10

1

T47

2

T34

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

95

1

T47

4

T34

1

T17

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

129

1

T1

1

T10

3

T47

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9306

1

T7

82

T11

109

T14

253

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6882

1

T7

86

T11

7

T14

32

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1420

1

T7

20

T11

6

T14

15

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1361

1

T7

18

T11

2

T14

29

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1724

1

T7

18

T11

7

T14

30

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1804

1

T7

25

T11

5

T14

25

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1480

1

T7

22

T11

13

T14

9

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1356

1

T7

23

T11

10

T14

26

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

119

1

T7

2

T14

7

T35

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

91

1

T7

1

T11

2

T35

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

74

1

T7

1

T14

1

T15

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

95

1

T7

1

T14

1

T35

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

86

1

T11

1

T14

1

T35

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

118

1

T14

3

T35

3

T104

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

82

1

T7

3

T14

1

T35

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

95

1

T7

3

T14

2

T15

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

102

1

T14

1

T15

8

T104

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

100

1

T7

1

T14

2

T15

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

75

1

T35

1

T86

1

T166

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

102

1

T11

5

T103

2

T35

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

91

1

T7

6

T14

1

T15

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

129

1

T7

2

T11

2

T14

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

92

1

T35

2

T15

2

T167

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

93

1

T11

4

T35

2

T105

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4342	1			T1	57		T10	26		T47	52
auto[0]	values[0]	valids[0x1]	18744	1			T1	510		T2	2		T5	8
auto[0]	values[1]	valids[0x1]	684	1			T1	10		T10	3		T47	5
auto[0]	values[2]	valids[0x0]	587	1			T1	2		T2	2		T10	2
auto[0]	values[2]	valids[0x1]	336	1			T1	2		T5	2		T10	2
auto[0]	values[3]	valids[0x0]	612	1			T1	2		T10	1		T47	7
auto[0]	values[3]	valids[0x1]	377	1			T1	5		T10	4		T47	4
auto[0]	values[4]	valids[0x0]	610	1			T1	1		T5	2		T50	2
auto[0]	values[4]	valids[0x1]	375	1			T10	3		T47	3		T88	2
auto[0]	values[5]	valids[0x0]	548	1			T1	5		T10	3		T47	7
auto[0]	values[5]	valids[0x1]	381	1			T1	1		T10	2		T34	3
auto[0]	values[6]	valids[0x0]	601	1			T1	10		T47	6		T34	5
auto[0]	values[6]	valids[0x1]	301	1			T1	2		T10	1		T47	3
auto[0]	values[7]	valids[0x0]	600	1			T1	9		T10	5		T47	6
auto[0]	values[7]	valids[0x1]	302	1			T1	4		T10	1		T47	2
auto[0]	values[8]	valids[0x0]	3994	1			T1	50		T10	12		T13	6
auto[0]	values[8]	valids[0x1]	2319	1			T1	26		T10	13		T12	2
auto[1]	values[0]	valids[0x0]	3691	1			T7	50		T11	12		T14	52
auto[1]	values[0]	valids[0x1]	14863	1			T7	154		T11	126		T14	267
auto[1]	values[1]	valids[0x1]	567	1			T7	6		T11	6		T14	3
auto[1]	values[2]	valids[0x0]	380	1			T7	9		T11	3		T14	7
auto[1]	values[2]	valids[0x1]	249	1			T7	1		T11	1		T14	4
auto[1]	values[3]	valids[0x0]	393	1			T7	7		T14	6		T103	2
auto[1]	values[3]	valids[0x1]	263	1			T7	1		T11	1		T14	3
auto[1]	values[4]	valids[0x0]	366	1			T7	9		T11	1		T14	8
auto[1]	values[4]	valids[0x1]	241	1			T7	2		T14	4		T103	2
auto[1]	values[5]	valids[0x0]	342	1			T7	6		T14	7		T35	3
auto[1]	values[5]	valids[0x1]	223	1			T7	7		T35	4		T15	2
auto[1]	values[6]	valids[0x0]	377	1			T14	8		T35	8		T15	10
auto[1]	values[6]	valids[0x1]	235	1			T7	4		T11	2		T14	3
auto[1]	values[7]	valids[0x0]	349	1			T7	3		T11	1		T14	9
auto[1]	values[7]	valids[0x1]	229	1			T7	10		T11	3		T14	2
auto[1]	values[8]	valids[0x0]	2444	1			T7	24		T11	11		T14	30
auto[1]	values[8]	valids[0x1]	1665	1			T7	21		T11	6		T14	28