Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3676641

1

T1

16933

T2

1

T5

1

auto[1]

30541

1

T1

436

T7

74

T10

37

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086849

1

T1

98

T2

1

T5

1

auto[1]

2620333

1

T1

17271

T7

10951

T10

2834

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	752186	1			T1	4337		T2	1		T5	1
auto[524288:1048575]	391813	1			T1	111		T7	3664		T10	536
auto[1048576:1572863]	426209	1			T1	3388		T7	263		T10	326
auto[1572864:2097151]	407463	1			T1	3440		T7	891		T10	566
auto[2097152:2621439]	427889	1			T1	2004		T7	39		T10	5
auto[2621440:3145727]	443499	1			T1	157		T7	3051		T10	154
auto[3145728:3670015]	415104	1			T1	3708		T7	295		T10	13
auto[3670016:4194303]	443019	1			T1	224		T7	2319		T10	293

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2654936

1

T1

17355

T2

1

T5

1

auto[1]

1052246

1

T1

14

T7

1

T10

5

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3212499

1

T1

15606

T2

1

T5

1

auto[1]

494683

1

T1

1763

T7

1295

T10

652

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	287043	1			T1	9		T2	1		T5	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	398691	1			T1	4266		T7	512		T10	1048
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	101932	1			T1	6		T7	19		T10	21
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	228724	1			T1	3		T7	3374		T10	512
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	128222	1			T1	16		T7	2		T10	47
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	246920	1			T1	2995		T7	261		T10	263
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	94874	1			T1	4		T7	4		T10	20
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	250492	1			T1	3410		T7	884		T10	12
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	111916	1			T1	9		T7	7		T10	5
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	250032	1			T1	1995		T7	4		T11	695
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	110347	1			T1	8		T7	9		T10	17
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	254191	1			T1	134		T7	3034		T10	133
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	121266	1			T1	11		T7	12		T10	13
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	225387	1			T1	2386		T7	263		T11	4153
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	117893	1			T1	5		T7	7		T10	27
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	260531	1			T1	1		T7	1280		T10	256
auto[0]	auto[1]	auto[0:524287]	auto[0]	761	1			T1	1		T7	2		T10	12
auto[0]	auto[1]	auto[0:524287]	auto[1]	60901	1			T10	98		T35	3		T15	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1411	1			T1	1		T7	4		T14	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	56905	1			T1	5		T7	257		T14	1860
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	644	1			T1	2		T11	2		T14	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	45598	1			T1	256		T14	7		T47	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2747	1			T7	1		T10	22		T47	61
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	56320	1			T7	1		T10	512		T47	1006
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	963	1			T11	2		T47	31		T34	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	60683	1			T47	3840		T34	1955		T35	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	657	1			T1	1		T10	4		T14	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	74045	1			T35	640		T15	385		T105	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1053	1			T1	4		T15	1		T104	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	63765	1			T1	1226		T11	358		T35	78
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1132	1			T1	2		T7	1		T10	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	60595	1			T1	177		T7	1024		T35	941
auto[1]	auto[0]	auto[0:524287]	auto[0]	539	1			T1	3		T10	12		T47	45
auto[1]	auto[0]	auto[0:524287]	auto[1]	3483	1			T1	58		T47	209		T34	46
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	389	1			T1	3		T7	3		T10	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2036	1			T1	55		T7	3		T35	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	387	1			T1	5		T10	16		T11	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3989	1			T1	114		T11	3		T14	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	317	1			T1	1		T11	2		T14	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1772	1			T1	25		T11	24		T14	58
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	398	1			T7	4		T11	1		T14	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2920	1			T7	24		T11	7		T14	79
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	415	1			T1	2		T7	2		T14	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2522	1			T1	12		T7	6		T14	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	363	1			T1	1		T7	3		T11	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2028	1			T1	30		T7	17		T11	53
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	402	1			T1	1		T7	3		T10	6
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2078	1			T1	38		T7	4		T34	38
auto[1]	auto[1]	auto[0:524287]	auto[0]	113	1			T35	3		T15	1		T52	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	655	1			T35	49		T15	13		T52	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	94	1			T1	1		T7	1		T14	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	322	1			T1	37		T7	3		T14	30
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	115	1			T167	1		T86	1		T17	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	334	1			T167	12		T86	21		T17	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	96	1			T7	1		T47	14		T35	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	845	1			T47	233		T35	8		T15	15
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	100	1			T47	10		T34	1		T15	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	877	1			T47	282		T34	3		T15	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	82	1			T15	1		T105	1		T81	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1240	1			T15	11		T81	1		T217	12
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	132	1			T1	2		T167	1		T92	12
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1110	1			T1	48		T167	3		T80	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	46	1			T52	2		T166	1		T18	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	342	1			T52	37		T166	32		T18	3

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2141222	1			T1	15250		T2	1		T5	1
auto[0]	auto[0]	auto[1]	1047239	1			T1	8		T7	1		T14	3
auto[0]	auto[1]	auto[0]	483842	1			T1	1673		T7	1290		T10	652
auto[0]	auto[1]	auto[1]	4338	1			T1	2		T14	1		T35	1
auto[1]	auto[0]	auto[0]	23512	1			T1	345		T7	69		T10	32
auto[1]	auto[0]	auto[1]	526	1			T1	3		T10	5		T47	19
auto[1]	auto[1]	auto[0]	6360	1			T1	87		T7	5		T14	31
auto[1]	auto[1]	auto[1]	143	1			T1	1		T47	7		T35	1