Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2870980	1			T1	1196		T2	1		T3	1
all_pins[1]	2870980	1			T1	1196		T2	1		T3	1
all_pins[2]	2870980	1			T1	1196		T2	1		T3	1
all_pins[3]	2870980	1			T1	1196		T2	1		T3	1
all_pins[4]	2870980	1			T1	1196		T2	1		T3	1
all_pins[5]	2870980	1			T1	1196		T2	1		T3	1
all_pins[6]	2870980	1			T1	1196		T2	1		T3	1
all_pins[7]	2870980	1			T1	1196		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22810272	1			T1	9568		T2	8		T3	8
values[0x1]	157568	1			T9	13		T16	40		T18	27
transitions[0x0=>0x1]	155845	1			T9	9		T16	24		T18	21
transitions[0x1=>0x0]	155855	1			T9	9		T16	24		T18	21

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2870720	1			T1	1196		T2	1		T3	1
all_pins[0]	values[0x1]	260	1			T9	1		T16	7		T18	6
all_pins[0]	transitions[0x0=>0x1]	194	1			T16	3		T18	5		T19	2
all_pins[0]	transitions[0x1=>0x0]	256	1			T9	2		T16	1		T19	2
all_pins[1]	values[0x0]	2870658	1			T1	1196		T2	1		T3	1
all_pins[1]	values[0x1]	322	1			T9	3		T16	5		T18	1
all_pins[1]	transitions[0x0=>0x1]	269	1			T9	1		T16	4		T18	1
all_pins[1]	transitions[0x1=>0x0]	208	1			T9	1		T16	3		T18	4
all_pins[2]	values[0x0]	2870719	1			T1	1196		T2	1		T3	1
all_pins[2]	values[0x1]	261	1			T9	3		T16	4		T18	4
all_pins[2]	transitions[0x0=>0x1]	208	1			T9	3		T16	3		T18	4
all_pins[2]	transitions[0x1=>0x0]	132	1			T9	1		T16	4		T18	2
all_pins[3]	values[0x0]	2870795	1			T1	1196		T2	1		T3	1
all_pins[3]	values[0x1]	185	1			T9	1		T16	5		T18	2
all_pins[3]	transitions[0x0=>0x1]	139	1			T9	1		T16	4		T18	1
all_pins[3]	transitions[0x1=>0x0]	132	1			T16	3		T18	4		T19	3
all_pins[4]	values[0x0]	2870802	1			T1	1196		T2	1		T3	1
all_pins[4]	values[0x1]	178	1			T16	4		T18	5		T19	3
all_pins[4]	transitions[0x0=>0x1]	137	1			T16	1		T18	4		T19	2
all_pins[4]	transitions[0x1=>0x0]	1736	1			T9	2		T16	4		T18	1
all_pins[5]	values[0x0]	2869203	1			T1	1196		T2	1		T3	1
all_pins[5]	values[0x1]	1777	1			T9	2		T16	7		T18	2
all_pins[5]	transitions[0x0=>0x1]	408	1			T9	2		T16	4		T18	2
all_pins[5]	transitions[0x1=>0x0]	153043	1			T9	2		T16	1		T18	4
all_pins[6]	values[0x0]	2716568	1			T1	1196		T2	1		T3	1
all_pins[6]	values[0x1]	154412	1			T9	2		T16	4		T18	4
all_pins[6]	transitions[0x0=>0x1]	154360	1			T9	1		T16	3		T18	2
all_pins[6]	transitions[0x1=>0x0]	121	1			T16	3		T18	1		T19	7
all_pins[7]	values[0x0]	2870807	1			T1	1196		T2	1		T3	1
all_pins[7]	values[0x1]	173	1			T9	1		T16	4		T18	3
all_pins[7]	transitions[0x0=>0x1]	130	1			T9	1		T16	2		T18	2
all_pins[7]	transitions[0x1=>0x0]	227	1			T9	1		T16	5		T18	5