Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20836

1

T1

339

T5

12

T10

66

auto[1]

14877

1

T1

357

T2

4

T10

54

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4878	1			T1	201		T10	20		T50	14
values[1]	4156	1			T1	129		T34	20		T51	53
values[2]	4369	1			T13	20		T47	20		T88	12
values[3]	4389	1			T47	60		T34	44		T204	10
values[4]	4859	1			T1	180		T10	20		T47	40
values[5]	4674	1			T1	20		T10	40		T47	60
values[6]	4138	1			T1	103		T5	12		T10	20
values[7]	4250	1			T1	63		T2	4		T10	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4418	1			T1	130		T10	40		T47	20
values[1]	3742	1			T5	12		T47	40		T88	12
values[2]	4772	1			T1	141		T10	20		T50	14
values[3]	4121	1			T1	59		T10	20		T47	60
values[4]	5654	1			T1	143		T47	20		T34	121
values[5]	4365	1			T1	57		T10	20		T12	10
values[6]	4037	1			T1	45		T2	4		T10	20
values[7]	4604	1			T1	121		T34	20		T222	14

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	390	1			T1	16		T51	8		T164	54
auto[0]	values[0]	values[1]	339	1			T81	9		T184	9		T185	13
auto[0]	values[0]	values[2]	373	1			T50	14		T54	13		T80	27
auto[0]	values[0]	values[3]	203	1			T178	24		T223	6		T221	13
auto[0]	values[0]	values[4]	354	1			T1	8		T47	9		T184	12
auto[0]	values[0]	values[5]	429	1			T1	51		T219	24		T20	19
auto[0]	values[0]	values[6]	486	1			T1	14		T10	12		T52	14
auto[0]	values[0]	values[7]	347	1			T1	11		T206	13		T198	44
auto[0]	values[1]	values[0]	304	1			T51	10		T81	10		T80	46
auto[0]	values[1]	values[1]	285	1			T184	13		T224	16		T225	10
auto[0]	values[1]	values[2]	336	1			T51	9		T226	13		T227	38
auto[0]	values[1]	values[3]	277	1			T1	12		T20	18		T228	12
auto[0]	values[1]	values[4]	328	1			T134	13		T80	6		T165	16
auto[0]	values[1]	values[5]	194	1			T54	13		T81	9		T229	26
auto[0]	values[1]	values[6]	189	1			T80	11		T184	12		T206	12
auto[0]	values[1]	values[7]	350	1			T1	10		T34	6		T81	11
auto[0]	values[2]	values[0]	312	1			T34	15		T54	10		T185	17
auto[0]	values[2]	values[1]	208	1			T88	12		T51	9		T198	11
auto[0]	values[2]	values[2]	187	1			T164	14		T134	13		T230	2
auto[0]	values[2]	values[3]	315	1			T165	11		T69	11		T179	58
auto[0]	values[2]	values[4]	495	1			T34	15		T17	14		T80	14
auto[0]	values[2]	values[5]	292	1			T34	9		T193	12		T210	15
auto[0]	values[2]	values[6]	352	1			T47	17		T34	13		T80	10
auto[0]	values[2]	values[7]	295	1			T216	24		T231	10		T232	20
auto[0]	values[3]	values[0]	388	1			T34	15		T189	6		T137	11
auto[0]	values[3]	values[1]	246	1			T34	14		T233	2		T20	6
auto[0]	values[3]	values[2]	472	1			T47	11		T206	75		T198	23
auto[0]	values[3]	values[3]	273	1			T47	9		T134	10		T36	13
auto[0]	values[3]	values[4]	210	1			T206	11		T207	9		T234	13
auto[0]	values[3]	values[5]	352	1			T183	16		T186	26		T190	4
auto[0]	values[3]	values[6]	346	1			T47	11		T17	10		T81	9
auto[0]	values[3]	values[7]	331	1			T204	10		T185	9		T198	84
auto[0]	values[4]	values[0]	387	1			T1	93		T184	10		T183	10
auto[0]	values[4]	values[1]	132	1			T18	9		T209	18		T137	14
auto[0]	values[4]	values[2]	574	1			T1	71		T47	9		T164	11
auto[0]	values[4]	values[3]	401	1			T10	11		T17	23		T134	12
auto[0]	values[4]	values[4]	396	1			T34	11		T54	6		T235	6
auto[0]	values[4]	values[5]	382	1			T47	15		T34	16		T137	15
auto[0]	values[4]	values[6]	258	1			T51	28		T201	10		T133	8
auto[0]	values[4]	values[7]	365	1			T52	63		T134	8		T80	12
auto[0]	values[5]	values[0]	357	1			T10	11		T54	14		T134	43
auto[0]	values[5]	values[1]	331	1			T47	23		T134	12		T215	22
auto[0]	values[5]	values[2]	248	1			T1	13		T81	13		T206	11
auto[0]	values[5]	values[3]	324	1			T47	15		T81	9		T188	24
auto[0]	values[5]	values[4]	447	1			T236	4		T81	49		T185	11
auto[0]	values[5]	values[5]	249	1			T10	10		T89	6		T200	10
auto[0]	values[5]	values[6]	219	1			T165	9		T185	14		T207	25
auto[0]	values[5]	values[7]	406	1			T51	15		T218	8		T91	2
auto[0]	values[6]	values[0]	333	1			T10	12		T47	4		T80	34
auto[0]	values[6]	values[1]	183	1			T5	12		T237	22		T165	11
auto[0]	values[6]	values[2]	461	1			T238	2		T198	12		T137	12
auto[0]	values[6]	values[3]	357	1			T47	14		T18	11		T90	14
auto[0]	values[6]	values[4]	424	1			T1	18		T34	42		T54	11
auto[0]	values[6]	values[5]	319	1			T52	9		T184	10		T20	20
auto[0]	values[6]	values[6]	247	1			T47	14		T206	10		T239	10
auto[0]	values[6]	values[7]	291	1			T195	20		T185	7		T186	10
auto[0]	values[7]	values[0]	297	1			T34	106		T202	12		T36	20
auto[0]	values[7]	values[1]	254	1			T54	14		T134	15		T80	20
auto[0]	values[7]	values[2]	286	1			T1	12		T10	10		T47	14
auto[0]	values[7]	values[3]	352	1			T25	8		T80	9		T20	33
auto[0]	values[7]	values[4]	306	1			T1	10		T27	14		T134	9
auto[0]	values[7]	values[5]	377	1			T12	10		T205	2		T197	14
auto[0]	values[7]	values[6]	309	1			T240	40		T241	30		T242	8
auto[0]	values[7]	values[7]	306	1			T222	14		T51	8		T36	11
auto[1]	values[0]	values[0]	237	1			T1	12		T51	22		T164	7
auto[1]	values[0]	values[1]	234	1			T81	12		T184	15		T185	7
auto[1]	values[0]	values[2]	182	1			T54	11		T80	9		T185	18
auto[1]	values[0]	values[3]	115	1			T221	7		T59	7		T211	11
auto[1]	values[0]	values[4]	294	1			T1	12		T47	11		T184	16
auto[1]	values[0]	values[5]	335	1			T1	6		T20	6		T137	5
auto[1]	values[0]	values[6]	136	1			T1	31		T10	8		T52	6
auto[1]	values[0]	values[7]	424	1			T1	40		T206	76		T198	13
auto[1]	values[1]	values[0]	172	1			T51	23		T81	10		T80	10
auto[1]	values[1]	values[1]	277	1			T243	2		T184	7		T225	23
auto[1]	values[1]	values[2]	151	1			T51	11		T226	11		T227	7
auto[1]	values[1]	values[3]	214	1			T1	47		T20	28		T196	7
auto[1]	values[1]	values[4]	516	1			T134	43		T80	21		T165	5
auto[1]	values[1]	values[5]	183	1			T54	9		T81	11		T183	5
auto[1]	values[1]	values[6]	184	1			T80	17		T184	15		T206	8
auto[1]	values[1]	values[7]	196	1			T1	60		T34	14		T81	11
auto[1]	values[2]	values[0]	270	1			T34	85		T54	11		T185	23
auto[1]	values[2]	values[1]	225	1			T51	11		T198	9		T72	8
auto[1]	values[2]	values[2]	221	1			T164	62		T134	36		T244	11
auto[1]	values[2]	values[3]	168	1			T165	9		T69	10		T179	12
auto[1]	values[2]	values[4]	425	1			T34	5		T17	7		T80	22
auto[1]	values[2]	values[5]	215	1			T13	20		T34	11		T210	9
auto[1]	values[2]	values[6]	167	1			T47	3		T34	7		T80	25
auto[1]	values[2]	values[7]	222	1			T245	4		T197	8		T227	10
auto[1]	values[3]	values[0]	239	1			T34	5		T137	9		T186	10
auto[1]	values[3]	values[1]	125	1			T34	10		T55	6		T20	14
auto[1]	values[3]	values[2]	313	1			T47	9		T206	8		T198	7
auto[1]	values[3]	values[3]	175	1			T47	11		T134	10		T36	22
auto[1]	values[3]	values[4]	271	1			T206	9		T207	11		T234	7
auto[1]	values[3]	values[5]	143	1			T183	4		T186	14		T59	6
auto[1]	values[3]	values[6]	333	1			T47	9		T17	15		T81	11
auto[1]	values[3]	values[7]	172	1			T185	11		T198	11		T209	8
auto[1]	values[4]	values[0]	282	1			T1	9		T184	10		T183	25
auto[1]	values[4]	values[1]	118	1			T18	39		T209	2		T137	8
auto[1]	values[4]	values[2]	202	1			T1	7		T47	11		T164	9
auto[1]	values[4]	values[3]	281	1			T10	9		T17	27		T134	13
auto[1]	values[4]	values[4]	296	1			T34	30		T54	17		T198	9
auto[1]	values[4]	values[5]	287	1			T47	5		T34	13		T137	12
auto[1]	values[4]	values[6]	224	1			T51	12		T81	27		T185	12
auto[1]	values[4]	values[7]	274	1			T52	8		T134	12		T80	8
auto[1]	values[5]	values[0]	142	1			T10	9		T54	6		T134	9
auto[1]	values[5]	values[1]	426	1			T47	17		T134	8		T165	6
auto[1]	values[5]	values[2]	361	1			T1	7		T81	7		T206	15
auto[1]	values[5]	values[3]	328	1			T47	5		T93	14		T53	12
auto[1]	values[5]	values[4]	312	1			T81	10		T185	9		T20	17
auto[1]	values[5]	values[5]	187	1			T10	10		T17	11		T134	14
auto[1]	values[5]	values[6]	101	1			T165	11		T185	6		T207	15
auto[1]	values[5]	values[7]	236	1			T51	10		T137	7		T210	9
auto[1]	values[6]	values[0]	242	1			T10	8		T47	16		T80	9
auto[1]	values[6]	values[1]	104	1			T165	15		T36	21		T207	8
auto[1]	values[6]	values[2]	154	1			T198	8		T137	10		T183	7
auto[1]	values[6]	values[3]	158	1			T47	6		T18	66		T198	5
auto[1]	values[6]	values[4]	256	1			T1	85		T34	18		T54	9
auto[1]	values[6]	values[5]	257	1			T52	11		T184	10		T20	10
auto[1]	values[6]	values[6]	240	1			T47	6		T206	10		T69	11
auto[1]	values[6]	values[7]	112	1			T185	13		T186	10		T36	12
auto[1]	values[7]	values[0]	66	1			T34	5		T36	6		T139	9
auto[1]	values[7]	values[1]	255	1			T54	13		T134	5		T80	6
auto[1]	values[7]	values[2]	251	1			T1	31		T10	10		T47	6
auto[1]	values[7]	values[3]	180	1			T80	40		T246	2		T20	4
auto[1]	values[7]	values[4]	324	1			T1	10		T134	11		T198	8
auto[1]	values[7]	values[5]	164	1			T197	6		T227	6		T247	8
auto[1]	values[7]	values[6]	246	1			T2	4		T241	12		T242	19
auto[1]	values[7]	values[7]	277	1			T51	12		T36	74		T207	9