Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	446	1			T1	3		T10	3		T47	2
auto[ReadAddrCrossIntoMailbox]	382	1			T1	2		T10	1		T47	5
auto[ReadAddrCrossOutOfMailbox]	384	1			T1	3		T47	4		T34	10
auto[ReadAddrCrossAllMailbox]	227	1			T10	1		T47	2		T34	3
auto[ReadAddrOutsideMailbox]	3869	1			T1	46		T2	2		T5	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2572

1

T1

31

T2

1

T5

1

auto[1]

2736

1

T1

23

T2

1

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	868	1			T1	7		T10	7		T50	4
read_ops[0x0b]	864	1			T1	8		T5	2		T10	6
read_ops[0x3b]	885	1			T1	10		T10	4		T47	11
read_ops[0x6b]	897	1			T1	13		T10	1		T50	2
read_ops[0xbb]	891	1			T1	6		T2	2		T10	1
read_ops[0xeb]	903	1			T1	10		T10	4		T12	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T165	1		T205	1		T186	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T10	1		T34	1		T54	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T47	1		T185	1		T36	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	37	1			T51	2		T54	1		T80	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T164	1		T89	1		T80	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T34	5		T89	1		T36	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T47	1		T165	1		T198	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T34	2		T51	1		T184	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	297	1			T1	4		T10	2		T50	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	325	1			T1	3		T10	4		T50	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T54	1		T81	1		T80	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T1	1		T134	1		T206	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T34	2		T80	1		T20	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T1	1		T10	1		T47	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T34	1		T18	1		T80	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T34	1		T220	2		T185	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T47	1		T20	1		T59	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T164	1		T165	1		T36	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	316	1			T1	4		T5	1		T10	5
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	332	1			T1	2		T5	1		T50	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T1	1		T52	1		T164	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T81	1		T165	1		T185	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T1	1		T52	1		T51	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T47	1		T81	1		T165	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T51	1		T54	1		T165	3
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T47	1		T18	1		T137	3
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T164	1		T236	1		T81	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T236	1		T18	1		T165	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	315	1			T1	5		T10	2		T47	6
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	331	1			T1	3		T10	2		T47	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T1	1		T54	1		T218	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T34	1		T51	1		T164	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T34	1		T206	1		T20	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	44	1			T164	2		T134	1		T81	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T47	1		T34	1		T89	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T1	1		T47	1		T51	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T89	1		T80	1		T137	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T52	1		T164	1		T89	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	327	1			T1	4		T50	1		T47	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	330	1			T1	7		T10	1		T50	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T47	2		T34	2		T52	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T164	1		T81	1		T220	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T34	1		T183	1		T179	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T34	1		T51	1		T80	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T34	1		T54	1		T220	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T52	1		T54	2		T81	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T51	1		T236	1		T220	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T51	1		T236	1		T54	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	329	1			T1	4		T2	1		T10	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	316	1			T1	2		T2	1		T50	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T10	1		T51	1		T184	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T10	1		T52	1		T51	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T47	1		T80	2		T185	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T80	1		T183	1		T186	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T1	1		T47	1		T34	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	41	1			T1	1		T51	1		T54	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T10	1		T34	1		T54	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T184	1		T198	2		T183	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	308	1			T1	6		T10	1		T12	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	343	1			T1	2		T12	1		T47	5