Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4754	1			T1	240		T10	20		T47	20
values[1]	4084	1			T1	63		T10	40		T13	20
values[2]	5482	1			T1	20		T47	40		T34	153
values[3]	4370	1			T1	102		T2	4		T47	40
values[4]	4617	1			T1	173		T88	12		T27	14
values[5]	3553	1			T1	78		T10	20		T47	60
values[6]	4461	1			T10	20		T50	14		T34	61
values[7]	4392	1			T1	20		T5	12		T10	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4016	1			T1	256		T50	14		T47	60
values[1]	3834	1			T34	20		T52	20		T51	53
values[2]	4588	1			T1	20		T10	60		T47	80
values[3]	4650	1			T1	100		T2	4		T47	20
values[4]	4523	1			T1	48		T10	40		T47	20
values[5]	4736	1			T1	137		T34	60		T53	12
values[6]	5362	1			T1	135		T5	12		T10	20
values[7]	4004	1			T12	10		T13	20		T47	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34805

1

T1

689

T2

4

T5

12

auto[1]

908

1

T1

7

T10

14

T13

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	346	1			T1	51		T34	20		T201	10
auto[0]	values[0]	values[1]	543	1			T52	20		T185	18		T248	2
auto[0]	values[0]	values[2]	555	1			T10	19		T47	20		T17	24
auto[0]	values[0]	values[3]	533	1			T1	57		T237	22		T54	26
auto[0]	values[0]	values[4]	536	1			T1	28		T34	20		T80	46
auto[0]	values[0]	values[5]	798	1			T1	59		T34	56		T54	19
auto[0]	values[0]	values[6]	673	1			T1	44		T34	109		T80	33
auto[0]	values[0]	values[7]	646	1			T20	20		T209	20		T183	42
auto[0]	values[1]	values[0]	591	1			T47	19		T52	20		T81	41
auto[0]	values[1]	values[1]	341	1			T34	20		T89	6		T246	2
auto[0]	values[1]	values[2]	572	1			T10	18		T47	20		T25	8
auto[0]	values[1]	values[3]	428	1			T1	42		T134	29		T185	20
auto[0]	values[1]	values[4]	604	1			T1	20		T10	18		T134	54
auto[0]	values[1]	values[5]	391	1			T234	24		T71	38		T244	45
auto[0]	values[1]	values[6]	607	1			T47	57		T51	27		T80	22
auto[0]	values[1]	values[7]	437	1			T13	18		T215	22		T90	14
auto[0]	values[2]	values[0]	575	1			T47	20		T51	38		T81	20
auto[0]	values[2]	values[1]	442	1			T51	18		T224	16		T137	40
auto[0]	values[2]	values[2]	416	1			T34	29		T164	61		T81	20
auto[0]	values[2]	values[3]	862	1			T47	20		T81	62		T249	20
auto[0]	values[2]	values[4]	969	1			T34	24		T51	25		T134	46
auto[0]	values[2]	values[5]	746	1			T53	10		T165	19		T185	20
auto[0]	values[2]	values[6]	870	1			T1	20		T34	100		T81	79
auto[0]	values[2]	values[7]	498	1			T20	26		T212	40		T213	41
auto[0]	values[3]	values[0]	395	1			T1	102		T34	20		T220	20
auto[0]	values[3]	values[1]	563	1			T51	32		T134	19		T80	21
auto[0]	values[3]	values[2]	460	1			T47	19		T72	18		T250	22
auto[0]	values[3]	values[3]	673	1			T2	4		T54	17		T184	43
auto[0]	values[3]	values[4]	334	1			T47	15		T210	22		T69	20
auto[0]	values[3]	values[5]	400	1			T184	94		T20	37		T183	35
auto[0]	values[3]	values[6]	940	1			T54	20		T185	18		T183	27
auto[0]	values[3]	values[7]	478	1			T238	2		T17	17		T193	12
auto[0]	values[4]	values[0]	492	1			T1	103		T88	12		T185	20
auto[0]	values[4]	values[1]	545	1			T134	20		T80	56		T185	20
auto[0]	values[4]	values[2]	707	1			T54	20		T133	8		T18	46
auto[0]	values[4]	values[3]	494	1			T27	14		T195	20		T164	75
auto[0]	values[4]	values[4]	455	1			T134	20		T226	24		T196	46
auto[0]	values[4]	values[5]	519	1			T185	18		T209	20		T231	10
auto[0]	values[4]	values[6]	656	1			T1	68		T81	20		T183	40
auto[0]	values[4]	values[7]	628	1			T17	24		T198	20		T36	91
auto[0]	values[5]	values[0]	552	1			T47	17		T222	14		T17	21
auto[0]	values[5]	values[1]	344	1			T186	18		T179	30		T158	25
auto[0]	values[5]	values[2]	303	1			T47	19		T165	24		T179	123
auto[0]	values[5]	values[3]	423	1			T164	17		T251	2		T80	36
auto[0]	values[5]	values[4]	354	1			T10	17		T93	14		T200	10
auto[0]	values[5]	values[5]	528	1			T1	75		T54	24		T81	24
auto[0]	values[5]	values[6]	504	1			T51	38		T184	19		T185	18
auto[0]	values[5]	values[7]	462	1			T47	16		T219	24		T51	30
auto[0]	values[6]	values[0]	577	1			T50	14		T18	24		T165	22
auto[0]	values[6]	values[1]	682	1			T198	20		T214	32		T137	22
auto[0]	values[6]	values[2]	477	1			T164	30		T81	31		T20	21
auto[0]	values[6]	values[3]	391	1			T137	25		T230	2		T221	18
auto[0]	values[6]	values[4]	536	1			T34	38		T36	20		T138	20
auto[0]	values[6]	values[5]	631	1			T134	44		T223	6		T179	18
auto[0]	values[6]	values[6]	424	1			T10	17		T34	20		T204	10
auto[0]	values[6]	values[7]	619	1			T206	29		T198	30		T207	19
auto[0]	values[7]	values[0]	377	1			T80	41		T165	20		T198	20
auto[0]	values[7]	values[1]	256	1			T165	17		T210	19		T240	40
auto[0]	values[7]	values[2]	974	1			T1	20		T10	17		T134	20
auto[0]	values[7]	values[3]	749	1			T134	51		T218	8		T188	24
auto[0]	values[7]	values[4]	618	1			T18	77		T80	28		T206	83
auto[0]	values[7]	values[5]	598	1			T134	23		T81	38		T192	4
auto[0]	values[7]	values[6]	568	1			T5	12		T47	17		T54	21
auto[0]	values[7]	values[7]	140	1			T12	10		T72	19		T211	20
auto[1]	values[0]	values[0]	9	1			T210	4		T227	1		T252	2
auto[1]	values[0]	values[1]	21	1			T185	2		T36	1		T207	2
auto[1]	values[0]	values[2]	18	1			T10	1		T20	2		T183	1
auto[1]	values[0]	values[3]	7	1			T54	1		T36	2		T162	2
auto[1]	values[0]	values[4]	15	1			T80	3		T185	2		T186	1
auto[1]	values[0]	values[5]	22	1			T34	4		T54	4		T210	4
auto[1]	values[0]	values[6]	16	1			T1	1		T34	2		T80	2
auto[1]	values[0]	values[7]	16	1			T183	2		T36	2		T197	1
auto[1]	values[1]	values[0]	10	1			T47	1		T137	1		T179	2
auto[1]	values[1]	values[1]	17	1			T20	2		T137	2		T186	1
auto[1]	values[1]	values[2]	17	1			T10	2		T52	2		T165	1
auto[1]	values[1]	values[3]	9	1			T1	1		T198	1		T253	2
auto[1]	values[1]	values[4]	14	1			T10	2		T134	2		T227	1
auto[1]	values[1]	values[5]	16	1			T234	1		T71	2		T244	3
auto[1]	values[1]	values[6]	17	1			T47	3		T80	4		T196	3
auto[1]	values[1]	values[7]	13	1			T13	2		T20	3		T207	1
auto[1]	values[2]	values[0]	12	1			T51	2		T59	2		T212	1
auto[1]	values[2]	values[1]	9	1			T51	2		T227	1		T247	2
auto[1]	values[2]	values[2]	10	1			T196	2		T161	1		T254	2
auto[1]	values[2]	values[3]	10	1			T81	1		T186	2		T161	2
auto[1]	values[2]	values[4]	25	1			T134	3		T206	2		T207	1
auto[1]	values[2]	values[5]	12	1			T53	2		T165	1		T161	3
auto[1]	values[2]	values[6]	15	1			T179	3		T242	2		T255	2
auto[1]	values[2]	values[7]	11	1			T256	1		T257	1		T258	1
auto[1]	values[3]	values[0]	10	1			T259	1		T260	2		T61	3
auto[1]	values[3]	values[1]	15	1			T51	1		T134	1		T206	1
auto[1]	values[3]	values[2]	11	1			T47	1		T72	2		T261	1
auto[1]	values[3]	values[3]	21	1			T54	3		T184	1		T185	1
auto[1]	values[3]	values[4]	22	1			T47	5		T210	3		T69	1
auto[1]	values[3]	values[5]	16	1			T184	2		T183	3		T211	1
auto[1]	values[3]	values[6]	17	1			T185	2		T227	5		T262	3
auto[1]	values[3]	values[7]	15	1			T17	3		T137	1		T177	2
auto[1]	values[4]	values[0]	11	1			T36	1		T210	2		T211	1
auto[1]	values[4]	values[1]	16	1			T186	1		T225	3		T263	1
auto[1]	values[4]	values[2]	26	1			T54	1		T18	2		T206	1
auto[1]	values[4]	values[3]	14	1			T164	1		T80	2		T221	1
auto[1]	values[4]	values[4]	8	1			T196	1		T264	1		T160	1
auto[1]	values[4]	values[5]	12	1			T185	2		T72	2		T59	1
auto[1]	values[4]	values[6]	19	1			T1	2		T81	2		T36	1
auto[1]	values[4]	values[7]	15	1			T17	1		T36	1		T213	1
auto[1]	values[5]	values[0]	14	1			T47	3		T59	1		T263	2
auto[1]	values[5]	values[1]	9	1			T186	2		T179	2		T158	1
auto[1]	values[5]	values[2]	5	1			T47	1		T165	2		T265	1
auto[1]	values[5]	values[3]	9	1			T164	3		T179	1		T247	1
auto[1]	values[5]	values[4]	17	1			T10	3		T55	2		T244	1
auto[1]	values[5]	values[5]	17	1			T1	3		T81	2		T198	1
auto[1]	values[5]	values[6]	7	1			T51	2		T184	1		T185	2
auto[1]	values[5]	values[7]	5	1			T47	4		T36	1		-	-
auto[1]	values[6]	values[0]	22	1			T165	1		T184	2		T209	3
auto[1]	values[6]	values[1]	25	1			T183	1		T36	2		T69	2
auto[1]	values[6]	values[2]	15	1			T164	3		T20	1		T211	3
auto[1]	values[6]	values[3]	13	1			T137	3		T221	2		T72	1
auto[1]	values[6]	values[4]	6	1			T34	3		T266	1		T267	1
auto[1]	values[6]	values[5]	14	1			T134	1		T179	2		T263	2
auto[1]	values[6]	values[6]	11	1			T10	3		T214	1		T196	1
auto[1]	values[6]	values[7]	18	1			T206	2		T207	1		T139	3
auto[1]	values[7]	values[0]	23	1			T80	2		T165	1		T221	1
auto[1]	values[7]	values[1]	6	1			T165	3		T210	1		T258	2
auto[1]	values[7]	values[2]	22	1			T10	3		T177	1		T60	3
auto[1]	values[7]	values[3]	14	1			T134	1		T196	2		T213	2
auto[1]	values[7]	values[4]	10	1			T247	3		T268	1		T269	3
auto[1]	values[7]	values[5]	16	1			T134	1		T81	1		T186	2
auto[1]	values[7]	values[6]	18	1			T47	3		T54	1		T17	1
auto[1]	values[7]	values[7]	3	1			T72	1		T61	2		-	-