Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	776	1			T9	7		T16	17		T18	18
all_values[1]	776	1			T9	7		T16	17		T18	18
all_values[2]	776	1			T9	7		T16	17		T18	18
all_values[3]	776	1			T9	7		T16	17		T18	18
all_values[4]	776	1			T9	7		T16	17		T18	18
all_values[5]	776	1			T9	7		T16	17		T18	18
all_values[6]	776	1			T9	7		T16	17		T18	18
all_values[7]	776	1			T9	7		T16	17		T18	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3332

1

T9

33

T16

69

T18

86

auto[1]

2876

1

T9

23

T16

67

T18

58

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2409

1

T9

24

T16

35

T18

59

auto[1]

3799

1

T9

32

T16

101

T18

85

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3504

1

T9

34

T16

60

T18

85

auto[1]

2704

1

T9

22

T16

76

T18

59

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	171	1			T9	1		T16	1		T19	5
all_values[0]	auto[0]	auto[0]	auto[1]	64	1			T9	2		T19	3		T21	2
all_values[0]	auto[0]	auto[1]	auto[0]	121	1			T9	1		T16	3		T18	7
all_values[0]	auto[0]	auto[1]	auto[1]	81	1			T16	3		T18	3		T19	3
all_values[0]	auto[1]	auto[0]	auto[1]	175	1			T16	1		T18	4		T19	5
all_values[0]	auto[1]	auto[1]	auto[1]	164	1			T9	3		T16	9		T18	4
all_values[1]	auto[0]	auto[0]	auto[0]	183	1			T9	3		T18	7		T19	10
all_values[1]	auto[0]	auto[0]	auto[1]	67	1			T16	3		T18	3		T19	2
all_values[1]	auto[0]	auto[1]	auto[0]	119	1			T9	1		T18	2		T19	3
all_values[1]	auto[0]	auto[1]	auto[1]	80	1			T9	1		T16	3		T19	2
all_values[1]	auto[1]	auto[0]	auto[1]	178	1			T9	1		T16	8		T18	4
all_values[1]	auto[1]	auto[1]	auto[1]	149	1			T9	1		T16	3		T18	2
all_values[2]	auto[0]	auto[0]	auto[0]	151	1			T9	1		T16	3		T19	1
all_values[2]	auto[0]	auto[0]	auto[1]	88	1			T9	1		T16	3		T18	2
all_values[2]	auto[0]	auto[1]	auto[0]	120	1			T16	2		T19	5		T21	3
all_values[2]	auto[0]	auto[1]	auto[1]	84	1			T9	2		T18	1		T19	4
all_values[2]	auto[1]	auto[0]	auto[1]	170	1			T9	2		T16	6		T18	10
all_values[2]	auto[1]	auto[1]	auto[1]	163	1			T9	1		T16	3		T18	5
all_values[3]	auto[0]	auto[0]	auto[0]	173	1			T16	2		T18	4		T19	6
all_values[3]	auto[0]	auto[0]	auto[1]	80	1			T9	1		T16	2		T18	6
all_values[3]	auto[0]	auto[1]	auto[0]	124	1			T9	3		T16	5		T18	2
all_values[3]	auto[0]	auto[1]	auto[1]	73	1			T16	2		T21	1		T22	1
all_values[3]	auto[1]	auto[0]	auto[1]	177	1			T9	3		T16	1		T18	6
all_values[3]	auto[1]	auto[1]	auto[1]	149	1			T16	5		T19	3		T21	4
all_values[4]	auto[0]	auto[0]	auto[0]	153	1			T9	3		T16	1		T18	3
all_values[4]	auto[0]	auto[0]	auto[1]	91	1			T9	1		T16	3		T18	4
all_values[4]	auto[0]	auto[1]	auto[0]	128	1			T9	1		T16	2		T18	4
all_values[4]	auto[0]	auto[1]	auto[1]	79	1			T16	1		T18	1		T21	1
all_values[4]	auto[1]	auto[0]	auto[1]	191	1			T9	2		T16	6		T18	2
all_values[4]	auto[1]	auto[1]	auto[1]	134	1			T16	4		T18	4		T19	5
all_values[5]	auto[0]	auto[0]	auto[0]	219	1			T9	2		T16	4		T18	6
all_values[5]	auto[0]	auto[1]	auto[0]	212	1			T9	3		T16	1		T18	7
all_values[5]	auto[1]	auto[0]	auto[1]	188	1			T9	1		T16	7		T18	3
all_values[5]	auto[1]	auto[1]	auto[1]	157	1			T9	1		T16	5		T18	2
all_values[6]	auto[0]	auto[0]	auto[0]	144	1			T16	2		T18	1		T19	9
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T9	2		T16	3		T18	2
all_values[6]	auto[0]	auto[1]	auto[0]	112	1			T16	1		T18	3		T19	3
all_values[6]	auto[0]	auto[1]	auto[1]	87	1			T18	2		T19	1		T21	1
all_values[6]	auto[1]	auto[0]	auto[1]	172	1			T9	3		T16	5		T18	7
all_values[6]	auto[1]	auto[1]	auto[1]	187	1			T9	2		T16	6		T18	3
all_values[7]	auto[0]	auto[0]	auto[0]	150	1			T9	3		T16	6		T18	10
all_values[7]	auto[0]	auto[0]	auto[1]	78	1			T18	1		T19	1		T21	1
all_values[7]	auto[0]	auto[1]	auto[0]	129	1			T9	2		T16	2		T18	3
all_values[7]	auto[0]	auto[1]	auto[1]	69	1			T16	2		T18	1		T19	4
all_values[7]	auto[1]	auto[0]	auto[1]	195	1			T9	1		T16	2		T18	1
all_values[7]	auto[1]	auto[1]	auto[1]	155	1			T9	1		T16	5		T18	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal