Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47399

1

T6

268

T7

358

T11

52

auto[1]

17020

1

T11

19

T14

3

T32

73

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47267

1

T6

172

T7

239

T11

46

auto[1]

17152

1

T6

96

T7

119

T11

25

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33126	1			T6	125		T7	177		T11	40
others[1]	5434	1			T6	13		T7	30		T11	7
others[2]	5423	1			T6	28		T7	32		T11	5
others[3]	6102	1			T6	35		T7	44		T11	3
interest[1]	3541	1			T6	18		T7	19		T11	2
interest[4]	21674	1			T6	81		T7	120		T11	24
interest[64]	10793	1			T6	49		T7	56		T11	14

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15367	1			T6	85		T7	119		T11	12
auto[0]	auto[0]	others[1]	2609	1			T6	9		T7	23		T11	2
auto[0]	auto[0]	others[2]	2565	1			T6	18		T7	18		T11	3
auto[0]	auto[0]	others[3]	2946	1			T6	21		T7	27		T11	3
auto[0]	auto[0]	interest[1]	1690	1			T6	13		T7	12		T29	4
auto[0]	auto[0]	interest[4]	10083	1			T6	54		T7	83		T11	7
auto[0]	auto[0]	interest[64]	5070	1			T6	26		T7	40		T11	7
auto[0]	auto[1]	others[0]	8961	1			T11	10		T14	2		T32	40
auto[0]	auto[1]	others[1]	1381	1			T11	4		T32	8		T33	21
auto[0]	auto[1]	others[2]	1403	1			T32	2		T33	25		T34	4
auto[0]	auto[1]	others[3]	1585	1			T14	1		T32	9		T33	27
auto[0]	auto[1]	interest[1]	884	1			T11	2		T32	5		T33	15
auto[0]	auto[1]	interest[4]	5899	1			T11	8		T14	1		T32	28
auto[0]	auto[1]	interest[64]	2806	1			T11	3		T32	9		T33	50
auto[1]	auto[0]	others[0]	8798	1			T6	40		T7	58		T11	18
auto[1]	auto[0]	others[1]	1444	1			T6	4		T7	7		T11	1
auto[1]	auto[0]	others[2]	1455	1			T6	10		T7	14		T11	2
auto[1]	auto[0]	others[3]	1571	1			T6	14		T7	17		T29	2
auto[1]	auto[0]	interest[1]	967	1			T6	5		T7	7		T29	5
auto[1]	auto[0]	interest[4]	5692	1			T6	27		T7	37		T11	9
auto[1]	auto[0]	interest[64]	2917	1			T6	23		T7	16		T11	4

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal