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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.44 94.08 98.62 89.36 97.28 95.43 99.21


Total test records in report: 1151
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T1038 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.901296588 Jul 13 05:57:51 PM PDT 24 Jul 13 05:57:53 PM PDT 24 90354024 ps
T106 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3455792434 Jul 13 05:57:50 PM PDT 24 Jul 13 05:57:57 PM PDT 24 213547779 ps
T107 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3453170225 Jul 13 05:58:00 PM PDT 24 Jul 13 05:58:04 PM PDT 24 117424371 ps
T118 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4081420084 Jul 13 05:57:57 PM PDT 24 Jul 13 05:58:00 PM PDT 24 355482431 ps
T100 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1315685612 Jul 13 05:57:52 PM PDT 24 Jul 13 05:58:13 PM PDT 24 328595091 ps
T119 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3620400063 Jul 13 05:57:49 PM PDT 24 Jul 13 05:57:52 PM PDT 24 402325040 ps
T126 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.110247376 Jul 13 05:57:32 PM PDT 24 Jul 13 05:57:59 PM PDT 24 1245262522 ps
T120 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3005469733 Jul 13 05:57:57 PM PDT 24 Jul 13 05:57:59 PM PDT 24 132172043 ps
T1039 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.76313301 Jul 13 05:58:06 PM PDT 24 Jul 13 05:58:07 PM PDT 24 64021236 ps
T1040 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2880396892 Jul 13 05:58:08 PM PDT 24 Jul 13 05:58:10 PM PDT 24 14324015 ps
T101 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.943827316 Jul 13 05:57:46 PM PDT 24 Jul 13 05:58:07 PM PDT 24 836375947 ps
T121 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1702510093 Jul 13 05:57:41 PM PDT 24 Jul 13 05:57:43 PM PDT 24 247405515 ps
T127 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.555716501 Jul 13 05:57:57 PM PDT 24 Jul 13 05:58:00 PM PDT 24 189485122 ps
T1041 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.600926526 Jul 13 05:58:05 PM PDT 24 Jul 13 05:58:06 PM PDT 24 29711144 ps
T1042 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2098010289 Jul 13 05:58:08 PM PDT 24 Jul 13 05:58:10 PM PDT 24 189837040 ps
T1043 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1556506312 Jul 13 05:58:07 PM PDT 24 Jul 13 05:58:09 PM PDT 24 12946670 ps
T154 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4029906240 Jul 13 05:57:44 PM PDT 24 Jul 13 05:57:48 PM PDT 24 216687896 ps
T122 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2329755558 Jul 13 05:57:44 PM PDT 24 Jul 13 05:58:09 PM PDT 24 1074241873 ps
T1044 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3898355093 Jul 13 05:57:50 PM PDT 24 Jul 13 05:57:54 PM PDT 24 41488804 ps
T102 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2092464185 Jul 13 05:57:57 PM PDT 24 Jul 13 05:58:11 PM PDT 24 193216200 ps
T1045 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2423987446 Jul 13 05:57:51 PM PDT 24 Jul 13 05:57:53 PM PDT 24 19038572 ps
T1046 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3188009284 Jul 13 05:58:08 PM PDT 24 Jul 13 05:58:10 PM PDT 24 189011385 ps
T1047 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3252025796 Jul 13 05:57:42 PM PDT 24 Jul 13 05:57:44 PM PDT 24 57415510 ps
T1048 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3123919731 Jul 13 05:57:51 PM PDT 24 Jul 13 05:57:53 PM PDT 24 41522401 ps
T1049 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.842976349 Jul 13 05:57:42 PM PDT 24 Jul 13 05:57:44 PM PDT 24 16464133 ps
T112 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.853082938 Jul 13 05:57:42 PM PDT 24 Jul 13 05:57:47 PM PDT 24 769999427 ps
T123 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.190854809 Jul 13 05:57:35 PM PDT 24 Jul 13 05:57:38 PM PDT 24 57262033 ps
T1050 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2520747150 Jul 13 05:58:08 PM PDT 24 Jul 13 05:58:10 PM PDT 24 41061924 ps
T1051 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3288816988 Jul 13 05:57:42 PM PDT 24 Jul 13 05:57:44 PM PDT 24 105492416 ps
T1052 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1233194779 Jul 13 05:57:51 PM PDT 24 Jul 13 05:57:54 PM PDT 24 30346847 ps
T1053 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2332389415 Jul 13 05:57:50 PM PDT 24 Jul 13 05:57:55 PM PDT 24 51374452 ps
T169 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.226613510 Jul 13 05:57:42 PM PDT 24 Jul 13 05:57:58 PM PDT 24 2229879492 ps
T1054 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.143043718 Jul 13 05:57:52 PM PDT 24 Jul 13 05:57:54 PM PDT 24 25558754 ps
T109 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1114183473 Jul 13 05:57:47 PM PDT 24 Jul 13 05:57:52 PM PDT 24 279120264 ps
T124 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1888797551 Jul 13 05:57:58 PM PDT 24 Jul 13 05:58:01 PM PDT 24 94985019 ps
T1055 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1765687618 Jul 13 05:58:08 PM PDT 24 Jul 13 05:58:11 PM PDT 24 195040958 ps
T1056 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3673383804 Jul 13 05:58:00 PM PDT 24 Jul 13 05:58:02 PM PDT 24 34775012 ps
T156 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1008720742 Jul 13 05:58:00 PM PDT 24 Jul 13 05:58:02 PM PDT 24 139203272 ps
T125 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3738436374 Jul 13 05:57:34 PM PDT 24 Jul 13 05:57:38 PM PDT 24 158512342 ps
T1057 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3855675387 Jul 13 05:57:58 PM PDT 24 Jul 13 05:58:00 PM PDT 24 31078021 ps
T108 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3825337252 Jul 13 05:57:51 PM PDT 24 Jul 13 05:57:56 PM PDT 24 269393015 ps
T1058 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.269356907 Jul 13 05:58:07 PM PDT 24 Jul 13 05:58:09 PM PDT 24 10497318 ps
T155 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1638591050 Jul 13 05:57:33 PM PDT 24 Jul 13 05:57:56 PM PDT 24 5028267681 ps
T128 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3492952507 Jul 13 05:57:41 PM PDT 24 Jul 13 05:57:45 PM PDT 24 501565173 ps
T111 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.823004533 Jul 13 05:58:00 PM PDT 24 Jul 13 05:58:03 PM PDT 24 64996493 ps
T129 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.361373130 Jul 13 05:57:42 PM PDT 24 Jul 13 05:58:26 PM PDT 24 11266969281 ps
T1059 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.473642718 Jul 13 05:58:06 PM PDT 24 Jul 13 05:58:08 PM PDT 24 52241901 ps
T157 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3834563322 Jul 13 05:57:57 PM PDT 24 Jul 13 05:58:06 PM PDT 24 378795508 ps
T1060 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4250332295 Jul 13 05:57:36 PM PDT 24 Jul 13 05:57:38 PM PDT 24 20857285 ps
T83 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1591324110 Jul 13 05:57:44 PM PDT 24 Jul 13 05:57:47 PM PDT 24 94550882 ps
T175 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3868652950 Jul 13 05:57:42 PM PDT 24 Jul 13 05:57:49 PM PDT 24 716102973 ps
T1061 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1884691267 Jul 13 05:57:41 PM PDT 24 Jul 13 05:57:58 PM PDT 24 3091547606 ps
T84 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3732142572 Jul 13 05:57:44 PM PDT 24 Jul 13 05:57:47 PM PDT 24 88184143 ps
T1062 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2667666644 Jul 13 05:58:09 PM PDT 24 Jul 13 05:58:11 PM PDT 24 14093758 ps
T1063 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2886247812 Jul 13 05:57:41 PM PDT 24 Jul 13 05:57:45 PM PDT 24 105047079 ps
T172 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.861926840 Jul 13 05:57:33 PM PDT 24 Jul 13 05:57:50 PM PDT 24 706179892 ps
T1064 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2009580581 Jul 13 05:57:34 PM PDT 24 Jul 13 05:57:37 PM PDT 24 13750385 ps
T1065 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.642336606 Jul 13 05:58:07 PM PDT 24 Jul 13 05:58:09 PM PDT 24 18841033 ps
T1066 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1032721647 Jul 13 05:57:58 PM PDT 24 Jul 13 05:58:04 PM PDT 24 775078200 ps
T1067 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2835801699 Jul 13 05:57:35 PM PDT 24 Jul 13 05:57:38 PM PDT 24 45598930 ps
T1068 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1176913219 Jul 13 05:57:44 PM PDT 24 Jul 13 05:57:47 PM PDT 24 134133652 ps
T1069 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3219886901 Jul 13 05:58:05 PM PDT 24 Jul 13 05:58:06 PM PDT 24 37658259 ps
T1070 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4029964535 Jul 13 05:57:57 PM PDT 24 Jul 13 05:58:00 PM PDT 24 79374480 ps
T1071 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3388028820 Jul 13 05:57:51 PM PDT 24 Jul 13 05:57:53 PM PDT 24 113285424 ps
T110 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.215243396 Jul 13 05:57:55 PM PDT 24 Jul 13 05:57:58 PM PDT 24 135935718 ps
T1072 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1058593558 Jul 13 05:57:58 PM PDT 24 Jul 13 05:58:04 PM PDT 24 549383880 ps
T1073 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3747326629 Jul 13 05:57:49 PM PDT 24 Jul 13 05:57:52 PM PDT 24 71054504 ps
T170 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1760125631 Jul 13 05:57:43 PM PDT 24 Jul 13 05:58:04 PM PDT 24 2462924631 ps
T1074 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.525043939 Jul 13 05:57:50 PM PDT 24 Jul 13 05:57:53 PM PDT 24 292682792 ps
T1075 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.493585245 Jul 13 05:57:52 PM PDT 24 Jul 13 05:57:58 PM PDT 24 721395199 ps
T1076 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.369568578 Jul 13 05:57:58 PM PDT 24 Jul 13 05:58:03 PM PDT 24 129768856 ps
T1077 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3276018946 Jul 13 05:57:42 PM PDT 24 Jul 13 05:57:44 PM PDT 24 18066251 ps
T1078 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2279190498 Jul 13 05:57:41 PM PDT 24 Jul 13 05:57:44 PM PDT 24 31857506 ps
T1079 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1569589811 Jul 13 05:57:41 PM PDT 24 Jul 13 05:57:51 PM PDT 24 1646681505 ps
T171 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.4123112110 Jul 13 05:57:59 PM PDT 24 Jul 13 05:58:12 PM PDT 24 196214374 ps
T1080 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.490306158 Jul 13 05:57:35 PM PDT 24 Jul 13 05:57:40 PM PDT 24 136900906 ps
T1081 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1985528295 Jul 13 05:57:59 PM PDT 24 Jul 13 05:58:02 PM PDT 24 42997611 ps
T1082 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.950265247 Jul 13 05:58:06 PM PDT 24 Jul 13 05:58:08 PM PDT 24 13215109 ps
T1083 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2510168002 Jul 13 05:57:51 PM PDT 24 Jul 13 05:57:55 PM PDT 24 69301419 ps
T1084 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1105084519 Jul 13 05:57:50 PM PDT 24 Jul 13 05:57:55 PM PDT 24 163365933 ps
T1085 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2583243563 Jul 13 05:57:44 PM PDT 24 Jul 13 05:57:49 PM PDT 24 39376707 ps
T1086 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.166769890 Jul 13 05:58:09 PM PDT 24 Jul 13 05:58:10 PM PDT 24 24199716 ps
T1087 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4263964032 Jul 13 05:57:42 PM PDT 24 Jul 13 05:57:44 PM PDT 24 22712121 ps
T1088 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1469075844 Jul 13 05:58:06 PM PDT 24 Jul 13 05:58:08 PM PDT 24 19292301 ps
T1089 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1246818110 Jul 13 05:58:07 PM PDT 24 Jul 13 05:58:09 PM PDT 24 24391930 ps
T173 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1535471371 Jul 13 05:58:01 PM PDT 24 Jul 13 05:58:18 PM PDT 24 3103967643 ps
T1090 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.340963670 Jul 13 05:57:58 PM PDT 24 Jul 13 05:57:59 PM PDT 24 15196939 ps
T1091 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.676824134 Jul 13 05:57:43 PM PDT 24 Jul 13 05:58:05 PM PDT 24 310571974 ps
T1092 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.371723499 Jul 13 05:57:53 PM PDT 24 Jul 13 05:57:55 PM PDT 24 70259124 ps
T1093 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4046187036 Jul 13 05:57:51 PM PDT 24 Jul 13 05:57:54 PM PDT 24 20896915 ps
T1094 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2065788427 Jul 13 05:57:52 PM PDT 24 Jul 13 05:57:55 PM PDT 24 155037158 ps
T1095 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4174818253 Jul 13 05:57:35 PM PDT 24 Jul 13 05:57:38 PM PDT 24 84507023 ps
T1096 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.281045831 Jul 13 05:58:05 PM PDT 24 Jul 13 05:58:06 PM PDT 24 24520256 ps
T1097 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.4037854354 Jul 13 05:58:07 PM PDT 24 Jul 13 05:58:08 PM PDT 24 12848718 ps
T1098 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.158878272 Jul 13 05:57:43 PM PDT 24 Jul 13 05:57:45 PM PDT 24 23407441 ps
T1099 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3508568782 Jul 13 05:58:08 PM PDT 24 Jul 13 05:58:10 PM PDT 24 128413920 ps
T168 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4218222891 Jul 13 05:57:56 PM PDT 24 Jul 13 05:58:00 PM PDT 24 182382808 ps
T174 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.263011284 Jul 13 05:58:01 PM PDT 24 Jul 13 05:58:15 PM PDT 24 862688233 ps
T1100 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.815983986 Jul 13 05:57:52 PM PDT 24 Jul 13 05:58:06 PM PDT 24 2818749680 ps
T1101 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1040201366 Jul 13 05:57:53 PM PDT 24 Jul 13 05:57:54 PM PDT 24 25171954 ps
T1102 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2618113238 Jul 13 05:57:52 PM PDT 24 Jul 13 05:57:55 PM PDT 24 82559669 ps
T1103 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1867138616 Jul 13 05:57:34 PM PDT 24 Jul 13 05:57:58 PM PDT 24 591234873 ps
T1104 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.723356142 Jul 13 05:58:01 PM PDT 24 Jul 13 05:58:05 PM PDT 24 215441286 ps
T1105 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2857464076 Jul 13 05:58:12 PM PDT 24 Jul 13 05:58:13 PM PDT 24 18975675 ps
T1106 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.195106768 Jul 13 05:58:01 PM PDT 24 Jul 13 05:58:06 PM PDT 24 84247649 ps
T1107 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3690326641 Jul 13 05:57:58 PM PDT 24 Jul 13 05:58:02 PM PDT 24 100559748 ps
T1108 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1452051735 Jul 13 05:57:51 PM PDT 24 Jul 13 05:57:58 PM PDT 24 268524269 ps
T1109 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4206220376 Jul 13 05:57:51 PM PDT 24 Jul 13 05:57:55 PM PDT 24 91799528 ps
T176 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.319994411 Jul 13 05:57:57 PM PDT 24 Jul 13 05:58:12 PM PDT 24 540745523 ps
T1110 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2763221255 Jul 13 05:57:43 PM PDT 24 Jul 13 05:57:47 PM PDT 24 88192444 ps
T1111 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2080126077 Jul 13 05:57:43 PM PDT 24 Jul 13 05:57:47 PM PDT 24 151700660 ps
T1112 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2843735490 Jul 13 05:58:07 PM PDT 24 Jul 13 05:58:11 PM PDT 24 194945909 ps
T1113 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2430173231 Jul 13 05:57:41 PM PDT 24 Jul 13 05:57:42 PM PDT 24 98973738 ps
T1114 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1152108417 Jul 13 05:57:50 PM PDT 24 Jul 13 05:57:53 PM PDT 24 56934484 ps
T1115 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.626700754 Jul 13 05:57:59 PM PDT 24 Jul 13 05:58:24 PM PDT 24 3179660911 ps
T1116 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.504724530 Jul 13 05:57:44 PM PDT 24 Jul 13 05:57:49 PM PDT 24 92717319 ps
T1117 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2484459798 Jul 13 05:58:00 PM PDT 24 Jul 13 05:58:02 PM PDT 24 17165382 ps
T1118 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1119097141 Jul 13 05:57:50 PM PDT 24 Jul 13 05:58:09 PM PDT 24 306024885 ps
T1119 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2497353796 Jul 13 05:57:41 PM PDT 24 Jul 13 05:57:46 PM PDT 24 166527700 ps
T1120 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2211651640 Jul 13 05:57:56 PM PDT 24 Jul 13 05:57:58 PM PDT 24 147376962 ps
T1121 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4068516141 Jul 13 05:57:33 PM PDT 24 Jul 13 05:57:38 PM PDT 24 60839148 ps
T1122 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.880158280 Jul 13 05:58:07 PM PDT 24 Jul 13 05:58:10 PM PDT 24 97673388 ps
T1123 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3775573563 Jul 13 05:57:44 PM PDT 24 Jul 13 05:58:00 PM PDT 24 1216187772 ps
T1124 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1604608764 Jul 13 05:57:40 PM PDT 24 Jul 13 05:57:44 PM PDT 24 209268980 ps
T1125 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1048379464 Jul 13 05:58:05 PM PDT 24 Jul 13 05:58:06 PM PDT 24 28471692 ps
T1126 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.990997635 Jul 13 05:58:12 PM PDT 24 Jul 13 05:58:13 PM PDT 24 27284378 ps
T1127 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.662280088 Jul 13 05:57:50 PM PDT 24 Jul 13 05:57:54 PM PDT 24 598936661 ps
T1128 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2006623831 Jul 13 05:57:49 PM PDT 24 Jul 13 05:57:51 PM PDT 24 50495811 ps
T1129 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3562631846 Jul 13 05:57:51 PM PDT 24 Jul 13 05:57:55 PM PDT 24 230544879 ps
T1130 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2676708777 Jul 13 05:57:35 PM PDT 24 Jul 13 05:57:38 PM PDT 24 14667658 ps
T1131 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3144504380 Jul 13 05:57:33 PM PDT 24 Jul 13 05:57:36 PM PDT 24 178098585 ps
T1132 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2799434510 Jul 13 05:57:50 PM PDT 24 Jul 13 05:57:59 PM PDT 24 531508380 ps
T1133 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1717101187 Jul 13 05:57:35 PM PDT 24 Jul 13 05:57:39 PM PDT 24 100602081 ps
T1134 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.941150789 Jul 13 05:57:34 PM PDT 24 Jul 13 05:57:50 PM PDT 24 8698374288 ps
T1135 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3059103639 Jul 13 05:57:44 PM PDT 24 Jul 13 05:57:51 PM PDT 24 121215486 ps
T1136 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4017912533 Jul 13 05:57:51 PM PDT 24 Jul 13 05:57:57 PM PDT 24 621786766 ps
T1137 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.392223433 Jul 13 05:57:58 PM PDT 24 Jul 13 05:58:00 PM PDT 24 12601585 ps
T1138 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2958669862 Jul 13 05:57:42 PM PDT 24 Jul 13 05:57:44 PM PDT 24 9989093 ps
T1139 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.796452975 Jul 13 05:57:51 PM PDT 24 Jul 13 05:57:56 PM PDT 24 153142212 ps
T1140 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.403991546 Jul 13 05:58:07 PM PDT 24 Jul 13 05:58:08 PM PDT 24 25206113 ps
T1141 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1671383802 Jul 13 05:58:01 PM PDT 24 Jul 13 05:58:06 PM PDT 24 194253027 ps
T1142 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1898507993 Jul 13 05:57:36 PM PDT 24 Jul 13 05:57:39 PM PDT 24 60718648 ps
T1143 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3564850644 Jul 13 05:57:44 PM PDT 24 Jul 13 05:57:50 PM PDT 24 152456014 ps
T1144 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3082669242 Jul 13 05:57:47 PM PDT 24 Jul 13 05:57:50 PM PDT 24 88500557 ps
T1145 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1827385523 Jul 13 05:58:07 PM PDT 24 Jul 13 05:58:11 PM PDT 24 37548919 ps
T1146 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1456743022 Jul 13 05:57:44 PM PDT 24 Jul 13 05:58:01 PM PDT 24 1412816749 ps
T1147 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.355958632 Jul 13 05:57:51 PM PDT 24 Jul 13 05:58:00 PM PDT 24 206569397 ps
T1148 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3573836647 Jul 13 05:57:43 PM PDT 24 Jul 13 05:57:47 PM PDT 24 109498131 ps
T1149 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2691967488 Jul 13 05:57:51 PM PDT 24 Jul 13 05:58:07 PM PDT 24 681886975 ps
T1150 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1303903396 Jul 13 05:57:42 PM PDT 24 Jul 13 05:58:07 PM PDT 24 370964698 ps
T1151 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2378146043 Jul 13 05:57:59 PM PDT 24 Jul 13 05:58:04 PM PDT 24 394493067 ps

Test location /workspace/coverage/default/14.spi_device_flash_all.2280189373
Short name T1
Test name
Test status
Simulation time 34738311196 ps
CPU time 124.92 seconds
Started Jul 13 05:29:36 PM PDT 24
Finished Jul 13 05:31:41 PM PDT 24
Peak memory 258480 kb
Host smart-93648175-1e38-4dc5-913d-caaddcc5ec6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280189373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2280189373
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3845871582
Short name T34
Test name
Test status
Simulation time 3333101667 ps
CPU time 90.16 seconds
Started Jul 13 05:32:58 PM PDT 24
Finished Jul 13 05:34:29 PM PDT 24
Peak memory 253916 kb
Host smart-6b8550ba-2b2a-4b94-a890-3174cc8af2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845871582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3845871582
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2810504996
Short name T22
Test name
Test status
Simulation time 47952031390 ps
CPU time 526.61 seconds
Started Jul 13 05:34:37 PM PDT 24
Finished Jul 13 05:43:25 PM PDT 24
Peak memory 283116 kb
Host smart-a9eeca0d-9fb7-4f5c-aec2-c1e1e70d13b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810504996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2810504996
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3538746724
Short name T7
Test name
Test status
Simulation time 7880365842 ps
CPU time 93.79 seconds
Started Jul 13 05:32:37 PM PDT 24
Finished Jul 13 05:34:11 PM PDT 24
Peak memory 256788 kb
Host smart-6bc74d9a-165a-4e88-b00d-6e4581879fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538746724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3538746724
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3526237172
Short name T94
Test name
Test status
Simulation time 112700985 ps
CPU time 2.88 seconds
Started Jul 13 05:57:50 PM PDT 24
Finished Jul 13 05:57:54 PM PDT 24
Peak memory 217828 kb
Host smart-648ac4e9-5c43-4592-b8ed-aa8ee0217a92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526237172 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3526237172
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3912090434
Short name T20
Test name
Test status
Simulation time 59237320516 ps
CPU time 255.64 seconds
Started Jul 13 05:33:41 PM PDT 24
Finished Jul 13 05:37:58 PM PDT 24
Peak memory 274920 kb
Host smart-0f364f95-0d68-4c64-a055-25be569a139a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912090434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3912090434
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3996468572
Short name T63
Test name
Test status
Simulation time 60446286 ps
CPU time 0.76 seconds
Started Jul 13 05:25:11 PM PDT 24
Finished Jul 13 05:25:12 PM PDT 24
Peak memory 217064 kb
Host smart-df0116fa-a0b9-4480-b597-9ec26a67c8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996468572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3996468572
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3399352541
Short name T81
Test name
Test status
Simulation time 75974561870 ps
CPU time 480.33 seconds
Started Jul 13 05:31:19 PM PDT 24
Finished Jul 13 05:39:20 PM PDT 24
Peak memory 273320 kb
Host smart-43803ee0-12c9-443d-a160-642ce70792c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399352541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3399352541
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2422343866
Short name T60
Test name
Test status
Simulation time 231321610014 ps
CPU time 620.81 seconds
Started Jul 13 05:34:55 PM PDT 24
Finished Jul 13 05:45:16 PM PDT 24
Peak memory 274820 kb
Host smart-dcbd6b65-4bd2-4072-a5a4-96d31e1dfd3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422343866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2422343866
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3275544500
Short name T80
Test name
Test status
Simulation time 8906241626 ps
CPU time 130.37 seconds
Started Jul 13 05:29:58 PM PDT 24
Finished Jul 13 05:32:09 PM PDT 24
Peak memory 257288 kb
Host smart-20349d2e-9691-4f47-9798-53c5e7cdebff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275544500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3275544500
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3877919511
Short name T59
Test name
Test status
Simulation time 455695492936 ps
CPU time 1012.18 seconds
Started Jul 13 05:30:11 PM PDT 24
Finished Jul 13 05:47:04 PM PDT 24
Peak memory 290376 kb
Host smart-e4a85367-2d16-4706-b5ab-39a1157566c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877919511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3877919511
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.943827316
Short name T101
Test name
Test status
Simulation time 836375947 ps
CPU time 20.6 seconds
Started Jul 13 05:57:46 PM PDT 24
Finished Jul 13 05:58:07 PM PDT 24
Peak memory 215476 kb
Host smart-54a1bf5d-3917-4615-ae4f-23797b9d90ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943827316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.943827316
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2909269293
Short name T48
Test name
Test status
Simulation time 6258455738 ps
CPU time 112.31 seconds
Started Jul 13 05:31:06 PM PDT 24
Finished Jul 13 05:32:58 PM PDT 24
Peak memory 239644 kb
Host smart-ceab3add-7a50-4dff-8623-cd5e229455f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909269293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2909269293
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.4237674137
Short name T47
Test name
Test status
Simulation time 21999497051 ps
CPU time 234.49 seconds
Started Jul 13 05:32:48 PM PDT 24
Finished Jul 13 05:36:43 PM PDT 24
Peak memory 274656 kb
Host smart-2fcdee90-39a9-49b8-9f1f-0a5b8cbe53ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237674137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.4237674137
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.26136491
Short name T298
Test name
Test status
Simulation time 24080571 ps
CPU time 0.72 seconds
Started Jul 13 05:29:57 PM PDT 24
Finished Jul 13 05:29:59 PM PDT 24
Peak memory 205724 kb
Host smart-ddb754b4-c883-406c-9f26-9cf8b3a21507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26136491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.26136491
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3455792434
Short name T106
Test name
Test status
Simulation time 213547779 ps
CPU time 5.22 seconds
Started Jul 13 05:57:50 PM PDT 24
Finished Jul 13 05:57:57 PM PDT 24
Peak memory 215768 kb
Host smart-8d16770c-1fc8-4ca9-901e-d16c697fe73e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455792434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3455792434
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3926305263
Short name T165
Test name
Test status
Simulation time 20043956443 ps
CPU time 229.79 seconds
Started Jul 13 05:33:38 PM PDT 24
Finished Jul 13 05:37:30 PM PDT 24
Peak memory 253632 kb
Host smart-2d5db9cd-3d50-499a-9bba-4ca347e0d0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926305263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3926305263
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2051826124
Short name T227
Test name
Test status
Simulation time 8932290221 ps
CPU time 122.17 seconds
Started Jul 13 05:32:56 PM PDT 24
Finished Jul 13 05:34:59 PM PDT 24
Peak memory 262816 kb
Host smart-99d17bde-0382-431d-b41a-378ed6a2e21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051826124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2051826124
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.59093041
Short name T82
Test name
Test status
Simulation time 43110747 ps
CPU time 0.96 seconds
Started Jul 13 05:57:42 PM PDT 24
Finished Jul 13 05:57:45 PM PDT 24
Peak memory 207036 kb
Host smart-bb375d6b-d167-4570-b2f2-b7f5cfae5d9e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59093041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
hw_reset.59093041
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2114191778
Short name T244
Test name
Test status
Simulation time 87390515509 ps
CPU time 676.1 seconds
Started Jul 13 05:29:57 PM PDT 24
Finished Jul 13 05:41:13 PM PDT 24
Peak memory 262660 kb
Host smart-0a205434-025e-4abf-a671-1828e1c5088b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114191778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2114191778
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3293013343
Short name T360
Test name
Test status
Simulation time 212146370 ps
CPU time 1.05 seconds
Started Jul 13 05:28:53 PM PDT 24
Finished Jul 13 05:28:54 PM PDT 24
Peak memory 218992 kb
Host smart-928747ad-f565-4398-a701-3e787a161e49
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293013343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3293013343
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1439754981
Short name T137
Test name
Test status
Simulation time 51238418142 ps
CPU time 524.66 seconds
Started Jul 13 05:28:54 PM PDT 24
Finished Jul 13 05:37:39 PM PDT 24
Peak memory 264408 kb
Host smart-25fadd51-b8d2-4b77-afb0-954b15ec8ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439754981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1439754981
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3626205320
Short name T36
Test name
Test status
Simulation time 371964735497 ps
CPU time 689.86 seconds
Started Jul 13 05:35:15 PM PDT 24
Finished Jul 13 05:46:45 PM PDT 24
Peak memory 282704 kb
Host smart-c64f926b-df40-40e7-8cb0-2f4f765a3ed2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626205320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3626205320
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.886222014
Short name T65
Test name
Test status
Simulation time 698619547 ps
CPU time 1.15 seconds
Started Jul 13 05:25:45 PM PDT 24
Finished Jul 13 05:25:46 PM PDT 24
Peak memory 236304 kb
Host smart-4abf667e-220a-410a-8e18-60eae253b6a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886222014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.886222014
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.832290016
Short name T211
Test name
Test status
Simulation time 284717924378 ps
CPU time 624.63 seconds
Started Jul 13 05:35:40 PM PDT 24
Finished Jul 13 05:46:05 PM PDT 24
Peak memory 259292 kb
Host smart-ae8983db-90e5-4e22-b614-e46743de7bfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832290016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.832290016
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2809160852
Short name T161
Test name
Test status
Simulation time 83613542586 ps
CPU time 766.93 seconds
Started Jul 13 05:32:26 PM PDT 24
Finished Jul 13 05:45:14 PM PDT 24
Peak memory 258500 kb
Host smart-7d466329-9ee6-415c-b188-285174cc343e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809160852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2809160852
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2550536627
Short name T308
Test name
Test status
Simulation time 5243338319 ps
CPU time 14.62 seconds
Started Jul 13 05:29:24 PM PDT 24
Finished Jul 13 05:29:39 PM PDT 24
Peak memory 217384 kb
Host smart-aadf8df5-8185-4c47-93c5-99e5e551a58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550536627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2550536627
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3635483162
Short name T15
Test name
Test status
Simulation time 339101465518 ps
CPU time 235.25 seconds
Started Jul 13 05:28:44 PM PDT 24
Finished Jul 13 05:32:40 PM PDT 24
Peak memory 269836 kb
Host smart-fc2e1a1d-8b80-4936-a7b2-12087f56089d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635483162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3635483162
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2663086419
Short name T1009
Test name
Test status
Simulation time 16026737513 ps
CPU time 101.14 seconds
Started Jul 13 05:33:05 PM PDT 24
Finished Jul 13 05:34:47 PM PDT 24
Peak memory 272100 kb
Host smart-f089f254-a39a-47aa-9a68-6338af138bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663086419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2663086419
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3157431803
Short name T134
Test name
Test status
Simulation time 48502247475 ps
CPU time 344.91 seconds
Started Jul 13 05:34:24 PM PDT 24
Finished Jul 13 05:40:10 PM PDT 24
Peak memory 256528 kb
Host smart-b6d535c8-1488-4565-bf29-e7dbec6a4cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157431803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3157431803
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.263011284
Short name T174
Test name
Test status
Simulation time 862688233 ps
CPU time 13.07 seconds
Started Jul 13 05:58:01 PM PDT 24
Finished Jul 13 05:58:15 PM PDT 24
Peak memory 215712 kb
Host smart-1bc8eda7-fa5a-4890-8900-98e185fe8431
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263011284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.263011284
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2691967488
Short name T1149
Test name
Test status
Simulation time 681886975 ps
CPU time 14.51 seconds
Started Jul 13 05:57:51 PM PDT 24
Finished Jul 13 05:58:07 PM PDT 24
Peak memory 216024 kb
Host smart-90e68e6d-dc29-4b63-bd38-1da99f6ff29c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691967488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2691967488
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1411997952
Short name T135
Test name
Test status
Simulation time 1960982644 ps
CPU time 27.05 seconds
Started Jul 13 05:29:45 PM PDT 24
Finished Jul 13 05:30:13 PM PDT 24
Peak memory 217308 kb
Host smart-e84c3a8d-2f2c-41f0-9410-f43cabefc792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411997952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1411997952
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1420304657
Short name T61
Test name
Test status
Simulation time 14781792625 ps
CPU time 251.21 seconds
Started Jul 13 05:30:22 PM PDT 24
Finished Jul 13 05:34:34 PM PDT 24
Peak memory 267064 kb
Host smart-91693a5d-20e9-4f2f-9df8-11820215b8a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420304657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1420304657
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3499184239
Short name T276
Test name
Test status
Simulation time 7854960426 ps
CPU time 43.48 seconds
Started Jul 13 05:31:30 PM PDT 24
Finished Jul 13 05:32:15 PM PDT 24
Peak memory 252040 kb
Host smart-ff50bf54-1499-45ea-89d1-f80e2adfa85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499184239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3499184239
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2610901363
Short name T158
Test name
Test status
Simulation time 16047858508 ps
CPU time 150.44 seconds
Started Jul 13 05:28:01 PM PDT 24
Finished Jul 13 05:30:32 PM PDT 24
Peak memory 258484 kb
Host smart-86beec84-b7e9-4d17-8a48-cf8b5f9b1f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610901363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2610901363
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1999187080
Short name T421
Test name
Test status
Simulation time 1605847105 ps
CPU time 22.06 seconds
Started Jul 13 05:28:57 PM PDT 24
Finished Jul 13 05:29:19 PM PDT 24
Peak memory 237628 kb
Host smart-c0745b48-99f1-4d7d-abe4-06d89e7a3fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999187080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1999187080
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1032721647
Short name T1066
Test name
Test status
Simulation time 775078200 ps
CPU time 4.42 seconds
Started Jul 13 05:57:58 PM PDT 24
Finished Jul 13 05:58:04 PM PDT 24
Peak memory 215772 kb
Host smart-18ba9db2-c85e-4147-9666-5988c49cece6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032721647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1032721647
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.4123112110
Short name T171
Test name
Test status
Simulation time 196214374 ps
CPU time 11.86 seconds
Started Jul 13 05:57:59 PM PDT 24
Finished Jul 13 05:58:12 PM PDT 24
Peak memory 215536 kb
Host smart-11097b35-d19b-41ea-8599-2ac75b0e9595
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123112110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.4123112110
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2965439008
Short name T268
Test name
Test status
Simulation time 40607214470 ps
CPU time 437.57 seconds
Started Jul 13 05:25:45 PM PDT 24
Finished Jul 13 05:33:03 PM PDT 24
Peak memory 270716 kb
Host smart-5c697e34-35ee-42bf-a78d-5e4f2d3330e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965439008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2965439008
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3820707048
Short name T270
Test name
Test status
Simulation time 7972823650 ps
CPU time 33.21 seconds
Started Jul 13 05:25:32 PM PDT 24
Finished Jul 13 05:26:05 PM PDT 24
Peak memory 250056 kb
Host smart-c3237e13-371f-4510-8692-66b6c3d7ccf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820707048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3820707048
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2714597928
Short name T272
Test name
Test status
Simulation time 7097764356 ps
CPU time 47.73 seconds
Started Jul 13 05:31:39 PM PDT 24
Finished Jul 13 05:32:27 PM PDT 24
Peak memory 241788 kb
Host smart-ce0ace3a-8904-408d-98c7-4c281cc11574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714597928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2714597928
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2337211525
Short name T262
Test name
Test status
Simulation time 13781799108 ps
CPU time 113.83 seconds
Started Jul 13 05:26:42 PM PDT 24
Finished Jul 13 05:28:36 PM PDT 24
Peak memory 269244 kb
Host smart-aaa5841d-bd57-48a1-8f2e-461135b2901a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337211525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2337211525
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3894485092
Short name T201
Test name
Test status
Simulation time 1214640884 ps
CPU time 10.15 seconds
Started Jul 13 05:29:08 PM PDT 24
Finished Jul 13 05:29:18 PM PDT 24
Peak memory 233796 kb
Host smart-c22e6041-137f-4a66-bd42-2fab2b0d803f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894485092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3894485092
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3732142572
Short name T84
Test name
Test status
Simulation time 88184143 ps
CPU time 1.43 seconds
Started Jul 13 05:57:44 PM PDT 24
Finished Jul 13 05:57:47 PM PDT 24
Peak memory 207252 kb
Host smart-766851cb-d289-4362-87ed-4fc06c54ddc1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732142572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3732142572
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3390555348
Short name T43
Test name
Test status
Simulation time 45527910724 ps
CPU time 105.17 seconds
Started Jul 13 05:26:23 PM PDT 24
Finished Jul 13 05:28:08 PM PDT 24
Peak memory 256960 kb
Host smart-f5d06dd8-dc76-4692-aa0d-00ebcb57e5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390555348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3390555348
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1867138616
Short name T1103
Test name
Test status
Simulation time 591234873 ps
CPU time 22.11 seconds
Started Jul 13 05:57:34 PM PDT 24
Finished Jul 13 05:57:58 PM PDT 24
Peak memory 215388 kb
Host smart-a53d47f1-0403-4e75-b6cc-ebbc02806bc3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867138616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1867138616
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.941150789
Short name T1134
Test name
Test status
Simulation time 8698374288 ps
CPU time 14.07 seconds
Started Jul 13 05:57:34 PM PDT 24
Finished Jul 13 05:57:50 PM PDT 24
Peak memory 207356 kb
Host smart-4c943235-38b1-46b8-8e7a-8a114a96586f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941150789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.941150789
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4174818253
Short name T1095
Test name
Test status
Simulation time 84507023 ps
CPU time 1.41 seconds
Started Jul 13 05:57:35 PM PDT 24
Finished Jul 13 05:57:38 PM PDT 24
Peak memory 207276 kb
Host smart-cf4cdf32-ccb0-4c89-809c-c475002d962d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174818253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.4174818253
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1717101187
Short name T1133
Test name
Test status
Simulation time 100602081 ps
CPU time 2.57 seconds
Started Jul 13 05:57:35 PM PDT 24
Finished Jul 13 05:57:39 PM PDT 24
Peak memory 216992 kb
Host smart-326ab039-b886-41f5-8a55-1b09895a55a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717101187 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1717101187
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.490306158
Short name T1080
Test name
Test status
Simulation time 136900906 ps
CPU time 2.81 seconds
Started Jul 13 05:57:35 PM PDT 24
Finished Jul 13 05:57:40 PM PDT 24
Peak memory 215428 kb
Host smart-550b4be2-579e-40c9-ae8b-d4d415f321b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490306158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.490306158
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2676708777
Short name T1130
Test name
Test status
Simulation time 14667658 ps
CPU time 0.77 seconds
Started Jul 13 05:57:35 PM PDT 24
Finished Jul 13 05:57:38 PM PDT 24
Peak memory 204304 kb
Host smart-c6f7edd9-1bb1-481a-b351-7bbed538471a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676708777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
676708777
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3144504380
Short name T1131
Test name
Test status
Simulation time 178098585 ps
CPU time 1.33 seconds
Started Jul 13 05:57:33 PM PDT 24
Finished Jul 13 05:57:36 PM PDT 24
Peak memory 215496 kb
Host smart-6fe2d72e-cca8-4185-96a0-72721e88d286
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144504380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3144504380
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2835801699
Short name T1067
Test name
Test status
Simulation time 45598930 ps
CPU time 0.67 seconds
Started Jul 13 05:57:35 PM PDT 24
Finished Jul 13 05:57:38 PM PDT 24
Peak memory 203884 kb
Host smart-cbef756d-a986-4448-97df-a9dbd3931e64
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835801699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2835801699
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.458513063
Short name T1029
Test name
Test status
Simulation time 112428635 ps
CPU time 3.11 seconds
Started Jul 13 05:57:38 PM PDT 24
Finished Jul 13 05:57:42 PM PDT 24
Peak memory 215660 kb
Host smart-57f30846-2a94-4134-8165-2509aa65efbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458513063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.458513063
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.38831384
Short name T99
Test name
Test status
Simulation time 31829611 ps
CPU time 2.32 seconds
Started Jul 13 05:57:36 PM PDT 24
Finished Jul 13 05:57:40 PM PDT 24
Peak memory 215732 kb
Host smart-72603d3d-28cf-474d-8f46-28433c8cfe2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38831384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.38831384
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1638591050
Short name T155
Test name
Test status
Simulation time 5028267681 ps
CPU time 21.83 seconds
Started Jul 13 05:57:33 PM PDT 24
Finished Jul 13 05:57:56 PM PDT 24
Peak memory 215664 kb
Host smart-2bdfcf8a-94c0-4bf3-b849-c3821380fb40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638591050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1638591050
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.676824134
Short name T1091
Test name
Test status
Simulation time 310571974 ps
CPU time 20.19 seconds
Started Jul 13 05:57:43 PM PDT 24
Finished Jul 13 05:58:05 PM PDT 24
Peak memory 215540 kb
Host smart-ae60836a-63c8-482b-8c7a-6e558110250b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676824134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.676824134
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.110247376
Short name T126
Test name
Test status
Simulation time 1245262522 ps
CPU time 25.97 seconds
Started Jul 13 05:57:32 PM PDT 24
Finished Jul 13 05:57:59 PM PDT 24
Peak memory 207268 kb
Host smart-28287f71-9587-4f1d-8398-5f638d63ee36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110247376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.110247376
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1898507993
Short name T1142
Test name
Test status
Simulation time 60718648 ps
CPU time 1.26 seconds
Started Jul 13 05:57:36 PM PDT 24
Finished Jul 13 05:57:39 PM PDT 24
Peak memory 216532 kb
Host smart-96a624d1-aa0c-4291-925b-c0623c170370
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898507993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1898507993
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1604608764
Short name T1124
Test name
Test status
Simulation time 209268980 ps
CPU time 3.85 seconds
Started Jul 13 05:57:40 PM PDT 24
Finished Jul 13 05:57:44 PM PDT 24
Peak memory 217296 kb
Host smart-8aee3865-f615-4708-93e9-b916280a56cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604608764 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1604608764
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.190854809
Short name T123
Test name
Test status
Simulation time 57262033 ps
CPU time 1.25 seconds
Started Jul 13 05:57:35 PM PDT 24
Finished Jul 13 05:57:38 PM PDT 24
Peak memory 207344 kb
Host smart-0bf4fdd3-6a09-46a1-b826-87833f4bd860
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190854809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.190854809
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2009580581
Short name T1064
Test name
Test status
Simulation time 13750385 ps
CPU time 0.72 seconds
Started Jul 13 05:57:34 PM PDT 24
Finished Jul 13 05:57:37 PM PDT 24
Peak memory 203900 kb
Host smart-0069d085-088b-4c94-b07b-4edf43512750
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009580581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
009580581
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3738436374
Short name T125
Test name
Test status
Simulation time 158512342 ps
CPU time 2.03 seconds
Started Jul 13 05:57:34 PM PDT 24
Finished Jul 13 05:57:38 PM PDT 24
Peak memory 215448 kb
Host smart-54d228fc-1eb1-4702-ab01-c26414f85287
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738436374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3738436374
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4250332295
Short name T1060
Test name
Test status
Simulation time 20857285 ps
CPU time 0.73 seconds
Started Jul 13 05:57:36 PM PDT 24
Finished Jul 13 05:57:38 PM PDT 24
Peak memory 203844 kb
Host smart-2c4cf0c9-ed61-4082-aab2-b83a0be09b20
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250332295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4250332295
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3573836647
Short name T1148
Test name
Test status
Simulation time 109498131 ps
CPU time 2.84 seconds
Started Jul 13 05:57:43 PM PDT 24
Finished Jul 13 05:57:47 PM PDT 24
Peak memory 215464 kb
Host smart-70c9d0d1-35a9-41d7-a9d8-7f4a7daec36e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573836647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3573836647
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4068516141
Short name T1121
Test name
Test status
Simulation time 60839148 ps
CPU time 3.71 seconds
Started Jul 13 05:57:33 PM PDT 24
Finished Jul 13 05:57:38 PM PDT 24
Peak memory 215680 kb
Host smart-a89a1a99-d308-435b-8455-ed8b7231533d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068516141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
068516141
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.861926840
Short name T172
Test name
Test status
Simulation time 706179892 ps
CPU time 15.42 seconds
Started Jul 13 05:57:33 PM PDT 24
Finished Jul 13 05:57:50 PM PDT 24
Peak memory 215628 kb
Host smart-e9b05c3b-b84f-438c-bee1-a866c3a3b2e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861926840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.861926840
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3562631846
Short name T1129
Test name
Test status
Simulation time 230544879 ps
CPU time 2.71 seconds
Started Jul 13 05:57:51 PM PDT 24
Finished Jul 13 05:57:55 PM PDT 24
Peak memory 217772 kb
Host smart-139702b3-a18a-4982-b7b0-d5c78ac6b1c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562631846 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3562631846
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3747326629
Short name T1073
Test name
Test status
Simulation time 71054504 ps
CPU time 2.34 seconds
Started Jul 13 05:57:49 PM PDT 24
Finished Jul 13 05:57:52 PM PDT 24
Peak memory 215448 kb
Host smart-ee687735-daf9-4eac-b7b2-8fb84c68fe52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747326629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3747326629
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.143043718
Short name T1054
Test name
Test status
Simulation time 25558754 ps
CPU time 0.71 seconds
Started Jul 13 05:57:52 PM PDT 24
Finished Jul 13 05:57:54 PM PDT 24
Peak memory 203924 kb
Host smart-2146d1ee-9365-48b4-a33c-4bfd354e4eff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143043718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.143043718
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2211651640
Short name T1120
Test name
Test status
Simulation time 147376962 ps
CPU time 1.68 seconds
Started Jul 13 05:57:56 PM PDT 24
Finished Jul 13 05:57:58 PM PDT 24
Peak memory 215340 kb
Host smart-ace3492f-2ebb-4409-9605-6f65275038bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211651640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2211651640
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4218222891
Short name T168
Test name
Test status
Simulation time 182382808 ps
CPU time 2.74 seconds
Started Jul 13 05:57:56 PM PDT 24
Finished Jul 13 05:58:00 PM PDT 24
Peak memory 215628 kb
Host smart-4ca3bbc4-a4e2-4484-bd6e-07525129da7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218222891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4218222891
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3834563322
Short name T157
Test name
Test status
Simulation time 378795508 ps
CPU time 8.64 seconds
Started Jul 13 05:57:57 PM PDT 24
Finished Jul 13 05:58:06 PM PDT 24
Peak memory 215564 kb
Host smart-256c637e-cf29-41da-8a0b-0d783432891e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834563322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3834563322
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2332389415
Short name T1053
Test name
Test status
Simulation time 51374452 ps
CPU time 3.55 seconds
Started Jul 13 05:57:50 PM PDT 24
Finished Jul 13 05:57:55 PM PDT 24
Peak memory 217948 kb
Host smart-3ff8c461-77c8-48a6-a674-b12ae3719a93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332389415 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2332389415
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.371723499
Short name T1092
Test name
Test status
Simulation time 70259124 ps
CPU time 1.3 seconds
Started Jul 13 05:57:53 PM PDT 24
Finished Jul 13 05:57:55 PM PDT 24
Peak memory 215456 kb
Host smart-45b75f9a-3c76-4702-9fac-59c0c575e023
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371723499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.371723499
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3388028820
Short name T1071
Test name
Test status
Simulation time 113285424 ps
CPU time 0.78 seconds
Started Jul 13 05:57:51 PM PDT 24
Finished Jul 13 05:57:53 PM PDT 24
Peak memory 204028 kb
Host smart-a6d69165-b6b5-484d-80d3-1ff98907ef89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388028820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3388028820
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2510168002
Short name T1083
Test name
Test status
Simulation time 69301419 ps
CPU time 2.1 seconds
Started Jul 13 05:57:51 PM PDT 24
Finished Jul 13 05:57:55 PM PDT 24
Peak memory 207248 kb
Host smart-20302d74-d4f9-4cbe-986e-42a3ef73f816
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510168002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2510168002
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1452051735
Short name T1108
Test name
Test status
Simulation time 268524269 ps
CPU time 5.15 seconds
Started Jul 13 05:57:51 PM PDT 24
Finished Jul 13 05:57:58 PM PDT 24
Peak memory 215820 kb
Host smart-5fae6a4f-7ce8-4397-b6b3-b172639dd481
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452051735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1452051735
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1119097141
Short name T1118
Test name
Test status
Simulation time 306024885 ps
CPU time 18.23 seconds
Started Jul 13 05:57:50 PM PDT 24
Finished Jul 13 05:58:09 PM PDT 24
Peak memory 215612 kb
Host smart-ba710163-83a9-4f07-a5fc-7070d22a0cd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119097141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1119097141
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1105084519
Short name T1084
Test name
Test status
Simulation time 163365933 ps
CPU time 3.95 seconds
Started Jul 13 05:57:50 PM PDT 24
Finished Jul 13 05:57:55 PM PDT 24
Peak memory 217392 kb
Host smart-7361e8a4-dd4e-43e5-945a-14e3b87209a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105084519 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1105084519
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4081420084
Short name T118
Test name
Test status
Simulation time 355482431 ps
CPU time 2.77 seconds
Started Jul 13 05:57:57 PM PDT 24
Finished Jul 13 05:58:00 PM PDT 24
Peak memory 215412 kb
Host smart-c97f73b3-cbef-44b2-97f2-867b798ece33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081420084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4081420084
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3123919731
Short name T1048
Test name
Test status
Simulation time 41522401 ps
CPU time 0.76 seconds
Started Jul 13 05:57:51 PM PDT 24
Finished Jul 13 05:57:53 PM PDT 24
Peak memory 204276 kb
Host smart-8c9d4318-838e-4b67-a6ac-4a7fd29b2c47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123919731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3123919731
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1233194779
Short name T1052
Test name
Test status
Simulation time 30346847 ps
CPU time 1.83 seconds
Started Jul 13 05:57:51 PM PDT 24
Finished Jul 13 05:57:54 PM PDT 24
Peak memory 215484 kb
Host smart-03fefa93-69a4-4c27-9faa-24ad9e91a557
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233194779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1233194779
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1315685612
Short name T100
Test name
Test status
Simulation time 328595091 ps
CPU time 19.51 seconds
Started Jul 13 05:57:52 PM PDT 24
Finished Jul 13 05:58:13 PM PDT 24
Peak memory 215516 kb
Host smart-b0c408e3-397c-4c81-9b64-6f07b1180201
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315685612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1315685612
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3835482831
Short name T114
Test name
Test status
Simulation time 110137349 ps
CPU time 3.86 seconds
Started Jul 13 05:57:58 PM PDT 24
Finished Jul 13 05:58:03 PM PDT 24
Peak memory 218264 kb
Host smart-f09694ee-2dc8-4051-adc6-49cc09cd2943
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835482831 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3835482831
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.662280088
Short name T1127
Test name
Test status
Simulation time 598936661 ps
CPU time 2.88 seconds
Started Jul 13 05:57:50 PM PDT 24
Finished Jul 13 05:57:54 PM PDT 24
Peak memory 215552 kb
Host smart-1d12c517-48cd-41b3-870c-c3d0ff354d43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662280088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.662280088
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.901296588
Short name T1038
Test name
Test status
Simulation time 90354024 ps
CPU time 0.85 seconds
Started Jul 13 05:57:51 PM PDT 24
Finished Jul 13 05:57:53 PM PDT 24
Peak memory 204016 kb
Host smart-002a9570-2d90-471f-88e8-1409cb00efe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901296588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.901296588
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3898355093
Short name T1044
Test name
Test status
Simulation time 41488804 ps
CPU time 2.68 seconds
Started Jul 13 05:57:50 PM PDT 24
Finished Jul 13 05:57:54 PM PDT 24
Peak memory 207320 kb
Host smart-e76dce41-ffa4-4451-8c1c-cf2aa3f0ba54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898355093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3898355093
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.215243396
Short name T110
Test name
Test status
Simulation time 135935718 ps
CPU time 2.1 seconds
Started Jul 13 05:57:55 PM PDT 24
Finished Jul 13 05:57:58 PM PDT 24
Peak memory 215720 kb
Host smart-d9d178fd-2f2f-48ec-b2df-c2184f520a12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215243396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.215243396
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.894964670
Short name T113
Test name
Test status
Simulation time 744817757 ps
CPU time 3.65 seconds
Started Jul 13 05:57:59 PM PDT 24
Finished Jul 13 05:58:04 PM PDT 24
Peak memory 217420 kb
Host smart-c4bdcd4e-e8b0-4078-b8a2-5c2ea9ed2f64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894964670 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.894964670
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1008720742
Short name T156
Test name
Test status
Simulation time 139203272 ps
CPU time 1.25 seconds
Started Jul 13 05:58:00 PM PDT 24
Finished Jul 13 05:58:02 PM PDT 24
Peak memory 215412 kb
Host smart-a0cad5b7-6ebb-484d-95b5-127f6c84293d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008720742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1008720742
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3855675387
Short name T1057
Test name
Test status
Simulation time 31078021 ps
CPU time 0.76 seconds
Started Jul 13 05:57:58 PM PDT 24
Finished Jul 13 05:58:00 PM PDT 24
Peak memory 203960 kb
Host smart-0785610e-403a-4cc3-a7d1-94472277c78d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855675387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3855675387
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1671383802
Short name T1141
Test name
Test status
Simulation time 194253027 ps
CPU time 4.52 seconds
Started Jul 13 05:58:01 PM PDT 24
Finished Jul 13 05:58:06 PM PDT 24
Peak memory 215468 kb
Host smart-4e3aa840-1df7-4acb-89da-3b2c0d49478b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671383802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1671383802
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.319994411
Short name T176
Test name
Test status
Simulation time 540745523 ps
CPU time 15.06 seconds
Started Jul 13 05:57:57 PM PDT 24
Finished Jul 13 05:58:12 PM PDT 24
Peak memory 215552 kb
Host smart-e6dbde73-3d9e-435b-8e7e-1084467a6d89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319994411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.319994411
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.723356142
Short name T1104
Test name
Test status
Simulation time 215441286 ps
CPU time 2.87 seconds
Started Jul 13 05:58:01 PM PDT 24
Finished Jul 13 05:58:05 PM PDT 24
Peak memory 217172 kb
Host smart-67a940e5-9729-44a3-a89e-06c46d6f8134
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723356142 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.723356142
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3690326641
Short name T1107
Test name
Test status
Simulation time 100559748 ps
CPU time 2.49 seconds
Started Jul 13 05:57:58 PM PDT 24
Finished Jul 13 05:58:02 PM PDT 24
Peak memory 215528 kb
Host smart-bdb394de-994d-4da7-a0f0-7ec37f3a2ceb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690326641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3690326641
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.392223433
Short name T1137
Test name
Test status
Simulation time 12601585 ps
CPU time 0.7 seconds
Started Jul 13 05:57:58 PM PDT 24
Finished Jul 13 05:58:00 PM PDT 24
Peak memory 203840 kb
Host smart-a56e78e4-2f10-4a56-aa0b-71cae3507d4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392223433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.392223433
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2061901736
Short name T1033
Test name
Test status
Simulation time 43001383 ps
CPU time 3.07 seconds
Started Jul 13 05:58:00 PM PDT 24
Finished Jul 13 05:58:04 PM PDT 24
Peak memory 215488 kb
Host smart-0e86c57b-6186-4895-92f7-1caaf2a4c167
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061901736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2061901736
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.195106768
Short name T1106
Test name
Test status
Simulation time 84247649 ps
CPU time 4.43 seconds
Started Jul 13 05:58:01 PM PDT 24
Finished Jul 13 05:58:06 PM PDT 24
Peak memory 215692 kb
Host smart-0846a70f-d8d6-42f7-aaa8-0e2ae124fe4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195106768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.195106768
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.134572416
Short name T116
Test name
Test status
Simulation time 192371361 ps
CPU time 1.94 seconds
Started Jul 13 05:57:59 PM PDT 24
Finished Jul 13 05:58:03 PM PDT 24
Peak memory 216780 kb
Host smart-66b961a4-1cd4-4e27-b05a-0907660018f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134572416 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.134572416
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1985528295
Short name T1081
Test name
Test status
Simulation time 42997611 ps
CPU time 1.46 seconds
Started Jul 13 05:57:59 PM PDT 24
Finished Jul 13 05:58:02 PM PDT 24
Peak memory 207352 kb
Host smart-fcd338bc-c627-48df-aaab-cc9bfd3b78a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985528295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1985528295
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3673383804
Short name T1056
Test name
Test status
Simulation time 34775012 ps
CPU time 0.71 seconds
Started Jul 13 05:58:00 PM PDT 24
Finished Jul 13 05:58:02 PM PDT 24
Peak memory 204244 kb
Host smart-1776df89-d722-4be6-9da6-2dca969713d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673383804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3673383804
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4029964535
Short name T1070
Test name
Test status
Simulation time 79374480 ps
CPU time 1.93 seconds
Started Jul 13 05:57:57 PM PDT 24
Finished Jul 13 05:58:00 PM PDT 24
Peak memory 215396 kb
Host smart-7bab21a6-27a9-48cb-91ec-50a9235c740a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029964535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4029964535
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1058593558
Short name T1072
Test name
Test status
Simulation time 549383880 ps
CPU time 3.74 seconds
Started Jul 13 05:57:58 PM PDT 24
Finished Jul 13 05:58:04 PM PDT 24
Peak memory 215888 kb
Host smart-1b745178-4eec-4598-b04a-64383a594fac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058593558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1058593558
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1535471371
Short name T173
Test name
Test status
Simulation time 3103967643 ps
CPU time 15.94 seconds
Started Jul 13 05:58:01 PM PDT 24
Finished Jul 13 05:58:18 PM PDT 24
Peak memory 215868 kb
Host smart-9e0f3cb8-3a19-4685-a55e-7f498d4c5e4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535471371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1535471371
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.369568578
Short name T1076
Test name
Test status
Simulation time 129768856 ps
CPU time 3.85 seconds
Started Jul 13 05:57:58 PM PDT 24
Finished Jul 13 05:58:03 PM PDT 24
Peak memory 217340 kb
Host smart-8d5c8f22-e782-45ea-8f7e-458155a122e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369568578 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.369568578
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3005469733
Short name T120
Test name
Test status
Simulation time 132172043 ps
CPU time 2.52 seconds
Started Jul 13 05:57:57 PM PDT 24
Finished Jul 13 05:57:59 PM PDT 24
Peak memory 207368 kb
Host smart-e2824760-d875-4302-bac8-d9d00ed1a1b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005469733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3005469733
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2484459798
Short name T1117
Test name
Test status
Simulation time 17165382 ps
CPU time 0.78 seconds
Started Jul 13 05:58:00 PM PDT 24
Finished Jul 13 05:58:02 PM PDT 24
Peak memory 203964 kb
Host smart-15bf977b-b4c1-40f0-8fdb-9c3a22e694ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484459798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2484459798
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1708876430
Short name T1037
Test name
Test status
Simulation time 232508777 ps
CPU time 1.85 seconds
Started Jul 13 05:57:58 PM PDT 24
Finished Jul 13 05:58:01 PM PDT 24
Peak memory 215516 kb
Host smart-af5e095c-1b43-4543-978f-933312b7d185
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708876430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1708876430
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.823004533
Short name T111
Test name
Test status
Simulation time 64996493 ps
CPU time 1.94 seconds
Started Jul 13 05:58:00 PM PDT 24
Finished Jul 13 05:58:03 PM PDT 24
Peak memory 215788 kb
Host smart-c25fff99-0e55-49f4-9582-02399d100ded
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823004533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.823004533
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2092464185
Short name T102
Test name
Test status
Simulation time 193216200 ps
CPU time 12.59 seconds
Started Jul 13 05:57:57 PM PDT 24
Finished Jul 13 05:58:11 PM PDT 24
Peak memory 215516 kb
Host smart-5d693fe5-199c-43b7-b876-007fd7dff51e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092464185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2092464185
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1930566792
Short name T96
Test name
Test status
Simulation time 998871055 ps
CPU time 2.78 seconds
Started Jul 13 05:57:59 PM PDT 24
Finished Jul 13 05:58:03 PM PDT 24
Peak memory 216660 kb
Host smart-1a106c53-9f8f-4bb3-a2fd-03f2fa7a0cce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930566792 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1930566792
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1888797551
Short name T124
Test name
Test status
Simulation time 94985019 ps
CPU time 1.91 seconds
Started Jul 13 05:57:58 PM PDT 24
Finished Jul 13 05:58:01 PM PDT 24
Peak memory 215452 kb
Host smart-afff8a18-abbc-4ce2-a9ae-a2f33200b46b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888797551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1888797551
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.340963670
Short name T1090
Test name
Test status
Simulation time 15196939 ps
CPU time 0.73 seconds
Started Jul 13 05:57:58 PM PDT 24
Finished Jul 13 05:57:59 PM PDT 24
Peak memory 204020 kb
Host smart-9234a0b3-bb9d-4e58-906c-c8839f2505c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340963670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.340963670
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2378146043
Short name T1151
Test name
Test status
Simulation time 394493067 ps
CPU time 3.06 seconds
Started Jul 13 05:57:59 PM PDT 24
Finished Jul 13 05:58:04 PM PDT 24
Peak memory 215552 kb
Host smart-bb0827d6-d600-4642-96b0-540e8dd328c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378146043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2378146043
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3275334350
Short name T97
Test name
Test status
Simulation time 531400958 ps
CPU time 4.48 seconds
Started Jul 13 05:58:01 PM PDT 24
Finished Jul 13 05:58:06 PM PDT 24
Peak memory 215720 kb
Host smart-7ee06308-124b-435f-af0d-1aa68ad21ba6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275334350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3275334350
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.626700754
Short name T1115
Test name
Test status
Simulation time 3179660911 ps
CPU time 24.24 seconds
Started Jul 13 05:57:59 PM PDT 24
Finished Jul 13 05:58:24 PM PDT 24
Peak memory 216188 kb
Host smart-d95b398b-b1e0-4ab2-af0f-a61ed516fb60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626700754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.626700754
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2843735490
Short name T1112
Test name
Test status
Simulation time 194945909 ps
CPU time 3.46 seconds
Started Jul 13 05:58:07 PM PDT 24
Finished Jul 13 05:58:11 PM PDT 24
Peak memory 218068 kb
Host smart-6afeb348-4bdb-4ebd-8df3-c1b5c5d37df6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843735490 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2843735490
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1827385523
Short name T1145
Test name
Test status
Simulation time 37548919 ps
CPU time 2.48 seconds
Started Jul 13 05:58:07 PM PDT 24
Finished Jul 13 05:58:11 PM PDT 24
Peak memory 215552 kb
Host smart-ad26dab9-1cdc-49b2-9a87-22d4a8a8f89a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827385523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1827385523
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4161390413
Short name T1034
Test name
Test status
Simulation time 77492410 ps
CPU time 0.72 seconds
Started Jul 13 05:57:59 PM PDT 24
Finished Jul 13 05:58:01 PM PDT 24
Peak memory 204000 kb
Host smart-174edb5b-1e3e-41c3-b4fe-eb404568a82e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161390413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
4161390413
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1765687618
Short name T1055
Test name
Test status
Simulation time 195040958 ps
CPU time 1.73 seconds
Started Jul 13 05:58:08 PM PDT 24
Finished Jul 13 05:58:11 PM PDT 24
Peak memory 215416 kb
Host smart-f2ae3b28-557a-4442-a60f-8a15d409efb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765687618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1765687618
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3453170225
Short name T107
Test name
Test status
Simulation time 117424371 ps
CPU time 2.81 seconds
Started Jul 13 05:58:00 PM PDT 24
Finished Jul 13 05:58:04 PM PDT 24
Peak memory 215680 kb
Host smart-bb502e94-e6b8-4457-bdfb-21fef83addcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453170225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3453170225
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1569589811
Short name T1079
Test name
Test status
Simulation time 1646681505 ps
CPU time 9.25 seconds
Started Jul 13 05:57:41 PM PDT 24
Finished Jul 13 05:57:51 PM PDT 24
Peak memory 215560 kb
Host smart-c9e95f1b-4fd7-4b0c-9939-e36e62b045e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569589811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1569589811
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3775573563
Short name T1123
Test name
Test status
Simulation time 1216187772 ps
CPU time 13.29 seconds
Started Jul 13 05:57:44 PM PDT 24
Finished Jul 13 05:58:00 PM PDT 24
Peak memory 207224 kb
Host smart-296b64d7-e6ff-41a1-9092-9e092faf37bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775573563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3775573563
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.265383047
Short name T98
Test name
Test status
Simulation time 185978805 ps
CPU time 1.7 seconds
Started Jul 13 05:57:43 PM PDT 24
Finished Jul 13 05:57:47 PM PDT 24
Peak memory 215516 kb
Host smart-4ca84907-dfb9-47bc-842c-30ceb1375605
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265383047 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.265383047
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2096664624
Short name T152
Test name
Test status
Simulation time 114907191 ps
CPU time 1.16 seconds
Started Jul 13 05:57:43 PM PDT 24
Finished Jul 13 05:57:47 PM PDT 24
Peak memory 207264 kb
Host smart-fd28ec52-7e5d-4fce-bd2e-5e2480a25eb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096664624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
096664624
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3276018946
Short name T1077
Test name
Test status
Simulation time 18066251 ps
CPU time 0.71 seconds
Started Jul 13 05:57:42 PM PDT 24
Finished Jul 13 05:57:44 PM PDT 24
Peak memory 203976 kb
Host smart-8b9aa343-8b70-408f-a9ee-8d72a0b89ea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276018946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
276018946
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4206220376
Short name T1109
Test name
Test status
Simulation time 91799528 ps
CPU time 1.9 seconds
Started Jul 13 05:57:51 PM PDT 24
Finished Jul 13 05:57:55 PM PDT 24
Peak memory 215400 kb
Host smart-5c0c5b0e-a401-449f-9cde-4b24ff708d62
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206220376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.4206220376
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2958669862
Short name T1138
Test name
Test status
Simulation time 9989093 ps
CPU time 0.7 seconds
Started Jul 13 05:57:42 PM PDT 24
Finished Jul 13 05:57:44 PM PDT 24
Peak memory 203888 kb
Host smart-36838853-8b5b-47d4-a455-88faa44d4eea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958669862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2958669862
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2583243563
Short name T1085
Test name
Test status
Simulation time 39376707 ps
CPU time 2.37 seconds
Started Jul 13 05:57:44 PM PDT 24
Finished Jul 13 05:57:49 PM PDT 24
Peak memory 215468 kb
Host smart-92ec1103-33f0-400c-8605-251b5725271b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583243563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2583243563
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.853082938
Short name T112
Test name
Test status
Simulation time 769999427 ps
CPU time 2.68 seconds
Started Jul 13 05:57:42 PM PDT 24
Finished Jul 13 05:57:47 PM PDT 24
Peak memory 215632 kb
Host smart-d830e766-cf10-491c-88e2-324550bb9056
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853082938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.853082938
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3868652950
Short name T175
Test name
Test status
Simulation time 716102973 ps
CPU time 6.78 seconds
Started Jul 13 05:57:42 PM PDT 24
Finished Jul 13 05:57:49 PM PDT 24
Peak memory 215520 kb
Host smart-4cb5c1d6-f77d-447a-adfa-7a71dd5d9600
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868652950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3868652950
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.403991546
Short name T1140
Test name
Test status
Simulation time 25206113 ps
CPU time 0.79 seconds
Started Jul 13 05:58:07 PM PDT 24
Finished Jul 13 05:58:08 PM PDT 24
Peak memory 204036 kb
Host smart-366bbc6b-9639-42dd-83c9-9a05e87f1a8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403991546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.403991546
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.281045831
Short name T1096
Test name
Test status
Simulation time 24520256 ps
CPU time 0.74 seconds
Started Jul 13 05:58:05 PM PDT 24
Finished Jul 13 05:58:06 PM PDT 24
Peak memory 204020 kb
Host smart-b8f70308-931e-444e-a72f-bfd1989e63c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281045831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.281045831
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3219886901
Short name T1069
Test name
Test status
Simulation time 37658259 ps
CPU time 0.68 seconds
Started Jul 13 05:58:05 PM PDT 24
Finished Jul 13 05:58:06 PM PDT 24
Peak memory 203912 kb
Host smart-b4c661de-7ce4-4888-a788-eef0c2e58543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219886901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3219886901
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.269356907
Short name T1058
Test name
Test status
Simulation time 10497318 ps
CPU time 0.71 seconds
Started Jul 13 05:58:07 PM PDT 24
Finished Jul 13 05:58:09 PM PDT 24
Peak memory 203924 kb
Host smart-376bc7d8-df1b-43e0-aa56-3ca51f70f68b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269356907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.269356907
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.76313301
Short name T1039
Test name
Test status
Simulation time 64021236 ps
CPU time 0.71 seconds
Started Jul 13 05:58:06 PM PDT 24
Finished Jul 13 05:58:07 PM PDT 24
Peak memory 204300 kb
Host smart-a1061b7d-60b9-465b-a2c3-725c4feff073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76313301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.76313301
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.600926526
Short name T1041
Test name
Test status
Simulation time 29711144 ps
CPU time 0.75 seconds
Started Jul 13 05:58:05 PM PDT 24
Finished Jul 13 05:58:06 PM PDT 24
Peak memory 203896 kb
Host smart-0333c769-c7f5-4f2d-ba30-ddd0e5a6ddfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600926526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.600926526
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3105559419
Short name T1035
Test name
Test status
Simulation time 44351102 ps
CPU time 0.75 seconds
Started Jul 13 05:58:07 PM PDT 24
Finished Jul 13 05:58:08 PM PDT 24
Peak memory 204320 kb
Host smart-cc58e43b-71fd-4625-9382-357d0f321249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105559419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3105559419
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.880158280
Short name T1122
Test name
Test status
Simulation time 97673388 ps
CPU time 0.79 seconds
Started Jul 13 05:58:07 PM PDT 24
Finished Jul 13 05:58:10 PM PDT 24
Peak memory 204264 kb
Host smart-50534517-f0cf-4fe9-bc08-4bc2ee6b9001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880158280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.880158280
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.473642718
Short name T1059
Test name
Test status
Simulation time 52241901 ps
CPU time 0.74 seconds
Started Jul 13 05:58:06 PM PDT 24
Finished Jul 13 05:58:08 PM PDT 24
Peak memory 203976 kb
Host smart-0214be11-c55f-46d4-af93-c4326a2fe047
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473642718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.473642718
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2857464076
Short name T1105
Test name
Test status
Simulation time 18975675 ps
CPU time 0.75 seconds
Started Jul 13 05:58:12 PM PDT 24
Finished Jul 13 05:58:13 PM PDT 24
Peak memory 204288 kb
Host smart-ba3cfaf1-7b85-4514-9436-e409a24a9b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857464076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2857464076
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1456743022
Short name T1146
Test name
Test status
Simulation time 1412816749 ps
CPU time 14.41 seconds
Started Jul 13 05:57:44 PM PDT 24
Finished Jul 13 05:58:01 PM PDT 24
Peak memory 207252 kb
Host smart-e54a6632-0a89-4cf9-85c0-b599b3c463b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456743022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1456743022
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.361373130
Short name T129
Test name
Test status
Simulation time 11266969281 ps
CPU time 41.69 seconds
Started Jul 13 05:57:42 PM PDT 24
Finished Jul 13 05:58:26 PM PDT 24
Peak memory 215316 kb
Host smart-8a1f4202-7d0f-4c0a-89f6-7bc7a0763b2e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361373130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.361373130
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1591324110
Short name T83
Test name
Test status
Simulation time 94550882 ps
CPU time 1.44 seconds
Started Jul 13 05:57:44 PM PDT 24
Finished Jul 13 05:57:47 PM PDT 24
Peak memory 207324 kb
Host smart-401a131a-de23-46e3-9a3e-751314d455f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591324110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1591324110
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2661619600
Short name T115
Test name
Test status
Simulation time 201470084 ps
CPU time 1.92 seconds
Started Jul 13 05:57:41 PM PDT 24
Finished Jul 13 05:57:44 PM PDT 24
Peak memory 216596 kb
Host smart-9c5d7fbd-3164-4fb5-a9a0-c4e81260653a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661619600 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2661619600
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2279190498
Short name T1078
Test name
Test status
Simulation time 31857506 ps
CPU time 1.95 seconds
Started Jul 13 05:57:41 PM PDT 24
Finished Jul 13 05:57:44 PM PDT 24
Peak memory 215484 kb
Host smart-7f6db2aa-e75b-42e4-8bf4-de2f33ae524c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279190498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
279190498
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.158878272
Short name T1098
Test name
Test status
Simulation time 23407441 ps
CPU time 0.75 seconds
Started Jul 13 05:57:43 PM PDT 24
Finished Jul 13 05:57:45 PM PDT 24
Peak memory 203980 kb
Host smart-245db120-a252-4f1e-be50-4d003b42ee50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158878272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.158878272
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1702510093
Short name T121
Test name
Test status
Simulation time 247405515 ps
CPU time 1.26 seconds
Started Jul 13 05:57:41 PM PDT 24
Finished Jul 13 05:57:43 PM PDT 24
Peak memory 215424 kb
Host smart-65178cc0-77a7-448d-8c6b-be53964b9356
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702510093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1702510093
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4263964032
Short name T1087
Test name
Test status
Simulation time 22712121 ps
CPU time 0.67 seconds
Started Jul 13 05:57:42 PM PDT 24
Finished Jul 13 05:57:44 PM PDT 24
Peak memory 203640 kb
Host smart-f49f6c9b-373f-4e81-b29a-33ca4a1117ba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263964032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.4263964032
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3578268703
Short name T153
Test name
Test status
Simulation time 217479592 ps
CPU time 4.94 seconds
Started Jul 13 05:57:42 PM PDT 24
Finished Jul 13 05:57:49 PM PDT 24
Peak memory 215476 kb
Host smart-61f61ea8-630f-40ff-92dc-856e297e3f1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578268703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3578268703
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1114183473
Short name T109
Test name
Test status
Simulation time 279120264 ps
CPU time 4.7 seconds
Started Jul 13 05:57:47 PM PDT 24
Finished Jul 13 05:57:52 PM PDT 24
Peak memory 215680 kb
Host smart-40c48030-a062-4165-993c-36316c7c748c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114183473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
114183473
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.355958632
Short name T1147
Test name
Test status
Simulation time 206569397 ps
CPU time 7.08 seconds
Started Jul 13 05:57:51 PM PDT 24
Finished Jul 13 05:58:00 PM PDT 24
Peak memory 215456 kb
Host smart-3034433c-35e5-4ee9-a5db-4abbe484f592
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355958632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.355958632
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.166769890
Short name T1086
Test name
Test status
Simulation time 24199716 ps
CPU time 0.74 seconds
Started Jul 13 05:58:09 PM PDT 24
Finished Jul 13 05:58:10 PM PDT 24
Peak memory 203988 kb
Host smart-c3bfa990-a18d-4b3f-a360-080f9b7a0d39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166769890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.166769890
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.642336606
Short name T1065
Test name
Test status
Simulation time 18841033 ps
CPU time 0.77 seconds
Started Jul 13 05:58:07 PM PDT 24
Finished Jul 13 05:58:09 PM PDT 24
Peak memory 204000 kb
Host smart-8c881cca-a71a-4bdc-803d-c8b031b6aadb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642336606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.642336606
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3508568782
Short name T1099
Test name
Test status
Simulation time 128413920 ps
CPU time 0.72 seconds
Started Jul 13 05:58:08 PM PDT 24
Finished Jul 13 05:58:10 PM PDT 24
Peak memory 203988 kb
Host smart-47a2c734-890d-4d1d-941f-573f29ec8207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508568782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3508568782
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2929533214
Short name T1031
Test name
Test status
Simulation time 54544450 ps
CPU time 0.77 seconds
Started Jul 13 05:58:07 PM PDT 24
Finished Jul 13 05:58:09 PM PDT 24
Peak memory 203984 kb
Host smart-ff8bf425-1792-48bb-9ea7-92dbb3a2c5b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929533214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2929533214
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2098010289
Short name T1042
Test name
Test status
Simulation time 189837040 ps
CPU time 0.71 seconds
Started Jul 13 05:58:08 PM PDT 24
Finished Jul 13 05:58:10 PM PDT 24
Peak memory 203636 kb
Host smart-febe7442-a962-49c7-bfea-6a5dc7d97516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098010289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2098010289
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3188009284
Short name T1046
Test name
Test status
Simulation time 189011385 ps
CPU time 0.7 seconds
Started Jul 13 05:58:08 PM PDT 24
Finished Jul 13 05:58:10 PM PDT 24
Peak memory 203944 kb
Host smart-5af32fe7-99d0-4dd3-88e1-6fa6a5fd71e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188009284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3188009284
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2667666644
Short name T1062
Test name
Test status
Simulation time 14093758 ps
CPU time 0.72 seconds
Started Jul 13 05:58:09 PM PDT 24
Finished Jul 13 05:58:11 PM PDT 24
Peak memory 204284 kb
Host smart-2151a1ca-a65c-467a-ab45-44783f449791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667666644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2667666644
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.990997635
Short name T1126
Test name
Test status
Simulation time 27284378 ps
CPU time 0.73 seconds
Started Jul 13 05:58:12 PM PDT 24
Finished Jul 13 05:58:13 PM PDT 24
Peak memory 204288 kb
Host smart-77da8276-b397-43c7-9793-5a90c3ece071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990997635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.990997635
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2280508027
Short name T1036
Test name
Test status
Simulation time 11761294 ps
CPU time 0.69 seconds
Started Jul 13 05:58:08 PM PDT 24
Finished Jul 13 05:58:10 PM PDT 24
Peak memory 203548 kb
Host smart-af0c74c6-3a3f-4b27-9d32-c48669e08732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280508027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2280508027
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.4037854354
Short name T1097
Test name
Test status
Simulation time 12848718 ps
CPU time 0.72 seconds
Started Jul 13 05:58:07 PM PDT 24
Finished Jul 13 05:58:08 PM PDT 24
Peak memory 204020 kb
Host smart-13487563-653c-45f2-bbc7-aee2f111ab1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037854354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
4037854354
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2329755558
Short name T122
Test name
Test status
Simulation time 1074241873 ps
CPU time 22.97 seconds
Started Jul 13 05:57:44 PM PDT 24
Finished Jul 13 05:58:09 PM PDT 24
Peak memory 215516 kb
Host smart-ddb97008-8b4e-4804-b743-5e6609669146
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329755558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2329755558
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1303903396
Short name T1150
Test name
Test status
Simulation time 370964698 ps
CPU time 23.66 seconds
Started Jul 13 05:57:42 PM PDT 24
Finished Jul 13 05:58:07 PM PDT 24
Peak memory 207264 kb
Host smart-04639d69-0f4e-4a93-81f2-3228ff6999ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303903396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1303903396
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4029906240
Short name T154
Test name
Test status
Simulation time 216687896 ps
CPU time 1.78 seconds
Started Jul 13 05:57:44 PM PDT 24
Finished Jul 13 05:57:48 PM PDT 24
Peak memory 215520 kb
Host smart-c098e603-c337-4659-a9ee-d7e058967151
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029906240 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4029906240
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3492952507
Short name T128
Test name
Test status
Simulation time 501565173 ps
CPU time 2.89 seconds
Started Jul 13 05:57:41 PM PDT 24
Finished Jul 13 05:57:45 PM PDT 24
Peak memory 215484 kb
Host smart-9bd2fa65-e692-4550-adbc-4ae320486501
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492952507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
492952507
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2423987446
Short name T1045
Test name
Test status
Simulation time 19038572 ps
CPU time 0.75 seconds
Started Jul 13 05:57:51 PM PDT 24
Finished Jul 13 05:57:53 PM PDT 24
Peak memory 204028 kb
Host smart-2a14aa21-e11e-4577-935a-b8f289039707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423987446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
423987446
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1152903266
Short name T117
Test name
Test status
Simulation time 126128562 ps
CPU time 2.03 seconds
Started Jul 13 05:57:43 PM PDT 24
Finished Jul 13 05:57:47 PM PDT 24
Peak memory 215416 kb
Host smart-40e9c73f-df92-4faa-a3f5-7a6d85bc314b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152903266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1152903266
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.842976349
Short name T1049
Test name
Test status
Simulation time 16464133 ps
CPU time 0.72 seconds
Started Jul 13 05:57:42 PM PDT 24
Finished Jul 13 05:57:44 PM PDT 24
Peak memory 203908 kb
Host smart-26d61ca1-9171-4af9-ad84-2e0a461076bd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842976349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.842976349
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2886247812
Short name T1063
Test name
Test status
Simulation time 105047079 ps
CPU time 2.83 seconds
Started Jul 13 05:57:41 PM PDT 24
Finished Jul 13 05:57:45 PM PDT 24
Peak memory 215516 kb
Host smart-8ee592a7-a657-4b3b-8170-1ab2286eb124
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886247812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2886247812
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3319153728
Short name T95
Test name
Test status
Simulation time 55217966 ps
CPU time 3.17 seconds
Started Jul 13 05:57:49 PM PDT 24
Finished Jul 13 05:57:53 PM PDT 24
Peak memory 215788 kb
Host smart-925f1656-6048-463c-bef1-fcde6a3c1337
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319153728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
319153728
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.226613510
Short name T169
Test name
Test status
Simulation time 2229879492 ps
CPU time 14.86 seconds
Started Jul 13 05:57:42 PM PDT 24
Finished Jul 13 05:57:58 PM PDT 24
Peak memory 216448 kb
Host smart-cf9f233c-0c61-48ef-8ab6-20214981c879
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226613510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.226613510
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2880396892
Short name T1040
Test name
Test status
Simulation time 14324015 ps
CPU time 0.75 seconds
Started Jul 13 05:58:08 PM PDT 24
Finished Jul 13 05:58:10 PM PDT 24
Peak memory 203952 kb
Host smart-3b6378eb-f556-4c83-8fc2-2ca0cc7e56d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880396892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2880396892
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1246818110
Short name T1089
Test name
Test status
Simulation time 24391930 ps
CPU time 0.78 seconds
Started Jul 13 05:58:07 PM PDT 24
Finished Jul 13 05:58:09 PM PDT 24
Peak memory 203936 kb
Host smart-29950851-ae6c-4adf-be13-70816127c79c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246818110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1246818110
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2731121653
Short name T1030
Test name
Test status
Simulation time 60157992 ps
CPU time 0.71 seconds
Started Jul 13 05:58:06 PM PDT 24
Finished Jul 13 05:58:07 PM PDT 24
Peak memory 203968 kb
Host smart-2c8b8667-efea-4f39-a9c4-a82f9c3b10ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731121653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2731121653
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1048379464
Short name T1125
Test name
Test status
Simulation time 28471692 ps
CPU time 0.74 seconds
Started Jul 13 05:58:05 PM PDT 24
Finished Jul 13 05:58:06 PM PDT 24
Peak memory 204052 kb
Host smart-5f0cf413-098b-4c19-8a10-af938eae7e82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048379464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1048379464
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.950265247
Short name T1082
Test name
Test status
Simulation time 13215109 ps
CPU time 0.74 seconds
Started Jul 13 05:58:06 PM PDT 24
Finished Jul 13 05:58:08 PM PDT 24
Peak memory 203972 kb
Host smart-3db2719d-5509-4a37-95b9-f5ddbcf7141f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950265247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.950265247
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1357156736
Short name T1028
Test name
Test status
Simulation time 16145106 ps
CPU time 0.7 seconds
Started Jul 13 05:58:07 PM PDT 24
Finished Jul 13 05:58:08 PM PDT 24
Peak memory 203928 kb
Host smart-2fa47832-d991-4a9a-a6f4-8042b863bdca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357156736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1357156736
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2520747150
Short name T1050
Test name
Test status
Simulation time 41061924 ps
CPU time 0.73 seconds
Started Jul 13 05:58:08 PM PDT 24
Finished Jul 13 05:58:10 PM PDT 24
Peak memory 204000 kb
Host smart-01cecf53-9874-4857-bee4-961138fdb8a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520747150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2520747150
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1556506312
Short name T1043
Test name
Test status
Simulation time 12946670 ps
CPU time 0.7 seconds
Started Jul 13 05:58:07 PM PDT 24
Finished Jul 13 05:58:09 PM PDT 24
Peak memory 203988 kb
Host smart-621de50f-a64a-4135-8938-49ee707eee9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556506312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1556506312
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3013553790
Short name T1032
Test name
Test status
Simulation time 18098488 ps
CPU time 0.78 seconds
Started Jul 13 05:58:07 PM PDT 24
Finished Jul 13 05:58:09 PM PDT 24
Peak memory 204284 kb
Host smart-cf04bd62-9a6c-4d54-a648-59fcda85d5ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013553790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3013553790
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1469075844
Short name T1088
Test name
Test status
Simulation time 19292301 ps
CPU time 0.7 seconds
Started Jul 13 05:58:06 PM PDT 24
Finished Jul 13 05:58:08 PM PDT 24
Peak memory 203912 kb
Host smart-f30d6da9-ce1d-4b1b-8897-9a782c4e8264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469075844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1469075844
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2763221255
Short name T1110
Test name
Test status
Simulation time 88192444 ps
CPU time 1.6 seconds
Started Jul 13 05:57:43 PM PDT 24
Finished Jul 13 05:57:47 PM PDT 24
Peak memory 215472 kb
Host smart-8a86a8b9-75c0-4bff-b730-bc5b5f4814f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763221255 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2763221255
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.504724530
Short name T1116
Test name
Test status
Simulation time 92717319 ps
CPU time 2.74 seconds
Started Jul 13 05:57:44 PM PDT 24
Finished Jul 13 05:57:49 PM PDT 24
Peak memory 215544 kb
Host smart-572fe1b0-411f-487e-be42-1c01401b1756
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504724530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.504724530
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3252025796
Short name T1047
Test name
Test status
Simulation time 57415510 ps
CPU time 0.77 seconds
Started Jul 13 05:57:42 PM PDT 24
Finished Jul 13 05:57:44 PM PDT 24
Peak memory 204052 kb
Host smart-36933489-e499-4779-99ab-9f562d4c34a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252025796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
252025796
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1176913219
Short name T1068
Test name
Test status
Simulation time 134133652 ps
CPU time 1.69 seconds
Started Jul 13 05:57:44 PM PDT 24
Finished Jul 13 05:57:47 PM PDT 24
Peak memory 207348 kb
Host smart-3f31f3d7-d7dc-4c92-a5b0-a6e327a5688c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176913219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1176913219
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2080126077
Short name T1111
Test name
Test status
Simulation time 151700660 ps
CPU time 2.84 seconds
Started Jul 13 05:57:43 PM PDT 24
Finished Jul 13 05:57:47 PM PDT 24
Peak memory 215732 kb
Host smart-555e80a7-6877-4c2a-bd6a-d316292035b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080126077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
080126077
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3082669242
Short name T1144
Test name
Test status
Simulation time 88500557 ps
CPU time 2.78 seconds
Started Jul 13 05:57:47 PM PDT 24
Finished Jul 13 05:57:50 PM PDT 24
Peak memory 216544 kb
Host smart-7647cbc8-203c-418b-82b1-239e072097c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082669242 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3082669242
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2006623831
Short name T1128
Test name
Test status
Simulation time 50495811 ps
CPU time 1.46 seconds
Started Jul 13 05:57:49 PM PDT 24
Finished Jul 13 05:57:51 PM PDT 24
Peak memory 215296 kb
Host smart-43f68e91-7ecd-411d-b4f0-cd1f344e3280
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006623831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
006623831
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3288816988
Short name T1051
Test name
Test status
Simulation time 105492416 ps
CPU time 0.73 seconds
Started Jul 13 05:57:42 PM PDT 24
Finished Jul 13 05:57:44 PM PDT 24
Peak memory 204040 kb
Host smart-e4688907-e7d1-48a3-9b25-8f3de6c13238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288816988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
288816988
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2497353796
Short name T1119
Test name
Test status
Simulation time 166527700 ps
CPU time 4 seconds
Started Jul 13 05:57:41 PM PDT 24
Finished Jul 13 05:57:46 PM PDT 24
Peak memory 215492 kb
Host smart-f463e367-965f-452d-bcce-e50c01dd3b71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497353796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2497353796
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3564850644
Short name T1143
Test name
Test status
Simulation time 152456014 ps
CPU time 3.76 seconds
Started Jul 13 05:57:44 PM PDT 24
Finished Jul 13 05:57:50 PM PDT 24
Peak memory 215812 kb
Host smart-b02bf9d5-52e4-4b49-ac5a-c2e6fbd438d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564850644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
564850644
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1884691267
Short name T1061
Test name
Test status
Simulation time 3091547606 ps
CPU time 16.41 seconds
Started Jul 13 05:57:41 PM PDT 24
Finished Jul 13 05:57:58 PM PDT 24
Peak memory 215928 kb
Host smart-c008b031-97e9-48e8-9b03-8a4e152c309b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884691267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1884691267
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.525043939
Short name T1074
Test name
Test status
Simulation time 292682792 ps
CPU time 2.06 seconds
Started Jul 13 05:57:50 PM PDT 24
Finished Jul 13 05:57:53 PM PDT 24
Peak memory 215596 kb
Host smart-7d42ec0d-c352-4cb2-a559-10ded8b10081
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525043939 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.525043939
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3620400063
Short name T119
Test name
Test status
Simulation time 402325040 ps
CPU time 2.76 seconds
Started Jul 13 05:57:49 PM PDT 24
Finished Jul 13 05:57:52 PM PDT 24
Peak memory 215208 kb
Host smart-c3d015ca-95b9-42f4-8a33-51f607645b89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620400063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
620400063
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2430173231
Short name T1113
Test name
Test status
Simulation time 98973738 ps
CPU time 0.78 seconds
Started Jul 13 05:57:41 PM PDT 24
Finished Jul 13 05:57:42 PM PDT 24
Peak memory 204024 kb
Host smart-d8b34e5c-7b44-4e0c-ae68-55df6c6eee75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430173231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
430173231
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2618113238
Short name T1102
Test name
Test status
Simulation time 82559669 ps
CPU time 1.97 seconds
Started Jul 13 05:57:52 PM PDT 24
Finished Jul 13 05:57:55 PM PDT 24
Peak memory 215560 kb
Host smart-86176cee-3662-4dba-a71a-3471e66fce3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618113238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2618113238
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3059103639
Short name T1135
Test name
Test status
Simulation time 121215486 ps
CPU time 4.29 seconds
Started Jul 13 05:57:44 PM PDT 24
Finished Jul 13 05:57:51 PM PDT 24
Peak memory 215744 kb
Host smart-f328d09b-0e56-4349-9003-050f8e070f11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059103639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
059103639
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1760125631
Short name T170
Test name
Test status
Simulation time 2462924631 ps
CPU time 18.09 seconds
Started Jul 13 05:57:43 PM PDT 24
Finished Jul 13 05:58:04 PM PDT 24
Peak memory 215528 kb
Host smart-361ebd10-8996-4cce-8533-7cacd4927940
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760125631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1760125631
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.555716501
Short name T127
Test name
Test status
Simulation time 189485122 ps
CPU time 2.79 seconds
Started Jul 13 05:57:57 PM PDT 24
Finished Jul 13 05:58:00 PM PDT 24
Peak memory 215352 kb
Host smart-b785a6d6-af6e-45d2-81af-4110cd6cd9fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555716501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.555716501
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1152108417
Short name T1114
Test name
Test status
Simulation time 56934484 ps
CPU time 0.74 seconds
Started Jul 13 05:57:50 PM PDT 24
Finished Jul 13 05:57:53 PM PDT 24
Peak memory 203956 kb
Host smart-a96eb887-7911-4498-9313-a239831c12ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152108417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
152108417
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2065788427
Short name T1094
Test name
Test status
Simulation time 155037158 ps
CPU time 1.97 seconds
Started Jul 13 05:57:52 PM PDT 24
Finished Jul 13 05:57:55 PM PDT 24
Peak memory 215524 kb
Host smart-8b1c345a-94bb-4945-bcfb-e17e99ea5b99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065788427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2065788427
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.493585245
Short name T1075
Test name
Test status
Simulation time 721395199 ps
CPU time 5.16 seconds
Started Jul 13 05:57:52 PM PDT 24
Finished Jul 13 05:57:58 PM PDT 24
Peak memory 215780 kb
Host smart-6eafb97f-ea87-4b72-b459-5d6f576bbcd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493585245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.493585245
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2799434510
Short name T1132
Test name
Test status
Simulation time 531508380 ps
CPU time 8.36 seconds
Started Jul 13 05:57:50 PM PDT 24
Finished Jul 13 05:57:59 PM PDT 24
Peak memory 215476 kb
Host smart-be87eb52-2544-47a7-a6a0-6e8deac86d3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799434510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2799434510
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4017912533
Short name T1136
Test name
Test status
Simulation time 621786766 ps
CPU time 3.67 seconds
Started Jul 13 05:57:51 PM PDT 24
Finished Jul 13 05:57:57 PM PDT 24
Peak memory 217472 kb
Host smart-0e88557c-171d-4f4d-b144-4ec4f9378a18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017912533 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.4017912533
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4046187036
Short name T1093
Test name
Test status
Simulation time 20896915 ps
CPU time 1.26 seconds
Started Jul 13 05:57:51 PM PDT 24
Finished Jul 13 05:57:54 PM PDT 24
Peak memory 207332 kb
Host smart-cb190ce6-b86f-4849-860b-b227dee6d510
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046187036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4
046187036
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1040201366
Short name T1101
Test name
Test status
Simulation time 25171954 ps
CPU time 0.74 seconds
Started Jul 13 05:57:53 PM PDT 24
Finished Jul 13 05:57:54 PM PDT 24
Peak memory 203888 kb
Host smart-227c8354-46a8-4851-aa5a-64503bd9ff84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040201366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
040201366
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.796452975
Short name T1139
Test name
Test status
Simulation time 153142212 ps
CPU time 2.8 seconds
Started Jul 13 05:57:51 PM PDT 24
Finished Jul 13 05:57:56 PM PDT 24
Peak memory 215492 kb
Host smart-03bdc4a8-29d3-4637-944b-17885c82bd49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796452975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.796452975
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3825337252
Short name T108
Test name
Test status
Simulation time 269393015 ps
CPU time 3.94 seconds
Started Jul 13 05:57:51 PM PDT 24
Finished Jul 13 05:57:56 PM PDT 24
Peak memory 215692 kb
Host smart-fda42b27-6998-4ca8-9df6-2ee09e9b48c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825337252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
825337252
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.815983986
Short name T1100
Test name
Test status
Simulation time 2818749680 ps
CPU time 13.05 seconds
Started Jul 13 05:57:52 PM PDT 24
Finished Jul 13 05:58:06 PM PDT 24
Peak memory 215672 kb
Host smart-6aef9612-b9ee-47cf-bccf-bb981347baea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815983986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.815983986
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.492930016
Short name T856
Test name
Test status
Simulation time 16266278 ps
CPU time 0.81 seconds
Started Jul 13 05:25:45 PM PDT 24
Finished Jul 13 05:25:46 PM PDT 24
Peak memory 206688 kb
Host smart-5549eedd-2613-4e51-85db-d12d4a84f47f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492930016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.492930016
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3330359141
Short name T665
Test name
Test status
Simulation time 103122195 ps
CPU time 3.01 seconds
Started Jul 13 05:25:31 PM PDT 24
Finished Jul 13 05:25:34 PM PDT 24
Peak memory 225564 kb
Host smart-2d1ce383-7626-4721-9f39-27881d6c4450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330359141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3330359141
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2689237621
Short name T293
Test name
Test status
Simulation time 58703596 ps
CPU time 0.84 seconds
Started Jul 13 05:25:14 PM PDT 24
Finished Jul 13 05:25:15 PM PDT 24
Peak memory 207444 kb
Host smart-83b34c51-d756-4f6f-a8b6-b53aae8de2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689237621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2689237621
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.982465481
Short name T989
Test name
Test status
Simulation time 2054547408 ps
CPU time 19.62 seconds
Started Jul 13 05:25:31 PM PDT 24
Finished Jul 13 05:25:51 PM PDT 24
Peak memory 241908 kb
Host smart-d0d03fbc-50fa-420e-95a5-9f4cb698013a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982465481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.982465481
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.4207131071
Short name T1015
Test name
Test status
Simulation time 47943787100 ps
CPU time 390.35 seconds
Started Jul 13 05:25:44 PM PDT 24
Finished Jul 13 05:32:15 PM PDT 24
Peak memory 263672 kb
Host smart-3eaa40cb-9d87-4270-842c-5ac8658ce406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207131071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.4207131071
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3997222726
Short name T730
Test name
Test status
Simulation time 4491002697 ps
CPU time 62.79 seconds
Started Jul 13 05:25:32 PM PDT 24
Finished Jul 13 05:26:35 PM PDT 24
Peak memory 254212 kb
Host smart-d4034d57-b528-4d55-94fb-8f42479d3515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997222726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3997222726
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3520436481
Short name T192
Test name
Test status
Simulation time 412812504 ps
CPU time 5.16 seconds
Started Jul 13 05:25:30 PM PDT 24
Finished Jul 13 05:25:36 PM PDT 24
Peak memory 225504 kb
Host smart-45c09c8c-73d3-4d1a-b378-10c0cd7fd3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520436481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3520436481
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4125433058
Short name T554
Test name
Test status
Simulation time 29119999670 ps
CPU time 22.92 seconds
Started Jul 13 05:25:29 PM PDT 24
Finished Jul 13 05:25:53 PM PDT 24
Peak memory 225480 kb
Host smart-5465ae0d-110f-4744-9200-4898e56ddaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125433058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4125433058
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3015847487
Short name T996
Test name
Test status
Simulation time 52304425 ps
CPU time 1.06 seconds
Started Jul 13 05:25:12 PM PDT 24
Finished Jul 13 05:25:13 PM PDT 24
Peak memory 218948 kb
Host smart-5b25b95e-e0e7-4a30-aca9-e47856269fec
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015847487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3015847487
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1404521554
Short name T987
Test name
Test status
Simulation time 405782121 ps
CPU time 2.37 seconds
Started Jul 13 05:25:21 PM PDT 24
Finished Jul 13 05:25:23 PM PDT 24
Peak memory 233540 kb
Host smart-601124cf-c5a2-4327-981f-32c53ba02c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404521554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1404521554
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3148308648
Short name T787
Test name
Test status
Simulation time 30041205 ps
CPU time 2.15 seconds
Started Jul 13 05:25:21 PM PDT 24
Finished Jul 13 05:25:23 PM PDT 24
Peak memory 224100 kb
Host smart-af9f439d-fc08-4186-9dd5-3c897e8c91d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148308648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3148308648
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2668425039
Short name T639
Test name
Test status
Simulation time 205375907 ps
CPU time 5.2 seconds
Started Jul 13 05:25:32 PM PDT 24
Finished Jul 13 05:25:38 PM PDT 24
Peak memory 224164 kb
Host smart-eb3c57dd-b761-4f0f-8521-90c57e6445c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2668425039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2668425039
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2609850182
Short name T413
Test name
Test status
Simulation time 7081804992 ps
CPU time 86.01 seconds
Started Jul 13 05:25:45 PM PDT 24
Finished Jul 13 05:27:12 PM PDT 24
Peak memory 251444 kb
Host smart-438b9e25-7f1b-42ca-88a3-8e0e112d17f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609850182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2609850182
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.112523551
Short name T533
Test name
Test status
Simulation time 3587314522 ps
CPU time 14.47 seconds
Started Jul 13 05:25:14 PM PDT 24
Finished Jul 13 05:25:29 PM PDT 24
Peak memory 217768 kb
Host smart-c3b392e8-cc82-4e75-ae34-7130668f0e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112523551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.112523551
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1059281529
Short name T322
Test name
Test status
Simulation time 48167735649 ps
CPU time 8.97 seconds
Started Jul 13 05:25:12 PM PDT 24
Finished Jul 13 05:25:22 PM PDT 24
Peak memory 217380 kb
Host smart-24e4f113-65e3-4434-b5a3-df3c2929b0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059281529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1059281529
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2679755308
Short name T364
Test name
Test status
Simulation time 64378667 ps
CPU time 0.67 seconds
Started Jul 13 05:25:13 PM PDT 24
Finished Jul 13 05:25:14 PM PDT 24
Peak memory 206468 kb
Host smart-5dbaf9d5-7b90-4e5c-9012-96ea880836ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679755308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2679755308
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.4105255410
Short name T456
Test name
Test status
Simulation time 24129155 ps
CPU time 0.81 seconds
Started Jul 13 05:25:12 PM PDT 24
Finished Jul 13 05:25:13 PM PDT 24
Peak memory 206884 kb
Host smart-1014e067-be94-4fc1-83ae-58fba6ae7f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105255410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.4105255410
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1081936860
Short name T772
Test name
Test status
Simulation time 401573155 ps
CPU time 2.85 seconds
Started Jul 13 05:25:31 PM PDT 24
Finished Jul 13 05:25:34 PM PDT 24
Peak memory 233740 kb
Host smart-39e2b450-298b-43cc-9267-abb226d8c2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081936860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1081936860
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1013913858
Short name T294
Test name
Test status
Simulation time 39769395 ps
CPU time 0.73 seconds
Started Jul 13 05:26:03 PM PDT 24
Finished Jul 13 05:26:04 PM PDT 24
Peak memory 206288 kb
Host smart-46d03aeb-b03f-477e-8e3d-31fbb07ba05d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013913858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
013913858
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3302221559
Short name T342
Test name
Test status
Simulation time 833308556 ps
CPU time 4.71 seconds
Started Jul 13 05:25:55 PM PDT 24
Finished Jul 13 05:26:01 PM PDT 24
Peak memory 233644 kb
Host smart-d1ee0ed3-4eb0-48da-a95c-ebda88a3f332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302221559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3302221559
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3501665388
Short name T566
Test name
Test status
Simulation time 59124123 ps
CPU time 0.79 seconds
Started Jul 13 05:25:44 PM PDT 24
Finished Jul 13 05:25:45 PM PDT 24
Peak memory 207496 kb
Host smart-1b2f5223-7c61-4f30-a3b9-d6030e6083bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501665388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3501665388
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.697945089
Short name T895
Test name
Test status
Simulation time 6915063250 ps
CPU time 31.13 seconds
Started Jul 13 05:25:58 PM PDT 24
Finished Jul 13 05:26:30 PM PDT 24
Peak memory 256156 kb
Host smart-0162be4c-a22c-4db5-823d-d1e53d016253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697945089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.697945089
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2154656209
Short name T140
Test name
Test status
Simulation time 54664786860 ps
CPU time 154.37 seconds
Started Jul 13 05:25:55 PM PDT 24
Finished Jul 13 05:28:30 PM PDT 24
Peak memory 251644 kb
Host smart-68a85d9a-0eee-4951-b798-ffba094403ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154656209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2154656209
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.774191046
Short name T511
Test name
Test status
Simulation time 5940962025 ps
CPU time 84 seconds
Started Jul 13 05:25:55 PM PDT 24
Finished Jul 13 05:27:20 PM PDT 24
Peak memory 250384 kb
Host smart-30a2bd86-9f0d-41ee-ae6a-49ce897143ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774191046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
774191046
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3678192749
Short name T347
Test name
Test status
Simulation time 160665435 ps
CPU time 3.79 seconds
Started Jul 13 05:25:55 PM PDT 24
Finished Jul 13 05:25:59 PM PDT 24
Peak memory 225488 kb
Host smart-ecf199dc-45a5-4d46-bd89-04f44ca1e329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678192749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3678192749
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3556489009
Short name T841
Test name
Test status
Simulation time 6712950995 ps
CPU time 23.8 seconds
Started Jul 13 05:25:57 PM PDT 24
Finished Jul 13 05:26:21 PM PDT 24
Peak memory 242108 kb
Host smart-53205cdf-6a1e-429f-93ea-ff4c7568c8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556489009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3556489009
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.49405148
Short name T420
Test name
Test status
Simulation time 1506781486 ps
CPU time 15.87 seconds
Started Jul 13 05:25:55 PM PDT 24
Finished Jul 13 05:26:12 PM PDT 24
Peak memory 225528 kb
Host smart-85ee1aa6-55b7-48ca-b11d-0f937569c5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49405148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.49405148
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1330386230
Short name T683
Test name
Test status
Simulation time 3011230936 ps
CPU time 9.68 seconds
Started Jul 13 05:25:54 PM PDT 24
Finished Jul 13 05:26:04 PM PDT 24
Peak memory 233876 kb
Host smart-e19d6654-e187-4f35-8bdf-db02bcd75416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330386230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1330386230
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.32306021
Short name T671
Test name
Test status
Simulation time 56013938 ps
CPU time 1.12 seconds
Started Jul 13 05:25:44 PM PDT 24
Finished Jul 13 05:25:46 PM PDT 24
Peak memory 217428 kb
Host smart-26578e58-6398-463d-b97c-620df9ab7e7e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32306021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.32306021
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3602705010
Short name T786
Test name
Test status
Simulation time 13322112816 ps
CPU time 10.95 seconds
Started Jul 13 05:25:56 PM PDT 24
Finished Jul 13 05:26:07 PM PDT 24
Peak memory 225700 kb
Host smart-10cef806-07a4-46ba-945a-4a70b1b03de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602705010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3602705010
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2033510092
Short name T1017
Test name
Test status
Simulation time 458210369 ps
CPU time 4.3 seconds
Started Jul 13 05:25:56 PM PDT 24
Finished Jul 13 05:26:01 PM PDT 24
Peak memory 233740 kb
Host smart-4c2c2a99-f989-477a-8147-745d53e8e6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033510092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2033510092
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.891563565
Short name T450
Test name
Test status
Simulation time 2757106686 ps
CPU time 11.94 seconds
Started Jul 13 05:25:55 PM PDT 24
Finished Jul 13 05:26:08 PM PDT 24
Peak memory 221560 kb
Host smart-e10ea54a-a898-4423-85b3-e8be4d732344
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=891563565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.891563565
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3378764038
Short name T66
Test name
Test status
Simulation time 169756553 ps
CPU time 1 seconds
Started Jul 13 05:26:03 PM PDT 24
Finished Jul 13 05:26:05 PM PDT 24
Peak memory 236688 kb
Host smart-dc95b2f8-5fc7-467c-b644-29539aacceea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378764038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3378764038
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.312036662
Short name T86
Test name
Test status
Simulation time 160824468062 ps
CPU time 277.23 seconds
Started Jul 13 05:26:02 PM PDT 24
Finished Jul 13 05:30:40 PM PDT 24
Peak memory 254232 kb
Host smart-20e4d85c-4170-425f-af48-e56f6bd6d510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312036662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.312036662
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2199217319
Short name T616
Test name
Test status
Simulation time 62332039 ps
CPU time 0.72 seconds
Started Jul 13 05:25:56 PM PDT 24
Finished Jul 13 05:25:57 PM PDT 24
Peak memory 206672 kb
Host smart-0127ba96-4c5a-465e-a0af-2d6d12e49d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199217319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2199217319
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3033580517
Short name T429
Test name
Test status
Simulation time 4299755984 ps
CPU time 7.52 seconds
Started Jul 13 05:25:58 PM PDT 24
Finished Jul 13 05:26:05 PM PDT 24
Peak memory 217412 kb
Host smart-1ea78cbf-da08-4457-abae-648f425e5b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033580517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3033580517
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3723324590
Short name T370
Test name
Test status
Simulation time 27573555 ps
CPU time 0.87 seconds
Started Jul 13 05:25:58 PM PDT 24
Finished Jul 13 05:25:59 PM PDT 24
Peak memory 207952 kb
Host smart-72afb80a-dd75-4003-a8d5-15c334f055ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723324590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3723324590
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3117530007
Short name T938
Test name
Test status
Simulation time 36473510 ps
CPU time 0.77 seconds
Started Jul 13 05:25:55 PM PDT 24
Finished Jul 13 05:25:57 PM PDT 24
Peak memory 206956 kb
Host smart-66e75d5b-fa5b-4f2e-9282-875814b9f962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117530007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3117530007
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1216507020
Short name T623
Test name
Test status
Simulation time 813586438 ps
CPU time 10.24 seconds
Started Jul 13 05:25:56 PM PDT 24
Finished Jul 13 05:26:07 PM PDT 24
Peak memory 241716 kb
Host smart-fb82082c-fa3b-4564-9c17-4b4daba1b2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216507020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1216507020
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3172266377
Short name T720
Test name
Test status
Simulation time 20472259 ps
CPU time 0.75 seconds
Started Jul 13 05:28:40 PM PDT 24
Finished Jul 13 05:28:41 PM PDT 24
Peak memory 206352 kb
Host smart-5918d5b2-fbee-4ba1-aa22-369aceb6b115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172266377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3172266377
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1118313067
Short name T235
Test name
Test status
Simulation time 222239214 ps
CPU time 5.5 seconds
Started Jul 13 05:28:31 PM PDT 24
Finished Jul 13 05:28:38 PM PDT 24
Peak memory 225540 kb
Host smart-08babb29-48a3-406c-9c77-4412b6961f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118313067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1118313067
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3257072509
Short name T28
Test name
Test status
Simulation time 17057483 ps
CPU time 0.81 seconds
Started Jul 13 05:28:29 PM PDT 24
Finished Jul 13 05:28:30 PM PDT 24
Peak memory 207496 kb
Host smart-8a69bd13-1840-4942-a33a-93b25907c251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257072509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3257072509
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.239609881
Short name T941
Test name
Test status
Simulation time 12420264306 ps
CPU time 136.09 seconds
Started Jul 13 05:28:40 PM PDT 24
Finished Jul 13 05:30:57 PM PDT 24
Peak memory 274288 kb
Host smart-d4659d89-177f-40d3-b3ca-adb87ee4a054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239609881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.239609881
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1558765001
Short name T629
Test name
Test status
Simulation time 12826535323 ps
CPU time 94.93 seconds
Started Jul 13 05:28:43 PM PDT 24
Finished Jul 13 05:30:19 PM PDT 24
Peak memory 267304 kb
Host smart-545c020e-8198-41e5-8a27-d1342b34a4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558765001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1558765001
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2304211057
Short name T518
Test name
Test status
Simulation time 2812835987 ps
CPU time 62.11 seconds
Started Jul 13 05:28:40 PM PDT 24
Finished Jul 13 05:29:42 PM PDT 24
Peak memory 253748 kb
Host smart-8016126a-8579-42c4-8adc-f69d84c21599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304211057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2304211057
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2254909575
Short name T488
Test name
Test status
Simulation time 255530664 ps
CPU time 8.19 seconds
Started Jul 13 05:28:31 PM PDT 24
Finished Jul 13 05:28:40 PM PDT 24
Peak memory 233648 kb
Host smart-0679ec42-8b35-4a17-8bf8-001e6846b5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254909575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2254909575
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1098331466
Short name T940
Test name
Test status
Simulation time 715303888157 ps
CPU time 357.06 seconds
Started Jul 13 05:28:31 PM PDT 24
Finished Jul 13 05:34:29 PM PDT 24
Peak memory 274700 kb
Host smart-5706404a-5e7f-4bab-91d6-2b6760a427d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098331466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1098331466
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2908595407
Short name T681
Test name
Test status
Simulation time 368768897 ps
CPU time 4.91 seconds
Started Jul 13 05:28:30 PM PDT 24
Finished Jul 13 05:28:35 PM PDT 24
Peak memory 233696 kb
Host smart-5d7802d3-0e8e-4173-8e21-8ad8a054f171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908595407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2908595407
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3536283477
Short name T603
Test name
Test status
Simulation time 14110375131 ps
CPU time 37.08 seconds
Started Jul 13 05:28:32 PM PDT 24
Finished Jul 13 05:29:09 PM PDT 24
Peak memory 225700 kb
Host smart-6e1bde49-6663-4736-9ecf-6cef6dd86885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536283477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3536283477
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3470893956
Short name T611
Test name
Test status
Simulation time 121371988 ps
CPU time 1 seconds
Started Jul 13 05:28:31 PM PDT 24
Finished Jul 13 05:28:33 PM PDT 24
Peak memory 218944 kb
Host smart-0f5a5416-e3e7-40e2-9b77-f27def37d48f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470893956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3470893956
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2273004832
Short name T908
Test name
Test status
Simulation time 4998851414 ps
CPU time 7.57 seconds
Started Jul 13 05:28:32 PM PDT 24
Finished Jul 13 05:28:40 PM PDT 24
Peak memory 225700 kb
Host smart-b20f921b-b3aa-4851-935c-74f194e21df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273004832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2273004832
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2500209921
Short name T767
Test name
Test status
Simulation time 11876999225 ps
CPU time 14.39 seconds
Started Jul 13 05:28:31 PM PDT 24
Finished Jul 13 05:28:46 PM PDT 24
Peak memory 234944 kb
Host smart-918bd1c0-63e5-4034-b225-124b5508aa67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500209921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2500209921
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2173842686
Short name T148
Test name
Test status
Simulation time 141209676 ps
CPU time 3.4 seconds
Started Jul 13 05:28:41 PM PDT 24
Finished Jul 13 05:28:45 PM PDT 24
Peak memory 223476 kb
Host smart-512d0ee3-70d2-4c91-b265-a78ede6b8f35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2173842686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2173842686
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.4190052611
Short name T1019
Test name
Test status
Simulation time 19647261077 ps
CPU time 28.06 seconds
Started Jul 13 05:28:32 PM PDT 24
Finished Jul 13 05:29:00 PM PDT 24
Peak memory 217480 kb
Host smart-28e0184f-aa39-4cc3-94d2-6811abd0a67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190052611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4190052611
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.762129759
Short name T556
Test name
Test status
Simulation time 591655591 ps
CPU time 3.92 seconds
Started Jul 13 05:28:30 PM PDT 24
Finished Jul 13 05:28:34 PM PDT 24
Peak memory 217340 kb
Host smart-dcaaf85e-ce4a-42e8-8e0b-39d0b23594d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762129759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.762129759
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2782220090
Short name T833
Test name
Test status
Simulation time 103840630 ps
CPU time 1.69 seconds
Started Jul 13 05:28:31 PM PDT 24
Finished Jul 13 05:28:34 PM PDT 24
Peak memory 217288 kb
Host smart-a8329405-fb67-4f13-b9e4-139c969b8117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782220090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2782220090
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1305990025
Short name T791
Test name
Test status
Simulation time 99036903 ps
CPU time 0.92 seconds
Started Jul 13 05:28:30 PM PDT 24
Finished Jul 13 05:28:32 PM PDT 24
Peak memory 206944 kb
Host smart-8ae2902f-fa19-4235-8b2b-a600bf5531cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305990025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1305990025
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.206087623
Short name T200
Test name
Test status
Simulation time 5356025201 ps
CPU time 6.41 seconds
Started Jul 13 05:28:29 PM PDT 24
Finished Jul 13 05:28:35 PM PDT 24
Peak memory 233768 kb
Host smart-b120e553-41ac-4ff1-9d92-ba2a4ce3a379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206087623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.206087623
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3728804747
Short name T944
Test name
Test status
Simulation time 21450629 ps
CPU time 0.74 seconds
Started Jul 13 05:28:57 PM PDT 24
Finished Jul 13 05:28:58 PM PDT 24
Peak memory 206332 kb
Host smart-e9ce6ea9-c4d8-4a08-b980-c898064d04df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728804747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3728804747
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1476850018
Short name T618
Test name
Test status
Simulation time 1959203671 ps
CPU time 10.34 seconds
Started Jul 13 05:28:53 PM PDT 24
Finished Jul 13 05:29:04 PM PDT 24
Peak memory 233724 kb
Host smart-3bc653dc-e4fb-4db5-b852-cda7176381ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476850018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1476850018
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3540814128
Short name T537
Test name
Test status
Simulation time 37419557 ps
CPU time 0.8 seconds
Started Jul 13 05:28:43 PM PDT 24
Finished Jul 13 05:28:44 PM PDT 24
Peak memory 207512 kb
Host smart-d4b71186-4d7a-4c0d-9c30-e3c13770b8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540814128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3540814128
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1317744216
Short name T103
Test name
Test status
Simulation time 853464655 ps
CPU time 7.93 seconds
Started Jul 13 05:28:52 PM PDT 24
Finished Jul 13 05:29:00 PM PDT 24
Peak memory 225548 kb
Host smart-0d86e09e-9561-44ad-bb2b-790a8a157b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317744216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1317744216
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2265888376
Short name T264
Test name
Test status
Simulation time 40637348887 ps
CPU time 229.83 seconds
Started Jul 13 05:28:53 PM PDT 24
Finished Jul 13 05:32:43 PM PDT 24
Peak memory 265080 kb
Host smart-b0be48a2-7e13-4f17-9c03-ae26020d93b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265888376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2265888376
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.4037986235
Short name T526
Test name
Test status
Simulation time 4336523080 ps
CPU time 17.38 seconds
Started Jul 13 05:28:56 PM PDT 24
Finished Jul 13 05:29:14 PM PDT 24
Peak memory 242308 kb
Host smart-1f9bd0d6-b4ce-4e15-9f4d-ab8e14ac67e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037986235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.4037986235
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3933638850
Short name T572
Test name
Test status
Simulation time 371758551 ps
CPU time 7.48 seconds
Started Jul 13 05:28:52 PM PDT 24
Finished Jul 13 05:29:00 PM PDT 24
Peak memory 233728 kb
Host smart-4d8e9717-0e40-4242-be48-680ced52b00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933638850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3933638850
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3997301452
Short name T424
Test name
Test status
Simulation time 14777386206 ps
CPU time 34.51 seconds
Started Jul 13 05:28:52 PM PDT 24
Finished Jul 13 05:29:27 PM PDT 24
Peak memory 237820 kb
Host smart-e32f4162-2e5e-4814-96cf-51ef636f1b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997301452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3997301452
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.74016203
Short name T624
Test name
Test status
Simulation time 32084944 ps
CPU time 1.06 seconds
Started Jul 13 05:28:41 PM PDT 24
Finished Jul 13 05:28:42 PM PDT 24
Peak memory 217596 kb
Host smart-57cda35c-d12a-411b-9c31-5e33c42ad845
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74016203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.74016203
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2373770310
Short name T2
Test name
Test status
Simulation time 2710917721 ps
CPU time 9.71 seconds
Started Jul 13 05:28:51 PM PDT 24
Finished Jul 13 05:29:01 PM PDT 24
Peak memory 239356 kb
Host smart-55879c84-2811-4271-be8c-6acf7f3f8de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373770310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2373770310
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.687980409
Short name T250
Test name
Test status
Simulation time 484336529 ps
CPU time 7.92 seconds
Started Jul 13 05:28:53 PM PDT 24
Finished Jul 13 05:29:01 PM PDT 24
Peak memory 233796 kb
Host smart-4856ea98-b27a-4bc6-a85c-64149feeaccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687980409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.687980409
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3425183855
Short name T146
Test name
Test status
Simulation time 1039412863 ps
CPU time 6.93 seconds
Started Jul 13 05:28:52 PM PDT 24
Finished Jul 13 05:29:00 PM PDT 24
Peak memory 224108 kb
Host smart-94425eda-2054-4372-92b2-ab5985bf0472
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3425183855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3425183855
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1491437521
Short name T19
Test name
Test status
Simulation time 95695865 ps
CPU time 0.98 seconds
Started Jul 13 05:28:50 PM PDT 24
Finished Jul 13 05:28:51 PM PDT 24
Peak memory 207616 kb
Host smart-3e6e1c49-3af0-43d9-9714-0d52aa4bb436
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491437521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1491437521
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3140337448
Short name T964
Test name
Test status
Simulation time 2515812624 ps
CPU time 13.77 seconds
Started Jul 13 05:28:41 PM PDT 24
Finished Jul 13 05:28:55 PM PDT 24
Peak memory 220624 kb
Host smart-efcf5fd8-2793-4627-9b4d-f985b3852a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140337448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3140337448
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3007034238
Short name T316
Test name
Test status
Simulation time 2713907650 ps
CPU time 6.09 seconds
Started Jul 13 05:28:42 PM PDT 24
Finished Jul 13 05:28:48 PM PDT 24
Peak memory 217396 kb
Host smart-992175f0-ec47-4d7f-aef1-e43303b19537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007034238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3007034238
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1401879455
Short name T399
Test name
Test status
Simulation time 147711250 ps
CPU time 1.07 seconds
Started Jul 13 05:28:41 PM PDT 24
Finished Jul 13 05:28:43 PM PDT 24
Peak memory 208048 kb
Host smart-bcf6b81f-b323-410c-993f-6cf8ef607867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401879455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1401879455
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1547174383
Short name T73
Test name
Test status
Simulation time 328525146 ps
CPU time 1.04 seconds
Started Jul 13 05:28:41 PM PDT 24
Finished Jul 13 05:28:42 PM PDT 24
Peak memory 207960 kb
Host smart-47dd63fa-1874-496e-aa9d-94ab7e63e6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547174383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1547174383
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1826221318
Short name T193
Test name
Test status
Simulation time 1520346428 ps
CPU time 4.51 seconds
Started Jul 13 05:28:52 PM PDT 24
Finished Jul 13 05:28:57 PM PDT 24
Peak memory 233732 kb
Host smart-c84a3344-2804-423c-b0f4-1fef1e63d422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826221318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1826221318
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2734501373
Short name T1025
Test name
Test status
Simulation time 12599688 ps
CPU time 0.75 seconds
Started Jul 13 05:29:14 PM PDT 24
Finished Jul 13 05:29:15 PM PDT 24
Peak memory 205772 kb
Host smart-43dab77e-cbda-4dd9-b779-8ca9c992b776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734501373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2734501373
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2325926676
Short name T919
Test name
Test status
Simulation time 386092928 ps
CPU time 3.15 seconds
Started Jul 13 05:29:08 PM PDT 24
Finished Jul 13 05:29:12 PM PDT 24
Peak memory 233708 kb
Host smart-9a929fd2-79eb-4720-bbcf-6c028f658d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325926676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2325926676
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.346851354
Short name T578
Test name
Test status
Simulation time 38649792 ps
CPU time 0.76 seconds
Started Jul 13 05:28:57 PM PDT 24
Finished Jul 13 05:28:58 PM PDT 24
Peak memory 207484 kb
Host smart-e423ee90-2682-4f06-b2e1-0981398f07b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346851354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.346851354
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3188137959
Short name T858
Test name
Test status
Simulation time 39113538197 ps
CPU time 138.27 seconds
Started Jul 13 05:29:14 PM PDT 24
Finished Jul 13 05:31:33 PM PDT 24
Peak memory 251272 kb
Host smart-ac719329-27e7-4ba5-a8d3-fc183030b0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188137959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3188137959
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2351791107
Short name T542
Test name
Test status
Simulation time 94610718712 ps
CPU time 275.9 seconds
Started Jul 13 05:29:13 PM PDT 24
Finished Jul 13 05:33:50 PM PDT 24
Peak memory 270404 kb
Host smart-427ddbcd-7652-489e-a432-3e07ae36eb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351791107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2351791107
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.215753563
Short name T144
Test name
Test status
Simulation time 44035874398 ps
CPU time 188.95 seconds
Started Jul 13 05:29:13 PM PDT 24
Finished Jul 13 05:32:22 PM PDT 24
Peak memory 258388 kb
Host smart-34684dab-7393-4331-83a6-407d5457c61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215753563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.215753563
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.273147381
Short name T531
Test name
Test status
Simulation time 668271610 ps
CPU time 6.04 seconds
Started Jul 13 05:29:03 PM PDT 24
Finished Jul 13 05:29:10 PM PDT 24
Peak memory 233760 kb
Host smart-7afda721-87c4-42f4-b479-11281a6323e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273147381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.273147381
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1914121787
Short name T177
Test name
Test status
Simulation time 17051346409 ps
CPU time 114.68 seconds
Started Jul 13 05:29:03 PM PDT 24
Finished Jul 13 05:30:58 PM PDT 24
Peak memory 255476 kb
Host smart-2aec7606-1f9a-4755-ae10-cc0edd4e6be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914121787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1914121787
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1220805369
Short name T599
Test name
Test status
Simulation time 8134224205 ps
CPU time 38 seconds
Started Jul 13 05:29:03 PM PDT 24
Finished Jul 13 05:29:42 PM PDT 24
Peak memory 233940 kb
Host smart-4ce925e2-4e0d-4bf5-8674-329a658251c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220805369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1220805369
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.338838759
Short name T458
Test name
Test status
Simulation time 4935868492 ps
CPU time 9.93 seconds
Started Jul 13 05:29:04 PM PDT 24
Finished Jul 13 05:29:14 PM PDT 24
Peak memory 233928 kb
Host smart-df59be2d-c833-4741-b45e-284744519250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338838759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.338838759
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2647236138
Short name T423
Test name
Test status
Simulation time 12541170058 ps
CPU time 25.81 seconds
Started Jul 13 05:29:04 PM PDT 24
Finished Jul 13 05:29:30 PM PDT 24
Peak memory 233832 kb
Host smart-b357a30f-1798-4665-ba3b-c59bc77a65ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647236138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2647236138
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3731614768
Short name T481
Test name
Test status
Simulation time 710746098 ps
CPU time 4.43 seconds
Started Jul 13 05:29:03 PM PDT 24
Finished Jul 13 05:29:07 PM PDT 24
Peak memory 220276 kb
Host smart-a6359369-cae6-4fd8-a63a-ee83b7ad9c15
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3731614768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3731614768
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.837847073
Short name T738
Test name
Test status
Simulation time 31057326930 ps
CPU time 285.46 seconds
Started Jul 13 05:29:13 PM PDT 24
Finished Jul 13 05:33:59 PM PDT 24
Peak memory 266500 kb
Host smart-7da60637-a561-4de1-b0b5-eb9f5005c33e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837847073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.837847073
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2701720087
Short name T285
Test name
Test status
Simulation time 1309568606 ps
CPU time 17.82 seconds
Started Jul 13 05:29:09 PM PDT 24
Finished Jul 13 05:29:27 PM PDT 24
Peak memory 217556 kb
Host smart-802f4d32-1b0b-458b-859b-cfeb46eaf7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701720087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2701720087
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.675546178
Short name T1008
Test name
Test status
Simulation time 9519468976 ps
CPU time 11.62 seconds
Started Jul 13 05:28:52 PM PDT 24
Finished Jul 13 05:29:04 PM PDT 24
Peak memory 217256 kb
Host smart-75e1466c-366d-417d-b5aa-8d527d754c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675546178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.675546178
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.702823191
Short name T995
Test name
Test status
Simulation time 172697843 ps
CPU time 1.72 seconds
Started Jul 13 05:29:08 PM PDT 24
Finished Jul 13 05:29:10 PM PDT 24
Peak memory 217344 kb
Host smart-28fc707d-c411-4772-a8ee-d445afc4ad32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702823191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.702823191
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2891381079
Short name T701
Test name
Test status
Simulation time 59484756 ps
CPU time 0.73 seconds
Started Jul 13 05:29:03 PM PDT 24
Finished Jul 13 05:29:04 PM PDT 24
Peak memory 206936 kb
Host smart-28bf256f-cf77-4915-8991-8fff701871ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891381079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2891381079
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.799253857
Short name T849
Test name
Test status
Simulation time 5242924359 ps
CPU time 10.16 seconds
Started Jul 13 05:29:02 PM PDT 24
Finished Jul 13 05:29:13 PM PDT 24
Peak memory 225708 kb
Host smart-316b8b58-9a2d-49d5-af57-13b089873390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799253857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.799253857
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3718416334
Short name T331
Test name
Test status
Simulation time 18905150 ps
CPU time 0.71 seconds
Started Jul 13 05:29:23 PM PDT 24
Finished Jul 13 05:29:25 PM PDT 24
Peak memory 205776 kb
Host smart-a6624812-87b9-4e46-93af-3c0fbc8bcfd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718416334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3718416334
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2581341205
Short name T180
Test name
Test status
Simulation time 867955094 ps
CPU time 11.52 seconds
Started Jul 13 05:29:15 PM PDT 24
Finished Jul 13 05:29:27 PM PDT 24
Peak memory 225508 kb
Host smart-5fd82e40-5677-49f9-b6cb-d2b6db498902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581341205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2581341205
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1968941011
Short name T735
Test name
Test status
Simulation time 13038030 ps
CPU time 0.76 seconds
Started Jul 13 05:29:15 PM PDT 24
Finished Jul 13 05:29:17 PM PDT 24
Peak memory 206460 kb
Host smart-22a46551-45ee-46aa-977f-5c76eb29ff7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968941011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1968941011
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2026083898
Short name T700
Test name
Test status
Simulation time 9222821530 ps
CPU time 17.88 seconds
Started Jul 13 05:29:25 PM PDT 24
Finished Jul 13 05:29:44 PM PDT 24
Peak memory 237116 kb
Host smart-1f6a0a59-f83d-42b2-beb6-0f1fc2952f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026083898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2026083898
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1200287008
Short name T558
Test name
Test status
Simulation time 2872974090 ps
CPU time 44.09 seconds
Started Jul 13 05:29:25 PM PDT 24
Finished Jul 13 05:30:10 PM PDT 24
Peak memory 253136 kb
Host smart-bd959a7f-f4aa-4330-8a95-a546aacd34dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200287008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1200287008
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.45224373
Short name T252
Test name
Test status
Simulation time 266105090267 ps
CPU time 655.05 seconds
Started Jul 13 05:29:23 PM PDT 24
Finished Jul 13 05:40:18 PM PDT 24
Peak memory 265140 kb
Host smart-1664ab35-30c4-4a72-a82a-d1459ee839f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45224373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.45224373
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.395211722
Short name T688
Test name
Test status
Simulation time 17888658786 ps
CPU time 61.32 seconds
Started Jul 13 05:29:14 PM PDT 24
Finished Jul 13 05:30:15 PM PDT 24
Peak memory 241572 kb
Host smart-307b0c29-0fbc-4471-8899-365fd81e6ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395211722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.395211722
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.271728235
Short name T971
Test name
Test status
Simulation time 375974190490 ps
CPU time 330.53 seconds
Started Jul 13 05:29:16 PM PDT 24
Finished Jul 13 05:34:47 PM PDT 24
Peak memory 255204 kb
Host smart-c589c43e-fca4-42a9-8e6e-a0901207f3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271728235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.271728235
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3906896629
Short name T218
Test name
Test status
Simulation time 498613743 ps
CPU time 6 seconds
Started Jul 13 05:29:14 PM PDT 24
Finished Jul 13 05:29:21 PM PDT 24
Peak memory 225504 kb
Host smart-084da547-7c8c-4d8e-9a13-78a7d14b0cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906896629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3906896629
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.393339432
Short name T89
Test name
Test status
Simulation time 426687288 ps
CPU time 9.89 seconds
Started Jul 13 05:29:13 PM PDT 24
Finished Jul 13 05:29:23 PM PDT 24
Peak memory 233732 kb
Host smart-2465f8fe-c188-4fe7-9805-d2a9ae29560e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393339432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.393339432
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1323208166
Short name T980
Test name
Test status
Simulation time 14257054 ps
CPU time 1.02 seconds
Started Jul 13 05:29:17 PM PDT 24
Finished Jul 13 05:29:18 PM PDT 24
Peak memory 219180 kb
Host smart-55d129a3-2faf-4487-98f4-5d27ee87c352
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323208166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1323208166
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1058506486
Short name T53
Test name
Test status
Simulation time 10565150520 ps
CPU time 8.16 seconds
Started Jul 13 05:29:13 PM PDT 24
Finished Jul 13 05:29:22 PM PDT 24
Peak memory 225612 kb
Host smart-47eab2f1-222c-4e51-a79a-e0f8c18846d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058506486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1058506486
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.4066038202
Short name T502
Test name
Test status
Simulation time 1467723149 ps
CPU time 5.16 seconds
Started Jul 13 05:29:14 PM PDT 24
Finished Jul 13 05:29:19 PM PDT 24
Peak memory 234760 kb
Host smart-0ba56ac6-4157-4f94-8681-1437c32baa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066038202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.4066038202
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.615187054
Short name T341
Test name
Test status
Simulation time 794761506 ps
CPU time 5.9 seconds
Started Jul 13 05:29:14 PM PDT 24
Finished Jul 13 05:29:21 PM PDT 24
Peak memory 224044 kb
Host smart-f3ccb806-2791-4806-a2e5-6e228d5e7f97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=615187054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.615187054
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3477188741
Short name T469
Test name
Test status
Simulation time 108005691 ps
CPU time 0.86 seconds
Started Jul 13 05:29:24 PM PDT 24
Finished Jul 13 05:29:25 PM PDT 24
Peak memory 207492 kb
Host smart-3b4301b2-69ce-48b5-9fc9-0b368ae6b4e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477188741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3477188741
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1992379103
Short name T710
Test name
Test status
Simulation time 2883186529 ps
CPU time 29.31 seconds
Started Jul 13 05:29:15 PM PDT 24
Finished Jul 13 05:29:45 PM PDT 24
Peak memory 217480 kb
Host smart-65fee6d0-fd71-4758-959f-90c02d5a92a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992379103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1992379103
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2761388636
Short name T335
Test name
Test status
Simulation time 2182503360 ps
CPU time 7.39 seconds
Started Jul 13 05:29:14 PM PDT 24
Finished Jul 13 05:29:22 PM PDT 24
Peak memory 217408 kb
Host smart-00cc6ee9-2620-4080-aba2-a539dba3b6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761388636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2761388636
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3534748293
Short name T871
Test name
Test status
Simulation time 249442651 ps
CPU time 5.25 seconds
Started Jul 13 05:29:14 PM PDT 24
Finished Jul 13 05:29:20 PM PDT 24
Peak memory 217236 kb
Host smart-75bcbe36-3b59-4c8b-bb3c-14565f6df38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534748293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3534748293
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3654684944
Short name T1003
Test name
Test status
Simulation time 41792117 ps
CPU time 0.78 seconds
Started Jul 13 05:29:13 PM PDT 24
Finished Jul 13 05:29:15 PM PDT 24
Peak memory 206972 kb
Host smart-7fed6686-fc3d-4a51-9bba-e3602ed54430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654684944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3654684944
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3881785162
Short name T763
Test name
Test status
Simulation time 2189974007 ps
CPU time 5.75 seconds
Started Jul 13 05:29:14 PM PDT 24
Finished Jul 13 05:29:20 PM PDT 24
Peak memory 236536 kb
Host smart-463c4951-b0a3-4082-b6c0-1751f4d1180f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881785162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3881785162
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3052724409
Short name T614
Test name
Test status
Simulation time 15105919 ps
CPU time 0.75 seconds
Started Jul 13 05:29:45 PM PDT 24
Finished Jul 13 05:29:46 PM PDT 24
Peak memory 205736 kb
Host smart-a174928f-1496-4622-be85-aa63dae702a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052724409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3052724409
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.307496342
Short name T751
Test name
Test status
Simulation time 91443814 ps
CPU time 3.53 seconds
Started Jul 13 05:29:34 PM PDT 24
Finished Jul 13 05:29:38 PM PDT 24
Peak memory 225584 kb
Host smart-f00cc5d2-6d80-44b2-84ff-cd256c3f8408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307496342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.307496342
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.778065798
Short name T76
Test name
Test status
Simulation time 18702954 ps
CPU time 0.82 seconds
Started Jul 13 05:29:23 PM PDT 24
Finished Jul 13 05:29:24 PM PDT 24
Peak memory 207488 kb
Host smart-ba05a133-c669-4217-8141-ff4ddfb0dcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778065798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.778065798
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3482428970
Short name T234
Test name
Test status
Simulation time 7851594588 ps
CPU time 108.89 seconds
Started Jul 13 05:29:33 PM PDT 24
Finished Jul 13 05:31:23 PM PDT 24
Peak memory 250404 kb
Host smart-ce2b9428-8402-48b8-a39e-cc22b7dbe2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482428970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3482428970
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.4104315235
Short name T869
Test name
Test status
Simulation time 175823858287 ps
CPU time 462.17 seconds
Started Jul 13 05:29:33 PM PDT 24
Finished Jul 13 05:37:16 PM PDT 24
Peak memory 255368 kb
Host smart-47e594ec-f11a-47f7-be5f-3a1ce03d2c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104315235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.4104315235
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2167069842
Short name T291
Test name
Test status
Simulation time 200528841 ps
CPU time 3.47 seconds
Started Jul 13 05:29:34 PM PDT 24
Finished Jul 13 05:29:38 PM PDT 24
Peak memory 233740 kb
Host smart-78737525-a021-4ac6-93b5-f48bfb7b985b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167069842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2167069842
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3802816647
Short name T956
Test name
Test status
Simulation time 1845434622 ps
CPU time 20.86 seconds
Started Jul 13 05:29:35 PM PDT 24
Finished Jul 13 05:29:56 PM PDT 24
Peak memory 255256 kb
Host smart-3aa4f016-5b22-49db-a4a1-752e6bdf4a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802816647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3802816647
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2393699004
Short name T682
Test name
Test status
Simulation time 446740522 ps
CPU time 2.98 seconds
Started Jul 13 05:29:33 PM PDT 24
Finished Jul 13 05:29:37 PM PDT 24
Peak memory 233744 kb
Host smart-6a258f91-b6c7-459a-9a9e-9a6f05500fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393699004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2393699004
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1026182777
Short name T741
Test name
Test status
Simulation time 252262982 ps
CPU time 6.21 seconds
Started Jul 13 05:29:36 PM PDT 24
Finished Jul 13 05:29:42 PM PDT 24
Peak memory 233780 kb
Host smart-5b66ccea-f8e0-4373-a223-2d5e2d195d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026182777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1026182777
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1742122103
Short name T352
Test name
Test status
Simulation time 29743171 ps
CPU time 1.1 seconds
Started Jul 13 05:29:23 PM PDT 24
Finished Jul 13 05:29:25 PM PDT 24
Peak memory 218936 kb
Host smart-40c37358-4a64-49ae-98b6-a62b95f29909
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742122103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1742122103
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.540215779
Short name T440
Test name
Test status
Simulation time 2077283045 ps
CPU time 10.41 seconds
Started Jul 13 05:29:23 PM PDT 24
Finished Jul 13 05:29:34 PM PDT 24
Peak memory 233688 kb
Host smart-7ac8c113-670b-40ac-8bf4-d59db9c47453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540215779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.540215779
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3769350336
Short name T216
Test name
Test status
Simulation time 429550193 ps
CPU time 5.67 seconds
Started Jul 13 05:29:24 PM PDT 24
Finished Jul 13 05:29:30 PM PDT 24
Peak memory 233624 kb
Host smart-034a6b7f-c1ad-4f72-b541-63125229b673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769350336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3769350336
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.312061908
Short name T49
Test name
Test status
Simulation time 138088102 ps
CPU time 4.1 seconds
Started Jul 13 05:29:36 PM PDT 24
Finished Jul 13 05:29:41 PM PDT 24
Peak memory 224108 kb
Host smart-3bf09ed6-f0bf-4457-a4be-ea3075962dc4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=312061908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.312061908
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1049941996
Short name T69
Test name
Test status
Simulation time 36750460717 ps
CPU time 367.88 seconds
Started Jul 13 05:29:36 PM PDT 24
Finished Jul 13 05:35:44 PM PDT 24
Peak memory 272524 kb
Host smart-5deedb2e-4425-4421-a4b3-1b158414f768
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049941996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1049941996
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1902351769
Short name T879
Test name
Test status
Simulation time 5848280144 ps
CPU time 22.51 seconds
Started Jul 13 05:29:24 PM PDT 24
Finished Jul 13 05:29:47 PM PDT 24
Peak memory 217440 kb
Host smart-9856c8bb-4fef-428a-865a-db399ca8d8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902351769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1902351769
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1756130887
Short name T837
Test name
Test status
Simulation time 137010679 ps
CPU time 0.93 seconds
Started Jul 13 05:29:25 PM PDT 24
Finished Jul 13 05:29:26 PM PDT 24
Peak memory 207992 kb
Host smart-eb0109d4-6053-430a-bc01-c93e320d5e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756130887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1756130887
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1382747430
Short name T795
Test name
Test status
Simulation time 147418028 ps
CPU time 0.96 seconds
Started Jul 13 05:29:25 PM PDT 24
Finished Jul 13 05:29:27 PM PDT 24
Peak memory 207468 kb
Host smart-7fdaa154-d1b4-4bd3-8ad7-e51d6d3833e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382747430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1382747430
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.628384541
Short name T178
Test name
Test status
Simulation time 1568866718 ps
CPU time 7.13 seconds
Started Jul 13 05:29:36 PM PDT 24
Finished Jul 13 05:29:44 PM PDT 24
Peak memory 225472 kb
Host smart-bd4c1db9-92de-470f-b25f-5be76f9b3618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628384541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.628384541
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3186956433
Short name T756
Test name
Test status
Simulation time 99208748 ps
CPU time 2.28 seconds
Started Jul 13 05:29:45 PM PDT 24
Finished Jul 13 05:29:48 PM PDT 24
Peak memory 225480 kb
Host smart-f2a20e2b-065e-4d9d-a9ec-76a17a748612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186956433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3186956433
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3047355080
Short name T861
Test name
Test status
Simulation time 52637849 ps
CPU time 0.79 seconds
Started Jul 13 05:29:45 PM PDT 24
Finished Jul 13 05:29:46 PM PDT 24
Peak memory 207520 kb
Host smart-26a68e76-d33d-4814-8352-0fc6890de679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047355080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3047355080
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.4017658281
Short name T269
Test name
Test status
Simulation time 127108634112 ps
CPU time 212.57 seconds
Started Jul 13 05:30:01 PM PDT 24
Finished Jul 13 05:33:34 PM PDT 24
Peak memory 255168 kb
Host smart-0fb360f6-83ec-4f2b-90ac-226b6a027c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017658281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.4017658281
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1461974821
Short name T206
Test name
Test status
Simulation time 11039314169 ps
CPU time 77.64 seconds
Started Jul 13 05:29:56 PM PDT 24
Finished Jul 13 05:31:14 PM PDT 24
Peak memory 251700 kb
Host smart-0a57da08-365b-433e-9f8c-5d1f6755576d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461974821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1461974821
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1511206531
Short name T277
Test name
Test status
Simulation time 630066819 ps
CPU time 8.46 seconds
Started Jul 13 05:29:47 PM PDT 24
Finished Jul 13 05:29:56 PM PDT 24
Peak memory 225540 kb
Host smart-03ae6e64-cde9-4658-9d7f-696ed700ea61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511206531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1511206531
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.520012252
Short name T907
Test name
Test status
Simulation time 54071243507 ps
CPU time 51.13 seconds
Started Jul 13 05:29:45 PM PDT 24
Finished Jul 13 05:30:37 PM PDT 24
Peak memory 233004 kb
Host smart-9d6f9d93-7324-49b9-b7e0-92b0a4781db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520012252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.520012252
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3935979129
Short name T462
Test name
Test status
Simulation time 29936209 ps
CPU time 2.1 seconds
Started Jul 13 05:29:46 PM PDT 24
Finished Jul 13 05:29:49 PM PDT 24
Peak memory 224264 kb
Host smart-30a92597-1595-4bc4-9ea8-0e46db24a19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935979129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3935979129
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1693179183
Short name T587
Test name
Test status
Simulation time 2432735601 ps
CPU time 4.8 seconds
Started Jul 13 05:29:46 PM PDT 24
Finished Jul 13 05:29:51 PM PDT 24
Peak memory 225576 kb
Host smart-2e4695b5-b6ee-417d-8227-8a627aac4a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693179183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1693179183
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3549501332
Short name T921
Test name
Test status
Simulation time 28083769 ps
CPU time 1.04 seconds
Started Jul 13 05:29:46 PM PDT 24
Finished Jul 13 05:29:47 PM PDT 24
Peak memory 218908 kb
Host smart-51904c34-f67a-4dcf-bdae-96dc0f0aa427
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549501332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3549501332
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1947451927
Short name T451
Test name
Test status
Simulation time 662291842 ps
CPU time 3 seconds
Started Jul 13 05:29:46 PM PDT 24
Finished Jul 13 05:29:50 PM PDT 24
Peak memory 233692 kb
Host smart-efa889f6-8f5f-421b-ac97-b6e0b4b322e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947451927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1947451927
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3002380360
Short name T219
Test name
Test status
Simulation time 1823118016 ps
CPU time 4.6 seconds
Started Jul 13 05:29:44 PM PDT 24
Finished Jul 13 05:29:49 PM PDT 24
Peak memory 233804 kb
Host smart-2ea2f439-92fc-438e-b8f4-ceccb902cade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002380360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3002380360
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1347248047
Short name T890
Test name
Test status
Simulation time 319683961 ps
CPU time 3.64 seconds
Started Jul 13 05:29:47 PM PDT 24
Finished Jul 13 05:29:51 PM PDT 24
Peak memory 224048 kb
Host smart-9063babb-bd87-401e-9fe7-2dc2de771835
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1347248047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1347248047
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.800183971
Short name T872
Test name
Test status
Simulation time 2497507437 ps
CPU time 8.27 seconds
Started Jul 13 05:29:47 PM PDT 24
Finished Jul 13 05:29:56 PM PDT 24
Peak memory 217504 kb
Host smart-4ae496ef-213e-4f60-904d-f202db279080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800183971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.800183971
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.4051132351
Short name T132
Test name
Test status
Simulation time 25415774 ps
CPU time 0.7 seconds
Started Jul 13 05:29:45 PM PDT 24
Finished Jul 13 05:29:46 PM PDT 24
Peak memory 206564 kb
Host smart-4ed0ca24-8421-4afe-b1e7-b995fb7df463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051132351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.4051132351
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2833294062
Short name T840
Test name
Test status
Simulation time 96627412 ps
CPU time 0.92 seconds
Started Jul 13 05:29:44 PM PDT 24
Finished Jul 13 05:29:45 PM PDT 24
Peak memory 207116 kb
Host smart-21d82e2b-a9b8-4a4b-8fb5-7ecba7835293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833294062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2833294062
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2812187427
Short name T581
Test name
Test status
Simulation time 167266003 ps
CPU time 3.25 seconds
Started Jul 13 05:29:44 PM PDT 24
Finished Jul 13 05:29:47 PM PDT 24
Peak memory 225576 kb
Host smart-8f7f5348-aa9b-4fcc-94a5-c2a173bd3b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812187427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2812187427
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1952615338
Short name T678
Test name
Test status
Simulation time 61961659 ps
CPU time 0.74 seconds
Started Jul 13 05:30:13 PM PDT 24
Finished Jul 13 05:30:14 PM PDT 24
Peak memory 206120 kb
Host smart-cb83c063-3a68-466c-855f-de5781347174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952615338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1952615338
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2046670921
Short name T664
Test name
Test status
Simulation time 879162637 ps
CPU time 3.24 seconds
Started Jul 13 05:30:12 PM PDT 24
Finished Jul 13 05:30:16 PM PDT 24
Peak memory 233760 kb
Host smart-08adcbdc-cd32-484c-8972-23ec0e5edc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046670921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2046670921
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3025869718
Short name T702
Test name
Test status
Simulation time 28970086 ps
CPU time 0.84 seconds
Started Jul 13 05:29:56 PM PDT 24
Finished Jul 13 05:29:58 PM PDT 24
Peak memory 207812 kb
Host smart-0406cf17-ce5c-4b97-b22e-02dcee7cb258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025869718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3025869718
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3904119415
Short name T862
Test name
Test status
Simulation time 3470146469 ps
CPU time 63.6 seconds
Started Jul 13 05:30:12 PM PDT 24
Finished Jul 13 05:31:16 PM PDT 24
Peak memory 257552 kb
Host smart-667b965b-7150-41e5-9bdd-568aa862ce7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904119415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3904119415
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4278525008
Short name T209
Test name
Test status
Simulation time 2674523653 ps
CPU time 66.61 seconds
Started Jul 13 05:30:12 PM PDT 24
Finished Jul 13 05:31:20 PM PDT 24
Peak memory 242000 kb
Host smart-d92dc465-5980-4233-90ca-ecef82e28a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278525008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4278525008
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.556743787
Short name T394
Test name
Test status
Simulation time 2292629967 ps
CPU time 48.6 seconds
Started Jul 13 05:30:12 PM PDT 24
Finished Jul 13 05:31:01 PM PDT 24
Peak memory 253896 kb
Host smart-95a53087-e7b5-4155-a13a-b65d589e794e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556743787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.556743787
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1029718682
Short name T339
Test name
Test status
Simulation time 12534109733 ps
CPU time 37.28 seconds
Started Jul 13 05:30:11 PM PDT 24
Finished Jul 13 05:30:49 PM PDT 24
Peak memory 225684 kb
Host smart-6a568d3d-cb28-450d-8aa3-d7c6834c8f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029718682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1029718682
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2731010946
Short name T970
Test name
Test status
Simulation time 941429168 ps
CPU time 13.17 seconds
Started Jul 13 05:30:11 PM PDT 24
Finished Jul 13 05:30:25 PM PDT 24
Peak memory 241960 kb
Host smart-973655c5-e956-431e-8901-7333e7749db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731010946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2731010946
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2408145546
Short name T857
Test name
Test status
Simulation time 216996125 ps
CPU time 2.69 seconds
Started Jul 13 05:29:56 PM PDT 24
Finished Jul 13 05:29:59 PM PDT 24
Peak memory 225548 kb
Host smart-3bed3445-5bc8-4340-bdea-6aa830c97a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408145546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2408145546
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1682044046
Short name T228
Test name
Test status
Simulation time 1015180927 ps
CPU time 7.09 seconds
Started Jul 13 05:30:12 PM PDT 24
Finished Jul 13 05:30:20 PM PDT 24
Peak memory 233680 kb
Host smart-ed9e43ed-df41-4939-98b8-ed8db06e69a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682044046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1682044046
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2912731396
Short name T379
Test name
Test status
Simulation time 32690438 ps
CPU time 1.03 seconds
Started Jul 13 05:29:56 PM PDT 24
Finished Jul 13 05:29:57 PM PDT 24
Peak memory 217676 kb
Host smart-258d319c-3d70-4dc6-8aeb-ea1bad35ecff
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912731396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2912731396
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3358248973
Short name T246
Test name
Test status
Simulation time 371153419 ps
CPU time 2.79 seconds
Started Jul 13 05:29:57 PM PDT 24
Finished Jul 13 05:30:01 PM PDT 24
Peak memory 233696 kb
Host smart-0cb1886c-9ea2-46d3-891f-170c28c53ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358248973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3358248973
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.585870171
Short name T224
Test name
Test status
Simulation time 776128057 ps
CPU time 5.58 seconds
Started Jul 13 05:29:58 PM PDT 24
Finished Jul 13 05:30:04 PM PDT 24
Peak memory 233768 kb
Host smart-8f6f8894-a9a2-447a-bd81-5acf376ddd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585870171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.585870171
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.510614618
Short name T687
Test name
Test status
Simulation time 5121790070 ps
CPU time 12.96 seconds
Started Jul 13 05:30:13 PM PDT 24
Finished Jul 13 05:30:27 PM PDT 24
Peak memory 220392 kb
Host smart-69bf4fa6-683e-41fd-a38a-3e33de6d4a80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=510614618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.510614618
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.4220837587
Short name T384
Test name
Test status
Simulation time 520322692 ps
CPU time 3.39 seconds
Started Jul 13 05:29:57 PM PDT 24
Finished Jul 13 05:30:01 PM PDT 24
Peak memory 217404 kb
Host smart-de2fe531-0423-451a-8550-340aeb03582d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220837587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.4220837587
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.528523842
Short name T844
Test name
Test status
Simulation time 3495560996 ps
CPU time 5.67 seconds
Started Jul 13 05:29:57 PM PDT 24
Finished Jul 13 05:30:03 PM PDT 24
Peak memory 217480 kb
Host smart-5b57268a-a187-42a0-8bf8-b7fa3943c54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528523842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.528523842
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1322078412
Short name T1026
Test name
Test status
Simulation time 16209272 ps
CPU time 0.7 seconds
Started Jul 13 05:30:00 PM PDT 24
Finished Jul 13 05:30:02 PM PDT 24
Peak memory 206752 kb
Host smart-b4363e05-17df-40fb-bb85-119e8d3eb383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322078412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1322078412
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1872168134
Short name T753
Test name
Test status
Simulation time 47919265 ps
CPU time 0.86 seconds
Started Jul 13 05:29:55 PM PDT 24
Finished Jul 13 05:29:56 PM PDT 24
Peak memory 206964 kb
Host smart-85577e16-82a5-41a8-ae20-9497eba0383c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872168134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1872168134
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.379728908
Short name T438
Test name
Test status
Simulation time 3038114476 ps
CPU time 12.08 seconds
Started Jul 13 05:30:12 PM PDT 24
Finished Jul 13 05:30:24 PM PDT 24
Peak memory 225672 kb
Host smart-02fb5f6a-d063-4563-8d7d-5b969f0759b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379728908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.379728908
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1640558498
Short name T62
Test name
Test status
Simulation time 90236683 ps
CPU time 0.72 seconds
Started Jul 13 05:30:23 PM PDT 24
Finished Jul 13 05:30:25 PM PDT 24
Peak memory 205820 kb
Host smart-69d290bd-1ca8-4bc4-8d6a-0c73f8bf3a60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640558498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1640558498
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1292208229
Short name T460
Test name
Test status
Simulation time 231444510 ps
CPU time 3.47 seconds
Started Jul 13 05:30:25 PM PDT 24
Finished Jul 13 05:30:29 PM PDT 24
Peak memory 225500 kb
Host smart-bb3d413e-edc6-4bdb-9532-6eb2564ee73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292208229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1292208229
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2225427845
Short name T612
Test name
Test status
Simulation time 28360983 ps
CPU time 0.79 seconds
Started Jul 13 05:30:11 PM PDT 24
Finished Jul 13 05:30:12 PM PDT 24
Peak memory 207512 kb
Host smart-2ef34a7a-1cd3-46de-873a-ddae75dfa086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225427845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2225427845
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2586259213
Short name T966
Test name
Test status
Simulation time 6053282714 ps
CPU time 81.38 seconds
Started Jul 13 05:30:24 PM PDT 24
Finished Jul 13 05:31:46 PM PDT 24
Peak memory 258224 kb
Host smart-3c874d2d-7b04-4475-94b5-fbe1d8577190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586259213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2586259213
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.4136263796
Short name T770
Test name
Test status
Simulation time 7810283059 ps
CPU time 21.78 seconds
Started Jul 13 05:30:23 PM PDT 24
Finished Jul 13 05:30:45 PM PDT 24
Peak memory 225716 kb
Host smart-4ada5206-985c-4b01-a890-518164e31760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136263796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.4136263796
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3505516214
Short name T221
Test name
Test status
Simulation time 272734100391 ps
CPU time 559.6 seconds
Started Jul 13 05:30:25 PM PDT 24
Finished Jul 13 05:39:45 PM PDT 24
Peak memory 265668 kb
Host smart-331bd416-bc45-49a4-b95f-5a5c4ad73d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505516214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3505516214
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2400148834
Short name T516
Test name
Test status
Simulation time 93314081 ps
CPU time 2.93 seconds
Started Jul 13 05:30:24 PM PDT 24
Finished Jul 13 05:30:28 PM PDT 24
Peak memory 225548 kb
Host smart-7a9fe8ea-148d-4f57-8eed-9d1101e2b60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400148834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2400148834
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.696843032
Short name T487
Test name
Test status
Simulation time 8808700760 ps
CPU time 79.04 seconds
Started Jul 13 05:30:24 PM PDT 24
Finished Jul 13 05:31:44 PM PDT 24
Peak memory 258368 kb
Host smart-d8f21b70-7558-44f5-be05-86b25e1b7cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696843032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.696843032
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2493107343
Short name T50
Test name
Test status
Simulation time 1679069300 ps
CPU time 8.32 seconds
Started Jul 13 05:30:12 PM PDT 24
Finished Jul 13 05:30:21 PM PDT 24
Peak memory 233584 kb
Host smart-44f158e5-0ed5-4b81-be0a-0290da926495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493107343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2493107343
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.4189892850
Short name T468
Test name
Test status
Simulation time 16175941730 ps
CPU time 27.6 seconds
Started Jul 13 05:30:11 PM PDT 24
Finished Jul 13 05:30:40 PM PDT 24
Peak memory 225660 kb
Host smart-665ec982-616b-487f-a69a-7bffa69ad44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189892850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.4189892850
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.909363321
Short name T445
Test name
Test status
Simulation time 42160190 ps
CPU time 1.07 seconds
Started Jul 13 05:30:11 PM PDT 24
Finished Jul 13 05:30:13 PM PDT 24
Peak memory 217640 kb
Host smart-e3b8dea3-a4f5-46a0-b6ab-26f57480a8c0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909363321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.909363321
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3750104547
Short name T812
Test name
Test status
Simulation time 3951875124 ps
CPU time 14.71 seconds
Started Jul 13 05:30:12 PM PDT 24
Finished Jul 13 05:30:27 PM PDT 24
Peak memory 233836 kb
Host smart-21dd1754-e2f3-4a48-b6d2-55745774bb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750104547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3750104547
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2962597928
Short name T75
Test name
Test status
Simulation time 741167135 ps
CPU time 2.95 seconds
Started Jul 13 05:30:13 PM PDT 24
Finished Jul 13 05:30:17 PM PDT 24
Peak memory 225528 kb
Host smart-ad766708-67cd-411e-8e1e-15a307f84579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962597928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2962597928
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2101125017
Short name T525
Test name
Test status
Simulation time 149968005 ps
CPU time 3.9 seconds
Started Jul 13 05:30:23 PM PDT 24
Finished Jul 13 05:30:27 PM PDT 24
Peak memory 221356 kb
Host smart-e1638975-c57c-4f82-9004-82a1cc0621ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2101125017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2101125017
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4054507038
Short name T993
Test name
Test status
Simulation time 1666782645 ps
CPU time 12.36 seconds
Started Jul 13 05:30:11 PM PDT 24
Finished Jul 13 05:30:23 PM PDT 24
Peak memory 217320 kb
Host smart-ef7f2f1d-643f-4faa-8a6a-eddfea839b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054507038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4054507038
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.172795879
Short name T708
Test name
Test status
Simulation time 571114000 ps
CPU time 3.81 seconds
Started Jul 13 05:30:12 PM PDT 24
Finished Jul 13 05:30:16 PM PDT 24
Peak memory 217312 kb
Host smart-d44cfee4-55aa-4a2e-a0b8-b236e7148698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172795879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.172795879
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1504500392
Short name T609
Test name
Test status
Simulation time 24144972 ps
CPU time 0.89 seconds
Started Jul 13 05:30:11 PM PDT 24
Finished Jul 13 05:30:13 PM PDT 24
Peak memory 207672 kb
Host smart-937a191c-8542-41c4-af44-ec2cf43247c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504500392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1504500392
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4249702155
Short name T798
Test name
Test status
Simulation time 85601778 ps
CPU time 0.78 seconds
Started Jul 13 05:30:12 PM PDT 24
Finished Jul 13 05:30:14 PM PDT 24
Peak memory 206872 kb
Host smart-4f80b437-e117-4c52-b2e0-8f36bc897e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249702155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4249702155
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1203486291
Short name T680
Test name
Test status
Simulation time 203168472 ps
CPU time 2.21 seconds
Started Jul 13 05:30:13 PM PDT 24
Finished Jul 13 05:30:16 PM PDT 24
Peak memory 224836 kb
Host smart-c89a4bd0-26cd-4afc-aea4-5330fb158395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203486291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1203486291
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1487462171
Short name T500
Test name
Test status
Simulation time 22109540 ps
CPU time 0.74 seconds
Started Jul 13 05:30:37 PM PDT 24
Finished Jul 13 05:30:38 PM PDT 24
Peak memory 205800 kb
Host smart-6d7fd210-57c1-4baf-896f-05fda213905a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487462171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1487462171
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1166016223
Short name T1014
Test name
Test status
Simulation time 188420133 ps
CPU time 3.1 seconds
Started Jul 13 05:30:34 PM PDT 24
Finished Jul 13 05:30:37 PM PDT 24
Peak memory 225540 kb
Host smart-1837e537-a911-482e-b09d-4f3098edf301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166016223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1166016223
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3025495813
Short name T541
Test name
Test status
Simulation time 21990540 ps
CPU time 0.77 seconds
Started Jul 13 05:30:25 PM PDT 24
Finished Jul 13 05:30:26 PM PDT 24
Peak memory 206480 kb
Host smart-b39bae71-fecf-4b59-bc6b-6f785d7a1e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025495813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3025495813
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2065302212
Short name T778
Test name
Test status
Simulation time 1904510795 ps
CPU time 26.16 seconds
Started Jul 13 05:30:33 PM PDT 24
Finished Jul 13 05:31:00 PM PDT 24
Peak memory 237924 kb
Host smart-04c334a9-4d6e-49f0-9754-f0f05d753e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065302212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2065302212
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.4273323287
Short name T870
Test name
Test status
Simulation time 16580662435 ps
CPU time 47.71 seconds
Started Jul 13 05:30:34 PM PDT 24
Finished Jul 13 05:31:22 PM PDT 24
Peak memory 242204 kb
Host smart-f09986af-3df3-4373-a549-9fdc21ddcd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273323287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.4273323287
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1145680993
Short name T203
Test name
Test status
Simulation time 13372451761 ps
CPU time 66.41 seconds
Started Jul 13 05:30:34 PM PDT 24
Finished Jul 13 05:31:40 PM PDT 24
Peak memory 251284 kb
Host smart-1d1b1fa2-c6f5-4d84-8bb6-6331855f5a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145680993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1145680993
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2709503059
Short name T943
Test name
Test status
Simulation time 1541748941 ps
CPU time 23.45 seconds
Started Jul 13 05:30:34 PM PDT 24
Finished Jul 13 05:30:58 PM PDT 24
Peak memory 225492 kb
Host smart-068609c2-fedd-4b58-ba4e-dff56233bbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709503059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2709503059
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.645405481
Short name T207
Test name
Test status
Simulation time 3744828578 ps
CPU time 85.82 seconds
Started Jul 13 05:30:37 PM PDT 24
Finished Jul 13 05:32:03 PM PDT 24
Peak memory 264380 kb
Host smart-75c2af23-4cb1-44cb-8496-60f7ba4ce2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645405481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.645405481
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3768882935
Short name T1004
Test name
Test status
Simulation time 210309283 ps
CPU time 5.84 seconds
Started Jul 13 05:30:25 PM PDT 24
Finished Jul 13 05:30:32 PM PDT 24
Peak memory 233780 kb
Host smart-36657e1e-2103-44ab-a4b2-86bfee65f8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768882935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3768882935
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1811052798
Short name T910
Test name
Test status
Simulation time 3449313692 ps
CPU time 18.54 seconds
Started Jul 13 05:30:35 PM PDT 24
Finished Jul 13 05:30:54 PM PDT 24
Peak memory 233956 kb
Host smart-8dafc242-3abd-4464-a087-63a356a57d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811052798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1811052798
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3404438707
Short name T46
Test name
Test status
Simulation time 121823246 ps
CPU time 1.08 seconds
Started Jul 13 05:30:23 PM PDT 24
Finished Jul 13 05:30:25 PM PDT 24
Peak memory 217676 kb
Host smart-83ebd119-56a0-4c05-91c1-0c8b0d9a612c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404438707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3404438707
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.889161541
Short name T509
Test name
Test status
Simulation time 108567638 ps
CPU time 2.48 seconds
Started Jul 13 05:30:23 PM PDT 24
Finished Jul 13 05:30:26 PM PDT 24
Peak memory 224172 kb
Host smart-830e821e-237e-4edf-bbb4-671c12050ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889161541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.889161541
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3166137330
Short name T797
Test name
Test status
Simulation time 468624062 ps
CPU time 5.96 seconds
Started Jul 13 05:30:24 PM PDT 24
Finished Jul 13 05:30:30 PM PDT 24
Peak memory 233728 kb
Host smart-47675141-08fd-48e3-865f-ff996daa341f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166137330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3166137330
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.4277417427
Short name T145
Test name
Test status
Simulation time 5050312230 ps
CPU time 11.64 seconds
Started Jul 13 05:30:34 PM PDT 24
Finished Jul 13 05:30:46 PM PDT 24
Peak memory 222684 kb
Host smart-8792b4d7-09d9-4dea-8018-74b1c7a5b21d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4277417427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.4277417427
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2947895862
Short name T18
Test name
Test status
Simulation time 1786520743 ps
CPU time 29.12 seconds
Started Jul 13 05:30:36 PM PDT 24
Finished Jul 13 05:31:05 PM PDT 24
Peak memory 250508 kb
Host smart-397f992e-b342-49d6-b174-6c372500dc03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947895862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2947895862
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3444533641
Short name T407
Test name
Test status
Simulation time 413540545 ps
CPU time 3.85 seconds
Started Jul 13 05:30:23 PM PDT 24
Finished Jul 13 05:30:27 PM PDT 24
Peak memory 217328 kb
Host smart-8acaafe4-0fd5-4a4f-aa76-b53d0a3fd1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444533641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3444533641
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3797890035
Short name T426
Test name
Test status
Simulation time 32914900 ps
CPU time 0.72 seconds
Started Jul 13 05:30:23 PM PDT 24
Finished Jul 13 05:30:25 PM PDT 24
Peak memory 206608 kb
Host smart-eaafdee7-6444-4eab-bf40-703cf398034b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797890035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3797890035
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.92944901
Short name T439
Test name
Test status
Simulation time 262263559 ps
CPU time 1.96 seconds
Started Jul 13 05:30:24 PM PDT 24
Finished Jul 13 05:30:27 PM PDT 24
Peak memory 217400 kb
Host smart-acd53302-f826-42d3-a85e-b28524234c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92944901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.92944901
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1242656687
Short name T850
Test name
Test status
Simulation time 13474827 ps
CPU time 0.75 seconds
Started Jul 13 05:30:23 PM PDT 24
Finished Jul 13 05:30:25 PM PDT 24
Peak memory 206548 kb
Host smart-e70a0833-8d06-465a-8ce8-12507aad8c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242656687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1242656687
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1388213131
Short name T851
Test name
Test status
Simulation time 1094764321 ps
CPU time 7.14 seconds
Started Jul 13 05:30:33 PM PDT 24
Finished Jul 13 05:30:41 PM PDT 24
Peak memory 225516 kb
Host smart-f35c9464-9685-4340-b350-b846ddca359e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388213131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1388213131
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3579294150
Short name T846
Test name
Test status
Simulation time 23757499 ps
CPU time 0.74 seconds
Started Jul 13 05:30:47 PM PDT 24
Finished Jul 13 05:30:49 PM PDT 24
Peak memory 205772 kb
Host smart-23495f18-45da-4e42-b413-473fc4b9715e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579294150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3579294150
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3498650937
Short name T734
Test name
Test status
Simulation time 132945481 ps
CPU time 3.68 seconds
Started Jul 13 05:30:46 PM PDT 24
Finished Jul 13 05:30:50 PM PDT 24
Peak memory 233716 kb
Host smart-ed5cff83-321b-4a05-8110-ff917869d626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498650937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3498650937
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3267679379
Short name T3
Test name
Test status
Simulation time 66769512 ps
CPU time 0.78 seconds
Started Jul 13 05:30:35 PM PDT 24
Finished Jul 13 05:30:36 PM PDT 24
Peak memory 207524 kb
Host smart-77e851a8-b841-464b-be71-cab48e999602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267679379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3267679379
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3262359114
Short name T167
Test name
Test status
Simulation time 84692390066 ps
CPU time 139.17 seconds
Started Jul 13 05:30:59 PM PDT 24
Finished Jul 13 05:33:19 PM PDT 24
Peak memory 251120 kb
Host smart-5ca88eb9-81c8-4e34-8397-b8d8547577fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262359114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3262359114
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1927371317
Short name T256
Test name
Test status
Simulation time 4402923839 ps
CPU time 64.03 seconds
Started Jul 13 05:30:44 PM PDT 24
Finished Jul 13 05:31:48 PM PDT 24
Peak memory 237472 kb
Host smart-56744011-8a91-4da4-9dfe-87d1e509d45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927371317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1927371317
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3123251291
Short name T179
Test name
Test status
Simulation time 21538743349 ps
CPU time 98.05 seconds
Started Jul 13 05:30:45 PM PDT 24
Finished Jul 13 05:32:23 PM PDT 24
Peak memory 274964 kb
Host smart-da4d30d8-6da4-4acd-bc8e-ee86f0d697ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123251291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3123251291
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.4149894001
Short name T571
Test name
Test status
Simulation time 54476110 ps
CPU time 2.37 seconds
Started Jul 13 05:30:42 PM PDT 24
Finished Jul 13 05:30:45 PM PDT 24
Peak memory 225512 kb
Host smart-e3a1d1c7-0ee6-4ec3-810b-8f4ea28db9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149894001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4149894001
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2138851688
Short name T880
Test name
Test status
Simulation time 31887126 ps
CPU time 0.83 seconds
Started Jul 13 05:30:45 PM PDT 24
Finished Jul 13 05:30:46 PM PDT 24
Peak memory 217072 kb
Host smart-622fa1fb-a1a8-4f6d-9548-96409c6f9279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138851688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2138851688
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3505765393
Short name T56
Test name
Test status
Simulation time 33663274 ps
CPU time 2.38 seconds
Started Jul 13 05:30:44 PM PDT 24
Finished Jul 13 05:30:46 PM PDT 24
Peak memory 233464 kb
Host smart-0ec6d4df-e0e5-4d56-8afd-b2870788f31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505765393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3505765393
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2379515624
Short name T383
Test name
Test status
Simulation time 3444116759 ps
CPU time 26.82 seconds
Started Jul 13 05:30:45 PM PDT 24
Finished Jul 13 05:31:12 PM PDT 24
Peak memory 225632 kb
Host smart-2deca2ae-966d-47b7-9176-5859911e2057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379515624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2379515624
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.441964783
Short name T45
Test name
Test status
Simulation time 89583596 ps
CPU time 1.02 seconds
Started Jul 13 05:30:35 PM PDT 24
Finished Jul 13 05:30:36 PM PDT 24
Peak memory 217636 kb
Host smart-d2883f2b-337a-4699-9ff3-4b3ef9ce7128
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441964783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.441964783
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1678129647
Short name T831
Test name
Test status
Simulation time 243913801 ps
CPU time 3.98 seconds
Started Jul 13 05:30:35 PM PDT 24
Finished Jul 13 05:30:40 PM PDT 24
Peak memory 225600 kb
Host smart-ee8e1ea8-c86c-454a-aaa6-5d1b9b26797f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678129647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1678129647
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2333165159
Short name T976
Test name
Test status
Simulation time 4477597734 ps
CPU time 4.44 seconds
Started Jul 13 05:30:33 PM PDT 24
Finished Jul 13 05:30:38 PM PDT 24
Peak memory 225700 kb
Host smart-1ac38aea-f826-4130-bca2-4e80e50ac4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333165159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2333165159
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3863440398
Short name T781
Test name
Test status
Simulation time 374504427 ps
CPU time 3.95 seconds
Started Jul 13 05:30:48 PM PDT 24
Finished Jul 13 05:30:52 PM PDT 24
Peak memory 221484 kb
Host smart-bba3f069-97bf-4a69-9cf8-c1b9d1c50253
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3863440398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3863440398
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2090333888
Short name T824
Test name
Test status
Simulation time 39831963 ps
CPU time 0.9 seconds
Started Jul 13 05:30:47 PM PDT 24
Finished Jul 13 05:30:48 PM PDT 24
Peak memory 206608 kb
Host smart-5a32d47b-bbd6-4301-bd68-67e2ee4702d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090333888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2090333888
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.453316459
Short name T497
Test name
Test status
Simulation time 8185202851 ps
CPU time 19.83 seconds
Started Jul 13 05:30:33 PM PDT 24
Finished Jul 13 05:30:53 PM PDT 24
Peak memory 217432 kb
Host smart-16008291-5c69-4ff2-8276-2e8160136857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453316459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.453316459
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1663391427
Short name T810
Test name
Test status
Simulation time 548009161 ps
CPU time 3.15 seconds
Started Jul 13 05:30:35 PM PDT 24
Finished Jul 13 05:30:38 PM PDT 24
Peak memory 217596 kb
Host smart-48431039-024a-4f17-8160-ec31e05e0ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663391427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1663391427
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1204182109
Short name T296
Test name
Test status
Simulation time 18433020 ps
CPU time 0.92 seconds
Started Jul 13 05:30:37 PM PDT 24
Finished Jul 13 05:30:38 PM PDT 24
Peak memory 207816 kb
Host smart-ddb534fb-e096-4ec7-bb8a-087ff010e1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204182109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1204182109
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2109687714
Short name T496
Test name
Test status
Simulation time 99028579 ps
CPU time 0.85 seconds
Started Jul 13 05:30:34 PM PDT 24
Finished Jul 13 05:30:36 PM PDT 24
Peak memory 206940 kb
Host smart-0ac3160a-dfe2-4c3f-b33b-7049a605b70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109687714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2109687714
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3118623440
Short name T853
Test name
Test status
Simulation time 220018311 ps
CPU time 2.48 seconds
Started Jul 13 05:30:44 PM PDT 24
Finished Jul 13 05:30:47 PM PDT 24
Peak memory 225548 kb
Host smart-72222bee-2ab0-45d7-ba93-04bf1e0879ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118623440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3118623440
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3262516958
Short name T632
Test name
Test status
Simulation time 31049790 ps
CPU time 0.72 seconds
Started Jul 13 05:26:21 PM PDT 24
Finished Jul 13 05:26:23 PM PDT 24
Peak memory 205748 kb
Host smart-bc52f33b-6026-4d82-bee8-8200341302bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262516958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
262516958
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2474177141
Short name T565
Test name
Test status
Simulation time 116594297 ps
CPU time 2.6 seconds
Started Jul 13 05:26:13 PM PDT 24
Finished Jul 13 05:26:17 PM PDT 24
Peak memory 233496 kb
Host smart-cfa8a426-d9cf-4f25-bf9a-ebb6a0a7257a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474177141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2474177141
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1393764105
Short name T507
Test name
Test status
Simulation time 16423915 ps
CPU time 0.81 seconds
Started Jul 13 05:26:06 PM PDT 24
Finished Jul 13 05:26:07 PM PDT 24
Peak memory 207696 kb
Host smart-9870fb6a-e78f-42a0-9e93-5ef46259d00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393764105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1393764105
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1590806166
Short name T194
Test name
Test status
Simulation time 16363156848 ps
CPU time 130.35 seconds
Started Jul 13 05:26:25 PM PDT 24
Finished Jul 13 05:28:35 PM PDT 24
Peak memory 250304 kb
Host smart-e9f69b88-1331-4e1f-8fd9-fe02766a3ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590806166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1590806166
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2274212679
Short name T506
Test name
Test status
Simulation time 71034095061 ps
CPU time 118.2 seconds
Started Jul 13 05:26:21 PM PDT 24
Finished Jul 13 05:28:20 PM PDT 24
Peak memory 249804 kb
Host smart-15e50e13-e374-4f32-833c-6806d36533fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274212679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2274212679
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2550931215
Short name T320
Test name
Test status
Simulation time 107083008 ps
CPU time 3.46 seconds
Started Jul 13 05:26:14 PM PDT 24
Finished Jul 13 05:26:18 PM PDT 24
Peak memory 233764 kb
Host smart-5e6f2820-55c2-4851-96d6-a4b1bd97b75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550931215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2550931215
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1816495806
Short name T510
Test name
Test status
Simulation time 25230105189 ps
CPU time 57.87 seconds
Started Jul 13 05:26:15 PM PDT 24
Finished Jul 13 05:27:14 PM PDT 24
Peak memory 241704 kb
Host smart-0d9bda26-04d4-42a0-87c3-064c1f7dfc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816495806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1816495806
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1484440854
Short name T947
Test name
Test status
Simulation time 1673372612 ps
CPU time 16.85 seconds
Started Jul 13 05:26:13 PM PDT 24
Finished Jul 13 05:26:30 PM PDT 24
Peak memory 225508 kb
Host smart-d3f395c1-0674-4f73-83b7-894d268e8596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484440854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1484440854
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3674580679
Short name T199
Test name
Test status
Simulation time 8970679274 ps
CPU time 81.96 seconds
Started Jul 13 05:26:15 PM PDT 24
Finished Jul 13 05:27:37 PM PDT 24
Peak memory 241760 kb
Host smart-a1ef9633-d590-4b8c-b3ca-70c67cd21ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674580679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3674580679
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1506654981
Short name T44
Test name
Test status
Simulation time 27561493 ps
CPU time 1.14 seconds
Started Jul 13 05:26:03 PM PDT 24
Finished Jul 13 05:26:05 PM PDT 24
Peak memory 218944 kb
Host smart-b9317ac5-73e9-4c24-97f7-87eff27004c4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506654981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1506654981
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1400277203
Short name T594
Test name
Test status
Simulation time 5140116552 ps
CPU time 4 seconds
Started Jul 13 05:26:13 PM PDT 24
Finished Jul 13 05:26:17 PM PDT 24
Peak memory 225636 kb
Host smart-b04034a9-ab08-4068-94f0-f9facc2c12bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400277203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1400277203
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.988867488
Short name T356
Test name
Test status
Simulation time 20084826365 ps
CPU time 6.88 seconds
Started Jul 13 05:26:12 PM PDT 24
Finished Jul 13 05:26:20 PM PDT 24
Peak memory 225632 kb
Host smart-cfa6ae60-db49-49ce-990b-95c40342c7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988867488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.988867488
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1493353602
Short name T532
Test name
Test status
Simulation time 215818331 ps
CPU time 4.55 seconds
Started Jul 13 05:26:13 PM PDT 24
Finished Jul 13 05:26:19 PM PDT 24
Peak memory 223564 kb
Host smart-349bc4fd-a153-44de-a610-adcae960a28a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1493353602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1493353602
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3656961476
Short name T64
Test name
Test status
Simulation time 56723712 ps
CPU time 1.14 seconds
Started Jul 13 05:26:21 PM PDT 24
Finished Jul 13 05:26:23 PM PDT 24
Peak memory 236348 kb
Host smart-9005b67a-03ad-43d6-a525-8c7db17c5275
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656961476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3656961476
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2562353306
Short name T213
Test name
Test status
Simulation time 45975532838 ps
CPU time 169.48 seconds
Started Jul 13 05:26:22 PM PDT 24
Finished Jul 13 05:29:11 PM PDT 24
Peak memory 281004 kb
Host smart-b937f36c-f81c-419e-89d8-3d084ec060a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562353306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2562353306
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1147193688
Short name T677
Test name
Test status
Simulation time 1270217653 ps
CPU time 17.64 seconds
Started Jul 13 05:26:05 PM PDT 24
Finished Jul 13 05:26:23 PM PDT 24
Peak memory 217404 kb
Host smart-1ab89fa3-bde8-49d0-bec1-16b735dda3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147193688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1147193688
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2013762427
Short name T344
Test name
Test status
Simulation time 13415551329 ps
CPU time 10.99 seconds
Started Jul 13 05:26:02 PM PDT 24
Finished Jul 13 05:26:13 PM PDT 24
Peak memory 217496 kb
Host smart-144cd9df-4164-4fae-8e24-f198595c0fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013762427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2013762427
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.573311443
Short name T306
Test name
Test status
Simulation time 73717123 ps
CPU time 1.06 seconds
Started Jul 13 05:26:15 PM PDT 24
Finished Jul 13 05:26:17 PM PDT 24
Peak memory 207976 kb
Host smart-4dcb98fa-30a2-4f4f-a55e-f252d0526303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573311443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.573311443
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.5925965
Short name T465
Test name
Test status
Simulation time 109627850 ps
CPU time 0.97 seconds
Started Jul 13 05:26:15 PM PDT 24
Finished Jul 13 05:26:17 PM PDT 24
Peak memory 206964 kb
Host smart-eeafacaf-5e89-4551-b89c-6a4801b070a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5925965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.5925965
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2577253319
Short name T896
Test name
Test status
Simulation time 1349325177 ps
CPU time 4.06 seconds
Started Jul 13 05:26:15 PM PDT 24
Finished Jul 13 05:26:19 PM PDT 24
Peak memory 225468 kb
Host smart-2b4d18fd-a039-47df-9d9a-5247e0eaa015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577253319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2577253319
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3581479976
Short name T739
Test name
Test status
Simulation time 57888025 ps
CPU time 0.74 seconds
Started Jul 13 05:30:55 PM PDT 24
Finished Jul 13 05:30:56 PM PDT 24
Peak memory 205832 kb
Host smart-48b85fe6-7141-48a0-bf1b-08ec1cbbfad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581479976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3581479976
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.4218126208
Short name T318
Test name
Test status
Simulation time 492137366 ps
CPU time 5.04 seconds
Started Jul 13 05:30:54 PM PDT 24
Finished Jul 13 05:31:00 PM PDT 24
Peak memory 233724 kb
Host smart-db2aa9cc-0881-4130-8cd2-084ffafbfb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218126208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4218126208
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1534404107
Short name T654
Test name
Test status
Simulation time 32256473 ps
CPU time 0.77 seconds
Started Jul 13 05:30:47 PM PDT 24
Finished Jul 13 05:30:49 PM PDT 24
Peak memory 206496 kb
Host smart-1c8ffa50-db36-453f-8188-9317f783f089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534404107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1534404107
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.757086901
Short name T668
Test name
Test status
Simulation time 10115619010 ps
CPU time 53.28 seconds
Started Jul 13 05:30:55 PM PDT 24
Finished Jul 13 05:31:49 PM PDT 24
Peak memory 256404 kb
Host smart-12be3653-0c83-475d-934d-f138ea990229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757086901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.757086901
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2361770716
Short name T640
Test name
Test status
Simulation time 17316004877 ps
CPU time 175.2 seconds
Started Jul 13 05:30:53 PM PDT 24
Finished Jul 13 05:33:49 PM PDT 24
Peak memory 258584 kb
Host smart-c9da37cd-d1e7-4b30-a06d-36657331ebc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361770716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2361770716
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3252759637
Short name T992
Test name
Test status
Simulation time 201992660332 ps
CPU time 569.62 seconds
Started Jul 13 05:30:54 PM PDT 24
Finished Jul 13 05:40:24 PM PDT 24
Peak memory 274744 kb
Host smart-017c5b3b-4e3c-4572-ae4e-89ae42d96914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252759637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3252759637
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3624808892
Short name T314
Test name
Test status
Simulation time 4275234760 ps
CPU time 18.22 seconds
Started Jul 13 05:30:53 PM PDT 24
Finished Jul 13 05:31:12 PM PDT 24
Peak memory 241524 kb
Host smart-6709fee6-7d5a-4d87-b5c8-75154dcc6a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624808892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3624808892
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2866159459
Short name T10
Test name
Test status
Simulation time 4271840954 ps
CPU time 59.82 seconds
Started Jul 13 05:30:54 PM PDT 24
Finished Jul 13 05:31:54 PM PDT 24
Peak memory 261108 kb
Host smart-55794bf9-ed96-4081-8339-ad3fa7cb3093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866159459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2866159459
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2215284806
Short name T416
Test name
Test status
Simulation time 1219458592 ps
CPU time 5.98 seconds
Started Jul 13 05:30:54 PM PDT 24
Finished Jul 13 05:31:01 PM PDT 24
Peak memory 225524 kb
Host smart-8edd5f60-b109-4515-8f30-4bc17a288e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215284806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2215284806
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3220222800
Short name T709
Test name
Test status
Simulation time 1944135384 ps
CPU time 10.7 seconds
Started Jul 13 05:30:55 PM PDT 24
Finished Jul 13 05:31:06 PM PDT 24
Peak memory 225336 kb
Host smart-b72200cb-5246-4327-8d64-592084dfdcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220222800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3220222800
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1194891128
Short name T670
Test name
Test status
Simulation time 33187971 ps
CPU time 2.67 seconds
Started Jul 13 05:30:54 PM PDT 24
Finished Jul 13 05:30:57 PM PDT 24
Peak memory 233476 kb
Host smart-58dbf842-6894-4404-bb11-f53d4931d5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194891128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1194891128
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3870398044
Short name T588
Test name
Test status
Simulation time 89507537 ps
CPU time 3.26 seconds
Started Jul 13 05:30:53 PM PDT 24
Finished Jul 13 05:30:57 PM PDT 24
Peak memory 233780 kb
Host smart-7259b6fa-a6e6-4573-bcc1-e374fea14c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870398044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3870398044
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.540181550
Short name T762
Test name
Test status
Simulation time 1033385243 ps
CPU time 4.88 seconds
Started Jul 13 05:30:54 PM PDT 24
Finished Jul 13 05:30:59 PM PDT 24
Peak memory 220672 kb
Host smart-b21c4341-fb16-4d9a-8303-ad8e5d2966d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=540181550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.540181550
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.4102810482
Short name T713
Test name
Test status
Simulation time 189353088 ps
CPU time 0.96 seconds
Started Jul 13 05:30:54 PM PDT 24
Finished Jul 13 05:30:55 PM PDT 24
Peak memory 207636 kb
Host smart-55d43d7e-a794-47a6-aabd-ac47defed06c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102810482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.4102810482
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.71123568
Short name T752
Test name
Test status
Simulation time 763609152 ps
CPU time 8.59 seconds
Started Jul 13 05:30:47 PM PDT 24
Finished Jul 13 05:30:56 PM PDT 24
Peak memory 217432 kb
Host smart-35838c9c-82d7-4f2f-8270-38878e818e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71123568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.71123568
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4109233865
Short name T885
Test name
Test status
Simulation time 30107599873 ps
CPU time 18.14 seconds
Started Jul 13 05:30:47 PM PDT 24
Finished Jul 13 05:31:06 PM PDT 24
Peak memory 217452 kb
Host smart-fd69f16a-a762-4dc9-b7e0-4f98cf2f7702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109233865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4109233865
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1707072961
Short name T351
Test name
Test status
Simulation time 11974201 ps
CPU time 0.76 seconds
Started Jul 13 05:30:45 PM PDT 24
Finished Jul 13 05:30:46 PM PDT 24
Peak memory 206968 kb
Host smart-72954ddd-2732-492f-83ca-e6d0c4ca7fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707072961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1707072961
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2187114842
Short name T899
Test name
Test status
Simulation time 20026706 ps
CPU time 0.75 seconds
Started Jul 13 05:30:47 PM PDT 24
Finished Jul 13 05:30:48 PM PDT 24
Peak memory 207164 kb
Host smart-1810531c-ee73-41ae-a9fd-3fd33b0ed195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187114842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2187114842
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.4143619130
Short name T239
Test name
Test status
Simulation time 1381070278 ps
CPU time 9.75 seconds
Started Jul 13 05:30:54 PM PDT 24
Finished Jul 13 05:31:05 PM PDT 24
Peak memory 234948 kb
Host smart-8b112e69-39fb-47c3-9a29-9e3d6297990c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143619130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.4143619130
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.319820631
Short name T408
Test name
Test status
Simulation time 13829344 ps
CPU time 0.75 seconds
Started Jul 13 05:31:21 PM PDT 24
Finished Jul 13 05:31:22 PM PDT 24
Peak memory 205780 kb
Host smart-ae7798f2-c691-48d6-b2b7-842200fd6c0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319820631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.319820631
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1755321717
Short name T843
Test name
Test status
Simulation time 115227966 ps
CPU time 2.24 seconds
Started Jul 13 05:31:04 PM PDT 24
Finished Jul 13 05:31:06 PM PDT 24
Peak memory 225148 kb
Host smart-46e25087-2360-4902-b1f4-5c6b4f4a7619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755321717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1755321717
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2055458560
Short name T884
Test name
Test status
Simulation time 53441849 ps
CPU time 0.8 seconds
Started Jul 13 05:30:53 PM PDT 24
Finished Jul 13 05:30:54 PM PDT 24
Peak memory 206464 kb
Host smart-2831f235-f1bf-422e-98e3-442c2dff31d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055458560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2055458560
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1082775466
Short name T71
Test name
Test status
Simulation time 12608917705 ps
CPU time 94.58 seconds
Started Jul 13 05:31:11 PM PDT 24
Finished Jul 13 05:32:46 PM PDT 24
Peak memory 250220 kb
Host smart-32631bf7-5e5f-4cfe-a6e1-b3681cf2b8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082775466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1082775466
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1062429514
Short name T582
Test name
Test status
Simulation time 8430176567 ps
CPU time 95.07 seconds
Started Jul 13 05:31:07 PM PDT 24
Finished Jul 13 05:32:43 PM PDT 24
Peak memory 266560 kb
Host smart-aecb340f-07e5-4aa9-9d73-2db252d6eace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062429514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1062429514
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1471845249
Short name T997
Test name
Test status
Simulation time 2798675700 ps
CPU time 22.57 seconds
Started Jul 13 05:31:19 PM PDT 24
Finished Jul 13 05:31:42 PM PDT 24
Peak memory 225988 kb
Host smart-18256b00-52bf-4a03-9c6d-6b917363365b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471845249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1471845249
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.84889096
Short name T868
Test name
Test status
Simulation time 27738107140 ps
CPU time 215.48 seconds
Started Jul 13 05:31:06 PM PDT 24
Finished Jul 13 05:34:42 PM PDT 24
Peak memory 255992 kb
Host smart-fb9f7a02-3fd3-4176-8d40-9841d261e9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84889096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.84889096
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.34795612
Short name T891
Test name
Test status
Simulation time 213740857 ps
CPU time 4.79 seconds
Started Jul 13 05:31:06 PM PDT 24
Finished Jul 13 05:31:11 PM PDT 24
Peak memory 233800 kb
Host smart-ce7c0364-8851-42dc-8e9a-05596d926f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34795612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.34795612
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2633349375
Short name T543
Test name
Test status
Simulation time 10441943575 ps
CPU time 94.47 seconds
Started Jul 13 05:31:12 PM PDT 24
Finished Jul 13 05:32:47 PM PDT 24
Peak memory 242076 kb
Host smart-cc6c4ddb-7437-431b-83b3-c9b3e0d05cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633349375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2633349375
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2533489404
Short name T760
Test name
Test status
Simulation time 4136415049 ps
CPU time 13.13 seconds
Started Jul 13 05:31:11 PM PDT 24
Finished Jul 13 05:31:24 PM PDT 24
Peak memory 233880 kb
Host smart-dd002115-e7f8-481e-a337-8402b67ea836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533489404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2533489404
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2308225636
Short name T731
Test name
Test status
Simulation time 13571207964 ps
CPU time 10.28 seconds
Started Jul 13 05:31:04 PM PDT 24
Finished Jul 13 05:31:14 PM PDT 24
Peak memory 234940 kb
Host smart-47480212-8a0d-4d72-a91a-331ccdead99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308225636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2308225636
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2177334703
Short name T151
Test name
Test status
Simulation time 1043438609 ps
CPU time 4.35 seconds
Started Jul 13 05:31:05 PM PDT 24
Finished Jul 13 05:31:10 PM PDT 24
Peak memory 220388 kb
Host smart-ef9334d7-7861-4b8a-be48-1a3f429cd158
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2177334703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2177334703
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2026436148
Short name T138
Test name
Test status
Simulation time 71986107378 ps
CPU time 387.75 seconds
Started Jul 13 05:31:19 PM PDT 24
Finished Jul 13 05:37:48 PM PDT 24
Peak memory 252080 kb
Host smart-83d3b99b-2609-4682-b7c0-7c918a572f64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026436148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2026436148
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3832102922
Short name T520
Test name
Test status
Simulation time 981835105 ps
CPU time 13.87 seconds
Started Jul 13 05:31:06 PM PDT 24
Finished Jul 13 05:31:21 PM PDT 24
Peak memory 220576 kb
Host smart-0bb4546d-ab1d-43c0-ab87-21e74eb90044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832102922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3832102922
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1407362236
Short name T967
Test name
Test status
Simulation time 674459507 ps
CPU time 1.46 seconds
Started Jul 13 05:31:04 PM PDT 24
Finished Jul 13 05:31:06 PM PDT 24
Peak memory 208896 kb
Host smart-435d9ae0-28f5-48a6-9b01-7658d89af1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407362236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1407362236
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.705523923
Short name T777
Test name
Test status
Simulation time 63098456 ps
CPU time 3.76 seconds
Started Jul 13 05:31:07 PM PDT 24
Finished Jul 13 05:31:11 PM PDT 24
Peak memory 217344 kb
Host smart-b8750af2-ce89-44d7-b009-9b5e70992395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705523923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.705523923
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1928832878
Short name T74
Test name
Test status
Simulation time 75005166 ps
CPU time 0.79 seconds
Started Jul 13 05:31:05 PM PDT 24
Finished Jul 13 05:31:06 PM PDT 24
Peak memory 206940 kb
Host smart-91f67672-8385-4f73-a53d-abdf9095302c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928832878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1928832878
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2791467248
Short name T441
Test name
Test status
Simulation time 2260368125 ps
CPU time 9.05 seconds
Started Jul 13 05:31:08 PM PDT 24
Finished Jul 13 05:31:17 PM PDT 24
Peak memory 225696 kb
Host smart-d5125044-6166-4963-88a7-7228293d39d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791467248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2791467248
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3030489582
Short name T780
Test name
Test status
Simulation time 30541872 ps
CPU time 0.71 seconds
Started Jul 13 05:31:31 PM PDT 24
Finished Jul 13 05:31:33 PM PDT 24
Peak memory 205824 kb
Host smart-f6c5eea4-5803-47cd-b3f5-3813bec7b426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030489582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3030489582
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2380564980
Short name T622
Test name
Test status
Simulation time 812823919 ps
CPU time 6.75 seconds
Started Jul 13 05:31:18 PM PDT 24
Finished Jul 13 05:31:25 PM PDT 24
Peak memory 233680 kb
Host smart-8788ed8e-0ba4-4d46-b144-13f12226d2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380564980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2380564980
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3441543307
Short name T427
Test name
Test status
Simulation time 76449778 ps
CPU time 0.79 seconds
Started Jul 13 05:31:19 PM PDT 24
Finished Jul 13 05:31:21 PM PDT 24
Peak memory 206684 kb
Host smart-15da6835-9d52-433e-a7a6-f54b6cbbda19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441543307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3441543307
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3844853286
Short name T814
Test name
Test status
Simulation time 1883868429 ps
CPU time 26.92 seconds
Started Jul 13 05:31:21 PM PDT 24
Finished Jul 13 05:31:48 PM PDT 24
Peak memory 241932 kb
Host smart-106ffaab-20e2-47b4-abe9-5e65d736a061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844853286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3844853286
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3220781059
Short name T242
Test name
Test status
Simulation time 317838845111 ps
CPU time 593.4 seconds
Started Jul 13 05:31:18 PM PDT 24
Finished Jul 13 05:41:12 PM PDT 24
Peak memory 262132 kb
Host smart-4ba2b99c-6eac-4b80-8b7b-1fc7d584049a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220781059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3220781059
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2534778706
Short name T273
Test name
Test status
Simulation time 648558793 ps
CPU time 14.11 seconds
Started Jul 13 05:31:18 PM PDT 24
Finished Jul 13 05:31:33 PM PDT 24
Peak memory 236884 kb
Host smart-4081ae8a-882d-4577-931d-8093f86a4435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534778706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2534778706
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1188922380
Short name T807
Test name
Test status
Simulation time 1446685501 ps
CPU time 6.28 seconds
Started Jul 13 05:31:18 PM PDT 24
Finished Jul 13 05:31:25 PM PDT 24
Peak memory 234840 kb
Host smart-30ca97bd-ae51-4d46-99f7-c91d837da3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188922380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1188922380
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.4284404765
Short name T593
Test name
Test status
Simulation time 10830995490 ps
CPU time 20.54 seconds
Started Jul 13 05:31:17 PM PDT 24
Finished Jul 13 05:31:39 PM PDT 24
Peak memory 225632 kb
Host smart-c495240f-3594-4a1e-9292-02dad2a65946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284404765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.4284404765
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.863423786
Short name T774
Test name
Test status
Simulation time 373960013 ps
CPU time 8.21 seconds
Started Jul 13 05:31:19 PM PDT 24
Finished Jul 13 05:31:28 PM PDT 24
Peak memory 241864 kb
Host smart-739a1b34-844e-4b4a-86f4-0569f6c6f2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863423786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.863423786
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3999015654
Short name T381
Test name
Test status
Simulation time 21362484519 ps
CPU time 28.6 seconds
Started Jul 13 05:31:18 PM PDT 24
Finished Jul 13 05:31:48 PM PDT 24
Peak memory 241848 kb
Host smart-332f822d-093b-4e38-8bf8-280a09255225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999015654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3999015654
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2074022846
Short name T961
Test name
Test status
Simulation time 3218627369 ps
CPU time 7.51 seconds
Started Jul 13 05:31:19 PM PDT 24
Finished Jul 13 05:31:27 PM PDT 24
Peak memory 233820 kb
Host smart-28aeb30e-1588-4823-9626-f68f45af91e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074022846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2074022846
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1748955573
Short name T634
Test name
Test status
Simulation time 752005542 ps
CPU time 6.65 seconds
Started Jul 13 05:31:18 PM PDT 24
Finished Jul 13 05:31:25 PM PDT 24
Peak memory 223692 kb
Host smart-caa586fa-fce4-4c6f-8109-8977f88853b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1748955573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1748955573
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3114351074
Short name T811
Test name
Test status
Simulation time 108526210118 ps
CPU time 381.9 seconds
Started Jul 13 05:31:30 PM PDT 24
Finished Jul 13 05:37:53 PM PDT 24
Peak memory 270552 kb
Host smart-3760a6ac-583e-46c1-84ee-bde36e87908e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114351074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3114351074
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2310714592
Short name T6
Test name
Test status
Simulation time 4690000677 ps
CPU time 31.2 seconds
Started Jul 13 05:31:18 PM PDT 24
Finished Jul 13 05:31:50 PM PDT 24
Peak memory 217380 kb
Host smart-aa55dd95-5352-42cf-a85c-5ce92bcf0b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310714592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2310714592
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4276908042
Short name T486
Test name
Test status
Simulation time 44224020160 ps
CPU time 8.64 seconds
Started Jul 13 05:31:20 PM PDT 24
Finished Jul 13 05:31:29 PM PDT 24
Peak memory 217500 kb
Host smart-0abd1b31-ec90-42ec-961a-7033af836a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276908042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4276908042
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3808691820
Short name T661
Test name
Test status
Simulation time 190168648 ps
CPU time 1.28 seconds
Started Jul 13 05:31:18 PM PDT 24
Finished Jul 13 05:31:20 PM PDT 24
Peak memory 217420 kb
Host smart-3f73c44c-96a3-496b-a22d-311dcf08a4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808691820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3808691820
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.713937133
Short name T805
Test name
Test status
Simulation time 29869702 ps
CPU time 0.72 seconds
Started Jul 13 05:31:19 PM PDT 24
Finished Jul 13 05:31:21 PM PDT 24
Peak memory 206960 kb
Host smart-c6df76ca-5ebf-4f9e-99ad-35aa0b07e092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713937133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.713937133
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1818820610
Short name T1000
Test name
Test status
Simulation time 4022591667 ps
CPU time 14.67 seconds
Started Jul 13 05:31:17 PM PDT 24
Finished Jul 13 05:31:33 PM PDT 24
Peak memory 233848 kb
Host smart-5b58a4c8-2d4f-425a-b1a1-66726bbf58a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818820610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1818820610
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.285938139
Short name T39
Test name
Test status
Simulation time 29782013 ps
CPU time 0.69 seconds
Started Jul 13 05:31:30 PM PDT 24
Finished Jul 13 05:31:31 PM PDT 24
Peak memory 206360 kb
Host smart-671ed1c8-82af-4f1e-ab5f-0bcaf10d53f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285938139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.285938139
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2181603321
Short name T299
Test name
Test status
Simulation time 383296760 ps
CPU time 4.47 seconds
Started Jul 13 05:31:31 PM PDT 24
Finished Jul 13 05:31:37 PM PDT 24
Peak memory 225516 kb
Host smart-d2ae648a-1f82-41e2-9008-26a6c7de0526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181603321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2181603321
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.553695897
Short name T834
Test name
Test status
Simulation time 17173130 ps
CPU time 0.77 seconds
Started Jul 13 05:31:31 PM PDT 24
Finished Jul 13 05:31:33 PM PDT 24
Peak memory 206456 kb
Host smart-87265747-02bc-43b2-91cf-a955796f9430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553695897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.553695897
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1578526761
Short name T591
Test name
Test status
Simulation time 3206095798 ps
CPU time 52.15 seconds
Started Jul 13 05:31:31 PM PDT 24
Finished Jul 13 05:32:25 PM PDT 24
Peak memory 250312 kb
Host smart-b507bc02-1659-4011-bd04-70464b466508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578526761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1578526761
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1191831644
Short name T732
Test name
Test status
Simulation time 7465258241 ps
CPU time 29.61 seconds
Started Jul 13 05:31:31 PM PDT 24
Finished Jul 13 05:32:02 PM PDT 24
Peak memory 242188 kb
Host smart-f7624595-52b6-4b44-875b-1f36f5b9f177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191831644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1191831644
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.943875363
Short name T226
Test name
Test status
Simulation time 6099591356 ps
CPU time 50.77 seconds
Started Jul 13 05:31:31 PM PDT 24
Finished Jul 13 05:32:23 PM PDT 24
Peak memory 235008 kb
Host smart-0efdab8c-99b3-4abc-b73e-b346a6a467dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943875363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.943875363
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.983918702
Short name T859
Test name
Test status
Simulation time 102527790121 ps
CPU time 203.34 seconds
Started Jul 13 05:31:31 PM PDT 24
Finished Jul 13 05:34:56 PM PDT 24
Peak memory 255276 kb
Host smart-0b8b0802-60e1-4c0e-b2ff-f303c5d91926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983918702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.983918702
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.708028169
Short name T205
Test name
Test status
Simulation time 65244357 ps
CPU time 3.48 seconds
Started Jul 13 05:31:30 PM PDT 24
Finished Jul 13 05:31:35 PM PDT 24
Peak memory 233668 kb
Host smart-f0713672-6007-4c03-abd2-6774ba3ae1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708028169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.708028169
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2076340033
Short name T860
Test name
Test status
Simulation time 2057700686 ps
CPU time 14.86 seconds
Started Jul 13 05:31:33 PM PDT 24
Finished Jul 13 05:31:48 PM PDT 24
Peak memory 233700 kb
Host smart-405b68ac-daa1-4135-a851-70da1439e681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076340033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2076340033
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3139258697
Short name T546
Test name
Test status
Simulation time 70504275 ps
CPU time 2.44 seconds
Started Jul 13 05:31:30 PM PDT 24
Finished Jul 13 05:31:34 PM PDT 24
Peak memory 233800 kb
Host smart-03aba8c6-2e83-42d9-9cd5-a70b74a2f8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139258697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3139258697
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1841635422
Short name T223
Test name
Test status
Simulation time 7909886968 ps
CPU time 7.51 seconds
Started Jul 13 05:31:30 PM PDT 24
Finished Jul 13 05:31:38 PM PDT 24
Peak memory 225560 kb
Host smart-cd7635b5-618b-4e3c-b452-b73ccb0eb76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841635422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1841635422
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3313379826
Short name T432
Test name
Test status
Simulation time 1321495229 ps
CPU time 9.64 seconds
Started Jul 13 05:31:28 PM PDT 24
Finished Jul 13 05:31:38 PM PDT 24
Peak memory 224224 kb
Host smart-6a5c7fb3-1f3f-4415-b558-210181ca9c4a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3313379826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3313379826
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.984246180
Short name T141
Test name
Test status
Simulation time 7312403840 ps
CPU time 56.17 seconds
Started Jul 13 05:31:30 PM PDT 24
Finished Jul 13 05:32:27 PM PDT 24
Peak memory 242244 kb
Host smart-21e67b82-def0-42fb-967a-6d66282f485f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984246180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.984246180
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.4270467992
Short name T759
Test name
Test status
Simulation time 10834020885 ps
CPU time 16.18 seconds
Started Jul 13 05:31:30 PM PDT 24
Finished Jul 13 05:31:47 PM PDT 24
Peak memory 217468 kb
Host smart-5eb6ef97-e423-4dd8-b3bf-1a8347285f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270467992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4270467992
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.987072793
Short name T328
Test name
Test status
Simulation time 16193384188 ps
CPU time 12.85 seconds
Started Jul 13 05:31:30 PM PDT 24
Finished Jul 13 05:31:44 PM PDT 24
Peak memory 217492 kb
Host smart-ac2a197e-de0e-4466-a9f2-9b73a844ef0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987072793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.987072793
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2292848753
Short name T319
Test name
Test status
Simulation time 92680674 ps
CPU time 1.97 seconds
Started Jul 13 05:31:29 PM PDT 24
Finished Jul 13 05:31:32 PM PDT 24
Peak memory 217324 kb
Host smart-5175ac18-1ee1-48cc-b808-f8091842117a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292848753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2292848753
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3192056285
Short name T817
Test name
Test status
Simulation time 77117829 ps
CPU time 0.79 seconds
Started Jul 13 05:31:31 PM PDT 24
Finished Jul 13 05:31:33 PM PDT 24
Peak memory 206976 kb
Host smart-0b10e020-ebc0-47dc-86f9-e7370a21b826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192056285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3192056285
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1869016084
Short name T613
Test name
Test status
Simulation time 44847936 ps
CPU time 2.54 seconds
Started Jul 13 05:31:33 PM PDT 24
Finished Jul 13 05:31:36 PM PDT 24
Peak memory 225236 kb
Host smart-928f80ff-0123-47a2-9d3e-d45f274ecea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869016084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1869016084
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3733247543
Short name T493
Test name
Test status
Simulation time 43527891 ps
CPU time 0.76 seconds
Started Jul 13 05:31:45 PM PDT 24
Finished Jul 13 05:31:46 PM PDT 24
Peak memory 206628 kb
Host smart-f50a0212-c02c-4716-8497-76e1460e1cbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733247543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3733247543
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1146560360
Short name T635
Test name
Test status
Simulation time 129738231 ps
CPU time 2.45 seconds
Started Jul 13 05:31:38 PM PDT 24
Finished Jul 13 05:31:41 PM PDT 24
Peak memory 225448 kb
Host smart-c6e1bf8a-9314-464f-9fe1-4c68b5659767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146560360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1146560360
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2389869483
Short name T630
Test name
Test status
Simulation time 15511101 ps
CPU time 0.8 seconds
Started Jul 13 05:31:30 PM PDT 24
Finished Jul 13 05:31:32 PM PDT 24
Peak memory 207520 kb
Host smart-cc22d3dd-66db-4a76-9e51-b736d0a704d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389869483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2389869483
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3233433179
Short name T164
Test name
Test status
Simulation time 2326204776 ps
CPU time 25.75 seconds
Started Jul 13 05:31:40 PM PDT 24
Finished Jul 13 05:32:07 PM PDT 24
Peak memory 252808 kb
Host smart-0fd51141-7f52-4f0b-8389-ac1abd2804d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233433179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3233433179
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1849209868
Short name T14
Test name
Test status
Simulation time 25304725031 ps
CPU time 82.34 seconds
Started Jul 13 05:31:45 PM PDT 24
Finished Jul 13 05:33:08 PM PDT 24
Peak memory 256704 kb
Host smart-3689051e-9c9f-4d86-aeb4-3e4550636b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849209868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1849209868
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4092632693
Short name T626
Test name
Test status
Simulation time 11307733520 ps
CPU time 40.09 seconds
Started Jul 13 05:31:41 PM PDT 24
Finished Jul 13 05:32:21 PM PDT 24
Peak memory 249816 kb
Host smart-f2d6ea7b-927b-42c5-a699-9827a7f694e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092632693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4092632693
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3157860617
Short name T983
Test name
Test status
Simulation time 18914351373 ps
CPU time 166.95 seconds
Started Jul 13 05:31:40 PM PDT 24
Finished Jul 13 05:34:27 PM PDT 24
Peak memory 266680 kb
Host smart-cec51db6-2ad9-432d-8e83-495368ef19d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157860617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3157860617
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1336991158
Short name T307
Test name
Test status
Simulation time 96531348 ps
CPU time 2.57 seconds
Started Jul 13 05:31:41 PM PDT 24
Finished Jul 13 05:31:44 PM PDT 24
Peak memory 233716 kb
Host smart-f6522895-4768-4ec7-b164-8a0cfc29bb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336991158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1336991158
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3573989871
Short name T233
Test name
Test status
Simulation time 3284973546 ps
CPU time 20.54 seconds
Started Jul 13 05:31:41 PM PDT 24
Finished Jul 13 05:32:02 PM PDT 24
Peak memory 249956 kb
Host smart-3016b466-0686-413f-89fa-e58fb1ae88cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573989871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3573989871
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.400773961
Short name T315
Test name
Test status
Simulation time 34905476 ps
CPU time 2.45 seconds
Started Jul 13 05:31:41 PM PDT 24
Finished Jul 13 05:31:44 PM PDT 24
Peak memory 233564 kb
Host smart-5c8e798f-5252-4f36-93c0-a5c82d3909fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400773961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.400773961
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.293829741
Short name T443
Test name
Test status
Simulation time 255211788 ps
CPU time 2.42 seconds
Started Jul 13 05:31:39 PM PDT 24
Finished Jul 13 05:31:41 PM PDT 24
Peak memory 225592 kb
Host smart-89eda4b4-e3db-4eeb-ad7f-e235e7a46c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293829741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.293829741
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3217220335
Short name T984
Test name
Test status
Simulation time 608071044 ps
CPU time 3.65 seconds
Started Jul 13 05:31:40 PM PDT 24
Finished Jul 13 05:31:44 PM PDT 24
Peak memory 219820 kb
Host smart-7d43d603-4922-44f4-9d2d-323bbdfe7656
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3217220335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3217220335
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3297082827
Short name T809
Test name
Test status
Simulation time 5294338649 ps
CPU time 22.02 seconds
Started Jul 13 05:31:38 PM PDT 24
Finished Jul 13 05:32:00 PM PDT 24
Peak memory 225832 kb
Host smart-43baa7ae-1383-4438-b631-666d813564c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297082827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3297082827
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3138515711
Short name T902
Test name
Test status
Simulation time 331913463 ps
CPU time 3.72 seconds
Started Jul 13 05:31:30 PM PDT 24
Finished Jul 13 05:31:35 PM PDT 24
Peak memory 217348 kb
Host smart-92c89a72-0cbd-4eb5-876f-6a22e7f43030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138515711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3138515711
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.559661003
Short name T398
Test name
Test status
Simulation time 4208265817 ps
CPU time 4.44 seconds
Started Jul 13 05:31:30 PM PDT 24
Finished Jul 13 05:31:36 PM PDT 24
Peak memory 217552 kb
Host smart-8ad8f173-1e9a-4726-9d13-73fe2182517f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559661003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.559661003
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2980601894
Short name T301
Test name
Test status
Simulation time 114313386 ps
CPU time 1.82 seconds
Started Jul 13 05:31:30 PM PDT 24
Finished Jul 13 05:31:33 PM PDT 24
Peak memory 217104 kb
Host smart-2a16b3cc-7abb-4172-9577-8c09b2c57e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980601894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2980601894
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3381955726
Short name T362
Test name
Test status
Simulation time 64068272 ps
CPU time 0.88 seconds
Started Jul 13 05:31:29 PM PDT 24
Finished Jul 13 05:31:30 PM PDT 24
Peak memory 206936 kb
Host smart-99c27b28-fcf1-4b03-ad73-87cdeb991f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381955726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3381955726
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2972508810
Short name T625
Test name
Test status
Simulation time 982697382 ps
CPU time 3.18 seconds
Started Jul 13 05:31:38 PM PDT 24
Finished Jul 13 05:31:42 PM PDT 24
Peak memory 225508 kb
Host smart-df2f983b-ed7e-4e4f-864a-2e9e5872fbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972508810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2972508810
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4013169642
Short name T473
Test name
Test status
Simulation time 16072343 ps
CPU time 0.73 seconds
Started Jul 13 05:32:00 PM PDT 24
Finished Jul 13 05:32:01 PM PDT 24
Peak memory 205800 kb
Host smart-c7c329df-20dc-465c-b887-d17e5c12bc5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013169642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4013169642
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2515402227
Short name T539
Test name
Test status
Simulation time 93264310 ps
CPU time 3.34 seconds
Started Jul 13 05:31:50 PM PDT 24
Finished Jul 13 05:31:53 PM PDT 24
Peak memory 225584 kb
Host smart-7515dbb6-94cb-4267-8977-bf828cb2a74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515402227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2515402227
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3728874149
Short name T300
Test name
Test status
Simulation time 81627083 ps
CPU time 0.76 seconds
Started Jul 13 05:31:39 PM PDT 24
Finished Jul 13 05:31:40 PM PDT 24
Peak memory 207264 kb
Host smart-5105513d-e436-48ca-8cb5-e4dc39f0f8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728874149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3728874149
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2280805029
Short name T214
Test name
Test status
Simulation time 7231635454 ps
CPU time 68.32 seconds
Started Jul 13 05:31:50 PM PDT 24
Finished Jul 13 05:32:59 PM PDT 24
Peak memory 258412 kb
Host smart-451c7287-d749-4594-bb6a-ca45318a1166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280805029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2280805029
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1119897977
Short name T617
Test name
Test status
Simulation time 18558425183 ps
CPU time 137.2 seconds
Started Jul 13 05:31:48 PM PDT 24
Finished Jul 13 05:34:05 PM PDT 24
Peak memory 265268 kb
Host smart-57c3c7c4-cf03-4f0b-934c-c021e56342a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119897977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1119897977
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3810919728
Short name T58
Test name
Test status
Simulation time 241437161833 ps
CPU time 524.69 seconds
Started Jul 13 05:31:50 PM PDT 24
Finished Jul 13 05:40:36 PM PDT 24
Peak memory 263036 kb
Host smart-925639b3-8448-4b83-85e9-0679ee650969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810919728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3810919728
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.391925565
Short name T573
Test name
Test status
Simulation time 47424881 ps
CPU time 2.7 seconds
Started Jul 13 05:31:48 PM PDT 24
Finished Jul 13 05:31:51 PM PDT 24
Peak memory 230320 kb
Host smart-cb593bcf-86f2-48b4-94c9-4d611453d517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391925565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.391925565
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2215170270
Short name T776
Test name
Test status
Simulation time 14343716420 ps
CPU time 125.51 seconds
Started Jul 13 05:31:49 PM PDT 24
Finished Jul 13 05:33:54 PM PDT 24
Peak memory 256424 kb
Host smart-60620f29-d667-412b-b467-3edbe3c1d73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215170270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2215170270
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.4164924720
Short name T191
Test name
Test status
Simulation time 815533886 ps
CPU time 3.51 seconds
Started Jul 13 05:31:48 PM PDT 24
Finished Jul 13 05:31:52 PM PDT 24
Peak memory 225536 kb
Host smart-ca143c5a-3cdf-461c-ba42-c3e07fa0881f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164924720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.4164924720
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2092388345
Short name T975
Test name
Test status
Simulation time 608819585 ps
CPU time 8.49 seconds
Started Jul 13 05:31:49 PM PDT 24
Finished Jul 13 05:31:58 PM PDT 24
Peak memory 241620 kb
Host smart-8cf6dad3-4b18-4d55-94d6-f81b362d0ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092388345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2092388345
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2567443122
Short name T785
Test name
Test status
Simulation time 8539174206 ps
CPU time 11.13 seconds
Started Jul 13 05:31:50 PM PDT 24
Finished Jul 13 05:32:01 PM PDT 24
Peak memory 225672 kb
Host smart-97a0ac44-e862-4991-84c0-c9c953ee9949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567443122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2567443122
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1815004900
Short name T195
Test name
Test status
Simulation time 81367032603 ps
CPU time 42.06 seconds
Started Jul 13 05:31:45 PM PDT 24
Finished Jul 13 05:32:27 PM PDT 24
Peak memory 258092 kb
Host smart-f1be1350-ef00-4a83-8b56-76cb4782b3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815004900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1815004900
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.473985362
Short name T77
Test name
Test status
Simulation time 131612228 ps
CPU time 3.65 seconds
Started Jul 13 05:31:50 PM PDT 24
Finished Jul 13 05:31:54 PM PDT 24
Peak memory 220408 kb
Host smart-ff6c7f71-06da-4e8a-9cd3-6c132dac7710
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=473985362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.473985362
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.862668753
Short name T585
Test name
Test status
Simulation time 117316886 ps
CPU time 1.24 seconds
Started Jul 13 05:32:00 PM PDT 24
Finished Jul 13 05:32:02 PM PDT 24
Peak memory 208800 kb
Host smart-98a7569c-6185-498a-b71e-1f71d0531eff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862668753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.862668753
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1102749306
Short name T475
Test name
Test status
Simulation time 1314763324 ps
CPU time 19.5 seconds
Started Jul 13 05:31:40 PM PDT 24
Finished Jul 13 05:32:00 PM PDT 24
Peak memory 217320 kb
Host smart-3dc00b3d-1488-43e4-9e9c-36aa29af1ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102749306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1102749306
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1992147539
Short name T948
Test name
Test status
Simulation time 7218927520 ps
CPU time 18.49 seconds
Started Jul 13 05:31:39 PM PDT 24
Finished Jul 13 05:31:58 PM PDT 24
Peak memory 217448 kb
Host smart-1ae6512d-0612-43af-baac-a9437ee58e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992147539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1992147539
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3726365319
Short name T313
Test name
Test status
Simulation time 403822623 ps
CPU time 1.19 seconds
Started Jul 13 05:31:39 PM PDT 24
Finished Jul 13 05:31:41 PM PDT 24
Peak memory 208828 kb
Host smart-6c8e6ff8-17ab-409d-9a53-3ba9d6d838e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726365319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3726365319
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.268010721
Short name T926
Test name
Test status
Simulation time 138433549 ps
CPU time 0.85 seconds
Started Jul 13 05:31:39 PM PDT 24
Finished Jul 13 05:31:41 PM PDT 24
Peak memory 206988 kb
Host smart-7e6af00f-a10e-47b0-af89-cf6758e2e699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268010721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.268010721
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.823444870
Short name T368
Test name
Test status
Simulation time 255401539 ps
CPU time 4.2 seconds
Started Jul 13 05:31:50 PM PDT 24
Finished Jul 13 05:31:54 PM PDT 24
Peak memory 225496 kb
Host smart-551e9eef-60b8-462d-84d3-5b85fdcc6ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823444870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.823444870
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2022095419
Short name T886
Test name
Test status
Simulation time 48405106 ps
CPU time 0.74 seconds
Started Jul 13 05:32:14 PM PDT 24
Finished Jul 13 05:32:15 PM PDT 24
Peak memory 205764 kb
Host smart-650061c1-c65d-47a8-af5c-79c13425d05f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022095419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2022095419
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2028548375
Short name T222
Test name
Test status
Simulation time 163330688 ps
CPU time 2.57 seconds
Started Jul 13 05:32:14 PM PDT 24
Finished Jul 13 05:32:17 PM PDT 24
Peak memory 225552 kb
Host smart-bed8f576-8490-446a-9ab2-bd25afceef02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028548375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2028548375
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.396948172
Short name T515
Test name
Test status
Simulation time 29082423 ps
CPU time 0.81 seconds
Started Jul 13 05:32:00 PM PDT 24
Finished Jul 13 05:32:01 PM PDT 24
Peak memory 207484 kb
Host smart-90ce5f90-11d2-4899-9602-d065d4edf8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396948172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.396948172
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3608912124
Short name T166
Test name
Test status
Simulation time 643016784 ps
CPU time 8.95 seconds
Started Jul 13 05:32:14 PM PDT 24
Finished Jul 13 05:32:24 PM PDT 24
Peak memory 241312 kb
Host smart-e4aed24f-0dce-4492-a7d9-d0ea2855f0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608912124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3608912124
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2398319640
Short name T286
Test name
Test status
Simulation time 15281050325 ps
CPU time 121.9 seconds
Started Jul 13 05:32:15 PM PDT 24
Finished Jul 13 05:34:18 PM PDT 24
Peak memory 239152 kb
Host smart-e5fea046-86fe-4e3e-af96-a9640085093a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398319640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2398319640
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1934984071
Short name T143
Test name
Test status
Simulation time 61340382369 ps
CPU time 185.12 seconds
Started Jul 13 05:32:14 PM PDT 24
Finished Jul 13 05:35:20 PM PDT 24
Peak memory 253364 kb
Host smart-a14cc75a-a1ba-4285-8850-985e23b50f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934984071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1934984071
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4162935056
Short name T464
Test name
Test status
Simulation time 6154802489 ps
CPU time 30.18 seconds
Started Jul 13 05:32:14 PM PDT 24
Finished Jul 13 05:32:44 PM PDT 24
Peak memory 241816 kb
Host smart-2aaa10f8-b913-46cf-bd5f-5ef201978082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162935056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4162935056
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2417232658
Short name T567
Test name
Test status
Simulation time 206557430776 ps
CPU time 327.56 seconds
Started Jul 13 05:32:14 PM PDT 24
Finished Jul 13 05:37:42 PM PDT 24
Peak memory 258308 kb
Host smart-79075d87-fe52-4945-a193-5d995db49b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417232658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2417232658
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.635817691
Short name T672
Test name
Test status
Simulation time 1687469896 ps
CPU time 19.47 seconds
Started Jul 13 05:31:59 PM PDT 24
Finished Jul 13 05:32:19 PM PDT 24
Peak memory 225552 kb
Host smart-6e03df8c-4b37-487b-b83e-f95b83d7eb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635817691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.635817691
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3226117997
Short name T952
Test name
Test status
Simulation time 2901460172 ps
CPU time 15.38 seconds
Started Jul 13 05:32:03 PM PDT 24
Finished Jul 13 05:32:18 PM PDT 24
Peak memory 234036 kb
Host smart-d9053235-e9fe-41f1-8f81-3048478e74b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226117997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3226117997
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1405724451
Short name T607
Test name
Test status
Simulation time 4986903039 ps
CPU time 6.76 seconds
Started Jul 13 05:31:59 PM PDT 24
Finished Jul 13 05:32:06 PM PDT 24
Peak memory 225648 kb
Host smart-5646899a-4595-47f3-b965-daf8615b2ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405724451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1405724451
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.591657537
Short name T491
Test name
Test status
Simulation time 1667407941 ps
CPU time 8.58 seconds
Started Jul 13 05:31:59 PM PDT 24
Finished Jul 13 05:32:07 PM PDT 24
Peak memory 233780 kb
Host smart-2bac3e8f-ee75-44be-8e18-8deca9f851d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591657537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.591657537
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1465327514
Short name T519
Test name
Test status
Simulation time 2551977273 ps
CPU time 6.94 seconds
Started Jul 13 05:32:15 PM PDT 24
Finished Jul 13 05:32:22 PM PDT 24
Peak memory 223008 kb
Host smart-abe4d5b8-104a-42fe-b722-134ec141eb9b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1465327514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1465327514
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1829414980
Short name T163
Test name
Test status
Simulation time 131945096931 ps
CPU time 334.28 seconds
Started Jul 13 05:32:15 PM PDT 24
Finished Jul 13 05:37:50 PM PDT 24
Peak memory 264680 kb
Host smart-bf00a71b-b05f-49cf-916e-750cd378233e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829414980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1829414980
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2715667866
Short name T652
Test name
Test status
Simulation time 4414675527 ps
CPU time 4.83 seconds
Started Jul 13 05:32:00 PM PDT 24
Finished Jul 13 05:32:05 PM PDT 24
Peak memory 217604 kb
Host smart-14bc1ca8-cee3-43b8-a3bf-4db8103fc1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715667866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2715667866
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.566250388
Short name T32
Test name
Test status
Simulation time 1475454078 ps
CPU time 2.22 seconds
Started Jul 13 05:32:00 PM PDT 24
Finished Jul 13 05:32:03 PM PDT 24
Peak memory 217356 kb
Host smart-9bdd654a-d5da-4b84-8065-7dbd44e5c420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566250388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.566250388
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3787123344
Short name T292
Test name
Test status
Simulation time 155177241 ps
CPU time 2.21 seconds
Started Jul 13 05:32:00 PM PDT 24
Finished Jul 13 05:32:03 PM PDT 24
Peak memory 217336 kb
Host smart-eb5596e6-2c40-4620-a779-3b804a452d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787123344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3787123344
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2412850952
Short name T338
Test name
Test status
Simulation time 23685120 ps
CPU time 0.81 seconds
Started Jul 13 05:31:59 PM PDT 24
Finished Jul 13 05:32:00 PM PDT 24
Peak memory 206944 kb
Host smart-9b661948-25cf-422c-8a8d-440fb725aa3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412850952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2412850952
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3030146719
Short name T495
Test name
Test status
Simulation time 225826983 ps
CPU time 5.41 seconds
Started Jul 13 05:31:58 PM PDT 24
Finished Jul 13 05:32:04 PM PDT 24
Peak memory 240588 kb
Host smart-5b5fa782-15aa-4614-a6e5-69b15947c940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030146719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3030146719
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2742883466
Short name T597
Test name
Test status
Simulation time 20448760 ps
CPU time 0.71 seconds
Started Jul 13 05:32:28 PM PDT 24
Finished Jul 13 05:32:29 PM PDT 24
Peak memory 205980 kb
Host smart-650cd82f-5ed4-461f-9599-9d4ae63da83c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742883466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2742883466
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.292508830
Short name T929
Test name
Test status
Simulation time 517116649 ps
CPU time 4.21 seconds
Started Jul 13 05:32:26 PM PDT 24
Finished Jul 13 05:32:31 PM PDT 24
Peak memory 225524 kb
Host smart-c2018c5f-d5c9-4ee8-9c79-bf462e489f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292508830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.292508830
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2479220560
Short name T570
Test name
Test status
Simulation time 14651446 ps
CPU time 0.76 seconds
Started Jul 13 05:32:15 PM PDT 24
Finished Jul 13 05:32:16 PM PDT 24
Peak memory 206452 kb
Host smart-6c638cbd-df68-40ff-b0c9-f6029d124cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479220560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2479220560
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2972854246
Short name T403
Test name
Test status
Simulation time 3673376343 ps
CPU time 49.47 seconds
Started Jul 13 05:32:25 PM PDT 24
Finished Jul 13 05:33:16 PM PDT 24
Peak memory 242044 kb
Host smart-cbb179b1-b7a4-4644-87d3-7ccf5f1ac74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972854246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2972854246
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.4071378128
Short name T740
Test name
Test status
Simulation time 335287119331 ps
CPU time 199.05 seconds
Started Jul 13 05:32:26 PM PDT 24
Finished Jul 13 05:35:46 PM PDT 24
Peak memory 250432 kb
Host smart-2013625f-23b6-40b2-bf8c-099647bc038f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071378128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.4071378128
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2881064657
Short name T974
Test name
Test status
Simulation time 97557490687 ps
CPU time 459.55 seconds
Started Jul 13 05:32:25 PM PDT 24
Finished Jul 13 05:40:05 PM PDT 24
Peak memory 257284 kb
Host smart-82827827-2865-480b-99b8-4577da2ac514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881064657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2881064657
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.998796869
Short name T274
Test name
Test status
Simulation time 164341803 ps
CPU time 6.99 seconds
Started Jul 13 05:32:27 PM PDT 24
Finished Jul 13 05:32:35 PM PDT 24
Peak memory 233428 kb
Host smart-0ce06e01-f79d-4083-b559-7254563e56d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998796869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.998796869
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.2049748426
Short name T406
Test name
Test status
Simulation time 14154428911 ps
CPU time 121.99 seconds
Started Jul 13 05:32:26 PM PDT 24
Finished Jul 13 05:34:29 PM PDT 24
Peak memory 256240 kb
Host smart-57d7482f-b906-4a64-a831-e5da5c1d6197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049748426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.2049748426
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3727952205
Short name T492
Test name
Test status
Simulation time 2986644126 ps
CPU time 22.13 seconds
Started Jul 13 05:32:26 PM PDT 24
Finished Jul 13 05:32:49 PM PDT 24
Peak memory 233932 kb
Host smart-af1dea6e-07a2-4125-ad19-1c32729dd381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727952205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3727952205
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2066042828
Short name T477
Test name
Test status
Simulation time 16745092184 ps
CPU time 75.34 seconds
Started Jul 13 05:32:24 PM PDT 24
Finished Jul 13 05:33:40 PM PDT 24
Peak memory 250216 kb
Host smart-2405c8da-a6bc-470f-b48b-8ea48cb68ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066042828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2066042828
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2292817597
Short name T243
Test name
Test status
Simulation time 118888130 ps
CPU time 2.43 seconds
Started Jul 13 05:32:27 PM PDT 24
Finished Jul 13 05:32:31 PM PDT 24
Peak memory 233688 kb
Host smart-f791c1b8-1769-4db0-97c1-05c142b14777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292817597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2292817597
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3284225929
Short name T415
Test name
Test status
Simulation time 370487432 ps
CPU time 3.1 seconds
Started Jul 13 05:32:25 PM PDT 24
Finished Jul 13 05:32:29 PM PDT 24
Peak memory 225488 kb
Host smart-5f1b23b2-46c7-4b4d-b949-6a7c450ff952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284225929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3284225929
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1585696502
Short name T958
Test name
Test status
Simulation time 15061737571 ps
CPU time 10.31 seconds
Started Jul 13 05:32:26 PM PDT 24
Finished Jul 13 05:32:38 PM PDT 24
Peak memory 221640 kb
Host smart-27ae98d7-8ba7-44e5-9dbe-238f6ce7a964
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1585696502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1585696502
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2747287837
Short name T446
Test name
Test status
Simulation time 327927575 ps
CPU time 6.01 seconds
Started Jul 13 05:32:15 PM PDT 24
Finished Jul 13 05:32:21 PM PDT 24
Peak memory 217400 kb
Host smart-941c0f68-ee9d-4437-8cc8-69c207765c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747287837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2747287837
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3929597836
Short name T395
Test name
Test status
Simulation time 19278980752 ps
CPU time 16.52 seconds
Started Jul 13 05:32:15 PM PDT 24
Finished Jul 13 05:32:32 PM PDT 24
Peak memory 217548 kb
Host smart-4bc10a6b-4bec-4646-bb3e-c9407f18a43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929597836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3929597836
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3674786098
Short name T728
Test name
Test status
Simulation time 672400155 ps
CPU time 1.62 seconds
Started Jul 13 05:32:15 PM PDT 24
Finished Jul 13 05:32:17 PM PDT 24
Peak memory 217368 kb
Host smart-36c1952b-7151-4c9a-9e63-1008e8e94435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674786098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3674786098
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3593942829
Short name T800
Test name
Test status
Simulation time 53204448 ps
CPU time 0.9 seconds
Started Jul 13 05:32:15 PM PDT 24
Finished Jul 13 05:32:16 PM PDT 24
Peak memory 206956 kb
Host smart-8b7456b5-f878-47d3-90b6-31f9ffc2e5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593942829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3593942829
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.432386605
Short name T757
Test name
Test status
Simulation time 216348947 ps
CPU time 2.76 seconds
Started Jul 13 05:32:27 PM PDT 24
Finished Jul 13 05:32:31 PM PDT 24
Peak memory 225532 kb
Host smart-f141516b-c1ce-4e0d-ab11-f1ecf38523f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432386605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.432386605
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2447086141
Short name T467
Test name
Test status
Simulation time 22701802 ps
CPU time 0.72 seconds
Started Jul 13 05:32:25 PM PDT 24
Finished Jul 13 05:32:26 PM PDT 24
Peak memory 206280 kb
Host smart-d15e825a-10dc-4ce3-b940-5c903c94e3ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447086141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2447086141
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1675702257
Short name T499
Test name
Test status
Simulation time 3028014627 ps
CPU time 11.2 seconds
Started Jul 13 05:32:27 PM PDT 24
Finished Jul 13 05:32:39 PM PDT 24
Peak memory 233932 kb
Host smart-b897f781-823f-424f-8468-e86d991c5ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675702257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1675702257
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1543274996
Short name T130
Test name
Test status
Simulation time 27087007 ps
CPU time 0.77 seconds
Started Jul 13 05:32:25 PM PDT 24
Finished Jul 13 05:32:27 PM PDT 24
Peak memory 206488 kb
Host smart-e939f4d3-817e-4bcd-9eba-cb0642b65e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543274996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1543274996
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1539943176
Short name T693
Test name
Test status
Simulation time 2054576737 ps
CPU time 19.68 seconds
Started Jul 13 05:32:26 PM PDT 24
Finished Jul 13 05:32:47 PM PDT 24
Peak memory 225492 kb
Host smart-d5b490e6-15e3-4310-b9cc-2d0eed80ac41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539943176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1539943176
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.315878907
Short name T142
Test name
Test status
Simulation time 444614502228 ps
CPU time 255.42 seconds
Started Jul 13 05:32:26 PM PDT 24
Finished Jul 13 05:36:42 PM PDT 24
Peak memory 250368 kb
Host smart-8168a1fa-fdba-4842-a87e-083bc9049988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315878907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.315878907
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.695829117
Short name T514
Test name
Test status
Simulation time 9098732611 ps
CPU time 13.25 seconds
Started Jul 13 05:32:27 PM PDT 24
Finished Jul 13 05:32:42 PM PDT 24
Peak memory 218968 kb
Host smart-1501008e-90da-4bc3-ac57-38ae0be5f9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695829117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.695829117
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3166068173
Short name T149
Test name
Test status
Simulation time 267751195 ps
CPU time 9.97 seconds
Started Jul 13 05:32:25 PM PDT 24
Finished Jul 13 05:32:36 PM PDT 24
Peak memory 250184 kb
Host smart-e632bfae-86f0-4f63-8e6b-13894770de7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166068173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3166068173
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3528770208
Short name T662
Test name
Test status
Simulation time 3579973180 ps
CPU time 53.36 seconds
Started Jul 13 05:32:25 PM PDT 24
Finished Jul 13 05:33:19 PM PDT 24
Peak memory 250328 kb
Host smart-b9b287ed-d3f3-489e-b2ca-55bc43c7e9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528770208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3528770208
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.817853167
Short name T202
Test name
Test status
Simulation time 3502543865 ps
CPU time 42.6 seconds
Started Jul 13 05:32:26 PM PDT 24
Finished Jul 13 05:33:10 PM PDT 24
Peak memory 225712 kb
Host smart-8d51d49f-b4d6-4bee-a280-6c4a8815d7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817853167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.817853167
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3210287498
Short name T569
Test name
Test status
Simulation time 6894644365 ps
CPU time 44.05 seconds
Started Jul 13 05:32:25 PM PDT 24
Finished Jul 13 05:33:11 PM PDT 24
Peak memory 233832 kb
Host smart-8da15fcf-8541-4293-88a9-cf55ab71e580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210287498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3210287498
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1918631296
Short name T820
Test name
Test status
Simulation time 626999700 ps
CPU time 6.71 seconds
Started Jul 13 05:32:27 PM PDT 24
Finished Jul 13 05:32:35 PM PDT 24
Peak memory 241556 kb
Host smart-c5118160-43f5-446f-81b8-210e618d047b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918631296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1918631296
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3386451920
Short name T435
Test name
Test status
Simulation time 7249255292 ps
CPU time 7.73 seconds
Started Jul 13 05:32:26 PM PDT 24
Finished Jul 13 05:32:35 PM PDT 24
Peak memory 233764 kb
Host smart-88edb76f-1b9a-4fb8-b474-c6d10ec1a048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386451920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3386451920
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3813803105
Short name T327
Test name
Test status
Simulation time 2690555915 ps
CPU time 13.25 seconds
Started Jul 13 05:32:27 PM PDT 24
Finished Jul 13 05:32:42 PM PDT 24
Peak memory 223560 kb
Host smart-29fdaa54-b949-4c67-a76d-7ef5b34950b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3813803105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3813803105
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2530188928
Short name T255
Test name
Test status
Simulation time 208276922842 ps
CPU time 502.11 seconds
Started Jul 13 05:32:25 PM PDT 24
Finished Jul 13 05:40:49 PM PDT 24
Peak memory 269768 kb
Host smart-590d4f94-4c76-45e5-be9b-dc190f0a7b50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530188928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2530188928
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3485199110
Short name T349
Test name
Test status
Simulation time 2237262681 ps
CPU time 2.53 seconds
Started Jul 13 05:32:25 PM PDT 24
Finished Jul 13 05:32:29 PM PDT 24
Peak memory 217816 kb
Host smart-1814bf67-0d3a-4180-8667-1ae2a77a5c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485199110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3485199110
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2463292928
Short name T758
Test name
Test status
Simulation time 1397317398 ps
CPU time 2.8 seconds
Started Jul 13 05:32:26 PM PDT 24
Finished Jul 13 05:32:30 PM PDT 24
Peak memory 217292 kb
Host smart-5b579a97-78f9-476f-afc7-5f02d518c2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463292928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2463292928
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.601644660
Short name T448
Test name
Test status
Simulation time 155463507 ps
CPU time 3.08 seconds
Started Jul 13 05:32:24 PM PDT 24
Finished Jul 13 05:32:28 PM PDT 24
Peak memory 217360 kb
Host smart-d7ba7026-c326-442f-af77-50cc7251c88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601644660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.601644660
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.4207117691
Short name T337
Test name
Test status
Simulation time 36956971 ps
CPU time 0.86 seconds
Started Jul 13 05:32:25 PM PDT 24
Finished Jul 13 05:32:28 PM PDT 24
Peak memory 206988 kb
Host smart-215fb6ee-c874-4d29-8a6f-098c1a07fc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207117691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.4207117691
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2884396768
Short name T409
Test name
Test status
Simulation time 2812438985 ps
CPU time 5.38 seconds
Started Jul 13 05:32:24 PM PDT 24
Finished Jul 13 05:32:30 PM PDT 24
Peak memory 225652 kb
Host smart-a81aed53-1541-4f80-a724-e367e7a00c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884396768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2884396768
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1844732808
Short name T901
Test name
Test status
Simulation time 43452719 ps
CPU time 0.72 seconds
Started Jul 13 05:32:36 PM PDT 24
Finished Jul 13 05:32:37 PM PDT 24
Peak memory 205716 kb
Host smart-137a1cf9-9e93-4731-83a7-3d253e2678ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844732808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1844732808
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.485216840
Short name T490
Test name
Test status
Simulation time 136438001 ps
CPU time 2.2 seconds
Started Jul 13 05:32:37 PM PDT 24
Finished Jul 13 05:32:40 PM PDT 24
Peak memory 224892 kb
Host smart-17691820-dacf-4ea3-bf8f-f0d8842511ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485216840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.485216840
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1362035565
Short name T31
Test name
Test status
Simulation time 110341893 ps
CPU time 0.79 seconds
Started Jul 13 05:32:25 PM PDT 24
Finished Jul 13 05:32:27 PM PDT 24
Peak memory 207488 kb
Host smart-8631901a-71fe-44c7-a79a-d1a450bf1a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362035565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1362035565
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3514105030
Short name T905
Test name
Test status
Simulation time 77250662026 ps
CPU time 83.65 seconds
Started Jul 13 05:32:36 PM PDT 24
Finished Jul 13 05:34:01 PM PDT 24
Peak memory 250276 kb
Host smart-3424a8d0-1130-43ea-b0cb-7df57ffc692f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514105030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3514105030
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3957815424
Short name T457
Test name
Test status
Simulation time 6542598177 ps
CPU time 29.74 seconds
Started Jul 13 05:32:35 PM PDT 24
Finished Jul 13 05:33:05 PM PDT 24
Peak memory 225712 kb
Host smart-4080029d-2bc5-4dad-b894-6aedeefd8958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957815424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3957815424
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.118023744
Short name T517
Test name
Test status
Simulation time 2166248500 ps
CPU time 11.96 seconds
Started Jul 13 05:32:36 PM PDT 24
Finished Jul 13 05:32:49 PM PDT 24
Peak memory 225724 kb
Host smart-2536855f-0dd2-4787-9b41-661bfef271f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118023744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.118023744
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.921256559
Short name T535
Test name
Test status
Simulation time 12181184586 ps
CPU time 34.98 seconds
Started Jul 13 05:32:37 PM PDT 24
Finished Jul 13 05:33:12 PM PDT 24
Peak memory 241996 kb
Host smart-51fd77e4-d889-455f-8ea2-fa13bd19dd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921256559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.921256559
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3989833667
Short name T534
Test name
Test status
Simulation time 12707315076 ps
CPU time 29.59 seconds
Started Jul 13 05:32:37 PM PDT 24
Finished Jul 13 05:33:07 PM PDT 24
Peak memory 225616 kb
Host smart-ea349499-4ed9-42be-bc9d-38704402bd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989833667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3989833667
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.243929857
Short name T402
Test name
Test status
Simulation time 741523112 ps
CPU time 5.96 seconds
Started Jul 13 05:32:37 PM PDT 24
Finished Jul 13 05:32:44 PM PDT 24
Peak memory 234072 kb
Host smart-dda78e65-c533-4b29-9595-c6cac163872d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243929857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.243929857
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.870888808
Short name T260
Test name
Test status
Simulation time 4965856930 ps
CPU time 13.07 seconds
Started Jul 13 05:32:37 PM PDT 24
Finished Jul 13 05:32:51 PM PDT 24
Peak memory 233880 kb
Host smart-bf6c8c1f-034e-4d80-b9d0-4f0597095136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870888808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.870888808
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.732197480
Short name T231
Test name
Test status
Simulation time 418669737 ps
CPU time 3.5 seconds
Started Jul 13 05:32:27 PM PDT 24
Finished Jul 13 05:32:32 PM PDT 24
Peak memory 225488 kb
Host smart-081fc497-0538-4f9e-9d65-04db5f807a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732197480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.732197480
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1627094137
Short name T819
Test name
Test status
Simulation time 1042458480 ps
CPU time 14.79 seconds
Started Jul 13 05:32:36 PM PDT 24
Finished Jul 13 05:32:52 PM PDT 24
Peak memory 221544 kb
Host smart-6947ca19-b902-4fe1-b9bd-622ee707e4de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1627094137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1627094137
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.152643602
Short name T471
Test name
Test status
Simulation time 13588630768 ps
CPU time 177.58 seconds
Started Jul 13 05:32:38 PM PDT 24
Finished Jul 13 05:35:36 PM PDT 24
Peak memory 258584 kb
Host smart-7ef90c85-287b-4f7c-a1ef-1524532dc161
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152643602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.152643602
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.418060476
Short name T281
Test name
Test status
Simulation time 12571211950 ps
CPU time 35.54 seconds
Started Jul 13 05:32:27 PM PDT 24
Finished Jul 13 05:33:04 PM PDT 24
Peak memory 217524 kb
Host smart-45210db8-0845-4191-aa66-49aef07ebb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418060476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.418060476
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1721148367
Short name T309
Test name
Test status
Simulation time 3023922214 ps
CPU time 13.1 seconds
Started Jul 13 05:32:24 PM PDT 24
Finished Jul 13 05:32:38 PM PDT 24
Peak memory 217536 kb
Host smart-11ea0fb3-86a3-443e-abbf-5397dd04011a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721148367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1721148367
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.667106689
Short name T761
Test name
Test status
Simulation time 23458095 ps
CPU time 1.05 seconds
Started Jul 13 05:32:24 PM PDT 24
Finished Jul 13 05:32:26 PM PDT 24
Peak memory 208876 kb
Host smart-fc81f77f-233a-4d06-83f9-f7b235fa0268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667106689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.667106689
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1266183386
Short name T698
Test name
Test status
Simulation time 25315805 ps
CPU time 0.79 seconds
Started Jul 13 05:32:27 PM PDT 24
Finished Jul 13 05:32:29 PM PDT 24
Peak memory 206896 kb
Host smart-15358d24-e02a-44ae-8feb-87f9379b634f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266183386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1266183386
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2858491808
Short name T942
Test name
Test status
Simulation time 1220627810 ps
CPU time 5.9 seconds
Started Jul 13 05:32:36 PM PDT 24
Finished Jul 13 05:32:43 PM PDT 24
Peak memory 225580 kb
Host smart-3e2eaa57-6baa-4318-a753-b5517532de4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858491808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2858491808
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4155762944
Short name T628
Test name
Test status
Simulation time 44792131 ps
CPU time 0.74 seconds
Started Jul 13 05:26:54 PM PDT 24
Finished Jul 13 05:26:55 PM PDT 24
Peak memory 206280 kb
Host smart-9e5b0b93-2728-44ec-bc2a-4be5d8db81e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155762944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
155762944
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.586584122
Short name T508
Test name
Test status
Simulation time 132073051 ps
CPU time 2.76 seconds
Started Jul 13 05:26:40 PM PDT 24
Finished Jul 13 05:26:43 PM PDT 24
Peak memory 233772 kb
Host smart-124ce0ae-e6d0-49da-9888-8807af79f547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586584122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.586584122
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.4164811687
Short name T350
Test name
Test status
Simulation time 36147831 ps
CPU time 0.78 seconds
Started Jul 13 05:26:32 PM PDT 24
Finished Jul 13 05:26:33 PM PDT 24
Peak memory 207596 kb
Host smart-5daac33c-902d-484f-883c-e868725b61f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164811687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4164811687
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.442881374
Short name T253
Test name
Test status
Simulation time 119448949208 ps
CPU time 223.16 seconds
Started Jul 13 05:26:41 PM PDT 24
Finished Jul 13 05:30:25 PM PDT 24
Peak memory 250736 kb
Host smart-830c1373-2346-4866-93ea-06bce46d630b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442881374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.442881374
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2452852922
Short name T699
Test name
Test status
Simulation time 17858215097 ps
CPU time 124.63 seconds
Started Jul 13 05:26:41 PM PDT 24
Finished Jul 13 05:28:46 PM PDT 24
Peak memory 269876 kb
Host smart-e6aed36a-f620-4db6-9c86-08b24d614f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452852922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2452852922
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1924942271
Short name T553
Test name
Test status
Simulation time 1049479557 ps
CPU time 9.6 seconds
Started Jul 13 05:26:42 PM PDT 24
Finished Jul 13 05:26:52 PM PDT 24
Peak memory 225512 kb
Host smart-e475e66f-59f7-490a-b8e0-0101571331a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924942271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1924942271
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.756456442
Short name T706
Test name
Test status
Simulation time 24097448444 ps
CPU time 214.4 seconds
Started Jul 13 05:26:41 PM PDT 24
Finished Jul 13 05:30:16 PM PDT 24
Peak memory 264744 kb
Host smart-2405c248-0529-40a5-a2be-d17b49d20bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756456442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
756456442
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1357042594
Short name T562
Test name
Test status
Simulation time 4744891403 ps
CPU time 12.7 seconds
Started Jul 13 05:26:40 PM PDT 24
Finished Jul 13 05:26:53 PM PDT 24
Peak memory 233816 kb
Host smart-d62876f0-1d8a-4280-90ac-cea7cf123191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357042594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1357042594
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1491220846
Short name T501
Test name
Test status
Simulation time 6878152468 ps
CPU time 26.12 seconds
Started Jul 13 05:26:41 PM PDT 24
Finished Jul 13 05:27:07 PM PDT 24
Peak memory 233836 kb
Host smart-fe56cd3b-0797-4fe3-bc60-16a4fc3ea433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491220846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1491220846
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3008160725
Short name T920
Test name
Test status
Simulation time 17737273 ps
CPU time 1.12 seconds
Started Jul 13 05:26:30 PM PDT 24
Finished Jul 13 05:26:32 PM PDT 24
Peak memory 217628 kb
Host smart-6bdd9bac-4298-4088-b738-20d5d8f7b555
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008160725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3008160725
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.100880345
Short name T832
Test name
Test status
Simulation time 469023111 ps
CPU time 4.33 seconds
Started Jul 13 05:26:33 PM PDT 24
Finished Jul 13 05:26:37 PM PDT 24
Peak memory 233704 kb
Host smart-90167dcc-b468-4207-a98d-7830acb94450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100880345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
100880345
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1123442678
Short name T237
Test name
Test status
Simulation time 2836394287 ps
CPU time 11.37 seconds
Started Jul 13 05:26:32 PM PDT 24
Finished Jul 13 05:26:44 PM PDT 24
Peak memory 241796 kb
Host smart-716e66de-dba7-4db4-aa14-da6353720a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123442678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1123442678
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.4249196603
Short name T385
Test name
Test status
Simulation time 1279409248 ps
CPU time 12.18 seconds
Started Jul 13 05:26:40 PM PDT 24
Finished Jul 13 05:26:53 PM PDT 24
Peak memory 222392 kb
Host smart-acc72284-6b1f-4b44-a344-547fb991641d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4249196603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.4249196603
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2604601651
Short name T68
Test name
Test status
Simulation time 270377398 ps
CPU time 1.21 seconds
Started Jul 13 05:26:40 PM PDT 24
Finished Jul 13 05:26:41 PM PDT 24
Peak memory 236828 kb
Host smart-6ecaac6b-943a-4de8-ac25-383f0da0958c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604601651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2604601651
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.249591396
Short name T160
Test name
Test status
Simulation time 20082347542 ps
CPU time 263.84 seconds
Started Jul 13 05:26:41 PM PDT 24
Finished Jul 13 05:31:05 PM PDT 24
Peak memory 274560 kb
Host smart-ded3b3ca-3d0d-4089-b2d5-7616816215fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249591396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.249591396
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.294938394
Short name T972
Test name
Test status
Simulation time 5950158299 ps
CPU time 11.16 seconds
Started Jul 13 05:26:31 PM PDT 24
Finished Jul 13 05:26:43 PM PDT 24
Peak memory 217524 kb
Host smart-ff441647-3328-411b-ab46-039ddfddaa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294938394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.294938394
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3403356162
Short name T414
Test name
Test status
Simulation time 492153237 ps
CPU time 1.39 seconds
Started Jul 13 05:26:32 PM PDT 24
Finished Jul 13 05:26:34 PM PDT 24
Peak memory 208928 kb
Host smart-7300192d-33be-48b1-b04e-10b04ef35a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403356162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3403356162
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2798613944
Short name T750
Test name
Test status
Simulation time 281163070 ps
CPU time 1.9 seconds
Started Jul 13 05:26:31 PM PDT 24
Finished Jul 13 05:26:33 PM PDT 24
Peak memory 217360 kb
Host smart-4650b33b-70fd-4142-b98e-bafeff71dfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798613944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2798613944
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1287071901
Short name T548
Test name
Test status
Simulation time 19548960 ps
CPU time 0.82 seconds
Started Jul 13 05:26:32 PM PDT 24
Finished Jul 13 05:26:33 PM PDT 24
Peak memory 206972 kb
Host smart-9702ff1f-a109-4452-bf73-292b42c6fd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287071901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1287071901
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.36560951
Short name T544
Test name
Test status
Simulation time 8422994630 ps
CPU time 14.49 seconds
Started Jul 13 05:26:42 PM PDT 24
Finished Jul 13 05:26:57 PM PDT 24
Peak memory 235228 kb
Host smart-6f86d4a4-9e63-4f75-9475-ccfe2881b3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36560951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.36560951
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.4182125861
Short name T965
Test name
Test status
Simulation time 13899150 ps
CPU time 0.73 seconds
Started Jul 13 05:32:47 PM PDT 24
Finished Jul 13 05:32:48 PM PDT 24
Peak memory 206656 kb
Host smart-d9d5b600-4050-4158-bb1e-8ed83ca039c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182125861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
4182125861
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.4201710754
Short name T650
Test name
Test status
Simulation time 1093332795 ps
CPU time 3.55 seconds
Started Jul 13 05:32:47 PM PDT 24
Finished Jul 13 05:32:51 PM PDT 24
Peak memory 225572 kb
Host smart-9d250d0a-8f7c-4dc9-bd69-7f41959f163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201710754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.4201710754
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1019038057
Short name T311
Test name
Test status
Simulation time 17721395 ps
CPU time 0.79 seconds
Started Jul 13 05:32:36 PM PDT 24
Finished Jul 13 05:32:37 PM PDT 24
Peak memory 207472 kb
Host smart-c7c9fbea-cde0-4696-897b-920c93a003bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019038057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1019038057
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2714151449
Short name T378
Test name
Test status
Simulation time 21862252787 ps
CPU time 58.89 seconds
Started Jul 13 05:32:48 PM PDT 24
Finished Jul 13 05:33:48 PM PDT 24
Peak memory 250280 kb
Host smart-fef13e86-94ab-4050-8e1f-7ca3e4b59c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714151449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2714151449
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3467493290
Short name T336
Test name
Test status
Simulation time 5864598227 ps
CPU time 47.69 seconds
Started Jul 13 05:32:48 PM PDT 24
Finished Jul 13 05:33:36 PM PDT 24
Peak memory 250388 kb
Host smart-6332c664-13a5-4f6b-9506-38251bff70a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467493290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3467493290
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.691581318
Short name T530
Test name
Test status
Simulation time 3192469211 ps
CPU time 17.12 seconds
Started Jul 13 05:32:48 PM PDT 24
Finished Jul 13 05:33:05 PM PDT 24
Peak memory 218848 kb
Host smart-34270b94-ce31-46c9-800b-90ab01d83acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691581318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.691581318
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1573413755
Short name T275
Test name
Test status
Simulation time 2512395190 ps
CPU time 40.4 seconds
Started Jul 13 05:32:48 PM PDT 24
Finished Jul 13 05:33:29 PM PDT 24
Peak memory 233904 kb
Host smart-735431dc-94f8-4e81-9e56-e2854501f6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573413755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1573413755
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1182535175
Short name T1018
Test name
Test status
Simulation time 786152162 ps
CPU time 8.65 seconds
Started Jul 13 05:32:46 PM PDT 24
Finished Jul 13 05:32:55 PM PDT 24
Peak memory 233732 kb
Host smart-b3a44a53-1376-4d69-8c2a-94c1cfefd758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182535175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1182535175
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.4063523687
Short name T220
Test name
Test status
Simulation time 85042899306 ps
CPU time 102.29 seconds
Started Jul 13 05:32:47 PM PDT 24
Finished Jul 13 05:34:30 PM PDT 24
Peak memory 251912 kb
Host smart-509a2b44-7f18-4f13-9642-b79ee194c66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063523687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.4063523687
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3362093346
Short name T647
Test name
Test status
Simulation time 19588475009 ps
CPU time 16.04 seconds
Started Jul 13 05:32:46 PM PDT 24
Finished Jul 13 05:33:02 PM PDT 24
Peak memory 240632 kb
Host smart-1a2ebe20-6203-4e2d-9ed1-54f976714977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362093346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3362093346
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2693225834
Short name T852
Test name
Test status
Simulation time 2070712230 ps
CPU time 6.71 seconds
Started Jul 13 05:32:48 PM PDT 24
Finished Jul 13 05:32:55 PM PDT 24
Peak memory 225592 kb
Host smart-1882e7ea-41f1-4abe-924c-97efae8b014e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693225834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2693225834
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3374094535
Short name T359
Test name
Test status
Simulation time 510657098 ps
CPU time 5.54 seconds
Started Jul 13 05:32:49 PM PDT 24
Finished Jul 13 05:32:55 PM PDT 24
Peak memory 224304 kb
Host smart-b5e6e42a-c4db-4d9f-b61b-016624dd154f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3374094535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3374094535
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2000066227
Short name T16
Test name
Test status
Simulation time 225856774 ps
CPU time 1.09 seconds
Started Jul 13 05:32:47 PM PDT 24
Finished Jul 13 05:32:48 PM PDT 24
Peak memory 208076 kb
Host smart-a5634f03-06ce-4c3a-b5be-feec9dd1e4ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000066227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2000066227
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3327966708
Short name T505
Test name
Test status
Simulation time 344376788 ps
CPU time 3.66 seconds
Started Jul 13 05:32:38 PM PDT 24
Finished Jul 13 05:32:42 PM PDT 24
Peak memory 217612 kb
Host smart-b3ada7b4-981d-48e6-b39e-e72c6788560b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327966708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3327966708
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.949828932
Short name T400
Test name
Test status
Simulation time 7791017995 ps
CPU time 11.57 seconds
Started Jul 13 05:32:36 PM PDT 24
Finished Jul 13 05:32:48 PM PDT 24
Peak memory 217492 kb
Host smart-3d915a75-e40c-465c-ae32-2503d101c5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949828932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.949828932
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3162136749
Short name T866
Test name
Test status
Simulation time 101544494 ps
CPU time 1.03 seconds
Started Jul 13 05:32:49 PM PDT 24
Finished Jul 13 05:32:50 PM PDT 24
Peak memory 208864 kb
Host smart-4630c07d-bc22-487b-95bc-4f2d98021ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162136749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3162136749
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3834714876
Short name T873
Test name
Test status
Simulation time 37865952 ps
CPU time 0.68 seconds
Started Jul 13 05:32:36 PM PDT 24
Finished Jul 13 05:32:38 PM PDT 24
Peak memory 206540 kb
Host smart-79cee4fb-75a7-499b-9ff8-f6ec2fd4fdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834714876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3834714876
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.117402055
Short name T660
Test name
Test status
Simulation time 1875450627 ps
CPU time 9.47 seconds
Started Jul 13 05:32:47 PM PDT 24
Finished Jul 13 05:32:57 PM PDT 24
Peak memory 233728 kb
Host smart-e89aa983-b115-4be0-9634-b3184c188aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117402055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.117402055
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3336248165
Short name T960
Test name
Test status
Simulation time 14174845 ps
CPU time 0.72 seconds
Started Jul 13 05:32:56 PM PDT 24
Finished Jul 13 05:32:57 PM PDT 24
Peak memory 206732 kb
Host smart-af4ff21a-368c-48b0-bcff-822bc1cb77dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336248165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3336248165
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2743035870
Short name T249
Test name
Test status
Simulation time 124410199 ps
CPU time 2.7 seconds
Started Jul 13 05:32:57 PM PDT 24
Finished Jul 13 05:33:00 PM PDT 24
Peak memory 225580 kb
Host smart-2ab8740e-5337-4d06-bf04-585c6f36bc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743035870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2743035870
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.216326814
Short name T583
Test name
Test status
Simulation time 79191207 ps
CPU time 0.76 seconds
Started Jul 13 05:32:50 PM PDT 24
Finished Jul 13 05:32:51 PM PDT 24
Peak memory 206732 kb
Host smart-f3bbc1dc-c6ef-4281-9789-67b79c762334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216326814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.216326814
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2293096918
Short name T104
Test name
Test status
Simulation time 275124787392 ps
CPU time 300.6 seconds
Started Jul 13 05:32:57 PM PDT 24
Finished Jul 13 05:37:58 PM PDT 24
Peak memory 255028 kb
Host smart-e83bead9-3704-4393-b8ab-87f12a2eb04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293096918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2293096918
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3936578371
Short name T463
Test name
Test status
Simulation time 3572805131 ps
CPU time 15.98 seconds
Started Jul 13 05:32:56 PM PDT 24
Finished Jul 13 05:33:12 PM PDT 24
Peak memory 225708 kb
Host smart-ed52cc4f-3e49-43d5-a93c-27c1f8aecbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936578371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3936578371
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2894279031
Short name T185
Test name
Test status
Simulation time 77045592865 ps
CPU time 531.29 seconds
Started Jul 13 05:32:57 PM PDT 24
Finished Jul 13 05:41:48 PM PDT 24
Peak memory 265848 kb
Host smart-cce2c651-777c-48b8-b459-8e8d38199955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894279031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2894279031
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1907512153
Short name T716
Test name
Test status
Simulation time 2403878401 ps
CPU time 6.83 seconds
Started Jul 13 05:32:48 PM PDT 24
Finished Jul 13 05:32:56 PM PDT 24
Peak memory 220012 kb
Host smart-bdfc7dfe-3e40-4a1b-a06e-511286f3999f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907512153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1907512153
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3146234181
Short name T482
Test name
Test status
Simulation time 374291653 ps
CPU time 6.69 seconds
Started Jul 13 05:32:56 PM PDT 24
Finished Jul 13 05:33:03 PM PDT 24
Peak memory 225528 kb
Host smart-d4ec6d43-76f3-4547-84b7-8e2606c50ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146234181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3146234181
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1906873494
Short name T358
Test name
Test status
Simulation time 651187679 ps
CPU time 4.51 seconds
Started Jul 13 05:32:47 PM PDT 24
Finished Jul 13 05:32:52 PM PDT 24
Peak memory 233732 kb
Host smart-c2d760a2-667e-467f-bf3f-313526e0e438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906873494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1906873494
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3496883966
Short name T251
Test name
Test status
Simulation time 597524976 ps
CPU time 3.6 seconds
Started Jul 13 05:32:45 PM PDT 24
Finished Jul 13 05:32:49 PM PDT 24
Peak memory 233716 kb
Host smart-c38c4a7c-9599-4ec1-b18a-7bf10ac25297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496883966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3496883966
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1101518669
Short name T769
Test name
Test status
Simulation time 1087409475 ps
CPU time 7.55 seconds
Started Jul 13 05:32:56 PM PDT 24
Finished Jul 13 05:33:04 PM PDT 24
Peak memory 223392 kb
Host smart-c922b6e0-6a7c-4d37-aef1-729c4272e704
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1101518669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1101518669
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3446936799
Short name T41
Test name
Test status
Simulation time 117812837008 ps
CPU time 539.37 seconds
Started Jul 13 05:32:58 PM PDT 24
Finished Jul 13 05:41:58 PM PDT 24
Peak memory 266100 kb
Host smart-0ee239cf-d847-4cf6-97a8-7e807e097f9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446936799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3446936799
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3333823211
Short name T353
Test name
Test status
Simulation time 5516826970 ps
CPU time 10.34 seconds
Started Jul 13 05:32:47 PM PDT 24
Finished Jul 13 05:32:58 PM PDT 24
Peak memory 217480 kb
Host smart-7e91e09f-315d-43d6-ae75-6930f53d255c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333823211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3333823211
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1619129581
Short name T412
Test name
Test status
Simulation time 559417086 ps
CPU time 3.81 seconds
Started Jul 13 05:32:47 PM PDT 24
Finished Jul 13 05:32:51 PM PDT 24
Peak memory 217308 kb
Host smart-717511a7-a26d-4f39-81e2-c13cfb85dbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619129581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1619129581
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3746529049
Short name T363
Test name
Test status
Simulation time 220833722 ps
CPU time 1.55 seconds
Started Jul 13 05:32:48 PM PDT 24
Finished Jul 13 05:32:50 PM PDT 24
Peak memory 209072 kb
Host smart-1270ee4c-76c8-485c-8f26-14aa5fe2f3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746529049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3746529049
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1062608183
Short name T695
Test name
Test status
Simulation time 246360876 ps
CPU time 0.78 seconds
Started Jul 13 05:32:49 PM PDT 24
Finished Jul 13 05:32:50 PM PDT 24
Peak memory 206876 kb
Host smart-4fd6e87c-7f5b-4163-8632-d2f664ac490b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062608183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1062608183
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.593132091
Short name T953
Test name
Test status
Simulation time 2007601738 ps
CPU time 3.96 seconds
Started Jul 13 05:32:57 PM PDT 24
Finished Jul 13 05:33:01 PM PDT 24
Peak memory 233764 kb
Host smart-0e8a4bc4-80dd-4704-8d9c-0d3c2e9c6437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593132091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.593132091
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.946850574
Short name T333
Test name
Test status
Simulation time 45537791 ps
CPU time 0.72 seconds
Started Jul 13 05:33:06 PM PDT 24
Finished Jul 13 05:33:08 PM PDT 24
Peak memory 206296 kb
Host smart-67934092-7758-4615-badb-32088b1426ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946850574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.946850574
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1399761189
Short name T615
Test name
Test status
Simulation time 191025711 ps
CPU time 2.83 seconds
Started Jul 13 05:33:06 PM PDT 24
Finished Jul 13 05:33:09 PM PDT 24
Peak memory 233732 kb
Host smart-4fedc09b-4cb9-464e-9284-e32e91e3e661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399761189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1399761189
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1265165288
Short name T310
Test name
Test status
Simulation time 59175401 ps
CPU time 0.76 seconds
Started Jul 13 05:33:06 PM PDT 24
Finished Jul 13 05:33:07 PM PDT 24
Peak memory 207448 kb
Host smart-bbb5ee94-1435-4715-afd8-566ee5db93e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265165288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1265165288
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.924952836
Short name T773
Test name
Test status
Simulation time 48431221542 ps
CPU time 469.04 seconds
Started Jul 13 05:33:05 PM PDT 24
Finished Jul 13 05:40:55 PM PDT 24
Peak memory 261900 kb
Host smart-33d30229-3364-4070-b2b1-c1186c4bc638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924952836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.924952836
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.517779769
Short name T959
Test name
Test status
Simulation time 10568252475 ps
CPU time 179.84 seconds
Started Jul 13 05:33:05 PM PDT 24
Finished Jul 13 05:36:05 PM PDT 24
Peak memory 267448 kb
Host smart-45409527-5a29-4fcb-8a7e-4bcda8866f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517779769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.517779769
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3418471340
Short name T279
Test name
Test status
Simulation time 1108349851 ps
CPU time 17.36 seconds
Started Jul 13 05:33:05 PM PDT 24
Finished Jul 13 05:33:23 PM PDT 24
Peak memory 233760 kb
Host smart-5f382c99-7943-4b3f-bd35-547321db9a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418471340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3418471340
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.211537949
Short name T1012
Test name
Test status
Simulation time 56695312 ps
CPU time 0.83 seconds
Started Jul 13 05:33:06 PM PDT 24
Finished Jul 13 05:33:08 PM PDT 24
Peak memory 217112 kb
Host smart-9ccdb5d1-1ed7-4ae5-b9b9-06de1be5dc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211537949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.211537949
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.240765044
Short name T40
Test name
Test status
Simulation time 30849428 ps
CPU time 2.09 seconds
Started Jul 13 05:33:07 PM PDT 24
Finished Jul 13 05:33:09 PM PDT 24
Peak memory 233500 kb
Host smart-8aefd255-187f-4b9e-a778-4e9a4994515a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240765044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.240765044
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3559946447
Short name T410
Test name
Test status
Simulation time 18244828273 ps
CPU time 14.62 seconds
Started Jul 13 05:33:06 PM PDT 24
Finished Jul 13 05:33:21 PM PDT 24
Peak memory 233888 kb
Host smart-9e8e79e7-9ac6-41df-b5e0-e19abeb53f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559946447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3559946447
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3709599827
Short name T521
Test name
Test status
Simulation time 7724280171 ps
CPU time 11.16 seconds
Started Jul 13 05:33:06 PM PDT 24
Finished Jul 13 05:33:18 PM PDT 24
Peak memory 225664 kb
Host smart-e0cca8be-64e2-4a08-b93f-ba3b04a024a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709599827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3709599827
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3017479355
Short name T894
Test name
Test status
Simulation time 312109783 ps
CPU time 2.44 seconds
Started Jul 13 05:33:07 PM PDT 24
Finished Jul 13 05:33:10 PM PDT 24
Peak memory 224304 kb
Host smart-243c6147-38e1-4b5e-b556-19aa6316630d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017479355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3017479355
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1547107892
Short name T1022
Test name
Test status
Simulation time 529573159 ps
CPU time 6.39 seconds
Started Jul 13 05:33:06 PM PDT 24
Finished Jul 13 05:33:14 PM PDT 24
Peak memory 221396 kb
Host smart-6ddcf735-3ee3-4bea-8aa6-b79b9eab5836
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1547107892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1547107892
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.785887416
Short name T924
Test name
Test status
Simulation time 7872929620 ps
CPU time 53.9 seconds
Started Jul 13 05:33:05 PM PDT 24
Finished Jul 13 05:34:00 PM PDT 24
Peak memory 241984 kb
Host smart-7633f0b2-1a7c-4e46-8295-4abd4df7fc01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785887416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.785887416
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1724899465
Short name T991
Test name
Test status
Simulation time 8937093996 ps
CPU time 24.81 seconds
Started Jul 13 05:33:05 PM PDT 24
Finished Jul 13 05:33:31 PM PDT 24
Peak memory 217476 kb
Host smart-c4232231-57ee-4433-9fc4-be666256c5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724899465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1724899465
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2704631435
Short name T388
Test name
Test status
Simulation time 1017261080 ps
CPU time 6.43 seconds
Started Jul 13 05:33:05 PM PDT 24
Finished Jul 13 05:33:12 PM PDT 24
Peak memory 217240 kb
Host smart-895ff624-4a5e-4037-8209-058ff616aaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704631435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2704631435
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.4203459106
Short name T479
Test name
Test status
Simulation time 176191589 ps
CPU time 1.62 seconds
Started Jul 13 05:33:06 PM PDT 24
Finished Jul 13 05:33:08 PM PDT 24
Peak memory 217260 kb
Host smart-ce64ae8a-4de2-4adc-ab94-982621f766d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203459106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.4203459106
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3472635170
Short name T823
Test name
Test status
Simulation time 507959606 ps
CPU time 0.86 seconds
Started Jul 13 05:33:45 PM PDT 24
Finished Jul 13 05:33:46 PM PDT 24
Peak memory 207172 kb
Host smart-7a28499e-f8bd-4727-8483-cde9cf032dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472635170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3472635170
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.675478684
Short name T1013
Test name
Test status
Simulation time 11914240767 ps
CPU time 15.63 seconds
Started Jul 13 05:33:05 PM PDT 24
Finished Jul 13 05:33:21 PM PDT 24
Peak memory 233876 kb
Host smart-a2c61319-5603-43f5-82f5-f8d53a92a416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675478684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.675478684
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1883012228
Short name T8
Test name
Test status
Simulation time 18205707 ps
CPU time 0.74 seconds
Started Jul 13 05:33:16 PM PDT 24
Finished Jul 13 05:33:18 PM PDT 24
Peak memory 206332 kb
Host smart-c8798af6-63a4-4816-a417-ce750c16a469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883012228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1883012228
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3251557158
Short name T564
Test name
Test status
Simulation time 421461427 ps
CPU time 2.65 seconds
Started Jul 13 05:33:16 PM PDT 24
Finished Jul 13 05:33:21 PM PDT 24
Peak memory 225276 kb
Host smart-1b2eaa32-4836-413a-851c-277439a69ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251557158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3251557158
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1390514657
Short name T704
Test name
Test status
Simulation time 16828400 ps
CPU time 0.79 seconds
Started Jul 13 05:33:05 PM PDT 24
Finished Jul 13 05:33:07 PM PDT 24
Peak memory 206392 kb
Host smart-862c70fe-8c30-43a7-9b6f-3649ef01edb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390514657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1390514657
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1360993915
Short name T198
Test name
Test status
Simulation time 6254819781 ps
CPU time 105.69 seconds
Started Jul 13 05:33:15 PM PDT 24
Finished Jul 13 05:35:01 PM PDT 24
Peak memory 270220 kb
Host smart-d4b533ce-9cf1-49d6-bb3f-fe136a42619d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360993915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1360993915
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2980674368
Short name T705
Test name
Test status
Simulation time 5089295814 ps
CPU time 39.71 seconds
Started Jul 13 05:33:16 PM PDT 24
Finished Jul 13 05:33:57 PM PDT 24
Peak memory 241524 kb
Host smart-4bdd4799-8ad4-449d-9e94-dc881b92c2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980674368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2980674368
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2373553697
Short name T184
Test name
Test status
Simulation time 30388393410 ps
CPU time 122.79 seconds
Started Jul 13 05:33:16 PM PDT 24
Finished Jul 13 05:35:20 PM PDT 24
Peak memory 253936 kb
Host smart-b41fff5b-dba8-48e2-80ac-439a2a008c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373553697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2373553697
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2588678713
Short name T951
Test name
Test status
Simulation time 2308461889 ps
CPU time 38.41 seconds
Started Jul 13 05:33:16 PM PDT 24
Finished Jul 13 05:33:55 PM PDT 24
Peak memory 233928 kb
Host smart-f75c4a1e-3d31-418a-a076-5fcea3300d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588678713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2588678713
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2815156231
Short name T768
Test name
Test status
Simulation time 89067855314 ps
CPU time 179.43 seconds
Started Jul 13 05:33:15 PM PDT 24
Finished Jul 13 05:36:15 PM PDT 24
Peak memory 258484 kb
Host smart-204d46e6-2792-4721-a28e-b76bcaba0922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815156231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2815156231
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1820414467
Short name T676
Test name
Test status
Simulation time 772441384 ps
CPU time 4.3 seconds
Started Jul 13 05:33:16 PM PDT 24
Finished Jul 13 05:33:22 PM PDT 24
Peak memory 225592 kb
Host smart-46ab3087-bf79-48c9-90c3-fb6834f37e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820414467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1820414467
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2486055787
Short name T973
Test name
Test status
Simulation time 75122666 ps
CPU time 2.31 seconds
Started Jul 13 05:33:16 PM PDT 24
Finished Jul 13 05:33:20 PM PDT 24
Peak memory 225264 kb
Host smart-cbc478af-1cd3-4abf-95b0-e368d10582a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486055787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2486055787
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1081057007
Short name T93
Test name
Test status
Simulation time 5514832682 ps
CPU time 10.88 seconds
Started Jul 13 05:33:16 PM PDT 24
Finished Jul 13 05:33:29 PM PDT 24
Peak memory 233596 kb
Host smart-35b6d318-0e96-4b52-8a29-b1ea03eef0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081057007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1081057007
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3008843508
Short name T483
Test name
Test status
Simulation time 9563615805 ps
CPU time 13.58 seconds
Started Jul 13 05:33:17 PM PDT 24
Finished Jul 13 05:33:32 PM PDT 24
Peak memory 233836 kb
Host smart-67988923-eb44-458e-8ad6-f267840ae125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008843508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3008843508
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.306302062
Short name T329
Test name
Test status
Simulation time 847337690 ps
CPU time 5.75 seconds
Started Jul 13 05:33:16 PM PDT 24
Finished Jul 13 05:33:23 PM PDT 24
Peak memory 220080 kb
Host smart-e3575286-9436-4414-8402-2b5d8d277114
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=306302062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.306302062
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2987951392
Short name T865
Test name
Test status
Simulation time 12335937259 ps
CPU time 131.13 seconds
Started Jul 13 05:33:18 PM PDT 24
Finished Jul 13 05:35:30 PM PDT 24
Peak memory 251160 kb
Host smart-bf5a352e-bcd7-4dae-bb03-65a6da5a5825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987951392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2987951392
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3393111803
Short name T667
Test name
Test status
Simulation time 3510939692 ps
CPU time 10.31 seconds
Started Jul 13 05:33:13 PM PDT 24
Finished Jul 13 05:33:24 PM PDT 24
Peak memory 217416 kb
Host smart-19e01e7b-a208-438a-9dc2-077f4ac2ae32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393111803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3393111803
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2629733862
Short name T657
Test name
Test status
Simulation time 3185914017 ps
CPU time 5.44 seconds
Started Jul 13 05:33:14 PM PDT 24
Finished Jul 13 05:33:20 PM PDT 24
Peak memory 217536 kb
Host smart-4fc9fc12-b293-4bd0-a9ad-c484122d966b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629733862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2629733862
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3505645254
Short name T949
Test name
Test status
Simulation time 109997792 ps
CPU time 1.45 seconds
Started Jul 13 05:33:16 PM PDT 24
Finished Jul 13 05:33:18 PM PDT 24
Peak memory 217364 kb
Host smart-ef5d6041-a4fa-474d-94bb-8228987bff39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505645254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3505645254
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.124792676
Short name T789
Test name
Test status
Simulation time 304640371 ps
CPU time 0.93 seconds
Started Jul 13 05:33:14 PM PDT 24
Finished Jul 13 05:33:16 PM PDT 24
Peak memory 206720 kb
Host smart-6dfe4086-1f4e-4c53-bece-610bb7252e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124792676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.124792676
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.649456600
Short name T962
Test name
Test status
Simulation time 2319955111 ps
CPU time 11.96 seconds
Started Jul 13 05:33:15 PM PDT 24
Finished Jul 13 05:33:29 PM PDT 24
Peak memory 233876 kb
Host smart-119cc478-de4c-4875-bf09-ba1ee90da085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649456600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.649456600
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.781459108
Short name T433
Test name
Test status
Simulation time 39112651 ps
CPU time 0.73 seconds
Started Jul 13 05:33:28 PM PDT 24
Finished Jul 13 05:33:29 PM PDT 24
Peak memory 206396 kb
Host smart-7a65f90b-39fe-44b5-96af-ae0528a87439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781459108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.781459108
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3186077617
Short name T712
Test name
Test status
Simulation time 246698315 ps
CPU time 4.88 seconds
Started Jul 13 05:33:28 PM PDT 24
Finished Jul 13 05:33:34 PM PDT 24
Peak memory 234024 kb
Host smart-4790e9b0-ff94-490d-a7de-58d53f51b150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186077617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3186077617
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2884049573
Short name T334
Test name
Test status
Simulation time 15618416 ps
CPU time 0.78 seconds
Started Jul 13 05:33:16 PM PDT 24
Finished Jul 13 05:33:18 PM PDT 24
Peak memory 207852 kb
Host smart-025937e1-5506-4bb5-9394-ef16a4b36753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884049573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2884049573
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1799912750
Short name T963
Test name
Test status
Simulation time 1368686675 ps
CPU time 5.79 seconds
Started Jul 13 05:33:28 PM PDT 24
Finished Jul 13 05:33:34 PM PDT 24
Peak memory 236620 kb
Host smart-9cff37e6-2d95-4eed-849f-dffcbdbc14d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799912750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1799912750
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1487558852
Short name T691
Test name
Test status
Simulation time 18448664505 ps
CPU time 91.68 seconds
Started Jul 13 05:33:30 PM PDT 24
Finished Jul 13 05:35:02 PM PDT 24
Peak memory 256588 kb
Host smart-58095265-507f-438b-9da8-f706d2197c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487558852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1487558852
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2307076399
Short name T210
Test name
Test status
Simulation time 507142093793 ps
CPU time 539.78 seconds
Started Jul 13 05:33:27 PM PDT 24
Finished Jul 13 05:42:27 PM PDT 24
Peak memory 256124 kb
Host smart-25de9655-3d8b-4e89-97de-8152f6ecd45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307076399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2307076399
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1114025528
Short name T365
Test name
Test status
Simulation time 1088955520 ps
CPU time 8.3 seconds
Started Jul 13 05:33:27 PM PDT 24
Finished Jul 13 05:33:36 PM PDT 24
Peak memory 225628 kb
Host smart-82e88694-ee98-44f9-9837-6392550b2734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114025528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1114025528
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2215462135
Short name T666
Test name
Test status
Simulation time 7456488259 ps
CPU time 52.46 seconds
Started Jul 13 05:33:27 PM PDT 24
Finished Jul 13 05:34:20 PM PDT 24
Peak memory 255576 kb
Host smart-a3de3104-3092-4515-a60c-1999cdc7e6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215462135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2215462135
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1603605403
Short name T619
Test name
Test status
Simulation time 1388345511 ps
CPU time 12.21 seconds
Started Jul 13 05:33:28 PM PDT 24
Finished Jul 13 05:33:40 PM PDT 24
Peak memory 225592 kb
Host smart-147fa075-3b07-4e6b-9076-c90c6addc1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603605403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1603605403
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.4263423725
Short name T405
Test name
Test status
Simulation time 47235309611 ps
CPU time 20.23 seconds
Started Jul 13 05:33:27 PM PDT 24
Finished Jul 13 05:33:48 PM PDT 24
Peak memory 238340 kb
Host smart-4c531aaa-9697-407e-9ca4-09c7228a9f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263423725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4263423725
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.892235042
Short name T373
Test name
Test status
Simulation time 10385786713 ps
CPU time 26.28 seconds
Started Jul 13 05:33:27 PM PDT 24
Finished Jul 13 05:33:54 PM PDT 24
Peak memory 239748 kb
Host smart-81276dca-5294-4936-a033-2c4cf453577b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892235042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.892235042
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.245586116
Short name T568
Test name
Test status
Simulation time 6138748873 ps
CPU time 19.3 seconds
Started Jul 13 05:33:28 PM PDT 24
Finished Jul 13 05:33:48 PM PDT 24
Peak memory 233888 kb
Host smart-9612e81a-c3d3-487c-bc33-2192229a4a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245586116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.245586116
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.176467156
Short name T724
Test name
Test status
Simulation time 151304914 ps
CPU time 4.7 seconds
Started Jul 13 05:33:28 PM PDT 24
Finished Jul 13 05:33:33 PM PDT 24
Peak memory 223624 kb
Host smart-54e356e7-3496-4040-bc29-6f803dbcafec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=176467156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.176467156
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.4119788986
Short name T404
Test name
Test status
Simulation time 68614330 ps
CPU time 1.28 seconds
Started Jul 13 05:33:28 PM PDT 24
Finished Jul 13 05:33:30 PM PDT 24
Peak memory 208156 kb
Host smart-e6d3fbbd-7bd3-4309-afa9-9513d853ea3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119788986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.4119788986
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.788040811
Short name T883
Test name
Test status
Simulation time 472159049 ps
CPU time 4.58 seconds
Started Jul 13 05:33:17 PM PDT 24
Finished Jul 13 05:33:23 PM PDT 24
Peak memory 217316 kb
Host smart-2468cda9-03e9-4f5a-8f33-f4f7a8ece792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788040811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.788040811
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3116026805
Short name T303
Test name
Test status
Simulation time 4735091141 ps
CPU time 13.16 seconds
Started Jul 13 05:33:18 PM PDT 24
Finished Jul 13 05:33:32 PM PDT 24
Peak memory 217512 kb
Host smart-7cc69578-46cd-48a2-9453-3357a8fb117c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116026805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3116026805
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2167109411
Short name T136
Test name
Test status
Simulation time 272822573 ps
CPU time 2.62 seconds
Started Jul 13 05:33:28 PM PDT 24
Finished Jul 13 05:33:31 PM PDT 24
Peak memory 217356 kb
Host smart-47204aa5-8cd0-45e6-9484-9e10a76b7ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167109411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2167109411
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3082125251
Short name T449
Test name
Test status
Simulation time 19465883 ps
CPU time 0.77 seconds
Started Jul 13 05:33:29 PM PDT 24
Finished Jul 13 05:33:30 PM PDT 24
Peak memory 206936 kb
Host smart-253cf590-2145-4f9c-a1aa-7c0179388e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082125251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3082125251
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2238727123
Short name T818
Test name
Test status
Simulation time 13433068516 ps
CPU time 11.79 seconds
Started Jul 13 05:33:31 PM PDT 24
Finished Jul 13 05:33:43 PM PDT 24
Peak memory 233916 kb
Host smart-5ba3940b-dfb9-497e-947f-8cc512efe532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238727123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2238727123
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3837098343
Short name T557
Test name
Test status
Simulation time 42025542 ps
CPU time 0.72 seconds
Started Jul 13 05:33:39 PM PDT 24
Finished Jul 13 05:33:41 PM PDT 24
Peak memory 205820 kb
Host smart-60c55793-0098-4dc0-83fc-d76feac6260e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837098343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3837098343
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.744159899
Short name T957
Test name
Test status
Simulation time 3563005983 ps
CPU time 8.95 seconds
Started Jul 13 05:33:41 PM PDT 24
Finished Jul 13 05:33:51 PM PDT 24
Peak memory 225652 kb
Host smart-cc35baa4-7c37-4a66-b122-d52018236c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744159899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.744159899
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3435306994
Short name T389
Test name
Test status
Simulation time 34196276 ps
CPU time 0.84 seconds
Started Jul 13 05:33:38 PM PDT 24
Finished Jul 13 05:33:40 PM PDT 24
Peak memory 207816 kb
Host smart-aa9d2ff7-9cf9-4e7a-ad71-ce7fba0c5642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435306994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3435306994
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3198162934
Short name T648
Test name
Test status
Simulation time 67368159370 ps
CPU time 266.28 seconds
Started Jul 13 05:33:38 PM PDT 24
Finished Jul 13 05:38:06 PM PDT 24
Peak memory 250308 kb
Host smart-32b4668b-f9e1-4091-8020-619a9ae6342a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198162934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3198162934
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1612718301
Short name T225
Test name
Test status
Simulation time 10189198714 ps
CPU time 112.86 seconds
Started Jul 13 05:33:41 PM PDT 24
Finished Jul 13 05:35:35 PM PDT 24
Peak memory 242180 kb
Host smart-611438c7-a2ab-4b2f-a0f3-798ad3500a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612718301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1612718301
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1139258966
Short name T897
Test name
Test status
Simulation time 18234362885 ps
CPU time 70.18 seconds
Started Jul 13 05:33:39 PM PDT 24
Finished Jul 13 05:34:51 PM PDT 24
Peak memory 250304 kb
Host smart-b35ec280-04a5-4966-9dfc-60bd206e0741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139258966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1139258966
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.903689638
Short name T212
Test name
Test status
Simulation time 65017440747 ps
CPU time 447.98 seconds
Started Jul 13 05:33:40 PM PDT 24
Finished Jul 13 05:41:10 PM PDT 24
Peak memory 254712 kb
Host smart-a08183b6-e72d-4616-a267-c137a6fcd325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903689638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.903689638
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3547483776
Short name T718
Test name
Test status
Simulation time 1789765879 ps
CPU time 11.97 seconds
Started Jul 13 05:33:40 PM PDT 24
Finished Jul 13 05:33:54 PM PDT 24
Peak memory 233728 kb
Host smart-2fa03563-def9-4977-9cd6-c3180048cb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547483776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3547483776
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1602378958
Short name T248
Test name
Test status
Simulation time 38084807 ps
CPU time 2.29 seconds
Started Jul 13 05:33:41 PM PDT 24
Finished Jul 13 05:33:45 PM PDT 24
Peak memory 225772 kb
Host smart-734a176f-b64a-4068-b48b-4547d06b37db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602378958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1602378958
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.797162139
Short name T842
Test name
Test status
Simulation time 899765377 ps
CPU time 3.06 seconds
Started Jul 13 05:33:39 PM PDT 24
Finished Jul 13 05:33:44 PM PDT 24
Peak memory 225268 kb
Host smart-b1fd8174-95f8-4591-8294-e434f69343c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797162139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.797162139
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1962384319
Short name T627
Test name
Test status
Simulation time 2605729358 ps
CPU time 10.46 seconds
Started Jul 13 05:33:39 PM PDT 24
Finished Jul 13 05:33:51 PM PDT 24
Peak memory 240668 kb
Host smart-ceb835d0-3a11-4f28-ab0c-58d0d83bb148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962384319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1962384319
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1467480833
Short name T605
Test name
Test status
Simulation time 524776390 ps
CPU time 4.14 seconds
Started Jul 13 05:33:41 PM PDT 24
Finished Jul 13 05:33:46 PM PDT 24
Peak memory 224204 kb
Host smart-7ed5c2bd-2868-4e7f-87b5-95c6d425d4fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1467480833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1467480833
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1106705787
Short name T655
Test name
Test status
Simulation time 18066164994 ps
CPU time 49.25 seconds
Started Jul 13 05:33:40 PM PDT 24
Finished Jul 13 05:34:30 PM PDT 24
Peak memory 217496 kb
Host smart-bc5dae12-6b0f-4a8d-808e-e3f7acba2be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106705787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1106705787
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1371780082
Short name T527
Test name
Test status
Simulation time 831328923 ps
CPU time 5.21 seconds
Started Jul 13 05:33:39 PM PDT 24
Finished Jul 13 05:33:45 PM PDT 24
Peak memory 217320 kb
Host smart-87df407b-f998-4c1f-aae4-be2d18c56861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371780082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1371780082
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3841822724
Short name T690
Test name
Test status
Simulation time 56616668 ps
CPU time 1.16 seconds
Started Jul 13 05:33:40 PM PDT 24
Finished Jul 13 05:33:43 PM PDT 24
Peak memory 208912 kb
Host smart-79efbe58-d47f-40ac-a427-23b1316fe252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841822724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3841822724
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1571162395
Short name T711
Test name
Test status
Simulation time 72858869 ps
CPU time 0.77 seconds
Started Jul 13 05:33:39 PM PDT 24
Finished Jul 13 05:33:41 PM PDT 24
Peak memory 206952 kb
Host smart-a46b5ac0-9e0a-4924-8ede-7322502afecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571162395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1571162395
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3413184313
Short name T621
Test name
Test status
Simulation time 209013693 ps
CPU time 4.67 seconds
Started Jul 13 05:33:38 PM PDT 24
Finished Jul 13 05:33:43 PM PDT 24
Peak memory 231180 kb
Host smart-af3d52d0-34e1-470a-b062-32d2968f4ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413184313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3413184313
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3388722188
Short name T550
Test name
Test status
Simulation time 11231191 ps
CPU time 0.73 seconds
Started Jul 13 05:33:49 PM PDT 24
Finished Jul 13 05:33:50 PM PDT 24
Peak memory 205780 kb
Host smart-4ebfe654-46a7-45b4-a7c1-8ef9c7685b7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388722188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3388722188
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1036608614
Short name T707
Test name
Test status
Simulation time 897743501 ps
CPU time 10.41 seconds
Started Jul 13 05:33:51 PM PDT 24
Finished Jul 13 05:34:02 PM PDT 24
Peak memory 233760 kb
Host smart-666b5c9e-e438-432c-9771-1c61287eebbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036608614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1036608614
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1447393498
Short name T815
Test name
Test status
Simulation time 53018604 ps
CPU time 0.82 seconds
Started Jul 13 05:33:39 PM PDT 24
Finished Jul 13 05:33:42 PM PDT 24
Peak memory 207848 kb
Host smart-927a2e2f-c7a5-4631-a847-63aae8ac6a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447393498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1447393498
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3242844147
Short name T419
Test name
Test status
Simulation time 39490919527 ps
CPU time 111.9 seconds
Started Jul 13 05:33:49 PM PDT 24
Finished Jul 13 05:35:41 PM PDT 24
Peak memory 258384 kb
Host smart-9f527db3-2be4-4690-b589-ec878c4f0c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242844147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3242844147
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1651328830
Short name T42
Test name
Test status
Simulation time 105609317618 ps
CPU time 516.29 seconds
Started Jul 13 05:33:51 PM PDT 24
Finished Jul 13 05:42:28 PM PDT 24
Peak memory 266732 kb
Host smart-49cea004-97e8-48f9-8539-0c077614f2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651328830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1651328830
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3577853045
Short name T513
Test name
Test status
Simulation time 8794795173 ps
CPU time 49.95 seconds
Started Jul 13 05:33:51 PM PDT 24
Finished Jul 13 05:34:41 PM PDT 24
Peak memory 233992 kb
Host smart-3dd8a780-7f83-402d-ad14-15ba45741b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577853045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3577853045
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2437719964
Short name T131
Test name
Test status
Simulation time 3130911956 ps
CPU time 31.26 seconds
Started Jul 13 05:33:49 PM PDT 24
Finished Jul 13 05:34:21 PM PDT 24
Peak memory 252648 kb
Host smart-979fa549-0b3c-42fa-b801-0dc3a347a482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437719964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2437719964
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2482266619
Short name T737
Test name
Test status
Simulation time 62349081874 ps
CPU time 120.85 seconds
Started Jul 13 05:33:49 PM PDT 24
Finished Jul 13 05:35:51 PM PDT 24
Peak memory 250228 kb
Host smart-9b732008-21e6-4da1-b385-b45a19aef172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482266619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2482266619
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2040265644
Short name T927
Test name
Test status
Simulation time 2176725372 ps
CPU time 19.57 seconds
Started Jul 13 05:33:49 PM PDT 24
Finished Jul 13 05:34:09 PM PDT 24
Peak memory 230828 kb
Host smart-d79bd578-30fe-4eb4-992b-f8d9ef2fe3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040265644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2040265644
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1875691896
Short name T453
Test name
Test status
Simulation time 54057424 ps
CPU time 2.18 seconds
Started Jul 13 05:33:50 PM PDT 24
Finished Jul 13 05:33:53 PM PDT 24
Peak memory 224120 kb
Host smart-448ab005-1b8c-4a09-ba9b-e92660f12ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875691896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1875691896
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2927663217
Short name T792
Test name
Test status
Simulation time 143701419 ps
CPU time 2.02 seconds
Started Jul 13 05:33:52 PM PDT 24
Finished Jul 13 05:33:54 PM PDT 24
Peak memory 219400 kb
Host smart-a0a9c653-6d8e-408d-9b7c-d35847458e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927663217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2927663217
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3255196112
Short name T641
Test name
Test status
Simulation time 983108790 ps
CPU time 2.62 seconds
Started Jul 13 05:33:38 PM PDT 24
Finished Jul 13 05:33:41 PM PDT 24
Peak memory 225536 kb
Host smart-9be86e87-edb1-4497-aa34-d1020ccc1040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255196112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3255196112
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3677885673
Short name T1002
Test name
Test status
Simulation time 438278580 ps
CPU time 5.51 seconds
Started Jul 13 05:33:51 PM PDT 24
Finished Jul 13 05:33:57 PM PDT 24
Peak memory 221016 kb
Host smart-8db0bd23-0d30-4e49-bf8b-816d796a75a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3677885673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3677885673
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.862921483
Short name T159
Test name
Test status
Simulation time 4114093778 ps
CPU time 70.68 seconds
Started Jul 13 05:33:49 PM PDT 24
Finished Jul 13 05:35:00 PM PDT 24
Peak memory 253528 kb
Host smart-49207357-61e5-4e0e-a647-9620c7570894
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862921483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.862921483
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.168390473
Short name T280
Test name
Test status
Simulation time 26075095338 ps
CPU time 33.88 seconds
Started Jul 13 05:33:40 PM PDT 24
Finished Jul 13 05:34:15 PM PDT 24
Peak memory 217532 kb
Host smart-152af139-75b0-4c15-bcff-0eb226e6343f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168390473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.168390473
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3833559595
Short name T380
Test name
Test status
Simulation time 21265991664 ps
CPU time 16.92 seconds
Started Jul 13 05:33:39 PM PDT 24
Finished Jul 13 05:33:57 PM PDT 24
Peak memory 217484 kb
Host smart-6728b459-19e5-43d7-872e-ff19826162eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833559595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3833559595
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3254337733
Short name T590
Test name
Test status
Simulation time 35750115 ps
CPU time 1.73 seconds
Started Jul 13 05:33:40 PM PDT 24
Finished Jul 13 05:33:44 PM PDT 24
Peak memory 217252 kb
Host smart-94d15a25-e8c1-4c8c-aebe-0f5fc812dfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254337733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3254337733
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.274336905
Short name T498
Test name
Test status
Simulation time 451700262 ps
CPU time 0.86 seconds
Started Jul 13 05:33:39 PM PDT 24
Finished Jul 13 05:33:42 PM PDT 24
Peak memory 206992 kb
Host smart-c0a39a80-381d-4cd3-856f-53954f5392f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274336905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.274336905
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.240361873
Short name T801
Test name
Test status
Simulation time 1870726101 ps
CPU time 4.93 seconds
Started Jul 13 05:33:50 PM PDT 24
Finished Jul 13 05:33:56 PM PDT 24
Peak memory 241004 kb
Host smart-a068f457-8c08-462c-bd34-7af0693b3c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240361873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.240361873
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.4183989527
Short name T656
Test name
Test status
Simulation time 14141196 ps
CPU time 0.75 seconds
Started Jul 13 05:34:00 PM PDT 24
Finished Jul 13 05:34:01 PM PDT 24
Peak memory 205568 kb
Host smart-c1543ce1-4bae-413f-9718-3645423345eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183989527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
4183989527
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2120259485
Short name T459
Test name
Test status
Simulation time 1130986617 ps
CPU time 7.56 seconds
Started Jul 13 05:34:04 PM PDT 24
Finished Jul 13 05:34:12 PM PDT 24
Peak memory 225480 kb
Host smart-8dd0b9f2-d63c-4fbd-b1b8-4697eaa57f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120259485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2120259485
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2784974883
Short name T549
Test name
Test status
Simulation time 21575463 ps
CPU time 0.82 seconds
Started Jul 13 05:33:49 PM PDT 24
Finished Jul 13 05:33:51 PM PDT 24
Peak memory 207476 kb
Host smart-c2f767a0-bb57-4d13-a6ae-5e0365f67bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784974883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2784974883
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2419523667
Short name T793
Test name
Test status
Simulation time 36419020622 ps
CPU time 76.81 seconds
Started Jul 13 05:34:01 PM PDT 24
Finished Jul 13 05:35:19 PM PDT 24
Peak memory 242012 kb
Host smart-c405e347-b18b-4e7d-b35b-3ca1058c99a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419523667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2419523667
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1675365928
Short name T981
Test name
Test status
Simulation time 16760825247 ps
CPU time 58.82 seconds
Started Jul 13 05:34:01 PM PDT 24
Finished Jul 13 05:35:01 PM PDT 24
Peak memory 264940 kb
Host smart-9adcb3ef-bfd9-43ca-b9ee-ce30d143c5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675365928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1675365928
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1508756068
Short name T503
Test name
Test status
Simulation time 28152388427 ps
CPU time 79.16 seconds
Started Jul 13 05:34:00 PM PDT 24
Finished Jul 13 05:35:19 PM PDT 24
Peak memory 242220 kb
Host smart-6f43b05c-37da-4f8e-a9df-7c509f529685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508756068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1508756068
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2854004957
Short name T600
Test name
Test status
Simulation time 1465711368 ps
CPU time 23.49 seconds
Started Jul 13 05:34:04 PM PDT 24
Finished Jul 13 05:34:28 PM PDT 24
Peak memory 234764 kb
Host smart-03ea9b1d-ab33-4346-96a3-7182ecab4b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854004957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2854004957
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.517207756
Short name T636
Test name
Test status
Simulation time 10423001 ps
CPU time 0.76 seconds
Started Jul 13 05:34:03 PM PDT 24
Finished Jul 13 05:34:04 PM PDT 24
Peak memory 216904 kb
Host smart-981ee18e-8f08-466a-b7ff-cd87c0186165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517207756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.517207756
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.866764264
Short name T204
Test name
Test status
Simulation time 4036648813 ps
CPU time 20.87 seconds
Started Jul 13 05:33:51 PM PDT 24
Finished Jul 13 05:34:12 PM PDT 24
Peak memory 220060 kb
Host smart-807996ba-d9fe-4b80-8f50-87615bc44ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866764264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.866764264
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.866330166
Short name T918
Test name
Test status
Simulation time 5829605415 ps
CPU time 57.63 seconds
Started Jul 13 05:33:50 PM PDT 24
Finished Jul 13 05:34:48 PM PDT 24
Peak memory 225660 kb
Host smart-4ea23f9d-99c0-44ca-8413-4ed48e3baccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866330166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.866330166
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2111751723
Short name T55
Test name
Test status
Simulation time 70653677 ps
CPU time 2.57 seconds
Started Jul 13 05:33:53 PM PDT 24
Finished Jul 13 05:33:56 PM PDT 24
Peak memory 233784 kb
Host smart-b789a6cb-b802-4f23-b446-b94a3544484b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111751723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2111751723
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1218051329
Short name T945
Test name
Test status
Simulation time 414643544 ps
CPU time 3.92 seconds
Started Jul 13 05:33:50 PM PDT 24
Finished Jul 13 05:33:55 PM PDT 24
Peak memory 225620 kb
Host smart-e43dd553-db1a-4cc7-8681-855e3df6faef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218051329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1218051329
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2740120334
Short name T430
Test name
Test status
Simulation time 358805042 ps
CPU time 4.87 seconds
Started Jul 13 05:34:03 PM PDT 24
Finished Jul 13 05:34:08 PM PDT 24
Peak memory 219912 kb
Host smart-6facce28-c9ee-46d7-b590-0495e9c4c8ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2740120334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2740120334
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.836103595
Short name T37
Test name
Test status
Simulation time 79905096 ps
CPU time 0.93 seconds
Started Jul 13 05:34:02 PM PDT 24
Finished Jul 13 05:34:03 PM PDT 24
Peak memory 207544 kb
Host smart-205537d4-c26c-4d3f-b825-7801ce79647f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836103595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.836103595
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1891128856
Short name T87
Test name
Test status
Simulation time 4024647129 ps
CPU time 19.69 seconds
Started Jul 13 05:33:49 PM PDT 24
Finished Jul 13 05:34:10 PM PDT 24
Peak memory 217424 kb
Host smart-57ebf13b-6545-4323-aafa-727765a82c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891128856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1891128856
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.4037123709
Short name T70
Test name
Test status
Simulation time 337712852 ps
CPU time 3.05 seconds
Started Jul 13 05:33:49 PM PDT 24
Finished Jul 13 05:33:53 PM PDT 24
Peak memory 217356 kb
Host smart-2b7371b5-cd74-496c-b66a-fe2b39c27347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037123709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4037123709
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.66198417
Short name T784
Test name
Test status
Simulation time 161507437 ps
CPU time 1.42 seconds
Started Jul 13 05:33:51 PM PDT 24
Finished Jul 13 05:33:53 PM PDT 24
Peak memory 217296 kb
Host smart-1a058cbe-6e82-4966-8b01-4a94b8ef156e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66198417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.66198417
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3638709441
Short name T916
Test name
Test status
Simulation time 266380762 ps
CPU time 0.95 seconds
Started Jul 13 05:33:48 PM PDT 24
Finished Jul 13 05:33:50 PM PDT 24
Peak memory 207224 kb
Host smart-8cb73345-4426-47e2-8ac9-df7293a0bffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638709441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3638709441
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3470596564
Short name T371
Test name
Test status
Simulation time 384075204 ps
CPU time 7.59 seconds
Started Jul 13 05:33:50 PM PDT 24
Finished Jul 13 05:33:59 PM PDT 24
Peak memory 233692 kb
Host smart-4272f8b1-8e4d-4376-aa40-fe5d7428b74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470596564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3470596564
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.49848038
Short name T875
Test name
Test status
Simulation time 66483691 ps
CPU time 0.76 seconds
Started Jul 13 05:34:11 PM PDT 24
Finished Jul 13 05:34:13 PM PDT 24
Peak memory 205780 kb
Host smart-0995bb85-a26f-4a9a-b5dc-bdb15dea2572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49848038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.49848038
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2381356022
Short name T746
Test name
Test status
Simulation time 3496628930 ps
CPU time 17.12 seconds
Started Jul 13 05:34:02 PM PDT 24
Finished Jul 13 05:34:19 PM PDT 24
Peak memory 233892 kb
Host smart-d4829fdc-2f69-4db6-92ca-ba3c0b774eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381356022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2381356022
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.340851185
Short name T930
Test name
Test status
Simulation time 14822393 ps
CPU time 0.78 seconds
Started Jul 13 05:34:00 PM PDT 24
Finished Jul 13 05:34:01 PM PDT 24
Peak memory 207828 kb
Host smart-d4bcb6a4-9ffa-4f11-a646-5481fef14035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340851185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.340851185
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3519301427
Short name T259
Test name
Test status
Simulation time 39037715010 ps
CPU time 300.11 seconds
Started Jul 13 05:34:11 PM PDT 24
Finished Jul 13 05:39:12 PM PDT 24
Peak memory 259100 kb
Host smart-175ef443-9b4a-4a9f-9921-82b74d59dd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519301427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3519301427
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1769105637
Short name T105
Test name
Test status
Simulation time 61768173127 ps
CPU time 281.79 seconds
Started Jul 13 05:34:14 PM PDT 24
Finished Jul 13 05:38:56 PM PDT 24
Peak memory 250956 kb
Host smart-3faceb28-0c70-4d30-a144-0efdd40c3d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769105637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1769105637
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.951588176
Short name T411
Test name
Test status
Simulation time 4558522861 ps
CPU time 38.96 seconds
Started Jul 13 05:34:11 PM PDT 24
Finished Jul 13 05:34:50 PM PDT 24
Peak memory 224952 kb
Host smart-b204e8a4-07a4-4b9d-b341-8cf4d06bd3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951588176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.951588176
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2181415280
Short name T312
Test name
Test status
Simulation time 191038907 ps
CPU time 4.76 seconds
Started Jul 13 05:34:10 PM PDT 24
Finished Jul 13 05:34:16 PM PDT 24
Peak memory 225532 kb
Host smart-702c2f82-22a1-4321-a6ef-d2c892af0f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181415280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2181415280
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2173716217
Short name T892
Test name
Test status
Simulation time 11867889505 ps
CPU time 56.61 seconds
Started Jul 13 05:34:10 PM PDT 24
Finished Jul 13 05:35:07 PM PDT 24
Peak memory 252264 kb
Host smart-5c182d45-80c3-445a-aea5-d37561d53516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173716217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2173716217
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1718005426
Short name T779
Test name
Test status
Simulation time 345149049 ps
CPU time 6.33 seconds
Started Jul 13 05:34:04 PM PDT 24
Finished Jul 13 05:34:11 PM PDT 24
Peak memory 233704 kb
Host smart-9acd7e03-5fa8-491e-98e0-ba386824f89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718005426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1718005426
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3055005360
Short name T302
Test name
Test status
Simulation time 13887717326 ps
CPU time 53.83 seconds
Started Jul 13 05:34:02 PM PDT 24
Finished Jul 13 05:34:56 PM PDT 24
Peak memory 234192 kb
Host smart-be798ba0-b2e6-4418-9848-e704f6d5b7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055005360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3055005360
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2379557034
Short name T749
Test name
Test status
Simulation time 3612092567 ps
CPU time 4.34 seconds
Started Jul 13 05:34:01 PM PDT 24
Finished Jul 13 05:34:06 PM PDT 24
Peak memory 225664 kb
Host smart-b4f21f60-00b0-41a4-82c3-2f8b7e7ffea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379557034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2379557034
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1481725921
Short name T928
Test name
Test status
Simulation time 432942725 ps
CPU time 2.93 seconds
Started Jul 13 05:33:59 PM PDT 24
Finished Jul 13 05:34:02 PM PDT 24
Peak memory 225516 kb
Host smart-352a2396-1545-4287-b5dd-48b397ad2e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481725921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1481725921
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.378391131
Short name T936
Test name
Test status
Simulation time 148971285 ps
CPU time 4.34 seconds
Started Jul 13 05:34:11 PM PDT 24
Finished Jul 13 05:34:16 PM PDT 24
Peak memory 223724 kb
Host smart-808449bd-79c1-4768-a763-f286b937eeea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=378391131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.378391131
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.4069378396
Short name T452
Test name
Test status
Simulation time 169427870 ps
CPU time 1.09 seconds
Started Jul 13 05:34:11 PM PDT 24
Finished Jul 13 05:34:13 PM PDT 24
Peak memory 208120 kb
Host smart-96c94620-ece1-4106-82cb-4e0d46b102ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069378396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.4069378396
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2960141532
Short name T295
Test name
Test status
Simulation time 36789826 ps
CPU time 0.79 seconds
Started Jul 13 05:34:01 PM PDT 24
Finished Jul 13 05:34:03 PM PDT 24
Peak memory 206612 kb
Host smart-be39acea-c448-47c6-897f-00598012cba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960141532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2960141532
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1422479369
Short name T1006
Test name
Test status
Simulation time 2097654310 ps
CPU time 6.62 seconds
Started Jul 13 05:34:04 PM PDT 24
Finished Jul 13 05:34:11 PM PDT 24
Peak memory 217512 kb
Host smart-1459d5a9-d26c-4f57-a285-c9d72b2043c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422479369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1422479369
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1245253258
Short name T304
Test name
Test status
Simulation time 15414072 ps
CPU time 0.83 seconds
Started Jul 13 05:34:01 PM PDT 24
Finished Jul 13 05:34:03 PM PDT 24
Peak memory 206940 kb
Host smart-637d01d7-0764-4450-b27f-1e42044e0a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245253258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1245253258
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1048052753
Short name T85
Test name
Test status
Simulation time 147973960 ps
CPU time 0.82 seconds
Started Jul 13 05:34:04 PM PDT 24
Finished Jul 13 05:34:05 PM PDT 24
Peak memory 206972 kb
Host smart-686b2afc-1787-4bac-931c-653d5054bc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048052753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1048052753
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3412603894
Short name T782
Test name
Test status
Simulation time 126382804 ps
CPU time 2.7 seconds
Started Jul 13 05:34:01 PM PDT 24
Finished Jul 13 05:34:04 PM PDT 24
Peak memory 225448 kb
Host smart-620c7086-1f93-4150-bea0-a7b9eafaa2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412603894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3412603894
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3945083559
Short name T715
Test name
Test status
Simulation time 31014425 ps
CPU time 0.72 seconds
Started Jul 13 05:34:26 PM PDT 24
Finished Jul 13 05:34:27 PM PDT 24
Peak memory 206676 kb
Host smart-5c26fdaa-3537-4a81-8761-076a668aab26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945083559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3945083559
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3307294883
Short name T561
Test name
Test status
Simulation time 244873541 ps
CPU time 5.11 seconds
Started Jul 13 05:34:26 PM PDT 24
Finished Jul 13 05:34:31 PM PDT 24
Peak memory 225472 kb
Host smart-ae0cfdd3-7860-4b61-862a-85a60b459670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307294883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3307294883
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.715308788
Short name T994
Test name
Test status
Simulation time 68219377 ps
CPU time 0.79 seconds
Started Jul 13 05:34:12 PM PDT 24
Finished Jul 13 05:34:13 PM PDT 24
Peak memory 207772 kb
Host smart-641f19e5-1dca-4150-b761-17a5f8c39217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715308788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.715308788
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.480830112
Short name T282
Test name
Test status
Simulation time 5996329186 ps
CPU time 38.27 seconds
Started Jul 13 05:34:26 PM PDT 24
Finished Jul 13 05:35:05 PM PDT 24
Peak memory 242184 kb
Host smart-0060dee6-0dac-4856-81e7-fd828cb18ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480830112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.480830112
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1384242319
Short name T266
Test name
Test status
Simulation time 8151081723 ps
CPU time 128.72 seconds
Started Jul 13 05:34:26 PM PDT 24
Finished Jul 13 05:36:35 PM PDT 24
Peak memory 252732 kb
Host smart-38348eb6-2212-44bd-a6c7-1cee5f9483d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384242319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1384242319
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2675577927
Short name T813
Test name
Test status
Simulation time 1511099766 ps
CPU time 6.22 seconds
Started Jul 13 05:34:25 PM PDT 24
Finished Jul 13 05:34:32 PM PDT 24
Peak memory 225572 kb
Host smart-3bb71f0b-5456-4607-b352-ea251f15732a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675577927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2675577927
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1842101861
Short name T733
Test name
Test status
Simulation time 3825173267 ps
CPU time 35 seconds
Started Jul 13 05:34:26 PM PDT 24
Finished Jul 13 05:35:02 PM PDT 24
Peak memory 250248 kb
Host smart-a90cbe6e-5375-4df7-b92a-36b9f65a9e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842101861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1842101861
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.28578473
Short name T726
Test name
Test status
Simulation time 341595936 ps
CPU time 3.48 seconds
Started Jul 13 05:34:11 PM PDT 24
Finished Jul 13 05:34:15 PM PDT 24
Peak memory 225588 kb
Host smart-48e20f55-7167-4642-8031-94301a2a2058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28578473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.28578473
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4104282409
Short name T189
Test name
Test status
Simulation time 5248912769 ps
CPU time 28.14 seconds
Started Jul 13 05:34:12 PM PDT 24
Finished Jul 13 05:34:41 PM PDT 24
Peak memory 233848 kb
Host smart-45a665a2-4320-402c-8f50-316d1de4e74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104282409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4104282409
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.746467949
Short name T355
Test name
Test status
Simulation time 119077465 ps
CPU time 2.55 seconds
Started Jul 13 05:34:14 PM PDT 24
Finished Jul 13 05:34:17 PM PDT 24
Peak memory 233516 kb
Host smart-fb960dd6-f26b-4586-ab12-b8f0bae1a68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746467949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.746467949
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1805042985
Short name T589
Test name
Test status
Simulation time 4320514536 ps
CPU time 15.74 seconds
Started Jul 13 05:34:15 PM PDT 24
Finished Jul 13 05:34:31 PM PDT 24
Peak memory 242080 kb
Host smart-89be2cd0-e697-4618-b704-da81791d87a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805042985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1805042985
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2811433663
Short name T480
Test name
Test status
Simulation time 995768555 ps
CPU time 3.78 seconds
Started Jul 13 05:34:26 PM PDT 24
Finished Jul 13 05:34:30 PM PDT 24
Peak memory 223772 kb
Host smart-18569508-9e2e-4cd9-9c79-3c8dc225645d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2811433663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2811433663
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3979605325
Short name T955
Test name
Test status
Simulation time 2108204601068 ps
CPU time 1430.62 seconds
Started Jul 13 05:34:25 PM PDT 24
Finished Jul 13 05:58:16 PM PDT 24
Peak memory 289284 kb
Host smart-90ccd2b3-944d-4bcf-9086-7bac593f93f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979605325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3979605325
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2133233941
Short name T29
Test name
Test status
Simulation time 2692126162 ps
CPU time 14.1 seconds
Started Jul 13 05:34:14 PM PDT 24
Finished Jul 13 05:34:28 PM PDT 24
Peak memory 217508 kb
Host smart-2be374b6-2b5a-4928-9430-7bbbefe186c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133233941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2133233941
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2411198696
Short name T586
Test name
Test status
Simulation time 6686222927 ps
CPU time 15.44 seconds
Started Jul 13 05:34:11 PM PDT 24
Finished Jul 13 05:34:27 PM PDT 24
Peak memory 217540 kb
Host smart-f549ed41-eafb-4c43-84ff-74c65cfdce09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411198696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2411198696
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1188151146
Short name T933
Test name
Test status
Simulation time 23177251 ps
CPU time 0.72 seconds
Started Jul 13 05:34:13 PM PDT 24
Finished Jul 13 05:34:14 PM PDT 24
Peak memory 206528 kb
Host smart-5f11b79b-f4f5-40e3-8be5-703013fb61ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188151146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1188151146
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.561562679
Short name T330
Test name
Test status
Simulation time 62536117 ps
CPU time 0.9 seconds
Started Jul 13 05:34:13 PM PDT 24
Finished Jul 13 05:34:15 PM PDT 24
Peak memory 207224 kb
Host smart-90b8c148-b6ff-44fc-8ccb-a3f37a32c890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561562679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.561562679
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3067626012
Short name T913
Test name
Test status
Simulation time 716563044 ps
CPU time 4.97 seconds
Started Jul 13 05:34:29 PM PDT 24
Finished Jul 13 05:34:34 PM PDT 24
Peak memory 234004 kb
Host smart-065a1f84-4c03-4ed7-986e-279e4e76a2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067626012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3067626012
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2353023678
Short name T447
Test name
Test status
Simulation time 24104180 ps
CPU time 0.78 seconds
Started Jul 13 05:27:01 PM PDT 24
Finished Jul 13 05:27:02 PM PDT 24
Peak memory 205764 kb
Host smart-20f837ea-6a24-405e-8049-fd018141ceaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353023678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
353023678
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.755570727
Short name T382
Test name
Test status
Simulation time 1689646555 ps
CPU time 3.61 seconds
Started Jul 13 05:27:04 PM PDT 24
Finished Jul 13 05:27:08 PM PDT 24
Peak memory 225492 kb
Host smart-4325408b-c742-49ac-a2b1-c59a4bdf036a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755570727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.755570727
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1031349148
Short name T24
Test name
Test status
Simulation time 13745315 ps
CPU time 0.78 seconds
Started Jul 13 05:26:51 PM PDT 24
Finished Jul 13 05:26:52 PM PDT 24
Peak memory 207480 kb
Host smart-d678ecae-3ff9-495f-b6a0-a5b92ebe21ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031349148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1031349148
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1409923384
Short name T689
Test name
Test status
Simulation time 461870094 ps
CPU time 6.81 seconds
Started Jul 13 05:27:01 PM PDT 24
Finished Jul 13 05:27:08 PM PDT 24
Peak memory 241980 kb
Host smart-ce16dc61-a3c2-4b07-97e7-63e646a2727d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409923384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1409923384
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1941510307
Short name T287
Test name
Test status
Simulation time 10802404952 ps
CPU time 25.92 seconds
Started Jul 13 05:27:01 PM PDT 24
Finished Jul 13 05:27:27 PM PDT 24
Peak memory 240064 kb
Host smart-a2f85bfa-24c6-4fa2-b10e-7162d3e54fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941510307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1941510307
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.51984179
Short name T466
Test name
Test status
Simulation time 18604656705 ps
CPU time 172.98 seconds
Started Jul 13 05:27:02 PM PDT 24
Finished Jul 13 05:29:56 PM PDT 24
Peak memory 259524 kb
Host smart-fffba0b7-f0b7-4f06-8139-d17369574806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51984179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.51984179
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.936050399
Short name T830
Test name
Test status
Simulation time 1333505167 ps
CPU time 10.74 seconds
Started Jul 13 05:27:02 PM PDT 24
Finished Jul 13 05:27:13 PM PDT 24
Peak memory 233792 kb
Host smart-a42fd82e-ff7c-43d6-b58e-6467a39bef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936050399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.936050399
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3803705548
Short name T686
Test name
Test status
Simulation time 645479796 ps
CPU time 16.37 seconds
Started Jul 13 05:27:01 PM PDT 24
Finished Jul 13 05:27:18 PM PDT 24
Peak memory 250156 kb
Host smart-db800a3e-4e42-4463-bd9a-1aaaabfda4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803705548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3803705548
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3397226810
Short name T723
Test name
Test status
Simulation time 7940298020 ps
CPU time 33.17 seconds
Started Jul 13 05:26:53 PM PDT 24
Finished Jul 13 05:27:27 PM PDT 24
Peak memory 225568 kb
Host smart-e496f3bb-87fd-48c6-b244-27d67d1381c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397226810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3397226810
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.116592973
Short name T771
Test name
Test status
Simulation time 41177995480 ps
CPU time 63.95 seconds
Started Jul 13 05:26:51 PM PDT 24
Finished Jul 13 05:27:55 PM PDT 24
Peak memory 225712 kb
Host smart-f368c65e-d06c-45bf-ae2a-ca4f0279874e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116592973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.116592973
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2535452123
Short name T719
Test name
Test status
Simulation time 59436704 ps
CPU time 1.07 seconds
Started Jul 13 05:26:52 PM PDT 24
Finished Jul 13 05:26:53 PM PDT 24
Peak memory 217588 kb
Host smart-ba81377e-7fbf-4de0-b8bd-fb3c792570c6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535452123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2535452123
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.827586976
Short name T982
Test name
Test status
Simulation time 3469081709 ps
CPU time 13.79 seconds
Started Jul 13 05:26:51 PM PDT 24
Finished Jul 13 05:27:05 PM PDT 24
Peak memory 233880 kb
Host smart-3097eb73-5fed-44ec-8b3e-0b4b075dd0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827586976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
827586976
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2560776223
Short name T828
Test name
Test status
Simulation time 2600416715 ps
CPU time 9.64 seconds
Started Jul 13 05:26:52 PM PDT 24
Finished Jul 13 05:27:02 PM PDT 24
Peak memory 225604 kb
Host smart-bab44517-18a0-4a39-ae16-c7d19754fa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560776223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2560776223
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2461952704
Short name T917
Test name
Test status
Simulation time 3905759729 ps
CPU time 9.52 seconds
Started Jul 13 05:27:02 PM PDT 24
Finished Jul 13 05:27:12 PM PDT 24
Peak memory 222000 kb
Host smart-df81cc3e-b8e2-479d-84e0-85a59a562558
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2461952704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2461952704
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.514341918
Short name T67
Test name
Test status
Simulation time 320007195 ps
CPU time 1.02 seconds
Started Jul 13 05:27:00 PM PDT 24
Finished Jul 13 05:27:02 PM PDT 24
Peak memory 236656 kb
Host smart-e36fd1cb-dc52-47e8-948b-c7d76a069c91
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514341918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.514341918
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.238805868
Short name T854
Test name
Test status
Simulation time 10559264303 ps
CPU time 147.84 seconds
Started Jul 13 05:27:02 PM PDT 24
Finished Jul 13 05:29:31 PM PDT 24
Peak memory 250168 kb
Host smart-029c2e47-d17a-4eb9-bdde-a83dcf00ffa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238805868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.238805868
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.448568122
Short name T669
Test name
Test status
Simulation time 11682712718 ps
CPU time 23.81 seconds
Started Jul 13 05:26:52 PM PDT 24
Finished Jul 13 05:27:16 PM PDT 24
Peak memory 217464 kb
Host smart-cf4c0aa2-b16a-4be5-bb1a-1e0f126d9dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448568122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.448568122
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.819003084
Short name T434
Test name
Test status
Simulation time 852594988 ps
CPU time 4.82 seconds
Started Jul 13 05:26:50 PM PDT 24
Finished Jul 13 05:26:55 PM PDT 24
Peak memory 217396 kb
Host smart-90639d3e-cfbb-4c28-ba24-168af48f796f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819003084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.819003084
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2649685450
Short name T79
Test name
Test status
Simulation time 23420093 ps
CPU time 0.71 seconds
Started Jul 13 05:26:53 PM PDT 24
Finished Jul 13 05:26:54 PM PDT 24
Peak memory 206524 kb
Host smart-134c7e31-23cf-45fa-90d5-f5d7f860b17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649685450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2649685450
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1822539271
Short name T822
Test name
Test status
Simulation time 23541352 ps
CPU time 0.74 seconds
Started Jul 13 05:26:51 PM PDT 24
Finished Jul 13 05:26:52 PM PDT 24
Peak memory 206584 kb
Host smart-d490014b-80dd-4a83-9463-4cd1c32db31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822539271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1822539271
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.600850566
Short name T1005
Test name
Test status
Simulation time 15605432464 ps
CPU time 10.74 seconds
Started Jul 13 05:26:51 PM PDT 24
Finished Jul 13 05:27:02 PM PDT 24
Peak memory 225564 kb
Host smart-34d63d6f-4c14-49bc-984a-6b5f65e568a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600850566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.600850566
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1037919918
Short name T576
Test name
Test status
Simulation time 12503780 ps
CPU time 0.7 seconds
Started Jul 13 05:34:36 PM PDT 24
Finished Jul 13 05:34:38 PM PDT 24
Peak memory 206356 kb
Host smart-4956e03d-274b-4edc-b734-efa9fd021721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037919918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1037919918
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1793267647
Short name T847
Test name
Test status
Simulation time 83909917 ps
CPU time 2.65 seconds
Started Jul 13 05:34:26 PM PDT 24
Finished Jul 13 05:34:30 PM PDT 24
Peak memory 233752 kb
Host smart-42896e5b-6e0a-4454-82c0-888ebc4fe8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793267647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1793267647
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2823287401
Short name T489
Test name
Test status
Simulation time 13879933 ps
CPU time 0.77 seconds
Started Jul 13 05:34:24 PM PDT 24
Finished Jul 13 05:34:26 PM PDT 24
Peak memory 207464 kb
Host smart-316e950f-eeee-4161-bc0e-026c12571ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823287401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2823287401
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.584240405
Short name T696
Test name
Test status
Simulation time 147043443299 ps
CPU time 147.18 seconds
Started Jul 13 05:34:35 PM PDT 24
Finished Jul 13 05:37:04 PM PDT 24
Peak memory 266588 kb
Host smart-997ef091-ec12-4168-992c-c3f441e3f47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584240405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.584240405
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1698459561
Short name T470
Test name
Test status
Simulation time 112594926266 ps
CPU time 163.27 seconds
Started Jul 13 05:34:38 PM PDT 24
Finished Jul 13 05:37:22 PM PDT 24
Peak memory 250284 kb
Host smart-7c3a311a-4bfe-4b04-a72c-799c2d08fa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698459561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1698459561
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2960909747
Short name T658
Test name
Test status
Simulation time 184056318584 ps
CPU time 412.84 seconds
Started Jul 13 05:34:36 PM PDT 24
Finished Jul 13 05:41:30 PM PDT 24
Peak memory 269020 kb
Host smart-7e1db541-da16-476f-952b-5158aee15861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960909747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2960909747
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3459421301
Short name T343
Test name
Test status
Simulation time 4139810155 ps
CPU time 35.65 seconds
Started Jul 13 05:34:34 PM PDT 24
Finished Jul 13 05:35:10 PM PDT 24
Peak memory 233912 kb
Host smart-f2e1a6a3-b1b5-4aa0-9406-1481012c8e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459421301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3459421301
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1145077701
Short name T376
Test name
Test status
Simulation time 31068127 ps
CPU time 0.77 seconds
Started Jul 13 05:34:36 PM PDT 24
Finished Jul 13 05:34:38 PM PDT 24
Peak memory 216908 kb
Host smart-2fa813fc-539e-4de1-b5f9-5cb977086861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145077701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1145077701
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.869297360
Short name T725
Test name
Test status
Simulation time 1040584120 ps
CPU time 12.42 seconds
Started Jul 13 05:34:26 PM PDT 24
Finished Jul 13 05:34:39 PM PDT 24
Peak memory 233752 kb
Host smart-6ed49406-cd62-4fe1-9497-ae7e4c00d0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869297360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.869297360
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3697147859
Short name T1023
Test name
Test status
Simulation time 32548390 ps
CPU time 2.11 seconds
Started Jul 13 05:34:29 PM PDT 24
Finished Jul 13 05:34:31 PM PDT 24
Peak memory 225460 kb
Host smart-a6e5d019-b9ac-42be-9937-a7bceaaa31c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697147859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3697147859
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1806698643
Short name T799
Test name
Test status
Simulation time 33268545 ps
CPU time 2.21 seconds
Started Jul 13 05:34:26 PM PDT 24
Finished Jul 13 05:34:29 PM PDT 24
Peak memory 233472 kb
Host smart-60a0087a-7d61-4c0b-8240-677db643bcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806698643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1806698643
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1623123661
Short name T743
Test name
Test status
Simulation time 2561822061 ps
CPU time 9.84 seconds
Started Jul 13 05:34:24 PM PDT 24
Finished Jul 13 05:34:34 PM PDT 24
Peak memory 241712 kb
Host smart-11ee164c-8801-46ba-995b-413534a43ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623123661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1623123661
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3097867736
Short name T323
Test name
Test status
Simulation time 129711818 ps
CPU time 4.06 seconds
Started Jul 13 05:34:35 PM PDT 24
Finished Jul 13 05:34:40 PM PDT 24
Peak memory 224180 kb
Host smart-706d8672-b5b0-405c-b98f-c29d890353a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3097867736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3097867736
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.220763293
Short name T284
Test name
Test status
Simulation time 5305936455 ps
CPU time 16.11 seconds
Started Jul 13 05:34:26 PM PDT 24
Finished Jul 13 05:34:42 PM PDT 24
Peak memory 217528 kb
Host smart-f35be6c3-b71f-4ec6-a2c6-e3e13a17ec49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220763293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.220763293
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2513158349
Short name T825
Test name
Test status
Simulation time 2808668105 ps
CPU time 12.76 seconds
Started Jul 13 05:34:25 PM PDT 24
Finished Jul 13 05:34:38 PM PDT 24
Peak memory 217520 kb
Host smart-f75f00ff-acac-45cb-9209-d14ac2ffa208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513158349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2513158349
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3710257486
Short name T369
Test name
Test status
Simulation time 63523924 ps
CPU time 1.5 seconds
Started Jul 13 05:34:25 PM PDT 24
Finished Jul 13 05:34:27 PM PDT 24
Peak memory 217404 kb
Host smart-82c4d5fa-05f5-465c-aaf7-94afbd7b3c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710257486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3710257486
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2839413351
Short name T835
Test name
Test status
Simulation time 106832484 ps
CPU time 0.83 seconds
Started Jul 13 05:34:25 PM PDT 24
Finished Jul 13 05:34:27 PM PDT 24
Peak memory 206944 kb
Host smart-0f30cf8e-759a-4880-b389-75298e5bdb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839413351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2839413351
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2767273293
Short name T367
Test name
Test status
Simulation time 19432174428 ps
CPU time 9.87 seconds
Started Jul 13 05:34:25 PM PDT 24
Finished Jul 13 05:34:35 PM PDT 24
Peak memory 225712 kb
Host smart-bd6690b3-9c0d-41e6-becd-e837fb7a1d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767273293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2767273293
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3987354318
Short name T361
Test name
Test status
Simulation time 37448722 ps
CPU time 0.72 seconds
Started Jul 13 05:34:35 PM PDT 24
Finished Jul 13 05:34:37 PM PDT 24
Peak memory 205800 kb
Host smart-db8c0050-3d99-48b9-91e9-04d1cdd86a84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987354318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3987354318
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3500216725
Short name T727
Test name
Test status
Simulation time 116249185 ps
CPU time 3.65 seconds
Started Jul 13 05:34:39 PM PDT 24
Finished Jul 13 05:34:43 PM PDT 24
Peak memory 233744 kb
Host smart-24f1150b-caa4-4f01-9b2b-0bd270fd285a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500216725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3500216725
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1915000571
Short name T909
Test name
Test status
Simulation time 64909018 ps
CPU time 0.77 seconds
Started Jul 13 05:34:35 PM PDT 24
Finished Jul 13 05:34:37 PM PDT 24
Peak memory 206480 kb
Host smart-bb5010c6-2b4c-4827-acfa-660db8d01bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915000571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1915000571
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2019510953
Short name T998
Test name
Test status
Simulation time 5202623636 ps
CPU time 46.67 seconds
Started Jul 13 05:34:36 PM PDT 24
Finished Jul 13 05:35:24 PM PDT 24
Peak memory 252536 kb
Host smart-09c7bf9b-e0c2-499f-8521-1b1f78b68e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019510953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2019510953
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2814763242
Short name T183
Test name
Test status
Simulation time 55200708367 ps
CPU time 403.24 seconds
Started Jul 13 05:34:35 PM PDT 24
Finished Jul 13 05:41:19 PM PDT 24
Peak memory 267548 kb
Host smart-fa43e300-180e-45f7-b00b-9b880abc0ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814763242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2814763242
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1947428270
Short name T182
Test name
Test status
Simulation time 4585538458 ps
CPU time 34.02 seconds
Started Jul 13 05:34:36 PM PDT 24
Finished Jul 13 05:35:12 PM PDT 24
Peak memory 250264 kb
Host smart-ba3acc10-cdd1-4fee-84ab-ffb81d3d619c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947428270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1947428270
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2740997579
Short name T278
Test name
Test status
Simulation time 2363216996 ps
CPU time 13.05 seconds
Started Jul 13 05:34:38 PM PDT 24
Finished Jul 13 05:34:52 PM PDT 24
Peak memory 242084 kb
Host smart-012ff99b-54c1-4801-a0c5-4e55190e27fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740997579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2740997579
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2395604317
Short name T92
Test name
Test status
Simulation time 35103111862 ps
CPU time 75.87 seconds
Started Jul 13 05:34:36 PM PDT 24
Finished Jul 13 05:35:53 PM PDT 24
Peak memory 250232 kb
Host smart-42d33020-b05c-460f-a38c-3c7795500674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395604317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2395604317
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.35837483
Short name T375
Test name
Test status
Simulation time 731563530 ps
CPU time 3.53 seconds
Started Jul 13 05:34:36 PM PDT 24
Finished Jul 13 05:34:41 PM PDT 24
Peak memory 225544 kb
Host smart-fd916473-ccf3-49d2-a1dd-d3c8aafc1eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35837483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.35837483
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1287601616
Short name T190
Test name
Test status
Simulation time 2109431693 ps
CPU time 17.41 seconds
Started Jul 13 05:34:36 PM PDT 24
Finished Jul 13 05:34:55 PM PDT 24
Peak memory 236172 kb
Host smart-e97254e8-7c97-48f2-95f0-56fd92619071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287601616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1287601616
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2242019441
Short name T911
Test name
Test status
Simulation time 241826134 ps
CPU time 5.24 seconds
Started Jul 13 05:34:36 PM PDT 24
Finished Jul 13 05:34:42 PM PDT 24
Peak memory 241904 kb
Host smart-e7b94c65-b8a0-4a9b-bf0b-ea78b71dba46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242019441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2242019441
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4276821344
Short name T1024
Test name
Test status
Simulation time 124018164 ps
CPU time 2.72 seconds
Started Jul 13 05:34:35 PM PDT 24
Finished Jul 13 05:34:39 PM PDT 24
Peak memory 233464 kb
Host smart-59282463-6983-4126-a7a9-b77800e0f8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276821344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4276821344
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.476907486
Short name T551
Test name
Test status
Simulation time 1915153665 ps
CPU time 3.95 seconds
Started Jul 13 05:34:34 PM PDT 24
Finished Jul 13 05:34:39 PM PDT 24
Peak memory 219916 kb
Host smart-cb590dd9-4e13-4140-a7b9-ab32319de3fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=476907486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.476907486
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2864828961
Short name T742
Test name
Test status
Simulation time 97484038 ps
CPU time 1.41 seconds
Started Jul 13 05:34:35 PM PDT 24
Finished Jul 13 05:34:37 PM PDT 24
Peak memory 217100 kb
Host smart-e308af90-3522-40b9-9190-bba3f6df61ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864828961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2864828961
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3666862199
Short name T898
Test name
Test status
Simulation time 4176434910 ps
CPU time 17.97 seconds
Started Jul 13 05:34:37 PM PDT 24
Finished Jul 13 05:34:56 PM PDT 24
Peak memory 220932 kb
Host smart-6d78b85f-e0aa-4e90-bf41-97497601943f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666862199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3666862199
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2860002075
Short name T545
Test name
Test status
Simulation time 649830848 ps
CPU time 2.01 seconds
Started Jul 13 05:34:35 PM PDT 24
Finished Jul 13 05:34:38 PM PDT 24
Peak memory 208924 kb
Host smart-88c3cd9f-1e21-4e89-904c-11465b5d38a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860002075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2860002075
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.124548633
Short name T745
Test name
Test status
Simulation time 292872185 ps
CPU time 1.44 seconds
Started Jul 13 05:34:35 PM PDT 24
Finished Jul 13 05:34:37 PM PDT 24
Peak memory 217364 kb
Host smart-f0272478-fe5a-4505-9785-c288783b4390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124548633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.124548633
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1451507002
Short name T559
Test name
Test status
Simulation time 444017868 ps
CPU time 1.07 seconds
Started Jul 13 05:34:38 PM PDT 24
Finished Jul 13 05:34:39 PM PDT 24
Peak memory 207988 kb
Host smart-81aa17a1-2d5d-4c79-a015-710171616cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451507002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1451507002
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1519200112
Short name T855
Test name
Test status
Simulation time 4661046074 ps
CPU time 17.09 seconds
Started Jul 13 05:34:38 PM PDT 24
Finished Jul 13 05:34:56 PM PDT 24
Peak memory 229700 kb
Host smart-3088c7fb-c911-4da7-b9ea-a28f79accbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519200112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1519200112
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.542476484
Short name T332
Test name
Test status
Simulation time 13181399 ps
CPU time 0.72 seconds
Started Jul 13 05:34:44 PM PDT 24
Finished Jul 13 05:34:45 PM PDT 24
Peak memory 206720 kb
Host smart-4e76ea5b-098f-432e-bb69-8736382e87af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542476484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.542476484
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.932784617
Short name T372
Test name
Test status
Simulation time 85521616 ps
CPU time 2.33 seconds
Started Jul 13 05:34:45 PM PDT 24
Finished Jul 13 05:34:48 PM PDT 24
Peak memory 233628 kb
Host smart-95584595-93a4-4e32-9d02-b952d4320ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932784617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.932784617
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1443864620
Short name T387
Test name
Test status
Simulation time 59148927 ps
CPU time 0.77 seconds
Started Jul 13 05:34:35 PM PDT 24
Finished Jul 13 05:34:36 PM PDT 24
Peak memory 206460 kb
Host smart-6d441bd5-8bc4-4ecf-9df1-ecbe03fb6594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443864620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1443864620
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.4156776544
Short name T922
Test name
Test status
Simulation time 3973442122 ps
CPU time 50.1 seconds
Started Jul 13 05:34:46 PM PDT 24
Finished Jul 13 05:35:37 PM PDT 24
Peak memory 242060 kb
Host smart-41fa49e6-db76-41bd-802c-357d0c2924b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156776544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.4156776544
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.4031714179
Short name T903
Test name
Test status
Simulation time 49585477038 ps
CPU time 409.35 seconds
Started Jul 13 05:34:49 PM PDT 24
Finished Jul 13 05:41:39 PM PDT 24
Peak memory 268584 kb
Host smart-d020a1d1-8e36-4512-9c7b-6689cf93f70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031714179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4031714179
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3090227909
Short name T186
Test name
Test status
Simulation time 63152313293 ps
CPU time 191.59 seconds
Started Jul 13 05:34:45 PM PDT 24
Finished Jul 13 05:37:57 PM PDT 24
Peak memory 269828 kb
Host smart-c28444fe-dd09-49e2-b5ab-ea535f8e0a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090227909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3090227909
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.106099418
Short name T990
Test name
Test status
Simulation time 199491821 ps
CPU time 6.78 seconds
Started Jul 13 05:34:49 PM PDT 24
Finished Jul 13 05:34:56 PM PDT 24
Peak memory 240044 kb
Host smart-cc423c9a-d4d5-4e3f-b4b9-351da7d5f7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106099418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.106099418
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3783462916
Short name T923
Test name
Test status
Simulation time 10280935580 ps
CPU time 135.85 seconds
Started Jul 13 05:34:45 PM PDT 24
Finished Jul 13 05:37:02 PM PDT 24
Peak memory 268804 kb
Host smart-3f05cf16-6704-4870-afda-21013ca29916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783462916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3783462916
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.443893831
Short name T461
Test name
Test status
Simulation time 1055061236 ps
CPU time 6.7 seconds
Started Jul 13 05:34:47 PM PDT 24
Finished Jul 13 05:34:54 PM PDT 24
Peak memory 225560 kb
Host smart-f22ef060-a1a4-4021-9ce7-9d31d24b4764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443893831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.443893831
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2749129886
Short name T714
Test name
Test status
Simulation time 424633836 ps
CPU time 9.09 seconds
Started Jul 13 05:34:46 PM PDT 24
Finished Jul 13 05:34:55 PM PDT 24
Peak memory 225508 kb
Host smart-ded78c57-3035-4db7-af18-07b7a5f7b268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749129886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2749129886
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2579096665
Short name T649
Test name
Test status
Simulation time 187911952 ps
CPU time 3.75 seconds
Started Jul 13 05:34:44 PM PDT 24
Finished Jul 13 05:34:48 PM PDT 24
Peak memory 233676 kb
Host smart-d314ca0d-0ef5-4208-8db9-d3f3aa2b95fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579096665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2579096665
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.971608530
Short name T317
Test name
Test status
Simulation time 919761273 ps
CPU time 4.62 seconds
Started Jul 13 05:34:45 PM PDT 24
Finished Jul 13 05:34:50 PM PDT 24
Peak memory 225596 kb
Host smart-a39cb68e-1d94-42c9-9030-d5921b4059a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971608530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.971608530
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.474085130
Short name T147
Test name
Test status
Simulation time 964757836 ps
CPU time 7.47 seconds
Started Jul 13 05:34:46 PM PDT 24
Finished Jul 13 05:34:54 PM PDT 24
Peak memory 223868 kb
Host smart-ee2fc273-4e5e-4324-a0e4-b8e00de46a13
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=474085130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.474085130
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.399496369
Short name T258
Test name
Test status
Simulation time 49571214345 ps
CPU time 514.34 seconds
Started Jul 13 05:34:46 PM PDT 24
Finished Jul 13 05:43:21 PM PDT 24
Peak memory 280716 kb
Host smart-39f7e16c-cabe-4b7e-a442-c59144785654
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399496369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.399496369
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.75047076
Short name T931
Test name
Test status
Simulation time 22010204981 ps
CPU time 28.91 seconds
Started Jul 13 05:34:36 PM PDT 24
Finished Jul 13 05:35:06 PM PDT 24
Peak memory 217484 kb
Host smart-1de2520a-eb16-43d1-900f-eca7440f7d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75047076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.75047076
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2360805066
Short name T366
Test name
Test status
Simulation time 1695544010 ps
CPU time 4.06 seconds
Started Jul 13 05:34:37 PM PDT 24
Finished Jul 13 05:34:42 PM PDT 24
Peak memory 217256 kb
Host smart-80f5e6d6-5bae-483d-b0dd-ff0ec5a81235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360805066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2360805066
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2312099463
Short name T788
Test name
Test status
Simulation time 37042171 ps
CPU time 0.69 seconds
Started Jul 13 05:34:46 PM PDT 24
Finished Jul 13 05:34:47 PM PDT 24
Peak memory 206312 kb
Host smart-6b66f87c-aedc-4b34-986e-178fadd4b1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312099463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2312099463
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3769449865
Short name T23
Test name
Test status
Simulation time 31550851 ps
CPU time 0.83 seconds
Started Jul 13 05:34:46 PM PDT 24
Finished Jul 13 05:34:47 PM PDT 24
Peak memory 206876 kb
Host smart-8dd0926c-a0ed-401d-8479-f963ff1b2d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769449865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3769449865
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3180362514
Short name T88
Test name
Test status
Simulation time 171912942 ps
CPU time 4.03 seconds
Started Jul 13 05:34:47 PM PDT 24
Finished Jul 13 05:34:51 PM PDT 24
Peak memory 225576 kb
Host smart-91a9257d-f179-4314-a32b-502842f8b820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180362514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3180362514
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1220230524
Short name T684
Test name
Test status
Simulation time 11214269 ps
CPU time 0.76 seconds
Started Jul 13 05:34:56 PM PDT 24
Finished Jul 13 05:34:57 PM PDT 24
Peak memory 205792 kb
Host smart-23d40311-62c3-449b-ae57-de04111bc3fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220230524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1220230524
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2992738937
Short name T232
Test name
Test status
Simulation time 4473060340 ps
CPU time 5.36 seconds
Started Jul 13 05:37:51 PM PDT 24
Finished Jul 13 05:37:57 PM PDT 24
Peak memory 225896 kb
Host smart-343c134c-3fe3-4e6e-a86b-a45a5aa7c5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992738937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2992738937
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3980892936
Short name T290
Test name
Test status
Simulation time 20776292 ps
CPU time 0.78 seconds
Started Jul 13 05:34:44 PM PDT 24
Finished Jul 13 05:34:45 PM PDT 24
Peak memory 207512 kb
Host smart-e6b1489c-0e83-4867-ac5c-6e0349e1f2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980892936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3980892936
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.823354475
Short name T888
Test name
Test status
Simulation time 4106668413 ps
CPU time 55.07 seconds
Started Jul 13 05:34:54 PM PDT 24
Finished Jul 13 05:35:50 PM PDT 24
Peak memory 254956 kb
Host smart-ccdaebe3-d6ef-43ab-a527-827ff6917b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823354475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.823354475
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2192828472
Short name T288
Test name
Test status
Simulation time 20791374135 ps
CPU time 247.07 seconds
Started Jul 13 05:34:57 PM PDT 24
Finished Jul 13 05:39:04 PM PDT 24
Peak memory 257440 kb
Host smart-3d9bc9db-fe16-4dec-bf19-a99d8a13ba13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192828472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2192828472
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1222547044
Short name T604
Test name
Test status
Simulation time 5571640916 ps
CPU time 40.37 seconds
Started Jul 13 05:34:57 PM PDT 24
Finished Jul 13 05:35:37 PM PDT 24
Peak memory 253132 kb
Host smart-6b52c8d9-e6fb-4eeb-a45e-5a3962c40e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222547044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1222547044
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2458341388
Short name T839
Test name
Test status
Simulation time 33468691 ps
CPU time 2.52 seconds
Started Jul 13 05:34:54 PM PDT 24
Finished Jul 13 05:34:57 PM PDT 24
Peak memory 225568 kb
Host smart-93103a85-78b5-4236-93da-fe1db088100b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458341388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2458341388
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.4164347596
Short name T893
Test name
Test status
Simulation time 5194935048 ps
CPU time 45.8 seconds
Started Jul 13 05:34:54 PM PDT 24
Finished Jul 13 05:35:40 PM PDT 24
Peak memory 250288 kb
Host smart-7e4c6682-7157-4f67-8842-483635d235f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164347596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.4164347596
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3054855141
Short name T396
Test name
Test status
Simulation time 1449099038 ps
CPU time 5.6 seconds
Started Jul 13 05:34:54 PM PDT 24
Finished Jul 13 05:35:00 PM PDT 24
Peak memory 225528 kb
Host smart-9ba43c57-ff94-4325-a6dd-60ef29afe00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054855141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3054855141
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3238120629
Short name T659
Test name
Test status
Simulation time 7527942224 ps
CPU time 25.93 seconds
Started Jul 13 05:34:54 PM PDT 24
Finished Jul 13 05:35:20 PM PDT 24
Peak memory 233828 kb
Host smart-20c19d71-84dc-43e4-a21c-68c791ff8d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238120629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3238120629
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2055104311
Short name T900
Test name
Test status
Simulation time 561578600 ps
CPU time 5.48 seconds
Started Jul 13 05:34:46 PM PDT 24
Finished Jul 13 05:34:52 PM PDT 24
Peak memory 233660 kb
Host smart-c91f0e26-18ac-4079-9111-d69ba0483395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055104311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2055104311
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2697240191
Short name T848
Test name
Test status
Simulation time 1490756148 ps
CPU time 8.34 seconds
Started Jul 13 05:34:44 PM PDT 24
Finished Jul 13 05:34:52 PM PDT 24
Peak memory 241708 kb
Host smart-467bdb9c-6bca-48a7-98f2-03dd713ed1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697240191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2697240191
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1819840528
Short name T150
Test name
Test status
Simulation time 921283019 ps
CPU time 7.52 seconds
Started Jul 13 05:34:55 PM PDT 24
Finished Jul 13 05:35:03 PM PDT 24
Peak memory 220276 kb
Host smart-1bb0a102-11be-4a9b-9d4b-49176a1d7a45
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1819840528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1819840528
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.320117632
Short name T283
Test name
Test status
Simulation time 2151635870 ps
CPU time 17.35 seconds
Started Jul 13 05:34:49 PM PDT 24
Finished Jul 13 05:35:07 PM PDT 24
Peak memory 217580 kb
Host smart-2b2b05c4-68d9-4e64-819d-366f8e3f79d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320117632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.320117632
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3838100761
Short name T33
Test name
Test status
Simulation time 1689356475 ps
CPU time 7.11 seconds
Started Jul 13 05:34:44 PM PDT 24
Finished Jul 13 05:34:52 PM PDT 24
Peak memory 217284 kb
Host smart-51aa88ed-02eb-42cb-b206-5279ac80d73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838100761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3838100761
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.351082027
Short name T78
Test name
Test status
Simulation time 63769679 ps
CPU time 0.68 seconds
Started Jul 13 05:34:44 PM PDT 24
Finished Jul 13 05:34:45 PM PDT 24
Peak memory 206492 kb
Host smart-a928daad-0d2c-400a-b4c8-687b205268d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351082027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.351082027
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1889073778
Short name T610
Test name
Test status
Simulation time 120365255 ps
CPU time 0.84 seconds
Started Jul 13 05:34:44 PM PDT 24
Finished Jul 13 05:34:46 PM PDT 24
Peak memory 206956 kb
Host smart-b03fc55b-9519-4db8-9dbc-5a417ba30297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889073778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1889073778
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2456744970
Short name T12
Test name
Test status
Simulation time 7240578652 ps
CPU time 9.16 seconds
Started Jul 13 05:34:54 PM PDT 24
Finished Jul 13 05:35:04 PM PDT 24
Peak memory 233848 kb
Host smart-2070a8c7-dd03-4d47-b150-edac4cc58d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456744970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2456744970
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3483296960
Short name T721
Test name
Test status
Simulation time 10986954 ps
CPU time 0.73 seconds
Started Jul 13 05:35:14 PM PDT 24
Finished Jul 13 05:35:15 PM PDT 24
Peak memory 206720 kb
Host smart-08dd9ee6-46d6-4147-97ca-5f4cb13f65a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483296960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3483296960
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1946805256
Short name T181
Test name
Test status
Simulation time 618005982 ps
CPU time 4.9 seconds
Started Jul 13 05:35:04 PM PDT 24
Finished Jul 13 05:35:09 PM PDT 24
Peak memory 233748 kb
Host smart-95397383-f1ee-4854-90e1-32e230012b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946805256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1946805256
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1823383749
Short name T391
Test name
Test status
Simulation time 57350837 ps
CPU time 0.75 seconds
Started Jul 13 05:34:55 PM PDT 24
Finished Jul 13 05:34:56 PM PDT 24
Peak memory 206472 kb
Host smart-169fd782-0b19-4327-b7a5-abe83aa21c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823383749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1823383749
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2094698078
Short name T867
Test name
Test status
Simulation time 989707513 ps
CPU time 10.76 seconds
Started Jul 13 05:35:06 PM PDT 24
Finished Jul 13 05:35:16 PM PDT 24
Peak memory 225548 kb
Host smart-29b8b78c-5390-4308-9e90-30a2701cea7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094698078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2094698078
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3371926604
Short name T882
Test name
Test status
Simulation time 88666373598 ps
CPU time 187.75 seconds
Started Jul 13 05:35:04 PM PDT 24
Finished Jul 13 05:38:12 PM PDT 24
Peak memory 250368 kb
Host smart-9aae9e47-efe8-4455-b750-b1ac8da94d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371926604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3371926604
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3334195640
Short name T803
Test name
Test status
Simulation time 30051790716 ps
CPU time 62.98 seconds
Started Jul 13 05:35:04 PM PDT 24
Finished Jul 13 05:36:08 PM PDT 24
Peak memory 242244 kb
Host smart-5c7b7233-b777-4572-a937-ae7f57c5a1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334195640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3334195640
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1586743707
Short name T877
Test name
Test status
Simulation time 7630783422 ps
CPU time 18.39 seconds
Started Jul 13 05:35:04 PM PDT 24
Finished Jul 13 05:35:22 PM PDT 24
Peak memory 237768 kb
Host smart-c8400889-18c3-4ac8-b348-2517889c26e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586743707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1586743707
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3960006377
Short name T197
Test name
Test status
Simulation time 8646873915 ps
CPU time 116.12 seconds
Started Jul 13 05:35:05 PM PDT 24
Finished Jul 13 05:37:01 PM PDT 24
Peak memory 267588 kb
Host smart-a58baa7e-8812-42b0-94f4-afd7c8cd4cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960006377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3960006377
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2431343113
Short name T663
Test name
Test status
Simulation time 10410261042 ps
CPU time 21.7 seconds
Started Jul 13 05:35:03 PM PDT 24
Finished Jul 13 05:35:25 PM PDT 24
Peak memory 233900 kb
Host smart-2fd4749d-0785-4a71-a946-db1ab16b733c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431343113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2431343113
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1618176341
Short name T187
Test name
Test status
Simulation time 13119075064 ps
CPU time 149.19 seconds
Started Jul 13 05:35:05 PM PDT 24
Finished Jul 13 05:37:35 PM PDT 24
Peak memory 233872 kb
Host smart-932f4162-71ed-49d5-bbd0-3525362fea77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618176341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1618176341
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1924848861
Short name T208
Test name
Test status
Simulation time 7119601600 ps
CPU time 21.82 seconds
Started Jul 13 05:34:54 PM PDT 24
Finished Jul 13 05:35:17 PM PDT 24
Peak memory 233880 kb
Host smart-32988a2e-bcb8-48ca-923f-6ed0abb23afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924848861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1924848861
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2454015849
Short name T325
Test name
Test status
Simulation time 310162267 ps
CPU time 4.26 seconds
Started Jul 13 05:34:54 PM PDT 24
Finished Jul 13 05:34:59 PM PDT 24
Peak memory 233736 kb
Host smart-4a6b0ee9-0973-4647-a1f1-f6db6c6ac9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454015849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2454015849
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.494361822
Short name T4
Test name
Test status
Simulation time 1111283971 ps
CPU time 11.62 seconds
Started Jul 13 05:35:03 PM PDT 24
Finished Jul 13 05:35:15 PM PDT 24
Peak memory 223012 kb
Host smart-a45eb3b8-d0c2-4363-bbb3-072a664fc27b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=494361822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.494361822
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.515574818
Short name T422
Test name
Test status
Simulation time 13766644271 ps
CPU time 28.74 seconds
Started Jul 13 05:34:54 PM PDT 24
Finished Jul 13 05:35:23 PM PDT 24
Peak memory 217604 kb
Host smart-6e852a55-2c5b-4537-83d5-78284c4b5852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515574818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.515574818
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1082849924
Short name T808
Test name
Test status
Simulation time 15202934391 ps
CPU time 16.48 seconds
Started Jul 13 05:34:55 PM PDT 24
Finished Jul 13 05:35:12 PM PDT 24
Peak memory 217484 kb
Host smart-03060e57-27cc-4000-beec-b3b8d4aedca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082849924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1082849924
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2370369522
Short name T346
Test name
Test status
Simulation time 46628030 ps
CPU time 1.18 seconds
Started Jul 13 05:34:57 PM PDT 24
Finished Jul 13 05:34:58 PM PDT 24
Peak memory 217308 kb
Host smart-3af44d72-17ca-4987-a7fa-7c86f070a5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370369522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2370369522
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3183105739
Short name T673
Test name
Test status
Simulation time 117439475 ps
CPU time 0.74 seconds
Started Jul 13 05:34:54 PM PDT 24
Finished Jul 13 05:34:55 PM PDT 24
Peak memory 206956 kb
Host smart-d7d4dae9-6f69-4f0b-a7bf-cc86318e41dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183105739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3183105739
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.415534780
Short name T240
Test name
Test status
Simulation time 10255565996 ps
CPU time 10.36 seconds
Started Jul 13 05:35:04 PM PDT 24
Finished Jul 13 05:35:15 PM PDT 24
Peak memory 225608 kb
Host smart-572acd65-d714-46f8-b154-5eed7fc1ac59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415534780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.415534780
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2166949622
Short name T454
Test name
Test status
Simulation time 21117243 ps
CPU time 0.73 seconds
Started Jul 13 05:35:16 PM PDT 24
Finished Jul 13 05:35:18 PM PDT 24
Peak memory 205808 kb
Host smart-7953e1a6-2935-4671-95c2-e4c928989a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166949622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2166949622
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.4072447550
Short name T472
Test name
Test status
Simulation time 608903666 ps
CPU time 3.35 seconds
Started Jul 13 05:35:17 PM PDT 24
Finished Jul 13 05:35:21 PM PDT 24
Peak memory 225776 kb
Host smart-75684de0-e0d3-43bf-857b-b7b7051d4693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072447550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.4072447550
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3156533254
Short name T601
Test name
Test status
Simulation time 109026345 ps
CPU time 0.76 seconds
Started Jul 13 05:35:16 PM PDT 24
Finished Jul 13 05:35:17 PM PDT 24
Peak memory 207536 kb
Host smart-c8893db8-7bc2-4ccb-889c-f49c41bf9549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156533254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3156533254
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1337727573
Short name T595
Test name
Test status
Simulation time 23511702092 ps
CPU time 177.57 seconds
Started Jul 13 05:35:17 PM PDT 24
Finished Jul 13 05:38:16 PM PDT 24
Peak memory 251236 kb
Host smart-f08640bd-d9d2-4fe0-a493-54a4a5276a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337727573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1337727573
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1986781839
Short name T925
Test name
Test status
Simulation time 3058400766 ps
CPU time 80.22 seconds
Started Jul 13 05:35:16 PM PDT 24
Finished Jul 13 05:36:38 PM PDT 24
Peak memory 253476 kb
Host smart-75834a89-c87d-48ac-a114-ba19d6ffb9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986781839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1986781839
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1519945448
Short name T444
Test name
Test status
Simulation time 20093328396 ps
CPU time 47.34 seconds
Started Jul 13 05:35:16 PM PDT 24
Finished Jul 13 05:36:04 PM PDT 24
Peak memory 242180 kb
Host smart-71c6db21-4f28-470d-b99e-60464d3d1333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519945448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1519945448
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.539243575
Short name T836
Test name
Test status
Simulation time 285829837 ps
CPU time 3.29 seconds
Started Jul 13 05:35:14 PM PDT 24
Finished Jul 13 05:35:18 PM PDT 24
Peak memory 225532 kb
Host smart-bce3895d-2739-4154-9c4f-dc6f31f407b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539243575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.539243575
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1500237128
Short name T651
Test name
Test status
Simulation time 21681638079 ps
CPU time 95.95 seconds
Started Jul 13 05:35:15 PM PDT 24
Finished Jul 13 05:36:51 PM PDT 24
Peak memory 250280 kb
Host smart-445b7527-4a96-4412-aa16-e283ceb55f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500237128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1500237128
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1775513361
Short name T575
Test name
Test status
Simulation time 305719510 ps
CPU time 4.16 seconds
Started Jul 13 05:35:17 PM PDT 24
Finished Jul 13 05:35:22 PM PDT 24
Peak memory 225592 kb
Host smart-b1cbe7d8-de10-4d25-8436-87f5f56db1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775513361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1775513361
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2029620850
Short name T357
Test name
Test status
Simulation time 12080132315 ps
CPU time 61.09 seconds
Started Jul 13 05:35:15 PM PDT 24
Finished Jul 13 05:36:17 PM PDT 24
Peak memory 240160 kb
Host smart-cf2363c3-185f-4fbc-b1d2-c935f1e47bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029620850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2029620850
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3198720414
Short name T13
Test name
Test status
Simulation time 5470037657 ps
CPU time 16.55 seconds
Started Jul 13 05:35:13 PM PDT 24
Finished Jul 13 05:35:30 PM PDT 24
Peak memory 225656 kb
Host smart-cc38dabe-d5d4-464b-a9d7-6c4aeb1d2f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198720414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3198720414
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2733921979
Short name T504
Test name
Test status
Simulation time 428030015 ps
CPU time 6.66 seconds
Started Jul 13 05:35:17 PM PDT 24
Finished Jul 13 05:35:25 PM PDT 24
Peak memory 225632 kb
Host smart-16e0b69e-c402-462b-8e6d-59ec9b2ba19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733921979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2733921979
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.950861185
Short name T754
Test name
Test status
Simulation time 4506688966 ps
CPU time 9.81 seconds
Started Jul 13 05:35:15 PM PDT 24
Finished Jul 13 05:35:25 PM PDT 24
Peak memory 223292 kb
Host smart-61c3463a-23a2-40e0-a4a8-7d55654a7249
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=950861185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.950861185
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.165788363
Short name T21
Test name
Test status
Simulation time 3049611076 ps
CPU time 23.03 seconds
Started Jul 13 05:35:16 PM PDT 24
Finished Jul 13 05:35:40 PM PDT 24
Peak memory 225972 kb
Host smart-43dad787-0b0e-4976-8d47-aa0a52ae3cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165788363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.165788363
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.581876047
Short name T1011
Test name
Test status
Simulation time 13651395927 ps
CPU time 10.91 seconds
Started Jul 13 05:35:16 PM PDT 24
Finished Jul 13 05:35:29 PM PDT 24
Peak memory 217380 kb
Host smart-af68a82f-683f-46e1-8f46-1e5a7aa1df9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581876047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.581876047
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2475677481
Short name T977
Test name
Test status
Simulation time 10796336514 ps
CPU time 9.01 seconds
Started Jul 13 05:35:17 PM PDT 24
Finished Jul 13 05:35:27 PM PDT 24
Peak memory 217500 kb
Host smart-4c0267c6-6c9d-4e9a-817f-60d2995807cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475677481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2475677481
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3572778842
Short name T876
Test name
Test status
Simulation time 78750826 ps
CPU time 1.05 seconds
Started Jul 13 05:35:15 PM PDT 24
Finished Jul 13 05:35:17 PM PDT 24
Peak memory 208496 kb
Host smart-a1a1b208-61b5-4b9b-b156-0f5a7ddd423f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572778842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3572778842
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2078139677
Short name T38
Test name
Test status
Simulation time 18106306 ps
CPU time 0.76 seconds
Started Jul 13 05:35:12 PM PDT 24
Finished Jul 13 05:35:13 PM PDT 24
Peak memory 206956 kb
Host smart-9ea3e664-cab1-4a2c-b0b7-d2a88bce2aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078139677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2078139677
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1834767578
Short name T188
Test name
Test status
Simulation time 28097803828 ps
CPU time 43.14 seconds
Started Jul 13 05:35:14 PM PDT 24
Finished Jul 13 05:35:58 PM PDT 24
Peak memory 233884 kb
Host smart-5ed6cbc7-c4b7-45af-80cc-3b64127fa218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834767578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1834767578
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1309373318
Short name T321
Test name
Test status
Simulation time 37920111 ps
CPU time 0.74 seconds
Started Jul 13 05:35:25 PM PDT 24
Finished Jul 13 05:35:26 PM PDT 24
Peak memory 206144 kb
Host smart-948478bc-d3e9-4777-830f-1c9cf30663a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309373318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1309373318
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3916445249
Short name T1020
Test name
Test status
Simulation time 3613059849 ps
CPU time 4.45 seconds
Started Jul 13 05:35:27 PM PDT 24
Finished Jul 13 05:35:33 PM PDT 24
Peak memory 225660 kb
Host smart-2f1cfc13-b84f-452c-987a-8874559e0551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916445249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3916445249
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2999059202
Short name T596
Test name
Test status
Simulation time 28662461 ps
CPU time 0.79 seconds
Started Jul 13 05:35:16 PM PDT 24
Finished Jul 13 05:35:18 PM PDT 24
Peak memory 206492 kb
Host smart-cab16273-7ebf-4297-81e0-d9181b1211ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999059202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2999059202
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.135390581
Short name T620
Test name
Test status
Simulation time 141548360651 ps
CPU time 86.64 seconds
Started Jul 13 05:35:26 PM PDT 24
Finished Jul 13 05:36:54 PM PDT 24
Peak memory 254028 kb
Host smart-25894003-43f4-4e1c-bc3d-c7dc418cd49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135390581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.135390581
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.4238256691
Short name T265
Test name
Test status
Simulation time 34881087660 ps
CPU time 132.79 seconds
Started Jul 13 05:35:26 PM PDT 24
Finished Jul 13 05:37:39 PM PDT 24
Peak memory 273404 kb
Host smart-4164dd3b-3949-4209-a9de-9094856e502e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238256691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.4238256691
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3292778498
Short name T722
Test name
Test status
Simulation time 1519926254 ps
CPU time 20.71 seconds
Started Jul 13 05:35:27 PM PDT 24
Finished Jul 13 05:35:50 PM PDT 24
Peak memory 225632 kb
Host smart-cec572d0-ee68-4325-a1e8-f37f29abd547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292778498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3292778498
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1416610608
Short name T764
Test name
Test status
Simulation time 315111511 ps
CPU time 8 seconds
Started Jul 13 05:35:27 PM PDT 24
Finished Jul 13 05:35:36 PM PDT 24
Peak memory 236260 kb
Host smart-afab929b-6fbb-43b4-8c0a-ac67afbf046b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416610608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1416610608
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.110922935
Short name T606
Test name
Test status
Simulation time 9727744220 ps
CPU time 17.21 seconds
Started Jul 13 05:35:25 PM PDT 24
Finished Jul 13 05:35:43 PM PDT 24
Peak memory 237952 kb
Host smart-bd89e3f7-6683-428d-b0ce-c3c3d4bb367a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110922935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.110922935
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.687527373
Short name T494
Test name
Test status
Simulation time 739248332 ps
CPU time 4.66 seconds
Started Jul 13 05:35:27 PM PDT 24
Finished Jul 13 05:35:34 PM PDT 24
Peak memory 225516 kb
Host smart-88290b88-c91f-4d13-a924-7e819795ce38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687527373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.687527373
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2337194270
Short name T694
Test name
Test status
Simulation time 10819342496 ps
CPU time 104.92 seconds
Started Jul 13 05:35:25 PM PDT 24
Finished Jul 13 05:37:10 PM PDT 24
Peak memory 236452 kb
Host smart-b3fd9653-1f39-4ea1-8874-88e136e55cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337194270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2337194270
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1112229171
Short name T529
Test name
Test status
Simulation time 109936521 ps
CPU time 2.43 seconds
Started Jul 13 05:35:26 PM PDT 24
Finished Jul 13 05:35:29 PM PDT 24
Peak memory 225532 kb
Host smart-6661e306-a0b3-42e0-abc6-bce5a3b082ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112229171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1112229171
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2252491563
Short name T969
Test name
Test status
Simulation time 3396777585 ps
CPU time 15.96 seconds
Started Jul 13 05:35:27 PM PDT 24
Finished Jul 13 05:35:44 PM PDT 24
Peak memory 233804 kb
Host smart-ffa92642-e200-4e04-8798-85e316754318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252491563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2252491563
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2407462169
Short name T354
Test name
Test status
Simulation time 5871254916 ps
CPU time 9.81 seconds
Started Jul 13 05:35:26 PM PDT 24
Finished Jul 13 05:35:36 PM PDT 24
Peak memory 220116 kb
Host smart-0efa69c6-66f2-427a-9a23-558a6fb723ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2407462169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2407462169
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4074551966
Short name T17
Test name
Test status
Simulation time 61901375311 ps
CPU time 319.31 seconds
Started Jul 13 05:35:25 PM PDT 24
Finished Jul 13 05:40:46 PM PDT 24
Peak memory 254412 kb
Host smart-f2992390-3f5d-4cb3-b3bc-1864d47005f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074551966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4074551966
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.953625630
Short name T1027
Test name
Test status
Simulation time 19700977159 ps
CPU time 29.34 seconds
Started Jul 13 05:35:16 PM PDT 24
Finished Jul 13 05:35:45 PM PDT 24
Peak memory 217444 kb
Host smart-b4e1b935-9a2e-40da-a948-29c21c37c73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953625630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.953625630
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.439697601
Short name T523
Test name
Test status
Simulation time 856462443 ps
CPU time 5.86 seconds
Started Jul 13 05:35:16 PM PDT 24
Finished Jul 13 05:35:22 PM PDT 24
Peak memory 217408 kb
Host smart-8f227314-38bb-498b-a955-5fa9542a3a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439697601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.439697601
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2799037760
Short name T638
Test name
Test status
Simulation time 84812941 ps
CPU time 1 seconds
Started Jul 13 05:35:13 PM PDT 24
Finished Jul 13 05:35:15 PM PDT 24
Peak memory 208412 kb
Host smart-6f6b8fd4-c8dd-42b4-be5b-b97d5d5b8b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799037760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2799037760
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2393855406
Short name T579
Test name
Test status
Simulation time 291144363 ps
CPU time 0.92 seconds
Started Jul 13 05:35:14 PM PDT 24
Finished Jul 13 05:35:15 PM PDT 24
Peak memory 206904 kb
Host smart-bd016e4f-2926-434a-aace-cedf18452f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393855406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2393855406
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.767548775
Short name T229
Test name
Test status
Simulation time 2278208339 ps
CPU time 10.5 seconds
Started Jul 13 05:35:26 PM PDT 24
Finished Jul 13 05:35:38 PM PDT 24
Peak memory 233796 kb
Host smart-7469a653-d1f5-4f36-bcc1-2e8996c027fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767548775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.767548775
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3640969833
Short name T827
Test name
Test status
Simulation time 92044250 ps
CPU time 0.7 seconds
Started Jul 13 05:35:39 PM PDT 24
Finished Jul 13 05:35:40 PM PDT 24
Peak memory 206368 kb
Host smart-7ab8588a-074c-4344-b4c9-577e15cf84d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640969833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3640969833
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2637778026
Short name T90
Test name
Test status
Simulation time 3559798977 ps
CPU time 7.13 seconds
Started Jul 13 05:35:27 PM PDT 24
Finished Jul 13 05:35:35 PM PDT 24
Peak memory 225736 kb
Host smart-b7827e64-7ed0-42ee-9306-df66733cc2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637778026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2637778026
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1344776931
Short name T794
Test name
Test status
Simulation time 41608937 ps
CPU time 0.78 seconds
Started Jul 13 05:35:27 PM PDT 24
Finished Jul 13 05:35:29 PM PDT 24
Peak memory 206460 kb
Host smart-8445521d-b579-40a1-bd3d-579aff7679f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344776931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1344776931
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1517259719
Short name T52
Test name
Test status
Simulation time 10084036565 ps
CPU time 85.9 seconds
Started Jul 13 05:35:40 PM PDT 24
Finished Jul 13 05:37:07 PM PDT 24
Peak memory 250276 kb
Host smart-95ce7a72-a8e3-417d-bb74-4c470cd711bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517259719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1517259719
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1586241088
Short name T257
Test name
Test status
Simulation time 13203434250 ps
CPU time 65.65 seconds
Started Jul 13 05:35:41 PM PDT 24
Finished Jul 13 05:36:47 PM PDT 24
Peak memory 252980 kb
Host smart-b45580ff-5b1c-423d-aaf8-0e89366a4fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586241088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1586241088
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1692009392
Short name T881
Test name
Test status
Simulation time 26269469854 ps
CPU time 88.1 seconds
Started Jul 13 05:35:37 PM PDT 24
Finished Jul 13 05:37:06 PM PDT 24
Peak memory 250320 kb
Host smart-a94484ab-7853-45bf-937d-e86a0df0d76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692009392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1692009392
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3889021119
Short name T999
Test name
Test status
Simulation time 7490555771 ps
CPU time 14.91 seconds
Started Jul 13 05:35:25 PM PDT 24
Finished Jul 13 05:35:41 PM PDT 24
Peak memory 237824 kb
Host smart-ff22b8af-7fac-4b37-b0ca-408278f75e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889021119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3889021119
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2279495984
Short name T536
Test name
Test status
Simulation time 9153151822 ps
CPU time 92.74 seconds
Started Jul 13 05:35:26 PM PDT 24
Finished Jul 13 05:37:00 PM PDT 24
Peak memory 250232 kb
Host smart-36720bb9-3753-4c98-9035-c90183abe1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279495984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2279495984
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3575709112
Short name T418
Test name
Test status
Simulation time 4918450465 ps
CPU time 9.77 seconds
Started Jul 13 05:35:26 PM PDT 24
Finished Jul 13 05:35:37 PM PDT 24
Peak memory 225648 kb
Host smart-98af8e6f-6f9e-437b-b021-c51d460afb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575709112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3575709112
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1001895534
Short name T802
Test name
Test status
Simulation time 289387089 ps
CPU time 2.27 seconds
Started Jul 13 05:35:26 PM PDT 24
Finished Jul 13 05:35:29 PM PDT 24
Peak memory 225476 kb
Host smart-fe1b4cea-d989-46b3-b2f2-dc6e128682ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001895534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1001895534
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3646335956
Short name T245
Test name
Test status
Simulation time 356838842 ps
CPU time 3.89 seconds
Started Jul 13 05:35:27 PM PDT 24
Finished Jul 13 05:35:32 PM PDT 24
Peak memory 233704 kb
Host smart-1b250e99-b226-4641-964b-59711f5db585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646335956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3646335956
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.565399050
Short name T598
Test name
Test status
Simulation time 4367255281 ps
CPU time 9.38 seconds
Started Jul 13 05:35:27 PM PDT 24
Finished Jul 13 05:35:38 PM PDT 24
Peak memory 233876 kb
Host smart-6b3c1dca-ee7f-4707-a9f7-60bc7fdb25b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565399050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.565399050
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2206427971
Short name T524
Test name
Test status
Simulation time 699036691 ps
CPU time 6.57 seconds
Started Jul 13 05:35:25 PM PDT 24
Finished Jul 13 05:35:33 PM PDT 24
Peak memory 220256 kb
Host smart-16634e67-51c8-42e1-9ade-b7cdbdd5cf52
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2206427971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2206427971
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2438520808
Short name T874
Test name
Test status
Simulation time 1564777212 ps
CPU time 18.11 seconds
Started Jul 13 05:35:26 PM PDT 24
Finished Jul 13 05:35:44 PM PDT 24
Peak memory 217408 kb
Host smart-67d5ce31-92f7-474f-82c6-c1de1ca7a5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438520808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2438520808
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1565462263
Short name T826
Test name
Test status
Simulation time 8804340701 ps
CPU time 7.92 seconds
Started Jul 13 05:35:26 PM PDT 24
Finished Jul 13 05:35:35 PM PDT 24
Peak memory 217400 kb
Host smart-4cc1b982-6fde-4849-86cb-15d100522c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565462263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1565462263
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1701746362
Short name T386
Test name
Test status
Simulation time 23104529 ps
CPU time 0.85 seconds
Started Jul 13 05:35:25 PM PDT 24
Finished Jul 13 05:35:27 PM PDT 24
Peak memory 207588 kb
Host smart-021051df-4c98-4bd1-b87d-0fc589fd61a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701746362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1701746362
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1049024114
Short name T829
Test name
Test status
Simulation time 102623265 ps
CPU time 0.86 seconds
Started Jul 13 05:35:27 PM PDT 24
Finished Jul 13 05:35:30 PM PDT 24
Peak memory 206908 kb
Host smart-3c148e7c-0266-479c-a862-b50b116bf24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049024114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1049024114
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3295586384
Short name T377
Test name
Test status
Simulation time 3269844261 ps
CPU time 4.84 seconds
Started Jul 13 05:35:27 PM PDT 24
Finished Jul 13 05:35:34 PM PDT 24
Peak memory 225652 kb
Host smart-f75a5a53-379d-4f15-a139-c8d1b0285f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295586384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3295586384
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3517326170
Short name T602
Test name
Test status
Simulation time 50863654 ps
CPU time 0.73 seconds
Started Jul 13 05:35:37 PM PDT 24
Finished Jul 13 05:35:39 PM PDT 24
Peak memory 206400 kb
Host smart-cfc75daf-98fd-448f-aca1-f7286cf0ad43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517326170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3517326170
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3762893102
Short name T436
Test name
Test status
Simulation time 378700189 ps
CPU time 4.77 seconds
Started Jul 13 05:35:39 PM PDT 24
Finished Jul 13 05:35:44 PM PDT 24
Peak memory 233740 kb
Host smart-047849f6-9dae-4ccf-8bcc-7fa0245544da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762893102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3762893102
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3735990508
Short name T979
Test name
Test status
Simulation time 33860038 ps
CPU time 0.83 seconds
Started Jul 13 05:35:41 PM PDT 24
Finished Jul 13 05:35:42 PM PDT 24
Peak memory 207496 kb
Host smart-43443a3c-927c-4fba-a1ef-4d2204b9eb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735990508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3735990508
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1811899883
Short name T241
Test name
Test status
Simulation time 6603635991 ps
CPU time 55.46 seconds
Started Jul 13 05:35:38 PM PDT 24
Finished Jul 13 05:36:35 PM PDT 24
Peak memory 242100 kb
Host smart-224d55f2-15b1-4ab9-9fab-c959749acc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811899883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1811899883
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1626321717
Short name T775
Test name
Test status
Simulation time 10145128268 ps
CPU time 175.76 seconds
Started Jul 13 05:35:37 PM PDT 24
Finished Jul 13 05:38:34 PM PDT 24
Peak memory 257240 kb
Host smart-4480b027-1dab-4243-9c19-b4bd3f646169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626321717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1626321717
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2056640022
Short name T247
Test name
Test status
Simulation time 18013286527 ps
CPU time 104.76 seconds
Started Jul 13 05:35:36 PM PDT 24
Finished Jul 13 05:37:22 PM PDT 24
Peak memory 263568 kb
Host smart-afb6ffee-782d-4e88-b165-e4c48ce78699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056640022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2056640022
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1458853000
Short name T643
Test name
Test status
Simulation time 18238085890 ps
CPU time 29.02 seconds
Started Jul 13 05:35:38 PM PDT 24
Finished Jul 13 05:36:08 PM PDT 24
Peak memory 233876 kb
Host smart-3abbbc32-2279-450f-94c8-c65e56eefc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458853000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1458853000
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3691809584
Short name T697
Test name
Test status
Simulation time 6859279504 ps
CPU time 98.26 seconds
Started Jul 13 05:35:38 PM PDT 24
Finished Jul 13 05:37:17 PM PDT 24
Peak memory 253456 kb
Host smart-1356f20e-34fe-49d1-805f-ee4e8ae4ce34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691809584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3691809584
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1302937799
Short name T946
Test name
Test status
Simulation time 4110807423 ps
CPU time 9.3 seconds
Started Jul 13 05:35:36 PM PDT 24
Finished Jul 13 05:35:47 PM PDT 24
Peak memory 233892 kb
Host smart-a5fd9057-6a05-4cdf-adfa-1658969fcbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302937799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1302937799
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.524197053
Short name T236
Test name
Test status
Simulation time 1566616949 ps
CPU time 17.12 seconds
Started Jul 13 05:35:37 PM PDT 24
Finished Jul 13 05:35:55 PM PDT 24
Peak memory 225472 kb
Host smart-25b86ea0-6d3d-4d70-b522-7913dae8389d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524197053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.524197053
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2046581310
Short name T538
Test name
Test status
Simulation time 697908126 ps
CPU time 4 seconds
Started Jul 13 05:35:37 PM PDT 24
Finished Jul 13 05:35:42 PM PDT 24
Peak memory 233724 kb
Host smart-ad143dc8-80ba-442d-bac5-6bd2798ca35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046581310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2046581310
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3987245656
Short name T1001
Test name
Test status
Simulation time 601381490 ps
CPU time 5.83 seconds
Started Jul 13 05:35:38 PM PDT 24
Finished Jul 13 05:35:44 PM PDT 24
Peak memory 233652 kb
Host smart-a1665be7-0b27-4234-8848-946548a5afc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987245656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3987245656
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3741684572
Short name T1021
Test name
Test status
Simulation time 427979360 ps
CPU time 3.98 seconds
Started Jul 13 05:35:36 PM PDT 24
Finished Jul 13 05:35:41 PM PDT 24
Peak memory 221596 kb
Host smart-d28e4b0b-9e73-4c58-b937-0c26d7f4cae1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3741684572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3741684572
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2214149294
Short name T939
Test name
Test status
Simulation time 6057588076 ps
CPU time 57.63 seconds
Started Jul 13 05:35:36 PM PDT 24
Finished Jul 13 05:36:35 PM PDT 24
Peak memory 225824 kb
Host smart-2614d2ca-8e5d-4669-a44f-938bc8e1c61c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214149294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2214149294
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.157688844
Short name T392
Test name
Test status
Simulation time 22470612283 ps
CPU time 25.38 seconds
Started Jul 13 05:35:37 PM PDT 24
Finished Jul 13 05:36:04 PM PDT 24
Peak memory 217548 kb
Host smart-b860b807-491f-47bc-a20a-54f8db541b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157688844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.157688844
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3970561832
Short name T968
Test name
Test status
Simulation time 16890151539 ps
CPU time 9.09 seconds
Started Jul 13 05:35:36 PM PDT 24
Finished Jul 13 05:35:46 PM PDT 24
Peak memory 217460 kb
Host smart-c7b50484-9534-4199-9a18-0ab8ddf15794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970561832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3970561832
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.539883837
Short name T397
Test name
Test status
Simulation time 73921256 ps
CPU time 1.38 seconds
Started Jul 13 05:35:36 PM PDT 24
Finished Jul 13 05:35:39 PM PDT 24
Peak memory 217344 kb
Host smart-028c8983-428a-40d1-b445-b83081a2782e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539883837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.539883837
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1446272065
Short name T289
Test name
Test status
Simulation time 111823908 ps
CPU time 0.81 seconds
Started Jul 13 05:35:37 PM PDT 24
Finished Jul 13 05:35:38 PM PDT 24
Peak memory 206944 kb
Host smart-4c43ad9d-dffc-45f0-9bab-e4d52872a53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446272065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1446272065
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3590550943
Short name T986
Test name
Test status
Simulation time 696601399 ps
CPU time 3.91 seconds
Started Jul 13 05:35:41 PM PDT 24
Finished Jul 13 05:35:45 PM PDT 24
Peak memory 233764 kb
Host smart-80c439cc-b0ac-4377-994a-5e77270b0ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590550943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3590550943
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3759713416
Short name T685
Test name
Test status
Simulation time 38830467 ps
CPU time 0.7 seconds
Started Jul 13 05:35:47 PM PDT 24
Finished Jul 13 05:35:48 PM PDT 24
Peak memory 206208 kb
Host smart-c7f10470-60c1-4557-8c74-bb7d4c327e02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759713416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3759713416
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.956249342
Short name T91
Test name
Test status
Simulation time 877257340 ps
CPU time 5.26 seconds
Started Jul 13 05:35:47 PM PDT 24
Finished Jul 13 05:35:52 PM PDT 24
Peak memory 225512 kb
Host smart-15a301eb-81aa-4de5-b76c-713defcd9164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956249342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.956249342
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.360806127
Short name T297
Test name
Test status
Simulation time 46106600 ps
CPU time 0.78 seconds
Started Jul 13 05:35:37 PM PDT 24
Finished Jul 13 05:35:39 PM PDT 24
Peak memory 207280 kb
Host smart-33a7952e-855d-4cff-b392-5427d39b6d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360806127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.360806127
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.345232399
Short name T51
Test name
Test status
Simulation time 11160553035 ps
CPU time 77.06 seconds
Started Jul 13 05:35:46 PM PDT 24
Finished Jul 13 05:37:04 PM PDT 24
Peak memory 256232 kb
Host smart-2e545ba0-e372-46b2-9e66-cf49dbd8585b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345232399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.345232399
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.138928426
Short name T217
Test name
Test status
Simulation time 3717353299 ps
CPU time 31.32 seconds
Started Jul 13 05:35:46 PM PDT 24
Finished Jul 13 05:36:18 PM PDT 24
Peak memory 241264 kb
Host smart-909aa322-14c7-4634-82d2-748aef40f264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138928426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.138928426
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1758564577
Short name T54
Test name
Test status
Simulation time 127467533044 ps
CPU time 317.76 seconds
Started Jul 13 05:35:47 PM PDT 24
Finished Jul 13 05:41:05 PM PDT 24
Peak memory 258588 kb
Host smart-97359a5c-76d9-49b2-9287-282b36b362c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758564577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1758564577
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3932223432
Short name T887
Test name
Test status
Simulation time 2966099258 ps
CPU time 26.04 seconds
Started Jul 13 05:35:48 PM PDT 24
Finished Jul 13 05:36:15 PM PDT 24
Peak memory 242180 kb
Host smart-2173ae66-67f8-4c48-ab0f-1a5b95fa8f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932223432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3932223432
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.321390811
Short name T637
Test name
Test status
Simulation time 65829386113 ps
CPU time 122.15 seconds
Started Jul 13 05:35:48 PM PDT 24
Finished Jul 13 05:37:50 PM PDT 24
Peak memory 250284 kb
Host smart-2e247db8-7a3d-4672-903b-01e83ba5082c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321390811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.321390811
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2550852152
Short name T417
Test name
Test status
Simulation time 5509027739 ps
CPU time 14.57 seconds
Started Jul 13 05:35:47 PM PDT 24
Finished Jul 13 05:36:02 PM PDT 24
Peak memory 233888 kb
Host smart-96c57875-4801-4c12-a3e0-7824eb5bc772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550852152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2550852152
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1951677853
Short name T485
Test name
Test status
Simulation time 1645056965 ps
CPU time 18.05 seconds
Started Jul 13 05:35:51 PM PDT 24
Finished Jul 13 05:36:09 PM PDT 24
Peak memory 241264 kb
Host smart-bb303af7-0362-43c0-947c-c9f878b51f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951677853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1951677853
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.942378081
Short name T633
Test name
Test status
Simulation time 15441048911 ps
CPU time 21.52 seconds
Started Jul 13 05:35:36 PM PDT 24
Finished Jul 13 05:35:58 PM PDT 24
Peak memory 233896 kb
Host smart-b1ccc81d-4c83-4296-83e6-f74f1fde24e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942378081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.942378081
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3097475121
Short name T574
Test name
Test status
Simulation time 1672477876 ps
CPU time 7.14 seconds
Started Jul 13 05:35:39 PM PDT 24
Finished Jul 13 05:35:47 PM PDT 24
Peak memory 225576 kb
Host smart-a2a8a495-64b4-43ac-b55c-d142fb1a9ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097475121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3097475121
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2793591357
Short name T674
Test name
Test status
Simulation time 16023836528 ps
CPU time 14.19 seconds
Started Jul 13 05:35:46 PM PDT 24
Finished Jul 13 05:36:01 PM PDT 24
Peak memory 220372 kb
Host smart-ba326ce3-5c6a-43c4-9d32-2317d2bf2fec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2793591357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2793591357
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.950992424
Short name T9
Test name
Test status
Simulation time 47065236 ps
CPU time 0.99 seconds
Started Jul 13 05:35:50 PM PDT 24
Finished Jul 13 05:35:51 PM PDT 24
Peak memory 207560 kb
Host smart-1ab000b2-0e41-4b32-bf85-c6a4d21706a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950992424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.950992424
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2109597729
Short name T838
Test name
Test status
Simulation time 8371436175 ps
CPU time 21.04 seconds
Started Jul 13 05:35:36 PM PDT 24
Finished Jul 13 05:35:58 PM PDT 24
Peak memory 221216 kb
Host smart-f5d31fca-f1cb-4308-b211-e75e82d7d748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109597729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2109597729
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1405258105
Short name T912
Test name
Test status
Simulation time 925861031 ps
CPU time 3.26 seconds
Started Jul 13 05:35:36 PM PDT 24
Finished Jul 13 05:35:40 PM PDT 24
Peak memory 217256 kb
Host smart-31cd3670-c24a-4b17-8160-7de2c10cc7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405258105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1405258105
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1289840358
Short name T580
Test name
Test status
Simulation time 54564216 ps
CPU time 1.23 seconds
Started Jul 13 05:35:40 PM PDT 24
Finished Jul 13 05:35:41 PM PDT 24
Peak memory 209196 kb
Host smart-66c4d982-3333-4718-9c75-881811a3b1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289840358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1289840358
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.885041128
Short name T305
Test name
Test status
Simulation time 20211673 ps
CPU time 0.74 seconds
Started Jul 13 05:35:38 PM PDT 24
Finished Jul 13 05:35:40 PM PDT 24
Peak memory 206816 kb
Host smart-e42545f9-ea67-4644-9a22-f0c0b29e96a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885041128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.885041128
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1489156517
Short name T25
Test name
Test status
Simulation time 238524473 ps
CPU time 4.19 seconds
Started Jul 13 05:35:48 PM PDT 24
Finished Jul 13 05:35:52 PM PDT 24
Peak memory 225540 kb
Host smart-94e9fbe3-fc08-421f-85a8-59807a6dbaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489156517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1489156517
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.537758802
Short name T703
Test name
Test status
Simulation time 14525501 ps
CPU time 0.76 seconds
Started Jul 13 05:27:20 PM PDT 24
Finished Jul 13 05:27:21 PM PDT 24
Peak memory 205728 kb
Host smart-7e6dd1d9-c346-42f3-9dd5-83c3024b470a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537758802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.537758802
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2883775331
Short name T522
Test name
Test status
Simulation time 125456189 ps
CPU time 4.35 seconds
Started Jul 13 05:27:08 PM PDT 24
Finished Jul 13 05:27:12 PM PDT 24
Peak memory 233796 kb
Host smart-566ae8ae-e276-4cce-aaf1-54ee6468d260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883775331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2883775331
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1946205673
Short name T437
Test name
Test status
Simulation time 35688239 ps
CPU time 0.81 seconds
Started Jul 13 05:27:05 PM PDT 24
Finished Jul 13 05:27:06 PM PDT 24
Peak memory 207428 kb
Host smart-f2baef13-ae31-4969-8836-316631a275ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946205673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1946205673
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1224599970
Short name T196
Test name
Test status
Simulation time 22815270109 ps
CPU time 101.32 seconds
Started Jul 13 05:27:11 PM PDT 24
Finished Jul 13 05:28:53 PM PDT 24
Peak memory 274800 kb
Host smart-01cd1e49-3aa4-44a8-85ac-bfa4cc6ac6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224599970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1224599970
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1655158140
Short name T631
Test name
Test status
Simulation time 40684610922 ps
CPU time 220.03 seconds
Started Jul 13 05:27:10 PM PDT 24
Finished Jul 13 05:30:51 PM PDT 24
Peak memory 266220 kb
Host smart-9493c86d-2007-457c-9e08-c51228aca68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655158140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1655158140
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3131259444
Short name T744
Test name
Test status
Simulation time 13373292947 ps
CPU time 138.88 seconds
Started Jul 13 05:27:11 PM PDT 24
Finished Jul 13 05:29:31 PM PDT 24
Peak memory 239812 kb
Host smart-649c81e5-e7e3-4eea-bae2-db3110ccdb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131259444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3131259444
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1168741996
Short name T1010
Test name
Test status
Simulation time 18325428842 ps
CPU time 66.45 seconds
Started Jul 13 05:27:08 PM PDT 24
Finished Jul 13 05:28:15 PM PDT 24
Peak memory 233664 kb
Host smart-445c594c-9faf-4b6f-96c7-2080285c57f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168741996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1168741996
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3214644789
Short name T72
Test name
Test status
Simulation time 42390936526 ps
CPU time 310.65 seconds
Started Jul 13 05:27:11 PM PDT 24
Finished Jul 13 05:32:23 PM PDT 24
Peak memory 254348 kb
Host smart-91fbd45a-02f8-4dbd-848c-f5c4fb848ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214644789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3214644789
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.655595407
Short name T646
Test name
Test status
Simulation time 38272720 ps
CPU time 2.7 seconds
Started Jul 13 05:27:02 PM PDT 24
Finished Jul 13 05:27:05 PM PDT 24
Peak memory 225488 kb
Host smart-3611a512-0940-446c-95d6-30c9d75a9a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655595407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.655595407
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2683750498
Short name T27
Test name
Test status
Simulation time 25673723431 ps
CPU time 46.86 seconds
Started Jul 13 05:27:00 PM PDT 24
Finished Jul 13 05:27:48 PM PDT 24
Peak memory 233900 kb
Host smart-f1256405-82c6-4aa4-b8c2-d3f1d8f61a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683750498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2683750498
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3479751300
Short name T547
Test name
Test status
Simulation time 39435009 ps
CPU time 1.05 seconds
Started Jul 13 05:27:03 PM PDT 24
Finished Jul 13 05:27:04 PM PDT 24
Peak memory 219100 kb
Host smart-50199691-3767-47b4-bb62-0c2bb5ad52c8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479751300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3479751300
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3129612711
Short name T577
Test name
Test status
Simulation time 402306063 ps
CPU time 6.79 seconds
Started Jul 13 05:27:02 PM PDT 24
Finished Jul 13 05:27:09 PM PDT 24
Peak memory 225520 kb
Host smart-16664ee4-dbe7-42fa-aeb4-da43f626acf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129612711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3129612711
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1113821912
Short name T133
Test name
Test status
Simulation time 1198665765 ps
CPU time 5.47 seconds
Started Jul 13 05:27:02 PM PDT 24
Finished Jul 13 05:27:08 PM PDT 24
Peak memory 233720 kb
Host smart-77df00f5-4992-4aed-a1d9-40f1eff16ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113821912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1113821912
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.20684444
Short name T935
Test name
Test status
Simulation time 2985581345 ps
CPU time 10.43 seconds
Started Jul 13 05:27:10 PM PDT 24
Finished Jul 13 05:27:21 PM PDT 24
Peak memory 223236 kb
Host smart-cf54e4d8-5be1-480f-bdf2-0728095d59df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=20684444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct
.20684444
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3582242176
Short name T644
Test name
Test status
Simulation time 50929849 ps
CPU time 0.97 seconds
Started Jul 13 05:27:12 PM PDT 24
Finished Jul 13 05:27:13 PM PDT 24
Peak memory 207728 kb
Host smart-67925b22-24d0-4fc6-b9dc-a10b480ca49f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582242176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3582242176
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3139271041
Short name T584
Test name
Test status
Simulation time 202460940 ps
CPU time 3.8 seconds
Started Jul 13 05:27:04 PM PDT 24
Finished Jul 13 05:27:09 PM PDT 24
Peak memory 217380 kb
Host smart-95354e2b-0619-4f61-9488-9d17fb51676e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139271041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3139271041
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2755409092
Short name T790
Test name
Test status
Simulation time 1286666199 ps
CPU time 5.28 seconds
Started Jul 13 05:27:04 PM PDT 24
Finished Jul 13 05:27:10 PM PDT 24
Peak memory 217236 kb
Host smart-b6a95c4a-6925-4703-ae58-380a7a8a598e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755409092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2755409092
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3207493648
Short name T932
Test name
Test status
Simulation time 137116776 ps
CPU time 1.56 seconds
Started Jul 13 05:27:01 PM PDT 24
Finished Jul 13 05:27:03 PM PDT 24
Peak memory 217324 kb
Host smart-62559050-b99f-4633-9483-f969d0906f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207493648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3207493648
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2085097659
Short name T326
Test name
Test status
Simulation time 373112792 ps
CPU time 1.05 seconds
Started Jul 13 05:27:02 PM PDT 24
Finished Jul 13 05:27:04 PM PDT 24
Peak memory 206980 kb
Host smart-be865cd3-0b35-43cf-84cb-a72945113a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085097659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2085097659
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.324150040
Short name T1007
Test name
Test status
Simulation time 1059835887 ps
CPU time 9.75 seconds
Started Jul 13 05:27:10 PM PDT 24
Finished Jul 13 05:27:20 PM PDT 24
Peak memory 233708 kb
Host smart-65e397e8-8ee8-490b-bec1-35da7296ef8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324150040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.324150040
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.466262381
Short name T915
Test name
Test status
Simulation time 65874409 ps
CPU time 0.78 seconds
Started Jul 13 05:27:42 PM PDT 24
Finished Jul 13 05:27:43 PM PDT 24
Peak memory 206312 kb
Host smart-ccb105a6-7fd7-46fa-960b-9df31a6756aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466262381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.466262381
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3261425157
Short name T230
Test name
Test status
Simulation time 4979391653 ps
CPU time 12.95 seconds
Started Jul 13 05:27:30 PM PDT 24
Finished Jul 13 05:27:44 PM PDT 24
Peak memory 233868 kb
Host smart-e370598e-6cf7-4428-840a-0b606d46d041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261425157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3261425157
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2261145404
Short name T390
Test name
Test status
Simulation time 19088526 ps
CPU time 0.79 seconds
Started Jul 13 05:27:25 PM PDT 24
Finished Jul 13 05:27:26 PM PDT 24
Peak memory 207500 kb
Host smart-75db72db-361e-463e-90bc-80c411b8d71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261145404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2261145404
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.666578822
Short name T267
Test name
Test status
Simulation time 39090900239 ps
CPU time 261.89 seconds
Started Jul 13 05:27:31 PM PDT 24
Finished Jul 13 05:31:53 PM PDT 24
Peak memory 255380 kb
Host smart-497254bb-e5e4-413f-815a-da3467cbca36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666578822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.666578822
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2592639477
Short name T889
Test name
Test status
Simulation time 29312357109 ps
CPU time 124.43 seconds
Started Jul 13 05:27:43 PM PDT 24
Finished Jul 13 05:29:48 PM PDT 24
Peak memory 267844 kb
Host smart-132561ca-c847-4dc8-9007-d1ad9efa83d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592639477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2592639477
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2156747136
Short name T783
Test name
Test status
Simulation time 39355474688 ps
CPU time 77.02 seconds
Started Jul 13 05:27:43 PM PDT 24
Finished Jul 13 05:29:00 PM PDT 24
Peak memory 238876 kb
Host smart-315521d1-cb70-4e6a-9175-195468fc5157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156747136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2156747136
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2412341574
Short name T806
Test name
Test status
Simulation time 382227425 ps
CPU time 10.88 seconds
Started Jul 13 05:27:31 PM PDT 24
Finished Jul 13 05:27:42 PM PDT 24
Peak memory 233780 kb
Host smart-b4a0e502-c4f2-433c-8b78-f2ea6c605f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412341574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2412341574
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1132092561
Short name T254
Test name
Test status
Simulation time 12815399960 ps
CPU time 131.67 seconds
Started Jul 13 05:27:29 PM PDT 24
Finished Jul 13 05:29:41 PM PDT 24
Peak memory 252052 kb
Host smart-93eb6db7-48d6-4846-a920-c14a41d8e46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132092561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1132092561
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1616964727
Short name T374
Test name
Test status
Simulation time 48333679 ps
CPU time 2.48 seconds
Started Jul 13 05:27:30 PM PDT 24
Finished Jul 13 05:27:32 PM PDT 24
Peak memory 233752 kb
Host smart-465d604f-fffd-4f1d-b044-0b2be644f748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616964727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1616964727
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2460648445
Short name T238
Test name
Test status
Simulation time 375340880 ps
CPU time 4.96 seconds
Started Jul 13 05:27:31 PM PDT 24
Finished Jul 13 05:27:36 PM PDT 24
Peak memory 233816 kb
Host smart-d40d7566-76ce-4793-b3cb-49a4d96f2832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460648445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2460648445
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3040545543
Short name T766
Test name
Test status
Simulation time 15390245 ps
CPU time 1.04 seconds
Started Jul 13 05:27:21 PM PDT 24
Finished Jul 13 05:27:23 PM PDT 24
Peak memory 218940 kb
Host smart-15910ffc-148d-4133-9f31-89e095f602ed
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040545543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3040545543
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3962228933
Short name T747
Test name
Test status
Simulation time 1160456249 ps
CPU time 10 seconds
Started Jul 13 05:27:31 PM PDT 24
Finished Jul 13 05:27:41 PM PDT 24
Peak memory 240788 kb
Host smart-a23d55e5-3c39-4da6-9429-d9deb2a81633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962228933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3962228933
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.841707945
Short name T5
Test name
Test status
Simulation time 786362371 ps
CPU time 7.39 seconds
Started Jul 13 05:27:30 PM PDT 24
Finished Jul 13 05:27:38 PM PDT 24
Peak memory 233672 kb
Host smart-d64dc814-4b43-40ac-b54c-47b03312d5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841707945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.841707945
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2372281050
Short name T324
Test name
Test status
Simulation time 174228533 ps
CPU time 4.01 seconds
Started Jul 13 05:27:30 PM PDT 24
Finished Jul 13 05:27:34 PM PDT 24
Peak memory 220564 kb
Host smart-e75c3df9-c39f-4927-a0fc-d3c02b310f99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2372281050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2372281050
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3613676390
Short name T139
Test name
Test status
Simulation time 2869541856 ps
CPU time 74.15 seconds
Started Jul 13 05:27:41 PM PDT 24
Finished Jul 13 05:28:56 PM PDT 24
Peak memory 257112 kb
Host smart-d6de3b34-cbbc-4e45-a6aa-3ee18c08653b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613676390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3613676390
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3683674693
Short name T528
Test name
Test status
Simulation time 5153003204 ps
CPU time 22.38 seconds
Started Jul 13 05:27:20 PM PDT 24
Finished Jul 13 05:27:43 PM PDT 24
Peak memory 217464 kb
Host smart-ff27dc35-d5b6-4755-afe3-167542f2611b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683674693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3683674693
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1139953510
Short name T431
Test name
Test status
Simulation time 19550335 ps
CPU time 0.71 seconds
Started Jul 13 05:27:24 PM PDT 24
Finished Jul 13 05:27:25 PM PDT 24
Peak memory 206636 kb
Host smart-df846391-fb16-4f03-ab8e-6e85c38bd091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139953510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1139953510
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2016608562
Short name T474
Test name
Test status
Simulation time 186242391 ps
CPU time 2.55 seconds
Started Jul 13 05:27:30 PM PDT 24
Finished Jul 13 05:27:33 PM PDT 24
Peak memory 217412 kb
Host smart-6eeb41b9-f8be-4d15-89ce-aa697778ba55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016608562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2016608562
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.319611398
Short name T914
Test name
Test status
Simulation time 80314822 ps
CPU time 0.78 seconds
Started Jul 13 05:27:25 PM PDT 24
Finished Jul 13 05:27:26 PM PDT 24
Peak memory 206964 kb
Host smart-677df1ae-59f2-4dab-a9b4-338b5934cee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319611398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.319611398
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3618479494
Short name T215
Test name
Test status
Simulation time 88869018502 ps
CPU time 24.95 seconds
Started Jul 13 05:27:30 PM PDT 24
Finished Jul 13 05:27:55 PM PDT 24
Peak memory 233892 kb
Host smart-9fa78cd8-400c-4a50-b7d6-24b3534db45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618479494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3618479494
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3341315310
Short name T340
Test name
Test status
Simulation time 22119549 ps
CPU time 0.73 seconds
Started Jul 13 05:28:02 PM PDT 24
Finished Jul 13 05:28:03 PM PDT 24
Peak memory 205828 kb
Host smart-03476155-3b0c-4d96-b33f-d0cbdf1ba560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341315310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
341315310
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2115106531
Short name T845
Test name
Test status
Simulation time 1833182083 ps
CPU time 10.78 seconds
Started Jul 13 05:27:43 PM PDT 24
Finished Jul 13 05:27:54 PM PDT 24
Peak memory 233644 kb
Host smart-3fab9d2f-b273-43c3-beb7-6d7ce78ab0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115106531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2115106531
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2189537680
Short name T934
Test name
Test status
Simulation time 151652052 ps
CPU time 0.75 seconds
Started Jul 13 05:27:41 PM PDT 24
Finished Jul 13 05:27:42 PM PDT 24
Peak memory 206788 kb
Host smart-ad7d3aa4-a90e-4963-92c9-718f7e9ae233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189537680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2189537680
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1586894500
Short name T878
Test name
Test status
Simulation time 4575130330 ps
CPU time 35.84 seconds
Started Jul 13 05:27:58 PM PDT 24
Finished Jul 13 05:28:35 PM PDT 24
Peak memory 242028 kb
Host smart-c84d4688-84c8-4be0-a443-62beda8d0813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586894500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1586894500
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3419057727
Short name T35
Test name
Test status
Simulation time 4396461208 ps
CPU time 91.09 seconds
Started Jul 13 05:28:00 PM PDT 24
Finished Jul 13 05:29:32 PM PDT 24
Peak memory 268040 kb
Host smart-3bbce331-d264-44a5-b90b-9dd9438e231e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419057727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3419057727
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1663993576
Short name T263
Test name
Test status
Simulation time 9417899387 ps
CPU time 59.54 seconds
Started Jul 13 05:27:58 PM PDT 24
Finished Jul 13 05:28:58 PM PDT 24
Peak memory 256408 kb
Host smart-301fa042-da62-426e-93df-deb1161e4b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663993576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1663993576
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1954105964
Short name T26
Test name
Test status
Simulation time 2283640801 ps
CPU time 12.32 seconds
Started Jul 13 05:27:43 PM PDT 24
Finished Jul 13 05:27:56 PM PDT 24
Peak memory 225704 kb
Host smart-41aabedc-29ec-4167-bb62-71235afc6a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954105964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1954105964
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3419865267
Short name T864
Test name
Test status
Simulation time 57891122924 ps
CPU time 113.47 seconds
Started Jul 13 05:27:58 PM PDT 24
Finished Jul 13 05:29:53 PM PDT 24
Peak memory 256056 kb
Host smart-8391b432-c051-4360-8690-fa7b1d617d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419865267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3419865267
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1383805728
Short name T540
Test name
Test status
Simulation time 193996508 ps
CPU time 2.29 seconds
Started Jul 13 05:27:44 PM PDT 24
Finished Jul 13 05:27:46 PM PDT 24
Peak memory 224380 kb
Host smart-c0a539a4-c4d1-44aa-bcda-6ea8bb423ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383805728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1383805728
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2426511657
Short name T988
Test name
Test status
Simulation time 1416190053 ps
CPU time 9.64 seconds
Started Jul 13 05:27:42 PM PDT 24
Finished Jul 13 05:27:52 PM PDT 24
Peak memory 230524 kb
Host smart-3cdbd1f0-32b8-40e6-8f83-7f22e676ba25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426511657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2426511657
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1318385045
Short name T642
Test name
Test status
Simulation time 28571797 ps
CPU time 1.07 seconds
Started Jul 13 05:27:41 PM PDT 24
Finished Jul 13 05:27:43 PM PDT 24
Peak memory 217680 kb
Host smart-91886f02-f42b-4978-9032-5c159b842783
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318385045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1318385045
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3630494967
Short name T560
Test name
Test status
Simulation time 2789353135 ps
CPU time 5.55 seconds
Started Jul 13 05:27:43 PM PDT 24
Finished Jul 13 05:27:49 PM PDT 24
Peak memory 225700 kb
Host smart-005f842c-64e3-4017-a436-189428b43fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630494967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3630494967
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1949694141
Short name T863
Test name
Test status
Simulation time 3990961480 ps
CPU time 4.91 seconds
Started Jul 13 05:27:49 PM PDT 24
Finished Jul 13 05:27:54 PM PDT 24
Peak memory 233836 kb
Host smart-a31bd276-fa40-4a44-b09c-a5e86be6cba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949694141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1949694141
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.225318690
Short name T645
Test name
Test status
Simulation time 223694876 ps
CPU time 5.46 seconds
Started Jul 13 05:27:58 PM PDT 24
Finished Jul 13 05:28:05 PM PDT 24
Peak memory 224092 kb
Host smart-6faf7d74-bbf7-49f3-8934-d9f96782c007
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=225318690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.225318690
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4133066292
Short name T30
Test name
Test status
Simulation time 5435862277 ps
CPU time 20.67 seconds
Started Jul 13 05:27:42 PM PDT 24
Finished Jul 13 05:28:03 PM PDT 24
Peak memory 217512 kb
Host smart-44cdf0a6-0b58-4536-813e-122fc2bce6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133066292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4133066292
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2516727917
Short name T679
Test name
Test status
Simulation time 16586787653 ps
CPU time 16.77 seconds
Started Jul 13 05:27:43 PM PDT 24
Finished Jul 13 05:28:01 PM PDT 24
Peak memory 217456 kb
Host smart-18dc445c-af52-4862-b9ec-16f6d9522738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516727917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2516727917
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1895905718
Short name T937
Test name
Test status
Simulation time 600724226 ps
CPU time 2.29 seconds
Started Jul 13 05:27:42 PM PDT 24
Finished Jul 13 05:27:45 PM PDT 24
Peak memory 217384 kb
Host smart-8bec8edb-8afd-431b-bbde-b35445111813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895905718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1895905718
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1392615392
Short name T816
Test name
Test status
Simulation time 25083400 ps
CPU time 0.65 seconds
Started Jul 13 05:27:41 PM PDT 24
Finished Jul 13 05:27:42 PM PDT 24
Peak memory 206552 kb
Host smart-24b1cd6c-49b2-400d-b122-850603cf3177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392615392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1392615392
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3920774952
Short name T804
Test name
Test status
Simulation time 4492310067 ps
CPU time 9.34 seconds
Started Jul 13 05:27:42 PM PDT 24
Finished Jul 13 05:27:51 PM PDT 24
Peak memory 233768 kb
Host smart-6c651197-70de-4eb7-a0d0-6f12010c363e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920774952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3920774952
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.433768400
Short name T748
Test name
Test status
Simulation time 73261445 ps
CPU time 0.73 seconds
Started Jul 13 05:28:10 PM PDT 24
Finished Jul 13 05:28:11 PM PDT 24
Peak memory 206400 kb
Host smart-3f3c158c-ecca-4b89-9137-73983165425f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433768400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.433768400
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1580291101
Short name T736
Test name
Test status
Simulation time 135840762 ps
CPU time 2.46 seconds
Started Jul 13 05:27:58 PM PDT 24
Finished Jul 13 05:28:02 PM PDT 24
Peak memory 233716 kb
Host smart-46a019a1-d167-4082-977f-43863f195733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580291101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1580291101
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3487116496
Short name T425
Test name
Test status
Simulation time 16323450 ps
CPU time 0.8 seconds
Started Jul 13 05:28:02 PM PDT 24
Finished Jul 13 05:28:03 PM PDT 24
Peak memory 207844 kb
Host smart-0acd8d93-969f-4fff-9bb7-d9e38425ef8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487116496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3487116496
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.497926488
Short name T692
Test name
Test status
Simulation time 171939847149 ps
CPU time 292.42 seconds
Started Jul 13 05:28:08 PM PDT 24
Finished Jul 13 05:33:01 PM PDT 24
Peak memory 255412 kb
Host smart-2fe27245-cdd8-4f5b-ab3e-5b6447d7533f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497926488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.497926488
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1265329913
Short name T393
Test name
Test status
Simulation time 7464595239 ps
CPU time 67.86 seconds
Started Jul 13 05:28:10 PM PDT 24
Finished Jul 13 05:29:18 PM PDT 24
Peak memory 250908 kb
Host smart-2abd305c-6c82-4865-aa24-ab3b1cf007dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265329913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1265329913
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.775458689
Short name T478
Test name
Test status
Simulation time 3752219831 ps
CPU time 62.85 seconds
Started Jul 13 05:28:09 PM PDT 24
Finished Jul 13 05:29:12 PM PDT 24
Peak memory 240936 kb
Host smart-09eabef5-235b-459e-8d51-5823b0c24609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775458689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
775458689
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.347719182
Short name T271
Test name
Test status
Simulation time 2376612446 ps
CPU time 34.47 seconds
Started Jul 13 05:27:58 PM PDT 24
Finished Jul 13 05:28:35 PM PDT 24
Peak memory 234052 kb
Host smart-931efa74-e170-4635-92c1-0b18657772bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347719182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.347719182
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1860377757
Short name T978
Test name
Test status
Simulation time 2850579060 ps
CPU time 39.25 seconds
Started Jul 13 05:27:59 PM PDT 24
Finished Jul 13 05:28:40 PM PDT 24
Peak memory 242100 kb
Host smart-6a8a11e6-fb09-4e52-a40a-1a71bba5662a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860377757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1860377757
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.852178281
Short name T653
Test name
Test status
Simulation time 424262678 ps
CPU time 2.11 seconds
Started Jul 13 05:27:59 PM PDT 24
Finished Jul 13 05:28:02 PM PDT 24
Peak memory 224068 kb
Host smart-33ccba1e-b0d1-4c37-b39e-f61aae5a6e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852178281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.852178281
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.676272405
Short name T675
Test name
Test status
Simulation time 6750893306 ps
CPU time 18.46 seconds
Started Jul 13 05:27:59 PM PDT 24
Finished Jul 13 05:28:19 PM PDT 24
Peak memory 225652 kb
Host smart-63073245-c193-4e86-af11-572e8d949728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676272405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.676272405
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.700281363
Short name T555
Test name
Test status
Simulation time 49489774 ps
CPU time 1.02 seconds
Started Jul 13 05:27:57 PM PDT 24
Finished Jul 13 05:27:59 PM PDT 24
Peak memory 217640 kb
Host smart-64bc184c-d792-423f-b35b-9e9ac94cdff0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700281363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.700281363
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2474557091
Short name T592
Test name
Test status
Simulation time 41458121927 ps
CPU time 21.74 seconds
Started Jul 13 05:27:57 PM PDT 24
Finished Jul 13 05:28:19 PM PDT 24
Peak memory 233872 kb
Host smart-4b0e2e3e-f309-45e8-a3b3-f3022be25da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474557091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2474557091
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1537415039
Short name T765
Test name
Test status
Simulation time 2760650767 ps
CPU time 6.73 seconds
Started Jul 13 05:27:59 PM PDT 24
Finished Jul 13 05:28:07 PM PDT 24
Peak memory 225696 kb
Host smart-b1d5248c-ed85-4e00-ba58-a915e94583ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537415039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1537415039
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3527310984
Short name T717
Test name
Test status
Simulation time 216063872 ps
CPU time 3.87 seconds
Started Jul 13 05:28:09 PM PDT 24
Finished Jul 13 05:28:13 PM PDT 24
Peak memory 220376 kb
Host smart-9b1ba912-2568-4194-8c6d-5ef408f9df80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3527310984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3527310984
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3954985992
Short name T906
Test name
Test status
Simulation time 19472280419 ps
CPU time 127.56 seconds
Started Jul 13 05:28:09 PM PDT 24
Finished Jul 13 05:30:17 PM PDT 24
Peak memory 238568 kb
Host smart-f57c6644-18db-475e-a878-d25366a42cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954985992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3954985992
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3085776858
Short name T348
Test name
Test status
Simulation time 2596994296 ps
CPU time 12.16 seconds
Started Jul 13 05:27:57 PM PDT 24
Finished Jul 13 05:28:10 PM PDT 24
Peak memory 217564 kb
Host smart-a8ac1e86-ac08-426e-8667-6dab4f053cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085776858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3085776858
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.620449022
Short name T345
Test name
Test status
Simulation time 4954304265 ps
CPU time 16.94 seconds
Started Jul 13 05:27:59 PM PDT 24
Finished Jul 13 05:28:17 PM PDT 24
Peak memory 217520 kb
Host smart-4601ec53-6b08-4934-b32a-e6bb2716dbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620449022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.620449022
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3581346013
Short name T455
Test name
Test status
Simulation time 163243860 ps
CPU time 2.54 seconds
Started Jul 13 05:27:59 PM PDT 24
Finished Jul 13 05:28:03 PM PDT 24
Peak memory 217276 kb
Host smart-842085a6-5e1d-4489-8dda-2a7bc48baefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581346013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3581346013
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1141446096
Short name T401
Test name
Test status
Simulation time 433721955 ps
CPU time 0.81 seconds
Started Jul 13 05:27:58 PM PDT 24
Finished Jul 13 05:28:01 PM PDT 24
Peak memory 206940 kb
Host smart-e88b7090-a5d6-4484-b338-0098136e43d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141446096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1141446096
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3772770593
Short name T729
Test name
Test status
Simulation time 125559051 ps
CPU time 3.04 seconds
Started Jul 13 05:28:02 PM PDT 24
Finished Jul 13 05:28:05 PM PDT 24
Peak memory 225564 kb
Host smart-8b8a2c59-05c7-40ee-be50-f57cc3332d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772770593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3772770593
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3436192814
Short name T484
Test name
Test status
Simulation time 13700098 ps
CPU time 0.8 seconds
Started Jul 13 05:28:32 PM PDT 24
Finished Jul 13 05:28:33 PM PDT 24
Peak memory 206008 kb
Host smart-92542b0c-127d-4864-a220-748f83576ffa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436192814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
436192814
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.207202289
Short name T476
Test name
Test status
Simulation time 198628448 ps
CPU time 4.42 seconds
Started Jul 13 05:28:19 PM PDT 24
Finished Jul 13 05:28:24 PM PDT 24
Peak memory 225512 kb
Host smart-472cf562-8bdc-4d3d-ad36-f289b772cf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207202289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.207202289
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.4270932552
Short name T608
Test name
Test status
Simulation time 13663276 ps
CPU time 0.77 seconds
Started Jul 13 05:28:09 PM PDT 24
Finished Jul 13 05:28:10 PM PDT 24
Peak memory 207456 kb
Host smart-de16e96b-7051-47f7-a069-8572530be8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270932552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4270932552
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1345758378
Short name T755
Test name
Test status
Simulation time 4548563664 ps
CPU time 51.62 seconds
Started Jul 13 05:28:19 PM PDT 24
Finished Jul 13 05:29:11 PM PDT 24
Peak memory 258504 kb
Host smart-afa0541f-ff1b-47c7-a6d3-f1e77abd641e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345758378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1345758378
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.4278877838
Short name T11
Test name
Test status
Simulation time 1678073509 ps
CPU time 24.82 seconds
Started Jul 13 05:28:19 PM PDT 24
Finished Jul 13 05:28:45 PM PDT 24
Peak memory 252276 kb
Host smart-56a1e8b8-8b68-482e-b32a-99392104f232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278877838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.4278877838
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1870016584
Short name T261
Test name
Test status
Simulation time 41173062444 ps
CPU time 353.51 seconds
Started Jul 13 05:28:30 PM PDT 24
Finished Jul 13 05:34:25 PM PDT 24
Peak memory 258520 kb
Host smart-2d370aad-05ff-4884-9b89-7055af49cfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870016584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1870016584
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.788556384
Short name T904
Test name
Test status
Simulation time 45777324800 ps
CPU time 43.36 seconds
Started Jul 13 05:28:19 PM PDT 24
Finished Jul 13 05:29:02 PM PDT 24
Peak memory 233688 kb
Host smart-aba522af-bd13-4ba8-9cda-95d69101ea4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788556384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.788556384
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3060363338
Short name T552
Test name
Test status
Simulation time 16511728137 ps
CPU time 132.47 seconds
Started Jul 13 05:28:20 PM PDT 24
Finished Jul 13 05:30:33 PM PDT 24
Peak memory 251316 kb
Host smart-15574c03-17f7-41f5-8e69-eb47d0abd11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060363338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3060363338
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3556735973
Short name T821
Test name
Test status
Simulation time 94458316 ps
CPU time 2.07 seconds
Started Jul 13 05:28:19 PM PDT 24
Finished Jul 13 05:28:22 PM PDT 24
Peak memory 224228 kb
Host smart-24fa7e6a-2371-46f1-912e-6ced5b3b153b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556735973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3556735973
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.215139017
Short name T1016
Test name
Test status
Simulation time 15596511673 ps
CPU time 22.14 seconds
Started Jul 13 05:28:19 PM PDT 24
Finished Jul 13 05:28:42 PM PDT 24
Peak memory 250212 kb
Host smart-dc6d4135-24b1-4429-80e3-602d3ed416fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215139017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.215139017
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2112460924
Short name T512
Test name
Test status
Simulation time 46141493 ps
CPU time 1.05 seconds
Started Jul 13 05:28:10 PM PDT 24
Finished Jul 13 05:28:11 PM PDT 24
Peak memory 218976 kb
Host smart-048b121a-95f2-49fb-b84c-cabaf3032e9b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112460924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2112460924
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2404672406
Short name T796
Test name
Test status
Simulation time 3181577984 ps
CPU time 9.58 seconds
Started Jul 13 05:28:13 PM PDT 24
Finished Jul 13 05:28:22 PM PDT 24
Peak memory 233904 kb
Host smart-1776e616-a748-463e-b41a-3b21750d30b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404672406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2404672406
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1541510880
Short name T563
Test name
Test status
Simulation time 9684009722 ps
CPU time 17.01 seconds
Started Jul 13 05:28:13 PM PDT 24
Finished Jul 13 05:28:30 PM PDT 24
Peak memory 233908 kb
Host smart-829a0e2c-682d-4c03-8aee-57de29ea2574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541510880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1541510880
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.987948307
Short name T442
Test name
Test status
Simulation time 462197127 ps
CPU time 3.59 seconds
Started Jul 13 05:28:20 PM PDT 24
Finished Jul 13 05:28:24 PM PDT 24
Peak memory 221152 kb
Host smart-92cac7a4-8056-4eb3-b0c0-6a7c28b4b124
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=987948307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.987948307
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3418414895
Short name T162
Test name
Test status
Simulation time 174991266138 ps
CPU time 408.2 seconds
Started Jul 13 05:28:31 PM PDT 24
Finished Jul 13 05:35:20 PM PDT 24
Peak memory 274852 kb
Host smart-3bc17894-4f18-4e38-8318-21fabde0c691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418414895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3418414895
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4239245603
Short name T57
Test name
Test status
Simulation time 15185129858 ps
CPU time 23.64 seconds
Started Jul 13 05:28:09 PM PDT 24
Finished Jul 13 05:28:33 PM PDT 24
Peak memory 217588 kb
Host smart-c433c6dd-718c-47a9-84fb-88cf887e9295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239245603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4239245603
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3077020400
Short name T985
Test name
Test status
Simulation time 19029267 ps
CPU time 0.73 seconds
Started Jul 13 05:28:09 PM PDT 24
Finished Jul 13 05:28:10 PM PDT 24
Peak memory 206652 kb
Host smart-5795ef91-b3d2-464a-b463-5f2d9503a9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077020400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3077020400
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2743645609
Short name T954
Test name
Test status
Simulation time 65788097 ps
CPU time 1.21 seconds
Started Jul 13 05:28:12 PM PDT 24
Finished Jul 13 05:28:14 PM PDT 24
Peak memory 208936 kb
Host smart-5d3f38f4-5e2d-46d8-b361-cdd983e34a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743645609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2743645609
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2314029038
Short name T950
Test name
Test status
Simulation time 72974489 ps
CPU time 0.73 seconds
Started Jul 13 05:28:13 PM PDT 24
Finished Jul 13 05:28:14 PM PDT 24
Peak memory 206932 kb
Host smart-80f42e96-42f8-4b33-8b5f-0a2231e4c1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314029038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2314029038
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2357230566
Short name T428
Test name
Test status
Simulation time 1594216786 ps
CPU time 7.42 seconds
Started Jul 13 05:28:19 PM PDT 24
Finished Jul 13 05:28:27 PM PDT 24
Peak memory 233736 kb
Host smart-452ed99d-4dde-47d3-9a98-65ccab231a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357230566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2357230566
Directory /workspace/9.spi_device_upload/latest
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