Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3197363	1			T1	1		T2	1		T3	1
all_values[1]	3197363	1			T1	1		T2	1		T3	1
all_values[2]	3197363	1			T1	1		T2	1		T3	1
all_values[3]	3197363	1			T1	1		T2	1		T3	1
all_values[4]	3197363	1			T1	1		T2	1		T3	1
all_values[5]	3197363	1			T1	1		T2	1		T3	1
all_values[6]	3197363	1			T1	1		T2	1		T3	1
all_values[7]	3197363	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24866652

1

T1

8

T2

8

T3

8

auto[1]

712252

1

T16

119

T17

57

T18

74

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25547756

1

T1

8

T2

8

T3

8

auto[1]

31148

1

T5

50

T7

96

T29

304

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	3134908	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	15208	1			T5	33		T7	67		T29	169
all_values[0]	auto[1]	auto[0]	46760	1			T16	10		T17	2		T18	4
all_values[0]	auto[1]	auto[1]	487	1			T16	2		T17	2		T18	1
all_values[1]	auto[0]	auto[0]	3115026	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	9658	1			T5	17		T7	29		T29	101
all_values[1]	auto[1]	auto[0]	72346	1			T16	9		T17	2		T18	10
all_values[1]	auto[1]	auto[1]	333	1			T16	6		T17	3		T18	1
all_values[2]	auto[0]	auto[0]	3114452	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	3217	1			T29	34		T30	34		T16	2
all_values[2]	auto[1]	auto[0]	79501	1			T16	8		T17	3		T18	5
all_values[2]	auto[1]	auto[1]	193	1			T16	12		T17	4		T18	1
all_values[3]	auto[0]	auto[0]	3056540	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	227	1			T16	2		T17	2		T18	6
all_values[3]	auto[1]	auto[0]	140395	1			T16	9		T17	2		T18	7
all_values[3]	auto[1]	auto[1]	201	1			T16	9		T17	4		T18	3
all_values[4]	auto[0]	auto[0]	3142589	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	214	1			T16	2		T18	4		T19	3
all_values[4]	auto[1]	auto[0]	54367	1			T16	4		T17	4		T18	5
all_values[4]	auto[1]	auto[1]	193	1			T16	8		T17	6		T18	7
all_values[5]	auto[0]	auto[0]	3126160	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	197	1			T16	7		T17	2		T18	5
all_values[5]	auto[1]	auto[0]	70819	1			T16	11		T17	8		T18	6
all_values[5]	auto[1]	auto[1]	187	1			T16	2		T17	1		T18	2
all_values[6]	auto[0]	auto[0]	3036768	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	205	1			T16	5		T18	2		T19	5
all_values[6]	auto[1]	auto[0]	160184	1			T16	11		T17	7		T18	6
all_values[6]	auto[1]	auto[1]	206	1			T16	4		T17	1		T18	4
all_values[7]	auto[0]	auto[0]	3111081	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	202	1			T16	4		T17	3		T18	1
all_values[7]	auto[1]	auto[0]	85860	1			T16	11		T17	5		T18	8
all_values[7]	auto[1]	auto[1]	220	1			T16	3		T17	3		T18	4