Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	37208	1			T2	20		T3	6		T5	221
auto[SpiFlashAddrCfg]	8108	1			T5	65		T7	18		T12	6
auto[SpiFlashAddr3b]	9687	1			T3	2		T5	64		T7	28
auto[SpiFlashAddr4b]	8312	1			T5	53		T7	21		T12	10

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35665

1

T2

20

T3

8

T5

259

auto[1]

27650

1

T5

144

T7

62

T13

53

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33260

1

T2

20

T3

4

T5

211

auto[1]

30055

1

T3

4

T5

192

T7

81

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	42331	1			T2	20		T3	8		T5	251
values[1]	1179	1			T5	5		T7	5		T13	2
values[2]	1638	1			T5	10		T7	7		T13	1
values[3]	1533	1			T5	11		T7	1		T13	2
values[4]	1501	1			T5	9		T7	1		T12	6
values[5]	1613	1			T5	2		T7	4		T12	2
values[6]	1541	1			T5	16		T7	2		T13	1
values[7]	1571	1			T5	15		T7	5		T13	6
values[8]	10408	1			T5	84		T7	27		T13	33

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31019

1

T2

20

T3

8

T5

403

auto[1]

32296

1

T30

254

T37

197

T17

280

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

59674

1

T2

20

T3

8

T5

383

write

3641

1

T5

20

T7

10

T12

10

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20622

1

T2

20

T5

130

T7

41

valids[0x1]

42693

1

T3

8

T5

273

T7

91

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1658	1			T5	10		T7	8		T13	4
internal_process_ops[0x5a]	1760	1			T3	2		T5	14		T7	2
internal_process_ops[0x05]	22111	1			T5	133		T7	33		T13	217
internal_process_ops[0x35]	1704	1			T3	2		T5	15		T7	4
internal_process_ops[0x15]	1676	1			T3	4		T5	10		T7	3
internal_process_ops[0x03]	1093	1			T5	13		T7	2		T13	2
internal_process_ops[0x0b]	1046	1			T5	16		T7	3		T13	4
internal_process_ops[0x3b]	1076	1			T5	12		T7	3		T13	7
internal_process_ops[0x6b]	1067	1			T5	7		T7	3		T13	6
internal_process_ops[0xbb]	1093	1			T5	11		T7	2		T12	6
internal_process_ops[0xeb]	1076	1			T5	7		T7	5		T12	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61558

1

T2

20

T3

8

T5

391

auto[1]

1757

1

T5

12

T7

8

T13

8

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60698

1

T2

20

T3

8

T5

387

auto[1]

2617

1

T5

16

T7

8

T13

7

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10655

1

T2

20

T3

6

T5

164

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6544

1

T5

55

T7

28

T13

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2089

1

T5

31

T7

7

T13

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1800

1

T5

23

T7

4

T13

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2420

1

T3

2

T5

17

T7

14

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2043

1

T5

45

T7

14

T13

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2025

1

T5

37

T7

6

T12

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1791

1

T5

11

T7

12

T13

22

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

124

1

T15

2

T29

1

T53

7

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

93

1

T13

2

T53

2

T47

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

95

1

T5

2

T29

1

T51

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

94

1

T53

1

T51

2

T54

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

116

1

T5

1

T7

1

T12

6

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

119

1

T5

8

T7

2

T13

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

79

1

T5

1

T7

1

T13

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

92

1

T5

1

T7

3

T13

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

122

1

T5

1

T29

1

T55

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

61

1

T53

2

T166

1

T31

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

81

1

T16

1

T53

3

T51

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

95

1

T5

1

T52

6

T53

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

147

1

T12

4

T29

1

T129

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

93

1

T7

3

T13

2

T29

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

92

1

T5

3

T13

1

T51

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

149

1

T5

2

T29

1

T53

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10852

1

T30

56

T37

67

T17

153

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8244

1

T30

75

T37

34

T17

19

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1672

1

T30

26

T37

12

T17

11

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1654

1

T30

13

T37

8

T17

10

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2221

1

T30

20

T37

6

T17

23

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2142

1

T30

20

T37

20

T17

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1847

1

T30

16

T37

16

T17

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1675

1

T30

13

T37

14

T17

18

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

129

1

T30

1

T37

1

T17

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

126

1

T30

2

T37

1

T17

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

127

1

T30

3

T17

2

T167

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

125

1

T37

2

T17

2

T46

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

126

1

T30

2

T17

2

T46

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

107

1

T37

2

T17

1

T46

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

129

1

T30

1

T37

1

T46

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

125

1

T30

1

T37

3

T46

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

145

1

T17

1

T46

3

T85

8

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

139

1

T30

3

T37

3

T46

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

109

1

T17

2

T46

3

T85

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

109

1

T167

2

T168

2

T169

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

129

1

T17

1

T46

1

T85

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

108

1

T37

1

T17

3

T85

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

134

1

T30

2

T37

6

T17

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

122

1

T17

4

T85

4

T167

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3749	1			T2	20		T5	52		T7	12
auto[0]	values[0]	valids[0x1]	16300	1			T3	8		T5	199		T7	68
auto[0]	values[1]	valids[0x1]	547	1			T5	5		T7	5		T13	2
auto[0]	values[2]	valids[0x0]	568	1			T5	6		T7	4		T50	2
auto[0]	values[2]	valids[0x1]	293	1			T5	4		T7	3		T13	1
auto[0]	values[3]	valids[0x0]	516	1			T5	10		T50	2		T29	3
auto[0]	values[3]	valids[0x1]	291	1			T5	1		T7	1		T13	2
auto[0]	values[4]	valids[0x0]	549	1			T5	1		T12	6		T13	1
auto[0]	values[4]	valids[0x1]	273	1			T5	8		T7	1		T13	1
auto[0]	values[5]	valids[0x0]	531	1			T5	1		T7	4		T12	2
auto[0]	values[5]	valids[0x1]	282	1			T5	1		T13	4		T29	2
auto[0]	values[6]	valids[0x0]	500	1			T5	13		T7	2		T16	1
auto[0]	values[6]	valids[0x1]	303	1			T5	3		T13	1		T49	2
auto[0]	values[7]	valids[0x0]	541	1			T5	6		T7	4		T13	5
auto[0]	values[7]	valids[0x1]	304	1			T5	9		T7	1		T13	1
auto[0]	values[8]	valids[0x0]	3393	1			T5	41		T7	15		T13	26
auto[0]	values[8]	valids[0x1]	2079	1			T5	43		T7	12		T13	7
auto[1]	values[0]	valids[0x0]	4793	1			T30	43		T37	47		T17	48
auto[1]	values[0]	valids[0x1]	17489	1			T30	123		T37	81		T17	154
auto[1]	values[1]	valids[0x1]	632	1			T30	3		T37	2		T17	6
auto[1]	values[2]	valids[0x0]	472	1			T30	6		T37	6		T17	3
auto[1]	values[2]	valids[0x1]	305	1			T30	3		T17	4		T46	1
auto[1]	values[3]	valids[0x0]	412	1			T30	6		T17	10		T46	3
auto[1]	values[3]	valids[0x1]	314	1			T30	1		T37	1		T46	5
auto[1]	values[4]	valids[0x0]	403	1			T30	4		T37	4		T17	5
auto[1]	values[4]	valids[0x1]	276	1			T30	1		T37	1		T46	3
auto[1]	values[5]	valids[0x0]	455	1			T30	8		T37	8		T17	2
auto[1]	values[5]	valids[0x1]	345	1			T30	4		T37	2		T17	6
auto[1]	values[6]	valids[0x0]	425	1			T30	1		T37	1		T17	2
auto[1]	values[6]	valids[0x1]	313	1			T37	2		T17	2		T48	1
auto[1]	values[7]	valids[0x0]	415	1			T17	4		T46	7		T85	1
auto[1]	values[7]	valids[0x1]	311	1			T30	4		T37	1		T17	2
auto[1]	values[8]	valids[0x0]	2900	1			T30	35		T37	28		T17	24
auto[1]	values[8]	valids[0x1]	2036	1			T30	12		T37	13		T17	8