Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3578910

1

T2

1173

T3

554

T5

24614

auto[1]

28702

1

T5

123

T7

32

T13

210

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1030409

1

T2

1173

T3

554

T5

91

auto[1]

2577203

1

T5

24646

T7

7740

T13

18693

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	708762	1			T2	10		T3	22		T5	485
auto[524288:1048575]	457442	1			T2	1		T3	166		T5	3998
auto[1048576:1572863]	443365	1			T2	112		T3	133		T5	3931
auto[1572864:2097151]	367025	1			T2	469		T3	1		T5	4045
auto[2097152:2621439]	402592	1			T2	455		T3	210		T5	1075
auto[2621440:3145727]	412421	1			T2	118		T3	13		T5	4
auto[3145728:3670015]	383957	1			T2	6		T3	2		T5	7567
auto[3670016:4194303]	432048	1			T2	2		T3	7		T5	3632

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2611934

1

T2

245

T3

24

T5

24724

auto[1]

995678

1

T2

928

T3

530

T5

13

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3135805

1

T2

243

T3

554

T5

22593

auto[1]

471807

1

T2

930

T5

2144

T7

1

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	228290	1			T2	7		T3	22		T5	10
auto[0]	auto[0]	auto[0:524287]	auto[1]	397339	1			T5	427		T7	1723		T13	6085
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	138973	1			T3	166		T5	11		T7	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	242435	1			T5	3714		T7	128		T13	2438
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	145754	1			T2	112		T3	133		T5	9
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	232018	1			T5	3893		T7	5087		T13	2624
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	120821	1			T2	4		T3	1		T5	8
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	192209	1			T5	4037		T13	2890		T29	129
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	95511	1			T3	210		T7	2		T13	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	252923	1			T13	2908		T29	1		T30	123
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	92073	1			T2	118		T3	13		T5	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	266191	1			T5	1		T7	775		T29	2542
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	99508	1			T3	2		T5	16		T13	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	230726	1			T5	7523		T13	1027		T29	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	91417	1			T2	2		T3	7		T5	8
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	286380	1			T5	2843		T7	3		T37	3
auto[0]	auto[1]	auto[0:524287]	auto[0]	1231	1			T2	3		T5	7		T7	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	77194	1			T5	2		T13	1		T53	1751
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1419	1			T2	1		T5	2		T29	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	71533	1			T5	256		T29	258		T53	5362
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1404	1			T5	2		T30	10		T17	6
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	61666	1			T30	673		T17	513		T85	6
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1303	1			T2	465		T30	1		T37	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	49697	1			T30	512		T37	3		T17	5331
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	4365	1			T2	455		T29	4		T46	14
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	45381	1			T5	1075		T29	3		T37	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	573	1			T85	1		T167	1		T168	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	48647	1			T85	434		T55	2672		T197	129
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1616	1			T2	6		T13	1		T30	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	49629	1			T13	1		T37	132		T167	257
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2021	1			T5	1		T13	3		T29	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	48663	1			T5	768		T13	516		T30	312
auto[1]	auto[0]	auto[0:524287]	auto[0]	516	1			T5	1		T7	2		T29	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3678	1			T5	7		T7	9		T29	3
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	448	1			T5	2		T30	1		T16	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2027	1			T5	13		T30	6		T16	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	422	1			T5	4		T7	1		T29	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1803	1			T5	23		T37	3		T17	33
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	376	1			T13	3		T29	1		T30	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2031	1			T13	91		T29	1		T16	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	370	1			T13	2		T29	1		T30	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3131	1			T13	56		T30	5		T37	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	467	1			T5	1		T7	2		T29	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3123	1			T5	1		T7	14		T30	6
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	325	1			T5	5		T30	1		T37	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1539	1			T5	23		T30	1		T37	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	432	1			T5	1		T7	3		T37	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2549	1			T5	11		T7	1		T53	54
auto[1]	auto[1]	auto[0:524287]	auto[0]	120	1			T5	2		T13	1		T53	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	394	1			T5	29		T13	31		T53	26
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	89	1			T46	8		T20	1		T31	4
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	518	1			T20	7		T31	66		T34	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	78	1			T30	4		T17	1		T46	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	220	1			T30	17		T17	14		T85	9
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	76	1			T37	3		T197	2		T186	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	512	1			T37	2		T197	40		T186	13
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	116	1			T29	3		T85	1		T168	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	795	1			T29	1		T85	23		T168	73
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	81	1			T46	3		T55	1		T197	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1266	1			T55	68		T197	7		T207	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	121	1			T13	1		T167	1		T39	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	493	1			T13	25		T167	1		T55	23
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	93	1			T37	1		T53	1		T168	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	493	1			T37	1		T53	23		T168	14

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2126748	1			T2	229		T3	24		T5	22494
auto[0]	auto[0]	auto[1]	985820	1			T2	14		T3	530		T5	7
auto[0]	auto[1]	auto[0]	457179	1			T2	16		T5	2113		T7	1
auto[0]	auto[1]	auto[1]	9163	1			T2	914		T17	1		T53	1
auto[1]	auto[0]	auto[0]	22663	1			T5	86		T7	31		T13	152
auto[1]	auto[0]	auto[1]	574	1			T5	6		T7	1		T17	5
auto[1]	auto[1]	auto[0]	5344	1			T5	31		T13	58		T29	4
auto[1]	auto[1]	auto[1]	121	1			T37	1		T17	1		T53	1