Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3197363	1			T1	1		T2	1		T3	1
all_pins[1]	3197363	1			T1	1		T2	1		T3	1
all_pins[2]	3197363	1			T1	1		T2	1		T3	1
all_pins[3]	3197363	1			T1	1		T2	1		T3	1
all_pins[4]	3197363	1			T1	1		T2	1		T3	1
all_pins[5]	3197363	1			T1	1		T2	1		T3	1
all_pins[6]	3197363	1			T1	1		T2	1		T3	1
all_pins[7]	3197363	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	25419436	1			T1	8		T2	8		T3	8
values[0x1]	159468	1			T16	46		T17	24		T18	23
transitions[0x0=>0x1]	158225	1			T16	28		T17	19		T18	18
transitions[0x1=>0x0]	158239	1			T16	28		T17	19		T18	19

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3196841	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	522	1			T16	2		T17	2		T18	1
all_pins[0]	transitions[0x0=>0x1]	409	1			T17	1		T18	1		T19	3
all_pins[0]	transitions[0x1=>0x0]	242	1			T16	4		T17	2		T18	1
all_pins[1]	values[0x0]	3197008	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	355	1			T16	6		T17	3		T18	1
all_pins[1]	transitions[0x0=>0x1]	303	1			T16	1		T17	2		T18	1
all_pins[1]	transitions[0x1=>0x0]	146	1			T16	7		T17	3		T18	1
all_pins[2]	values[0x0]	3197165	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	198	1			T16	12		T17	4		T18	1
all_pins[2]	transitions[0x0=>0x1]	149	1			T16	6		T17	4		T18	1
all_pins[2]	transitions[0x1=>0x0]	152	1			T16	3		T17	4		T18	3
all_pins[3]	values[0x0]	3197162	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	201	1			T16	9		T17	4		T18	3
all_pins[3]	transitions[0x0=>0x1]	151	1			T16	4		T17	2		T18	2
all_pins[3]	transitions[0x1=>0x0]	143	1			T16	3		T17	4		T18	6
all_pins[4]	values[0x0]	3197170	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	193	1			T16	8		T17	6		T18	7
all_pins[4]	transitions[0x0=>0x1]	162	1			T16	8		T17	5		T18	6
all_pins[4]	transitions[0x1=>0x0]	1545	1			T16	2		T18	1		T19	5
all_pins[5]	values[0x0]	3195787	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	1576	1			T16	2		T17	1		T18	2
all_pins[5]	transitions[0x0=>0x1]	737	1			T16	2		T17	1		T18	2
all_pins[5]	transitions[0x1=>0x0]	155364	1			T16	4		T17	1		T18	4
all_pins[6]	values[0x0]	3041160	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	156203	1			T16	4		T17	1		T18	4
all_pins[6]	transitions[0x0=>0x1]	156151	1			T16	4		T17	1		T18	3
all_pins[6]	transitions[0x1=>0x0]	168	1			T16	3		T17	3		T18	3
all_pins[7]	values[0x0]	3197143	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	220	1			T16	3		T17	3		T18	4
all_pins[7]	transitions[0x0=>0x1]	163	1			T16	3		T17	3		T18	2
all_pins[7]	transitions[0x1=>0x0]	479	1			T16	2		T17	2		T19	4