Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18064

1

T2

20

T3

8

T5

259

auto[1]

12955

1

T5

144

T7

62

T13

53

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3808	1			T3	8		T5	132		T7	56
values[1]	4581	1			T5	103		T13	192		T29	22
values[2]	4046	1			T5	30		T7	30		T36	12
values[3]	3526	1			T2	20		T5	40		T12	20
values[4]	3629	1			T5	20		T7	46		T49	12
values[5]	3864	1			T13	20		T29	43		T51	24
values[6]	3894	1			T5	55		T228	2		T53	139
values[7]	3671	1			T5	23		T38	16		T229	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3707	1			T2	20		T5	85		T50	14
values[1]	4011	1			T5	101		T12	20		T13	52
values[2]	4177	1			T5	20		T7	32		T13	46
values[3]	3901	1			T49	12		T29	23		T16	28
values[4]	3346	1			T5	82		T7	21		T13	20
values[5]	4156	1			T3	8		T7	79		T13	160
values[6]	3822	1			T5	95		T13	52		T23	6
values[7]	3899	1			T5	20		T116	6		T53	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	344	1			T5	38		T54	8		T178	9
auto[0]	values[0]	values[1]	228	1			T13	44		T29	10		T55	16
auto[0]	values[0]	values[2]	522	1			T5	17		T7	16		T53	50
auto[0]	values[0]	values[3]	208	1			T29	18		T201	11		T230	13
auto[0]	values[0]	values[4]	348	1			T5	53		T53	39		T201	13
auto[0]	values[0]	values[5]	200	1			T3	8		T7	9		T13	15
auto[0]	values[0]	values[6]	143	1			T51	9		T32	16		T231	18
auto[0]	values[0]	values[7]	233	1			T51	12		T232	2		T227	14
auto[0]	values[1]	values[0]	300	1			T5	10		T51	13		T55	11
auto[0]	values[1]	values[1]	245	1			T5	21		T29	12		T186	14
auto[0]	values[1]	values[2]	127	1			T34	7		T185	9		T41	11
auto[0]	values[1]	values[3]	321	1			T16	12		T78	32		T182	15
auto[0]	values[1]	values[4]	236	1			T53	36		T32	13		T152	10
auto[0]	values[1]	values[5]	530	1			T13	127		T186	12		T78	7
auto[0]	values[1]	values[6]	666	1			T5	28		T13	44		T78	20
auto[0]	values[1]	values[7]	492	1			T233	4		T31	161		T32	13
auto[0]	values[2]	values[0]	229	1			T36	12		T54	14		T34	10
auto[0]	values[2]	values[1]	372	1			T5	21		T97	24		T189	4
auto[0]	values[2]	values[2]	293	1			T21	11		T211	12		T234	10
auto[0]	values[2]	values[3]	345	1			T78	14		T152	6		T219	31
auto[0]	values[2]	values[4]	369	1			T32	7		T34	24		T231	25
auto[0]	values[2]	values[5]	123	1			T7	19		T222	10		T216	16
auto[0]	values[2]	values[6]	251	1			T182	43		T235	4		T223	12
auto[0]	values[2]	values[7]	267	1			T236	14		T31	29		T231	12
auto[0]	values[3]	values[0]	288	1			T2	20		T53	11		T51	10
auto[0]	values[3]	values[1]	208	1			T12	20		T29	22		T206	10
auto[0]	values[3]	values[2]	265	1			T13	35		T55	13		T217	8
auto[0]	values[3]	values[3]	155	1			T183	14		T237	17		T132	16
auto[0]	values[3]	values[4]	190	1			T5	9		T214	14		T238	20
auto[0]	values[3]	values[5]	230	1			T53	11		T55	15		T78	11
auto[0]	values[3]	values[6]	238	1			T5	9		T53	47		T31	13
auto[0]	values[3]	values[7]	506	1			T166	15		T32	14		T239	16
auto[0]	values[4]	values[0]	347	1			T129	10		T54	5		T240	65
auto[0]	values[4]	values[1]	161	1			T51	8		T55	12		T32	16
auto[0]	values[4]	values[2]	489	1			T55	13		T202	6		T32	15
auto[0]	values[4]	values[3]	214	1			T49	12		T241	12		T181	20
auto[0]	values[4]	values[4]	278	1			T7	8		T53	35		T51	19
auto[0]	values[4]	values[5]	297	1			T7	18		T53	45		T198	10
auto[0]	values[4]	values[6]	139	1			T23	6		T47	5		T220	14
auto[0]	values[4]	values[7]	285	1			T5	9		T116	6		T53	12
auto[0]	values[5]	values[0]	252	1			T29	13		T166	10		T242	6
auto[0]	values[5]	values[1]	244	1			T29	13		T243	15		T34	8
auto[0]	values[5]	values[2]	441	1			T231	14		T154	104		T227	14
auto[0]	values[5]	values[3]	272	1			T244	2		T55	44		T245	7
auto[0]	values[5]	values[4]	256	1			T13	12		T246	10		T32	20
auto[0]	values[5]	values[5]	294	1			T51	17		T31	12		T186	11
auto[0]	values[5]	values[6]	200	1			T31	13		T78	14		T221	18
auto[0]	values[5]	values[7]	294	1			T78	10		T182	31		T201	9
auto[0]	values[6]	values[0]	225	1			T53	69		T78	13		T93	6
auto[0]	values[6]	values[1]	340	1			T5	13		T228	2		T54	5
auto[0]	values[6]	values[2]	204	1			T31	39		T152	15		T154	6
auto[0]	values[6]	values[3]	250	1			T55	14		T78	15		T204	6
auto[0]	values[6]	values[4]	254	1			T93	12		T247	12		T237	7
auto[0]	values[6]	values[5]	320	1			T53	11		T47	9		T55	11
auto[0]	values[6]	values[6]	256	1			T5	14		T234	13		T185	13
auto[0]	values[6]	values[7]	216	1			T204	17		T248	13		T184	16
auto[0]	values[7]	values[0]	158	1			T38	16		T162	2		T178	18
auto[0]	values[7]	values[1]	316	1			T5	17		T249	8		T31	12
auto[0]	values[7]	values[2]	287	1			T250	12		T201	18		T227	12
auto[0]	values[7]	values[3]	266	1			T251	8		T178	15		T219	17
auto[0]	values[7]	values[4]	172	1			T252	4		T54	14		T31	11
auto[0]	values[7]	values[5]	355	1			T166	7		T186	45		T77	6
auto[0]	values[7]	values[6]	253	1			T152	28		T216	15		T154	27
auto[0]	values[7]	values[7]	257	1			T195	10		T78	9		T93	23
auto[1]	values[0]	values[0]	214	1			T5	12		T54	38		T178	11
auto[1]	values[0]	values[1]	201	1			T13	8		T29	10		T55	40
auto[1]	values[0]	values[2]	298	1			T5	3		T7	16		T53	12
auto[1]	values[0]	values[3]	134	1			T29	5		T201	14		T230	16
auto[1]	values[0]	values[4]	209	1			T5	9		T53	21		T201	41
auto[1]	values[0]	values[5]	308	1			T7	15		T13	5		T55	118
auto[1]	values[0]	values[6]	97	1			T51	14		T32	9		T231	10
auto[1]	values[0]	values[7]	121	1			T51	8		T227	8		T247	10
auto[1]	values[1]	values[0]	228	1			T5	25		T51	10		T55	29
auto[1]	values[1]	values[1]	150	1			T5	7		T29	10		T186	6
auto[1]	values[1]	values[2]	98	1			T34	13		T185	11		T41	13
auto[1]	values[1]	values[3]	164	1			T16	16		T78	28		T182	5
auto[1]	values[1]	values[4]	127	1			T53	3		T32	8		T152	13
auto[1]	values[1]	values[5]	283	1			T13	13		T186	8		T78	13
auto[1]	values[1]	values[6]	499	1			T5	12		T13	8		T52	20
auto[1]	values[1]	values[7]	115	1			T31	12		T32	7		T34	12
auto[1]	values[2]	values[0]	171	1			T54	8		T34	10		T152	7
auto[1]	values[2]	values[1]	277	1			T5	9		T51	13		T186	7
auto[1]	values[2]	values[2]	307	1			T21	9		T253	4		T211	8
auto[1]	values[2]	values[3]	474	1			T78	45		T152	14		T219	10
auto[1]	values[2]	values[4]	184	1			T32	18		T34	30		T231	30
auto[1]	values[2]	values[5]	92	1			T7	11		T222	11		T216	7
auto[1]	values[2]	values[6]	157	1			T56	22		T182	10		T223	8
auto[1]	values[2]	values[7]	135	1			T31	20		T231	8		T223	11
auto[1]	values[3]	values[0]	228	1			T50	14		T53	69		T51	10
auto[1]	values[3]	values[1]	119	1			T29	5		T206	10		T178	14
auto[1]	values[3]	values[2]	307	1			T13	11		T55	41		T211	8
auto[1]	values[3]	values[3]	110	1			T254	10		T183	6		T237	6
auto[1]	values[3]	values[4]	92	1			T5	11		T191	26		T255	3
auto[1]	values[3]	values[5]	245	1			T53	91		T55	5		T78	9
auto[1]	values[3]	values[6]	161	1			T5	11		T53	9		T31	22
auto[1]	values[3]	values[7]	184	1			T166	5		T32	7		T216	5
auto[1]	values[4]	values[0]	266	1			T54	15		T132	16		T256	2
auto[1]	values[4]	values[1]	207	1			T51	13		T55	8		T32	7
auto[1]	values[4]	values[2]	177	1			T55	21		T32	7		T93	7
auto[1]	values[4]	values[3]	131	1			T200	18		T257	6		T256	22
auto[1]	values[4]	values[4]	197	1			T7	13		T53	10		T51	21
auto[1]	values[4]	values[5]	155	1			T7	7		T53	6		T31	20
auto[1]	values[4]	values[6]	124	1			T47	15		T78	10		T154	8
auto[1]	values[4]	values[7]	162	1			T5	11		T53	8		T31	13
auto[1]	values[5]	values[0]	138	1			T29	8		T166	10		T258	9
auto[1]	values[5]	values[1]	422	1			T29	9		T243	7		T34	14
auto[1]	values[5]	values[2]	127	1			T231	6		T154	6		T227	6
auto[1]	values[5]	values[3]	229	1			T55	12		T245	13		T166	11
auto[1]	values[5]	values[4]	117	1			T13	8		T32	3		T216	6
auto[1]	values[5]	values[5]	131	1			T51	7		T31	18		T186	9
auto[1]	values[5]	values[6]	128	1			T31	14		T78	6		T216	8
auto[1]	values[5]	values[7]	319	1			T78	10		T182	9		T201	11
auto[1]	values[6]	values[0]	217	1			T53	6		T78	17		T93	14
auto[1]	values[6]	values[1]	295	1			T5	7		T54	15		T152	6
auto[1]	values[6]	values[2]	94	1			T31	7		T152	5		T154	14
auto[1]	values[6]	values[3]	492	1			T55	75		T78	29		T204	40
auto[1]	values[6]	values[4]	194	1			T93	8		T247	30		T237	14
auto[1]	values[6]	values[5]	230	1			T53	53		T47	11		T55	9
auto[1]	values[6]	values[6]	160	1			T5	21		T234	7		T185	7
auto[1]	values[6]	values[7]	147	1			T204	4		T248	7		T184	26
auto[1]	values[7]	values[0]	102	1			T178	22		T222	21		T231	10
auto[1]	values[7]	values[1]	226	1			T5	6		T31	8		T34	14
auto[1]	values[7]	values[2]	141	1			T201	2		T227	8		T41	11
auto[1]	values[7]	values[3]	136	1			T178	5		T219	7		T231	14
auto[1]	values[7]	values[4]	123	1			T54	9		T31	12		T248	6
auto[1]	values[7]	values[5]	363	1			T166	13		T186	8		T182	14
auto[1]	values[7]	values[6]	350	1			T229	2		T152	18		T216	8
auto[1]	values[7]	values[7]	166	1			T78	20		T93	17		T184	8