Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	406	1			T5	4		T7	6		T29	5
auto[ReadAddrCrossIntoMailbox]	308	1			T5	6		T7	2		T13	1
auto[ReadAddrCrossOutOfMailbox]	294	1			T5	4		T7	2		T29	1
auto[ReadAddrCrossAllMailbox]	204	1			T5	3		T7	2		T53	1
auto[ReadAddrOutsideMailbox]	3414	1			T5	49		T7	6		T12	8

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2251

1

T5

35

T7

11

T12

4

auto[1]

2375

1

T5

31

T7

7

T12

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	785	1			T5	13		T7	2		T13	2
read_ops[0x0b]	746	1			T5	16		T7	3		T13	4
read_ops[0x3b]	794	1			T5	12		T7	3		T13	7
read_ops[0x6b]	759	1			T5	7		T7	3		T13	6
read_ops[0xbb]	783	1			T5	11		T7	2		T12	6
read_ops[0xeb]	759	1			T5	7		T7	5		T12	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T54	2		T246	1		T182	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T51	1		T246	1		T245	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T7	1		T53	1		T54	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T5	1		T31	3		T178	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T7	1		T182	1		T231	3
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T53	1		T245	1		T31	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T5	1		T53	1		T166	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T5	1		T206	1		T166	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T5	8		T13	2		T49	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	294	1			T5	2		T49	1		T29	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T29	1		T51	1		T166	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T5	1		T53	1		T54	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T211	1		T231	1		T260	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T5	2		T32	1		T34	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T29	1		T53	1		T55	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T5	1		T7	1		T51	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T55	1		T166	1		T152	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T5	1		T7	1		T31	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	259	1			T5	9		T7	1		T13	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T5	2		T13	3		T29	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T7	1		T29	1		T219	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T5	2		T55	1		T231	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T13	1		T53	2		T51	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T54	1		T211	1		T154	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T32	1		T222	1		T216	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T53	2		T152	1		T261	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T54	1		T34	1		T216	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T54	1		T166	1		T204	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	299	1			T5	5		T7	2		T13	5
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	311	1			T5	5		T13	1		T49	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T7	1		T51	3		T54	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T5	1		T7	1		T54	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T51	1		T54	1		T55	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T5	1		T55	1		T245	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T5	1		T55	1		T206	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T55	1		T178	1		T34	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T51	1		T34	1		T231	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T31	1		T204	1		T211	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	252	1			T5	1		T7	1		T13	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	292	1			T5	3		T13	4		T16	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T7	1		T29	3		T246	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T246	1		T21	1		T34	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T5	1		T55	1		T166	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T53	2		T55	1		T245	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T55	1		T152	3		T211	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T51	2		T152	1		T219	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T31	1		T152	1		T211	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T21	1		T184	1		T185	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	282	1			T5	3		T7	1		T12	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	296	1			T5	7		T12	3		T13	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T189	1		T53	2		T51	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T7	2		T189	1		T53	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T5	1		T55	1		T166	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T7	1		T31	2		T34	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T5	2		T53	1		T32	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T51	1		T31	1		T186	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T51	1		T54	2		T32	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T7	1		T51	1		T178	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	283	1			T5	3		T7	1		T12	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	272	1			T5	1		T12	1		T50	1