Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3313	1			T3	8		T5	40		T7	21
values[1]	3627	1			T5	20		T7	32		T52	20
values[2]	3617	1			T5	82		T12	20		T53	125
values[3]	4313	1			T5	55		T7	30		T13	186
values[4]	3848	1			T5	83		T7	24		T13	20
values[5]	4036	1			T5	70		T13	52		T22	12
values[6]	4547	1			T2	20		T5	23		T13	52
values[7]	3718	1			T5	30		T7	25		T13	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3475	1			T5	20		T129	10		T53	20
values[1]	3723	1			T5	20		T7	32		T12	20
values[2]	3584	1			T3	8		T5	40		T13	98
values[3]	3692	1			T2	20		T5	123		T7	76
values[4]	4081	1			T5	35		T13	52		T16	28
values[5]	4006	1			T5	90		T15	10		T38	16
values[6]	4862	1			T5	20		T13	20		T50	14
values[7]	3596	1			T5	55		T7	24		T29	70

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30223

1

T2

20

T3

8

T5

391

auto[1]

796

1

T5

12

T7

8

T13

8

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	431	1			T166	16		T211	26		T223	20
auto[0]	values[0]	values[1]	263	1			T162	2		T34	22		T78	20
auto[0]	values[0]	values[2]	424	1			T3	8		T31	44		T201	20
auto[0]	values[0]	values[3]	386	1			T5	19		T7	17		T186	20
auto[0]	values[0]	values[4]	521	1			T53	20		T182	51		T234	18
auto[0]	values[0]	values[5]	450	1			T15	10		T205	8		T178	20
auto[0]	values[0]	values[6]	442	1			T23	6		T41	21		T237	68
auto[0]	values[0]	values[7]	317	1			T5	20		T259	12		T262	16
auto[0]	values[1]	values[0]	593	1			T5	20		T55	96		T251	8
auto[0]	values[1]	values[1]	394	1			T7	32		T55	54		T178	20
auto[0]	values[1]	values[2]	356	1			T52	14		T51	20		T31	20
auto[0]	values[1]	values[3]	484	1			T53	75		T263	16		T247	41
auto[0]	values[1]	values[4]	431	1			T166	18		T222	23		T216	20
auto[0]	values[1]	values[5]	415	1			T56	20		T82	16		T204	18
auto[0]	values[1]	values[6]	425	1			T31	27		T34	20		T211	20
auto[0]	values[1]	values[7]	444	1			T47	20		T178	20		T201	54
auto[0]	values[2]	values[0]	270	1			T55	20		T93	17		T231	56
auto[0]	values[2]	values[1]	692	1			T5	20		T12	20		T53	78
auto[0]	values[2]	values[2]	314	1			T54	20		T31	19		T264	19
auto[0]	values[2]	values[3]	279	1			T78	20		T211	21		T231	24
auto[0]	values[2]	values[4]	372	1			T233	4		T31	20		T216	20
auto[0]	values[2]	values[5]	529	1			T5	62		T53	42		T245	20
auto[0]	values[2]	values[6]	613	1			T55	56		T249	8		T202	6
auto[0]	values[2]	values[7]	447	1			T51	41		T178	20		T190	8
auto[0]	values[3]	values[0]	369	1			T198	10		T232	2		T154	20
auto[0]	values[3]	values[1]	339	1			T13	137		T243	20		T242	6
auto[0]	values[3]	values[2]	467	1			T5	20		T13	45		T166	20
auto[0]	values[3]	values[3]	594	1			T7	30		T182	20		T201	59
auto[0]	values[3]	values[4]	772	1			T5	34		T16	28		T53	61
auto[0]	values[3]	values[5]	450	1			T54	22		T222	21		T184	20
auto[0]	values[3]	values[6]	733	1			T50	14		T116	6		T229	2
auto[0]	values[3]	values[7]	465	1			T29	20		T36	12		T55	20
auto[0]	values[4]	values[0]	399	1			T53	19		T51	24		T21	18
auto[0]	values[4]	values[1]	229	1			T166	19		T231	27		T265	8
auto[0]	values[4]	values[2]	453	1			T53	20		T31	20		T204	17
auto[0]	values[4]	values[3]	589	1			T13	18		T29	19		T253	2
auto[0]	values[4]	values[4]	512	1			T192	17		T234	20		T209	64
auto[0]	values[4]	values[5]	567	1			T5	28		T163	2		T54	46
auto[0]	values[4]	values[6]	659	1			T5	20		T53	39		T51	20
auto[0]	values[4]	values[7]	311	1			T5	29		T7	21		T201	20
auto[0]	values[5]	values[0]	321	1			T54	20		T236	14		T200	18
auto[0]	values[5]	values[1]	787	1			T53	101		T32	23		T261	30
auto[0]	values[5]	values[2]	445	1			T5	20		T13	52		T214	14
auto[0]	values[5]	values[3]	320	1			T5	49		T31	35		T154	20
auto[0]	values[5]	values[4]	544	1			T53	62		T152	20		T222	46
auto[0]	values[5]	values[5]	417	1			T38	16		T31	23		T32	25
auto[0]	values[5]	values[6]	607	1			T22	12		T51	19		T204	46
auto[0]	values[5]	values[7]	513	1			T189	4		T215	4		T191	26
auto[0]	values[6]	values[0]	500	1			T55	19		T32	21		T204	21
auto[0]	values[6]	values[1]	457	1			T241	12		T201	19		T266	2
auto[0]	values[6]	values[2]	722	1			T29	22		T97	24		T51	20
auto[0]	values[6]	values[3]	496	1			T2	20		T5	23		T49	12
auto[0]	values[6]	values[4]	517	1			T13	50		T53	50		T54	21
auto[0]	values[6]	values[5]	319	1			T178	20		T32	20		T267	6
auto[0]	values[6]	values[6]	846	1			T47	17		T54	20		T34	19
auto[0]	values[6]	values[7]	570	1			T29	25		T268	6		T184	49
auto[0]	values[7]	values[0]	489	1			T129	10		T166	20		T152	20
auto[0]	values[7]	values[1]	488	1			T55	33		T31	30		T182	28
auto[0]	values[7]	values[2]	312	1			T244	2		T261	25		T227	21
auto[0]	values[7]	values[3]	433	1			T5	27		T7	24		T228	2
auto[0]	values[7]	values[4]	325	1			T252	4		T55	89		T31	29
auto[0]	values[7]	values[5]	749	1			T53	20		T51	23		T206	20
auto[0]	values[7]	values[6]	422	1			T13	20		T51	19		T245	20
auto[0]	values[7]	values[7]	424	1			T29	23		T53	56		T217	8
auto[1]	values[0]	values[0]	26	1			T166	4		T211	4		T234	1
auto[1]	values[0]	values[1]	13	1			T269	6		T270	2		T271	1
auto[1]	values[0]	values[2]	9	1			T31	2		T258	2		T272	1
auto[1]	values[0]	values[3]	9	1			T5	1		T7	4		T178	1
auto[1]	values[0]	values[4]	11	1			T182	2		T234	2		T41	1
auto[1]	values[0]	values[5]	6	1			T93	1		T209	1		T156	2
auto[1]	values[0]	values[6]	4	1			T273	1		T274	3		-	-
auto[1]	values[0]	values[7]	1	1			T154	1		-	-		-	-
auto[1]	values[1]	values[0]	15	1			T31	6		T216	2		T258	1
auto[1]	values[1]	values[1]	2	1			T132	1		T275	1		-	-
auto[1]	values[1]	values[2]	10	1			T52	6		T51	1		T130	2
auto[1]	values[1]	values[3]	8	1			T247	1		T276	3		T230	1
auto[1]	values[1]	values[4]	12	1			T166	2		T222	1		T216	2
auto[1]	values[1]	values[5]	12	1			T56	2		T204	4		T93	2
auto[1]	values[1]	values[6]	19	1			T231	3		T227	2		T130	2
auto[1]	values[1]	values[7]	7	1			T130	1		T132	1		T277	3
auto[1]	values[2]	values[0]	11	1			T93	3		T231	2		T255	1
auto[1]	values[2]	values[1]	11	1			T53	2		T186	2		T32	1
auto[1]	values[2]	values[2]	16	1			T54	2		T31	1		T264	1
auto[1]	values[2]	values[3]	12	1			T184	3		T209	1		T247	4
auto[1]	values[2]	values[4]	7	1			T183	1		T247	1		T278	1
auto[1]	values[2]	values[5]	19	1			T53	3		T32	1		T261	1
auto[1]	values[2]	values[6]	16	1			T237	2		T258	5		T279	1
auto[1]	values[2]	values[7]	9	1			T152	1		T216	2		T209	2
auto[1]	values[3]	values[0]	9	1			T185	1		T209	1		T260	1
auto[1]	values[3]	values[1]	7	1			T13	3		T243	2		T185	1
auto[1]	values[3]	values[2]	13	1			T13	1		T209	3		T237	1
auto[1]	values[3]	values[3]	23	1			T201	2		T231	1		T258	4
auto[1]	values[3]	values[4]	17	1			T5	1		T53	3		T154	3
auto[1]	values[3]	values[5]	15	1			T41	1		T264	2		T280	3
auto[1]	values[3]	values[6]	22	1			T152	1		T234	1		T41	1
auto[1]	values[3]	values[7]	18	1			T78	1		T216	1		T192	5
auto[1]	values[4]	values[0]	12	1			T53	1		T21	2		T219	3
auto[1]	values[4]	values[1]	7	1			T166	1		T281	2		T158	3
auto[1]	values[4]	values[2]	12	1			T204	4		T216	1		T260	1
auto[1]	values[4]	values[3]	26	1			T13	2		T29	2		T253	2
auto[1]	values[4]	values[4]	17	1			T192	3		T272	2		T282	4
auto[1]	values[4]	values[5]	24	1			T283	2		T41	2		T258	1
auto[1]	values[4]	values[6]	15	1			T154	1		T130	2		T284	3
auto[1]	values[4]	values[7]	16	1			T5	6		T7	3		T184	1
auto[1]	values[5]	values[0]	13	1			T285	2		T273	3		T58	3
auto[1]	values[5]	values[1]	16	1			T53	1		T261	2		T278	4
auto[1]	values[5]	values[2]	10	1			T32	1		T152	1		T231	2
auto[1]	values[5]	values[3]	4	1			T5	1		T209	2		T286	1
auto[1]	values[5]	values[4]	8	1			T256	3		T155	2		T287	1
auto[1]	values[5]	values[5]	6	1			T256	1		T288	2		T155	1
auto[1]	values[5]	values[6]	8	1			T51	1		T93	2		T288	3
auto[1]	values[5]	values[7]	17	1			T247	1		T203	3		T289	3
auto[1]	values[6]	values[0]	13	1			T55	1		T32	2		T290	3
auto[1]	values[6]	values[1]	13	1			T201	1		T211	6		T216	1
auto[1]	values[6]	values[2]	15	1			T55	1		T34	1		T237	1
auto[1]	values[6]	values[3]	16	1			T29	2		T216	2		T223	2
auto[1]	values[6]	values[4]	14	1			T13	2		T53	1		T54	2
auto[1]	values[6]	values[5]	12	1			T247	2		T278	7		T291	2
auto[1]	values[6]	values[6]	16	1			T47	3		T34	2		T216	1
auto[1]	values[6]	values[7]	21	1			T29	2		T184	4		T247	2
auto[1]	values[7]	values[0]	4	1			T216	1		T292	1		T293	2
auto[1]	values[7]	values[1]	5	1			T55	1		T192	2		T274	1
auto[1]	values[7]	values[2]	6	1			T261	2		T227	1		T208	1
auto[1]	values[7]	values[3]	13	1			T5	3		T7	1		T32	1
auto[1]	values[7]	values[4]	1	1			T278	1		-	-		-	-
auto[1]	values[7]	values[5]	16	1			T192	1		T248	2		T255	3
auto[1]	values[7]	values[6]	15	1			T51	4		T182	3		T223	1
auto[1]	values[7]	values[7]	16	1			T32	3		T227	1		T247	1