Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	853	1			T16	21		T17	10		T18	14
all_values[1]	853	1			T16	21		T17	10		T18	14
all_values[2]	853	1			T16	21		T17	10		T18	14
all_values[3]	853	1			T16	21		T17	10		T18	14
all_values[4]	853	1			T16	21		T17	10		T18	14
all_values[5]	853	1			T16	21		T17	10		T18	14
all_values[6]	853	1			T16	21		T17	10		T18	14
all_values[7]	853	1			T16	21		T17	10		T18	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3612

1

T16

73

T17

28

T18

51

auto[1]

3212

1

T16

95

T17

52

T18

61

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2669

1

T16

69

T17

25

T18

48

auto[1]

4155

1

T16

99

T17

55

T18

64

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3845

1

T16

98

T17

38

T18

64

auto[1]

2979

1

T16

70

T17

42

T18

48

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	154	1			T16	5		T17	2		T18	5
all_values[0]	auto[0]	auto[0]	auto[1]	80	1			T16	2		T17	1		T19	1
all_values[0]	auto[0]	auto[1]	auto[0]	139	1			T16	5		T17	2		T18	3
all_values[0]	auto[0]	auto[1]	auto[1]	102	1			T16	2		T17	1		T19	3
all_values[0]	auto[1]	auto[0]	auto[1]	188	1			T16	6		T17	1		T18	4
all_values[0]	auto[1]	auto[1]	auto[1]	190	1			T16	1		T17	3		T18	2
all_values[1]	auto[0]	auto[0]	auto[0]	183	1			T16	2		T17	2		T18	3
all_values[1]	auto[0]	auto[0]	auto[1]	96	1			T16	4		T19	1		T20	1
all_values[1]	auto[0]	auto[1]	auto[0]	132	1			T16	3		T18	6		T19	4
all_values[1]	auto[0]	auto[1]	auto[1]	73	1			T16	2		T17	1		T18	1
all_values[1]	auto[1]	auto[0]	auto[1]	212	1			T16	5		T17	4		T18	2
all_values[1]	auto[1]	auto[1]	auto[1]	157	1			T16	5		T17	3		T18	2
all_values[2]	auto[0]	auto[0]	auto[0]	188	1			T16	2		T18	4		T19	3
all_values[2]	auto[0]	auto[0]	auto[1]	81	1			T16	3		T18	2		T19	3
all_values[2]	auto[0]	auto[1]	auto[0]	151	1			T16	3		T18	4		T19	3
all_values[2]	auto[0]	auto[1]	auto[1]	79	1			T16	4		T17	2		T18	1
all_values[2]	auto[1]	auto[0]	auto[1]	189	1			T17	6		T18	2		T19	5
all_values[2]	auto[1]	auto[1]	auto[1]	165	1			T16	9		T17	2		T18	1
all_values[3]	auto[0]	auto[0]	auto[0]	165	1			T16	3		T19	3		T20	2
all_values[3]	auto[0]	auto[0]	auto[1]	97	1			T16	1		T17	1		T18	2
all_values[3]	auto[0]	auto[1]	auto[0]	132	1			T16	6		T17	2		T18	2
all_values[3]	auto[0]	auto[1]	auto[1]	75	1			T16	2		T18	1		T19	3
all_values[3]	auto[1]	auto[0]	auto[1]	204	1			T16	1		T17	1		T18	8
all_values[3]	auto[1]	auto[1]	auto[1]	180	1			T16	8		T17	6		T18	1
all_values[4]	auto[0]	auto[0]	auto[0]	172	1			T16	7		T19	3		T20	4
all_values[4]	auto[0]	auto[0]	auto[1]	86	1			T16	1		T18	3		T19	1
all_values[4]	auto[0]	auto[1]	auto[0]	156	1			T16	2		T18	2		T19	6
all_values[4]	auto[0]	auto[1]	auto[1]	69	1			T16	1		T17	2		T18	3
all_values[4]	auto[1]	auto[0]	auto[1]	193	1			T16	1		T18	1		T19	4
all_values[4]	auto[1]	auto[1]	auto[1]	177	1			T16	9		T17	8		T18	5
all_values[5]	auto[0]	auto[0]	auto[0]	239	1			T16	5		T17	3		T18	2
all_values[5]	auto[0]	auto[1]	auto[0]	230	1			T16	7		T17	4		T18	5
all_values[5]	auto[1]	auto[0]	auto[1]	193	1			T16	7		T17	1		T18	5
all_values[5]	auto[1]	auto[1]	auto[1]	191	1			T16	2		T17	2		T18	2
all_values[6]	auto[0]	auto[0]	auto[0]	170	1			T16	1		T17	2		T18	3
all_values[6]	auto[0]	auto[0]	auto[1]	83	1			T16	1		T17	1		T19	2
all_values[6]	auto[0]	auto[1]	auto[0]	134	1			T16	6		T17	6		T18	2
all_values[6]	auto[0]	auto[1]	auto[1]	91	1			T16	3		T18	2		T19	3
all_values[6]	auto[1]	auto[0]	auto[1]	206	1			T16	7		T18	3		T19	3
all_values[6]	auto[1]	auto[1]	auto[1]	169	1			T16	3		T17	1		T18	4
all_values[7]	auto[0]	auto[0]	auto[0]	159	1			T16	5		T17	1		T18	1
all_values[7]	auto[0]	auto[0]	auto[1]	82	1			T17	1		T19	2		T20	3
all_values[7]	auto[0]	auto[1]	auto[0]	165	1			T16	7		T17	1		T18	6
all_values[7]	auto[0]	auto[1]	auto[1]	82	1			T16	3		T17	3		T18	1
all_values[7]	auto[1]	auto[0]	auto[1]	192	1			T16	4		T17	1		T18	1
all_values[7]	auto[1]	auto[1]	auto[1]	173	1			T16	2		T17	3		T18	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal