Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1690

1

T1

7

T6

6

T7

1

auto[1]

1749

1

T1

7

T5

3

T6

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1887

1

T5

3

T6

5

T7

3

auto[1]

1552

1

T1

14

T6

4

T8

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2738

1

T1

14

T5

3

T6

6

auto[1]

701

1

T6

3

T7

1

T8

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	668	1			T1	1		T6	2		T7	2
valid[1]	689	1			T1	2		T6	3		T8	1
valid[2]	660	1			T1	2		T5	1		T6	2
valid[3]	708	1			T1	4		T28	2		T29	4
valid[4]	714	1			T1	5		T5	2		T6	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	122	1			T8	2		T29	1		T30	4
auto[0]	auto[0]	valid[0]	auto[1]	154	1			T28	1		T91	1		T308	3
auto[0]	auto[0]	valid[1]	auto[0]	131	1			T8	1		T29	5		T45	1
auto[0]	auto[0]	valid[1]	auto[1]	148	1			T6	1		T16	1		T90	2
auto[0]	auto[0]	valid[2]	auto[0]	109	1			T29	3		T30	1		T51	2
auto[0]	auto[0]	valid[2]	auto[1]	135	1			T1	2		T6	1		T28	2
auto[0]	auto[0]	valid[3]	auto[0]	124	1			T29	1		T45	1		T16	1
auto[0]	auto[0]	valid[3]	auto[1]	153	1			T1	2		T28	1		T308	3
auto[0]	auto[0]	valid[4]	auto[0]	102	1			T6	1		T8	1		T10	1
auto[0]	auto[0]	valid[4]	auto[1]	173	1			T1	3		T6	1		T28	1
auto[0]	auto[1]	valid[0]	auto[0]	108	1			T6	1		T7	1		T29	1
auto[0]	auto[1]	valid[0]	auto[1]	151	1			T1	1		T28	2		T90	1
auto[0]	auto[1]	valid[1]	auto[0]	123	1			T30	1		T45	2		T167	1
auto[0]	auto[1]	valid[1]	auto[1]	152	1			T1	2		T28	1		T90	2
auto[0]	auto[1]	valid[2]	auto[0]	109	1			T5	1		T7	1		T45	1
auto[0]	auto[1]	valid[2]	auto[1]	167	1			T6	1		T8	1		T28	2
auto[0]	auto[1]	valid[3]	auto[0]	128	1			T29	1		T30	2		T16	1
auto[0]	auto[1]	valid[3]	auto[1]	153	1			T1	2		T28	1		T30	1
auto[0]	auto[1]	valid[4]	auto[0]	130	1			T5	2		T30	3		T45	1
auto[0]	auto[1]	valid[4]	auto[1]	166	1			T1	2		T16	1		T90	1
auto[1]	auto[0]	valid[0]	auto[0]	68	1			T6	1		T7	1		T30	1
auto[1]	auto[0]	valid[1]	auto[0]	66	1			T6	1		T30	3		T16	1
auto[1]	auto[0]	valid[2]	auto[0]	66	1			T29	1		T16	1		T306	1
auto[1]	auto[0]	valid[3]	auto[0]	68	1			T306	2		T39	1		T54	1
auto[1]	auto[0]	valid[4]	auto[0]	71	1			T29	3		T30	1		T35	1
auto[1]	auto[1]	valid[0]	auto[0]	65	1			T8	1		T29	2		T35	1
auto[1]	auto[1]	valid[1]	auto[0]	69	1			T6	1		T29	1		T30	1
auto[1]	auto[1]	valid[2]	auto[0]	74	1			T16	1		T35	2		T37	1
auto[1]	auto[1]	valid[3]	auto[0]	82	1			T29	2		T30	1		T45	1
auto[1]	auto[1]	valid[4]	auto[0]	72	1			T17	1		T51	1		T167	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal