Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48252

1

T5

78

T6

272

T7

103

auto[1]

16526

1

T1

14

T6

68

T8

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47133

1

T1

14

T5

59

T6

239

auto[1]

17645

1

T5

19

T6

101

T7

40

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33240	1			T1	14		T5	45		T6	162
others[1]	5492	1			T5	5		T6	32		T7	2
others[2]	5477	1			T5	11		T6	32		T7	11
others[3]	6229	1			T5	5		T6	36		T7	13
interest[1]	3594	1			T5	2		T6	21		T7	6
interest[4]	21752	1			T1	14		T5	29		T6	99
interest[64]	10746	1			T5	10		T6	57		T7	16

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15570	1			T5	33		T6	82		T7	30
auto[0]	auto[0]	others[1]	2606	1			T5	3		T6	18		T7	2
auto[0]	auto[0]	others[2]	2619	1			T5	10		T6	18		T7	6
auto[0]	auto[0]	others[3]	2960	1			T5	3		T6	16		T7	9
auto[0]	auto[0]	interest[1]	1701	1			T5	2		T6	11		T7	5
auto[0]	auto[0]	interest[4]	10139	1			T5	19		T6	48		T7	20
auto[0]	auto[0]	interest[64]	5151	1			T5	8		T6	26		T7	11
auto[0]	auto[1]	others[0]	8643	1			T1	14		T6	29		T8	3
auto[0]	auto[1]	others[1]	1390	1			T6	6		T28	9		T30	4
auto[0]	auto[1]	others[2]	1354	1			T6	6		T8	1		T28	18
auto[0]	auto[1]	others[3]	1555	1			T6	5		T8	1		T28	17
auto[0]	auto[1]	interest[1]	913	1			T6	6		T28	9		T30	2
auto[0]	auto[1]	interest[4]	5734	1			T1	14		T6	14		T8	2
auto[0]	auto[1]	interest[64]	2671	1			T6	16		T8	1		T28	31
auto[1]	auto[0]	others[0]	9027	1			T5	12		T6	51		T7	25
auto[1]	auto[0]	others[1]	1496	1			T5	2		T6	8		T8	3
auto[1]	auto[0]	others[2]	1504	1			T5	1		T6	8		T7	5
auto[1]	auto[0]	others[3]	1714	1			T5	2		T6	15		T7	4
auto[1]	auto[0]	interest[1]	980	1			T6	4		T7	1		T29	11
auto[1]	auto[0]	interest[4]	5879	1			T5	10		T6	37		T7	14
auto[1]	auto[0]	interest[64]	2924	1			T5	2		T6	15		T7	5

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal