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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.10 98.62 89.36 97.29 95.43 99.26


Total test records in report: 1151
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T1037 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2857811493 Jul 14 05:48:54 PM PDT 24 Jul 14 05:48:55 PM PDT 24 22940982 ps
T1038 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3408017216 Jul 14 05:48:32 PM PDT 24 Jul 14 05:48:33 PM PDT 24 48308665 ps
T104 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2234218594 Jul 14 05:47:52 PM PDT 24 Jul 14 05:48:15 PM PDT 24 865149820 ps
T1039 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3526643352 Jul 14 05:49:06 PM PDT 24 Jul 14 05:49:07 PM PDT 24 15763416 ps
T120 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.724274638 Jul 14 05:47:55 PM PDT 24 Jul 14 05:47:57 PM PDT 24 124928861 ps
T111 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3729312728 Jul 14 05:48:20 PM PDT 24 Jul 14 05:48:39 PM PDT 24 710985148 ps
T1040 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2974932197 Jul 14 05:49:08 PM PDT 24 Jul 14 05:49:10 PM PDT 24 15307528 ps
T174 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2493973497 Jul 14 05:48:09 PM PDT 24 Jul 14 05:48:17 PM PDT 24 2163916491 ps
T1041 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3664428439 Jul 14 05:49:00 PM PDT 24 Jul 14 05:49:03 PM PDT 24 29748784 ps
T108 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1772887724 Jul 14 05:48:25 PM PDT 24 Jul 14 05:48:28 PM PDT 24 1231816519 ps
T1042 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2089722809 Jul 14 05:49:00 PM PDT 24 Jul 14 05:49:05 PM PDT 24 204392044 ps
T176 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1474952065 Jul 14 05:48:39 PM PDT 24 Jul 14 05:48:52 PM PDT 24 618058106 ps
T1043 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2783686574 Jul 14 05:49:00 PM PDT 24 Jul 14 05:49:02 PM PDT 24 20966386 ps
T109 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1115420008 Jul 14 05:47:41 PM PDT 24 Jul 14 05:47:45 PM PDT 24 285541641 ps
T145 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3328446692 Jul 14 05:48:32 PM PDT 24 Jul 14 05:48:42 PM PDT 24 345112927 ps
T1044 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4169763767 Jul 14 05:48:03 PM PDT 24 Jul 14 05:48:12 PM PDT 24 593406997 ps
T1045 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4155099425 Jul 14 05:49:13 PM PDT 24 Jul 14 05:49:14 PM PDT 24 11864174 ps
T1046 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4263114303 Jul 14 05:48:24 PM PDT 24 Jul 14 05:48:27 PM PDT 24 44322373 ps
T150 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1280855937 Jul 14 05:48:09 PM PDT 24 Jul 14 05:48:11 PM PDT 24 81872837 ps
T1047 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2248438502 Jul 14 05:49:05 PM PDT 24 Jul 14 05:49:06 PM PDT 24 11731261 ps
T170 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.294484330 Jul 14 05:48:53 PM PDT 24 Jul 14 05:49:13 PM PDT 24 2348922590 ps
T121 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1989353101 Jul 14 05:48:25 PM PDT 24 Jul 14 05:48:28 PM PDT 24 142110396 ps
T122 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2537383809 Jul 14 05:47:48 PM PDT 24 Jul 14 05:47:51 PM PDT 24 84548797 ps
T1048 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.976102806 Jul 14 05:49:06 PM PDT 24 Jul 14 05:49:08 PM PDT 24 30898011 ps
T171 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4035113826 Jul 14 05:48:45 PM PDT 24 Jul 14 05:49:04 PM PDT 24 1129408153 ps
T1049 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3442655999 Jul 14 05:48:32 PM PDT 24 Jul 14 05:48:37 PM PDT 24 65499176 ps
T123 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.294543540 Jul 14 05:48:23 PM PDT 24 Jul 14 05:48:25 PM PDT 24 29352323 ps
T1050 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2855055719 Jul 14 05:47:03 PM PDT 24 Jul 14 05:47:04 PM PDT 24 12675115 ps
T146 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1069715908 Jul 14 05:48:59 PM PDT 24 Jul 14 05:49:02 PM PDT 24 632468819 ps
T1051 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1379861448 Jul 14 05:48:59 PM PDT 24 Jul 14 05:49:00 PM PDT 24 42618476 ps
T1052 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.914188549 Jul 14 05:49:01 PM PDT 24 Jul 14 05:49:02 PM PDT 24 40814436 ps
T1053 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.705636530 Jul 14 05:48:53 PM PDT 24 Jul 14 05:48:58 PM PDT 24 63295221 ps
T1054 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.50379656 Jul 14 05:48:03 PM PDT 24 Jul 14 05:48:06 PM PDT 24 168709904 ps
T173 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4164465104 Jul 14 05:48:24 PM PDT 24 Jul 14 05:48:44 PM PDT 24 1195614997 ps
T1055 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.978970476 Jul 14 05:49:04 PM PDT 24 Jul 14 05:49:05 PM PDT 24 18926513 ps
T1056 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3780661071 Jul 14 05:48:42 PM PDT 24 Jul 14 05:48:43 PM PDT 24 171054139 ps
T124 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1422587412 Jul 14 05:48:58 PM PDT 24 Jul 14 05:49:01 PM PDT 24 250540210 ps
T112 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.464254732 Jul 14 05:47:10 PM PDT 24 Jul 14 05:47:14 PM PDT 24 532637909 ps
T1057 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4292603349 Jul 14 05:48:04 PM PDT 24 Jul 14 05:48:06 PM PDT 24 34591837 ps
T147 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2078226591 Jul 14 05:48:42 PM PDT 24 Jul 14 05:48:58 PM PDT 24 2710829092 ps
T148 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4199395075 Jul 14 05:47:32 PM PDT 24 Jul 14 05:47:41 PM PDT 24 698679940 ps
T1058 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.816019224 Jul 14 05:47:39 PM PDT 24 Jul 14 05:47:54 PM PDT 24 854951087 ps
T149 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2589222371 Jul 14 05:48:39 PM PDT 24 Jul 14 05:48:43 PM PDT 24 159278498 ps
T151 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.186666560 Jul 14 05:47:40 PM PDT 24 Jul 14 05:47:43 PM PDT 24 137842748 ps
T1059 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3394793028 Jul 14 05:48:53 PM PDT 24 Jul 14 05:48:54 PM PDT 24 25774691 ps
T1060 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.805326069 Jul 14 05:47:05 PM PDT 24 Jul 14 05:47:08 PM PDT 24 79174013 ps
T1061 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1093557751 Jul 14 05:49:07 PM PDT 24 Jul 14 05:49:09 PM PDT 24 123032073 ps
T125 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2858587688 Jul 14 05:47:26 PM PDT 24 Jul 14 05:47:50 PM PDT 24 1294307809 ps
T165 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.280008734 Jul 14 05:48:25 PM PDT 24 Jul 14 05:48:27 PM PDT 24 58866406 ps
T1062 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3634050946 Jul 14 05:47:19 PM PDT 24 Jul 14 05:47:20 PM PDT 24 78018734 ps
T1063 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3929768339 Jul 14 05:48:31 PM PDT 24 Jul 14 05:48:33 PM PDT 24 123627735 ps
T1064 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1291418064 Jul 14 05:49:14 PM PDT 24 Jul 14 05:49:16 PM PDT 24 13025677 ps
T1065 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1700308314 Jul 14 05:48:10 PM PDT 24 Jul 14 05:48:11 PM PDT 24 35790670 ps
T113 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.561306025 Jul 14 05:48:37 PM PDT 24 Jul 14 05:48:42 PM PDT 24 147502873 ps
T177 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1948193887 Jul 14 05:49:01 PM PDT 24 Jul 14 05:49:21 PM PDT 24 799217408 ps
T126 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3701563384 Jul 14 05:48:52 PM PDT 24 Jul 14 05:48:53 PM PDT 24 180744330 ps
T1066 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4260849371 Jul 14 05:47:01 PM PDT 24 Jul 14 05:47:02 PM PDT 24 21555041 ps
T1067 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.878395444 Jul 14 05:49:05 PM PDT 24 Jul 14 05:49:07 PM PDT 24 41434668 ps
T1068 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.5159724 Jul 14 05:47:20 PM PDT 24 Jul 14 05:47:22 PM PDT 24 11046927 ps
T1069 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.130835473 Jul 14 05:49:07 PM PDT 24 Jul 14 05:49:08 PM PDT 24 12744011 ps
T127 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.137661884 Jul 14 05:48:45 PM PDT 24 Jul 14 05:48:48 PM PDT 24 100284540 ps
T1070 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2328905514 Jul 14 05:49:01 PM PDT 24 Jul 14 05:49:02 PM PDT 24 22951929 ps
T1071 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.958113049 Jul 14 05:49:00 PM PDT 24 Jul 14 05:49:01 PM PDT 24 13044039 ps
T110 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2157257100 Jul 14 05:47:41 PM PDT 24 Jul 14 05:48:01 PM PDT 24 295383923 ps
T1072 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1866801803 Jul 14 05:47:09 PM PDT 24 Jul 14 05:47:12 PM PDT 24 87930732 ps
T1073 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3302003099 Jul 14 05:47:40 PM PDT 24 Jul 14 05:48:07 PM PDT 24 3605234945 ps
T1074 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.18402876 Jul 14 05:47:40 PM PDT 24 Jul 14 05:47:42 PM PDT 24 20111121 ps
T86 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3052600029 Jul 14 05:47:32 PM PDT 24 Jul 14 05:47:33 PM PDT 24 26131162 ps
T172 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3201324336 Jul 14 05:48:04 PM PDT 24 Jul 14 05:48:23 PM PDT 24 1315189147 ps
T1075 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2663927242 Jul 14 05:48:32 PM PDT 24 Jul 14 05:48:36 PM PDT 24 52640264 ps
T1076 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1571263162 Jul 14 05:48:46 PM PDT 24 Jul 14 05:48:48 PM PDT 24 929899394 ps
T1077 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3782792838 Jul 14 05:47:47 PM PDT 24 Jul 14 05:47:50 PM PDT 24 64954237 ps
T128 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1877577275 Jul 14 05:47:54 PM PDT 24 Jul 14 05:47:56 PM PDT 24 56688137 ps
T1078 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2121418080 Jul 14 05:49:15 PM PDT 24 Jul 14 05:49:16 PM PDT 24 14371643 ps
T1079 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1546046613 Jul 14 05:48:52 PM PDT 24 Jul 14 05:48:56 PM PDT 24 50673115 ps
T87 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1008264104 Jul 14 05:47:21 PM PDT 24 Jul 14 05:47:22 PM PDT 24 24337575 ps
T1080 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4142118283 Jul 14 05:49:06 PM PDT 24 Jul 14 05:49:07 PM PDT 24 47007094 ps
T1081 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.966840247 Jul 14 05:48:44 PM PDT 24 Jul 14 05:48:46 PM PDT 24 603215293 ps
T1082 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1643986203 Jul 14 05:49:05 PM PDT 24 Jul 14 05:49:06 PM PDT 24 17323956 ps
T1083 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.830306835 Jul 14 05:49:12 PM PDT 24 Jul 14 05:49:14 PM PDT 24 86133506 ps
T1084 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1833713325 Jul 14 05:47:11 PM PDT 24 Jul 14 05:47:14 PM PDT 24 170787016 ps
T1085 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.548522552 Jul 14 05:47:33 PM PDT 24 Jul 14 05:47:35 PM PDT 24 14146935 ps
T1086 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1463819531 Jul 14 05:48:11 PM PDT 24 Jul 14 05:48:14 PM PDT 24 69470300 ps
T1087 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1282364875 Jul 14 05:49:13 PM PDT 24 Jul 14 05:49:14 PM PDT 24 25359639 ps
T88 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3711569053 Jul 14 05:47:09 PM PDT 24 Jul 14 05:47:10 PM PDT 24 21125741 ps
T1088 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1657223696 Jul 14 05:48:08 PM PDT 24 Jul 14 05:48:11 PM PDT 24 30747876 ps
T1089 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3464764702 Jul 14 05:48:44 PM PDT 24 Jul 14 05:48:45 PM PDT 24 16417338 ps
T1090 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3579986837 Jul 14 05:47:49 PM PDT 24 Jul 14 05:47:52 PM PDT 24 140968557 ps
T1091 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.377353077 Jul 14 05:47:46 PM PDT 24 Jul 14 05:48:11 PM PDT 24 2854543830 ps
T175 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2566218257 Jul 14 05:48:52 PM PDT 24 Jul 14 05:49:07 PM PDT 24 2156231306 ps
T1092 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3040909159 Jul 14 05:49:00 PM PDT 24 Jul 14 05:49:03 PM PDT 24 248766249 ps
T1093 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3088997798 Jul 14 05:48:44 PM PDT 24 Jul 14 05:48:47 PM PDT 24 480785988 ps
T1094 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1161939142 Jul 14 05:49:14 PM PDT 24 Jul 14 05:49:16 PM PDT 24 25952970 ps
T1095 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.944858762 Jul 14 05:48:42 PM PDT 24 Jul 14 05:48:47 PM PDT 24 313825351 ps
T1096 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2041568115 Jul 14 05:48:31 PM PDT 24 Jul 14 05:48:33 PM PDT 24 63613515 ps
T1097 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3124468034 Jul 14 05:47:40 PM PDT 24 Jul 14 05:47:41 PM PDT 24 29164255 ps
T1098 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2941807320 Jul 14 05:48:33 PM PDT 24 Jul 14 05:48:36 PM PDT 24 284401046 ps
T1099 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1041878807 Jul 14 05:49:12 PM PDT 24 Jul 14 05:49:13 PM PDT 24 14244908 ps
T1100 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.634188586 Jul 14 05:48:27 PM PDT 24 Jul 14 05:48:28 PM PDT 24 49937855 ps
T1101 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.524297351 Jul 14 05:48:03 PM PDT 24 Jul 14 05:48:04 PM PDT 24 173451309 ps
T1102 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3001619200 Jul 14 05:48:46 PM PDT 24 Jul 14 05:48:49 PM PDT 24 74591695 ps
T1103 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3887773812 Jul 14 05:47:27 PM PDT 24 Jul 14 05:47:29 PM PDT 24 328113147 ps
T1104 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3482945936 Jul 14 05:48:56 PM PDT 24 Jul 14 05:49:00 PM PDT 24 740597162 ps
T1105 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.4285394920 Jul 14 05:48:13 PM PDT 24 Jul 14 05:48:16 PM PDT 24 247637607 ps
T1106 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3904067213 Jul 14 05:47:54 PM PDT 24 Jul 14 05:47:55 PM PDT 24 125846465 ps
T1107 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3800231174 Jul 14 05:48:45 PM PDT 24 Jul 14 05:48:48 PM PDT 24 671011720 ps
T1108 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.529699622 Jul 14 05:49:07 PM PDT 24 Jul 14 05:49:08 PM PDT 24 14975004 ps
T1109 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3296772035 Jul 14 05:48:24 PM PDT 24 Jul 14 05:48:28 PM PDT 24 181526838 ps
T1110 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.34770539 Jul 14 05:48:22 PM PDT 24 Jul 14 05:48:25 PM PDT 24 28817575 ps
T89 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2885539487 Jul 14 05:47:49 PM PDT 24 Jul 14 05:47:50 PM PDT 24 37080955 ps
T1111 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3120787297 Jul 14 05:48:18 PM PDT 24 Jul 14 05:48:20 PM PDT 24 42437208 ps
T1112 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4292943363 Jul 14 05:49:02 PM PDT 24 Jul 14 05:49:04 PM PDT 24 19302766 ps
T1113 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1291377145 Jul 14 05:47:26 PM PDT 24 Jul 14 05:47:28 PM PDT 24 60910786 ps
T1114 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3455513464 Jul 14 05:49:02 PM PDT 24 Jul 14 05:49:07 PM PDT 24 1763175310 ps
T1115 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2753469730 Jul 14 05:48:27 PM PDT 24 Jul 14 05:48:36 PM PDT 24 1226179716 ps
T1116 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3966829797 Jul 14 05:47:16 PM PDT 24 Jul 14 05:47:18 PM PDT 24 173790401 ps
T1117 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.990879167 Jul 14 05:47:20 PM PDT 24 Jul 14 05:47:22 PM PDT 24 15425556 ps
T1118 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2142103073 Jul 14 05:47:54 PM PDT 24 Jul 14 05:47:55 PM PDT 24 11061741 ps
T1119 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4113599139 Jul 14 05:47:46 PM PDT 24 Jul 14 05:47:49 PM PDT 24 98841592 ps
T1120 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.53758098 Jul 14 05:48:10 PM PDT 24 Jul 14 05:48:18 PM PDT 24 1322634498 ps
T1121 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1912378731 Jul 14 05:49:12 PM PDT 24 Jul 14 05:49:14 PM PDT 24 35984369 ps
T1122 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.760586644 Jul 14 05:48:10 PM PDT 24 Jul 14 05:48:11 PM PDT 24 13510658 ps
T1123 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1603516136 Jul 14 05:47:32 PM PDT 24 Jul 14 05:47:34 PM PDT 24 66933461 ps
T1124 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2159042897 Jul 14 05:47:42 PM PDT 24 Jul 14 05:47:44 PM PDT 24 102759605 ps
T1125 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2129722092 Jul 14 05:47:47 PM PDT 24 Jul 14 05:47:48 PM PDT 24 10291345 ps
T1126 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2155885832 Jul 14 05:48:21 PM PDT 24 Jul 14 05:48:24 PM PDT 24 819072443 ps
T1127 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1722378384 Jul 14 05:46:58 PM PDT 24 Jul 14 05:47:01 PM PDT 24 600439280 ps
T1128 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2360611681 Jul 14 05:48:03 PM PDT 24 Jul 14 05:48:06 PM PDT 24 106102821 ps
T1129 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1637263700 Jul 14 05:47:53 PM PDT 24 Jul 14 05:47:55 PM PDT 24 16881861 ps
T1130 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1459751865 Jul 14 05:48:53 PM PDT 24 Jul 14 05:48:55 PM PDT 24 98125167 ps
T1131 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2667480769 Jul 14 05:48:32 PM PDT 24 Jul 14 05:48:36 PM PDT 24 128353686 ps
T1132 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1205731275 Jul 14 05:49:09 PM PDT 24 Jul 14 05:49:10 PM PDT 24 28660209 ps
T1133 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2687349133 Jul 14 05:48:25 PM PDT 24 Jul 14 05:48:26 PM PDT 24 42079333 ps
T1134 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.321187284 Jul 14 05:48:46 PM PDT 24 Jul 14 05:48:50 PM PDT 24 48302708 ps
T1135 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2034707286 Jul 14 05:48:54 PM PDT 24 Jul 14 05:48:56 PM PDT 24 16965703 ps
T1136 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4128112129 Jul 14 05:48:43 PM PDT 24 Jul 14 05:48:44 PM PDT 24 11538309 ps
T1137 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2375699188 Jul 14 05:47:19 PM PDT 24 Jul 14 05:47:32 PM PDT 24 8714864357 ps
T1138 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2762502926 Jul 14 05:48:18 PM PDT 24 Jul 14 05:48:23 PM PDT 24 236300381 ps
T1139 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3309237397 Jul 14 05:47:12 PM PDT 24 Jul 14 05:47:15 PM PDT 24 87382587 ps
T1140 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3480104343 Jul 14 05:47:34 PM PDT 24 Jul 14 05:47:35 PM PDT 24 17942826 ps
T1141 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.448701401 Jul 14 05:48:23 PM PDT 24 Jul 14 05:48:25 PM PDT 24 158037302 ps
T1142 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1245142597 Jul 14 05:48:18 PM PDT 24 Jul 14 05:48:21 PM PDT 24 102560816 ps
T1143 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1476026981 Jul 14 05:48:04 PM PDT 24 Jul 14 05:48:09 PM PDT 24 57438380 ps
T1144 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4268459357 Jul 14 05:48:59 PM PDT 24 Jul 14 05:49:00 PM PDT 24 41838153 ps
T1145 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2218835805 Jul 14 05:48:05 PM PDT 24 Jul 14 05:48:09 PM PDT 24 1390022206 ps
T1146 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3426835834 Jul 14 05:47:10 PM PDT 24 Jul 14 05:47:24 PM PDT 24 187727729 ps
T1147 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3039772754 Jul 14 05:48:51 PM PDT 24 Jul 14 05:48:54 PM PDT 24 221911993 ps
T1148 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.807970913 Jul 14 05:47:50 PM PDT 24 Jul 14 05:48:32 PM PDT 24 5508336899 ps
T1149 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3226930504 Jul 14 05:49:07 PM PDT 24 Jul 14 05:49:08 PM PDT 24 21942438 ps
T1150 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2946861939 Jul 14 05:49:12 PM PDT 24 Jul 14 05:49:13 PM PDT 24 16445612 ps
T1151 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.160864386 Jul 14 05:46:59 PM PDT 24 Jul 14 05:47:21 PM PDT 24 6710208221 ps

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3254275288
Short name T5
Test name
Test status
Simulation time 42690734540 ps
CPU time 372.45 seconds
Started Jul 14 05:56:06 PM PDT 24
Finished Jul 14 06:02:19 PM PDT 24
Peak memory 264764 kb
Host smart-ed2ca6ec-3352-4b32-b0e4-d56518b20896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254275288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3254275288
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1025847147
Short name T30
Test name
Test status
Simulation time 22294943404 ps
CPU time 98.82 seconds
Started Jul 14 05:51:06 PM PDT 24
Finished Jul 14 05:52:46 PM PDT 24
Peak memory 266788 kb
Host smart-3d65dc34-2fe1-4b91-9760-eef7af54e9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025847147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1025847147
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2719484190
Short name T32
Test name
Test status
Simulation time 508479512942 ps
CPU time 759.89 seconds
Started Jul 14 05:52:34 PM PDT 24
Finished Jul 14 06:05:15 PM PDT 24
Peak memory 274092 kb
Host smart-0d5291f9-6c46-426e-bbc4-a990e84cfd3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719484190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2719484190
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1265887538
Short name T115
Test name
Test status
Simulation time 177529511 ps
CPU time 4.5 seconds
Started Jul 14 05:48:25 PM PDT 24
Finished Jul 14 05:48:30 PM PDT 24
Peak memory 218212 kb
Host smart-25847871-9e5a-43fa-90a8-da85b3325c39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265887538 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1265887538
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1046601045
Short name T29
Test name
Test status
Simulation time 38992237780 ps
CPU time 324.27 seconds
Started Jul 14 05:53:25 PM PDT 24
Finished Jul 14 05:58:50 PM PDT 24
Peak memory 266240 kb
Host smart-0a0b50cd-14bb-4ccb-bb1a-cc84f4eb880e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046601045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1046601045
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1112912585
Short name T31
Test name
Test status
Simulation time 15177442558 ps
CPU time 151.9 seconds
Started Jul 14 05:52:47 PM PDT 24
Finished Jul 14 05:55:19 PM PDT 24
Peak memory 274004 kb
Host smart-e5848faa-ef03-4c64-94f8-e4decb688cf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112912585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1112912585
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.30977883
Short name T72
Test name
Test status
Simulation time 44193789 ps
CPU time 0.73 seconds
Started Jul 14 05:51:04 PM PDT 24
Finished Jul 14 05:51:05 PM PDT 24
Peak memory 217036 kb
Host smart-ed1beded-1ff4-4bbe-9610-c6871ff3939f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30977883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.30977883
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1994918296
Short name T152
Test name
Test status
Simulation time 22048504000 ps
CPU time 322.99 seconds
Started Jul 14 05:56:07 PM PDT 24
Finished Jul 14 06:01:31 PM PDT 24
Peak memory 274816 kb
Host smart-575ca5fd-ed7a-4307-b967-e9e268d892fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994918296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1994918296
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1171775665
Short name T6
Test name
Test status
Simulation time 3041686236 ps
CPU time 17.74 seconds
Started Jul 14 05:56:58 PM PDT 24
Finished Jul 14 05:57:16 PM PDT 24
Peak memory 218836 kb
Host smart-f169d1b9-08a7-4db5-9cd6-4744d2145124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171775665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1171775665
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1984137997
Short name T33
Test name
Test status
Simulation time 737096678 ps
CPU time 1.2 seconds
Started Jul 14 05:51:09 PM PDT 24
Finished Jul 14 05:51:10 PM PDT 24
Peak memory 237344 kb
Host smart-454bb46d-da4c-4117-8d3c-fef407b9d99f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984137997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1984137997
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2736922180
Short name T51
Test name
Test status
Simulation time 459050707770 ps
CPU time 532.68 seconds
Started Jul 14 05:54:45 PM PDT 24
Finished Jul 14 06:03:38 PM PDT 24
Peak memory 264580 kb
Host smart-c5cb4523-06e0-427f-bbc5-cc2959350f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736922180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2736922180
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.94345834
Short name T48
Test name
Test status
Simulation time 3097055831 ps
CPU time 9.01 seconds
Started Jul 14 05:57:15 PM PDT 24
Finished Jul 14 05:57:24 PM PDT 24
Peak memory 234936 kb
Host smart-f93fc02d-8039-4d33-b8a0-3cff42dbd7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94345834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.94345834
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.606345460
Short name T231
Test name
Test status
Simulation time 1016189450605 ps
CPU time 544.5 seconds
Started Jul 14 05:53:26 PM PDT 24
Finished Jul 14 06:02:31 PM PDT 24
Peak memory 267656 kb
Host smart-34f4c7b1-5da1-403f-9529-13665833d730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606345460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.606345460
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.176625705
Short name T209
Test name
Test status
Simulation time 89930773420 ps
CPU time 773 seconds
Started Jul 14 05:51:45 PM PDT 24
Finished Jul 14 06:04:39 PM PDT 24
Peak memory 268736 kb
Host smart-ce4688cc-b24f-4d6c-828b-913841d7e4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176625705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.176625705
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.358225332
Short name T130
Test name
Test status
Simulation time 254150967163 ps
CPU time 661.03 seconds
Started Jul 14 05:57:03 PM PDT 24
Finished Jul 14 06:08:04 PM PDT 24
Peak memory 299572 kb
Host smart-99cbeccf-abe7-48d1-b37a-59fe45c3a0f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358225332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.358225332
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.567983854
Short name T100
Test name
Test status
Simulation time 799111895 ps
CPU time 19.87 seconds
Started Jul 14 05:48:44 PM PDT 24
Finished Jul 14 05:49:05 PM PDT 24
Peak memory 215576 kb
Host smart-37e963fb-aea2-4378-aa0b-aca3fa7e2310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567983854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.567983854
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2583134796
Short name T20
Test name
Test status
Simulation time 13574479695 ps
CPU time 193.76 seconds
Started Jul 14 05:54:46 PM PDT 24
Finished Jul 14 05:58:00 PM PDT 24
Peak memory 265916 kb
Host smart-73fea063-8ac1-4303-8602-b228ac23231c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583134796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2583134796
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3437829789
Short name T247
Test name
Test status
Simulation time 14426837618 ps
CPU time 87.6 seconds
Started Jul 14 05:53:54 PM PDT 24
Finished Jul 14 05:55:23 PM PDT 24
Peak memory 274124 kb
Host smart-c4efd361-d9a4-407a-921e-05666b6aeb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437829789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3437829789
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.166711386
Short name T107
Test name
Test status
Simulation time 420088589 ps
CPU time 4.65 seconds
Started Jul 14 05:48:54 PM PDT 24
Finished Jul 14 05:48:59 PM PDT 24
Peak memory 216688 kb
Host smart-b5943a4a-9f0b-42cc-a2f1-e3e331c6fc13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166711386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.166711386
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2391195313
Short name T117
Test name
Test status
Simulation time 1067293933 ps
CPU time 21.07 seconds
Started Jul 14 05:47:13 PM PDT 24
Finished Jul 14 05:47:34 PM PDT 24
Peak memory 207272 kb
Host smart-6462dd45-17c1-4ae4-8720-a5cedbbac711
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391195313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2391195313
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.296358314
Short name T55
Test name
Test status
Simulation time 5841374600 ps
CPU time 94.67 seconds
Started Jul 14 05:55:43 PM PDT 24
Finished Jul 14 05:57:18 PM PDT 24
Peak memory 253596 kb
Host smart-41fa56e2-9c6e-4146-a561-14b9ed5c8856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296358314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.296358314
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1877798225
Short name T461
Test name
Test status
Simulation time 28210580 ps
CPU time 1.16 seconds
Started Jul 14 05:51:00 PM PDT 24
Finished Jul 14 05:51:02 PM PDT 24
Peak memory 217672 kb
Host smart-e9bafc6d-673e-4d9d-98ca-4c924e617e5e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877798225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1877798225
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1977139988
Short name T216
Test name
Test status
Simulation time 73100470269 ps
CPU time 737.4 seconds
Started Jul 14 05:52:08 PM PDT 24
Finished Jul 14 06:04:26 PM PDT 24
Peak memory 274956 kb
Host smart-78b01300-5729-47d0-8937-b576cd129271
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977139988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1977139988
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.4273385854
Short name T256
Test name
Test status
Simulation time 267543457769 ps
CPU time 633.95 seconds
Started Jul 14 05:52:48 PM PDT 24
Finished Jul 14 06:03:23 PM PDT 24
Peak memory 266668 kb
Host smart-8671acfb-95d7-4881-ae26-ad4fbb4d7270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273385854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.4273385854
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2721250878
Short name T96
Test name
Test status
Simulation time 26757994653 ps
CPU time 94.82 seconds
Started Jul 14 05:52:43 PM PDT 24
Finished Jul 14 05:54:19 PM PDT 24
Peak memory 252784 kb
Host smart-e0bf932f-0eb6-46db-bdcc-59b0db6e6cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721250878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2721250878
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.268492667
Short name T41
Test name
Test status
Simulation time 199529157967 ps
CPU time 533.15 seconds
Started Jul 14 05:55:58 PM PDT 24
Finished Jul 14 06:04:52 PM PDT 24
Peak memory 268304 kb
Host smart-b571a7ca-1980-4b7d-9512-1cfc350bfc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268492667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.268492667
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.346452742
Short name T40
Test name
Test status
Simulation time 246892466372 ps
CPU time 336.64 seconds
Started Jul 14 05:53:10 PM PDT 24
Finished Jul 14 05:58:48 PM PDT 24
Peak memory 255480 kb
Host smart-39cc475b-29b7-4137-af41-202e4052b860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346452742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.346452742
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1483758679
Short name T264
Test name
Test status
Simulation time 48006379954 ps
CPU time 142.19 seconds
Started Jul 14 05:51:17 PM PDT 24
Finished Jul 14 05:53:40 PM PDT 24
Peak memory 255792 kb
Host smart-4970c920-7f2c-4b93-870f-21de7787349b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483758679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1483758679
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3015910061
Short name T352
Test name
Test status
Simulation time 28829668 ps
CPU time 0.71 seconds
Started Jul 14 05:52:50 PM PDT 24
Finished Jul 14 05:52:51 PM PDT 24
Peak memory 206748 kb
Host smart-0fea225e-7e18-4360-a68a-6b8768d46535
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015910061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3015910061
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3030682689
Short name T155
Test name
Test status
Simulation time 205160344191 ps
CPU time 506.03 seconds
Started Jul 14 05:52:40 PM PDT 24
Finished Jul 14 06:01:06 PM PDT 24
Peak memory 268180 kb
Host smart-17883cef-7062-4c42-8cce-7127e0f07494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030682689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3030682689
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3432530793
Short name T13
Test name
Test status
Simulation time 6703312433 ps
CPU time 43.47 seconds
Started Jul 14 05:51:47 PM PDT 24
Finished Jul 14 05:52:31 PM PDT 24
Peak memory 253760 kb
Host smart-088873ec-f078-442f-b37e-4f27788c3c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432530793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3432530793
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3159926054
Short name T34
Test name
Test status
Simulation time 65024126624 ps
CPU time 613.55 seconds
Started Jul 14 05:56:23 PM PDT 24
Finished Jul 14 06:06:37 PM PDT 24
Peak memory 265900 kb
Host smart-cf0e76d6-b8d0-4098-9fbe-860e10b868e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159926054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3159926054
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.571057759
Short name T58
Test name
Test status
Simulation time 16721131183 ps
CPU time 140.27 seconds
Started Jul 14 05:54:24 PM PDT 24
Finished Jul 14 05:56:45 PM PDT 24
Peak memory 274544 kb
Host smart-462d5050-be72-4434-81d1-980d1bb02a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571057759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.571057759
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.561306025
Short name T113
Test name
Test status
Simulation time 147502873 ps
CPU time 4.58 seconds
Started Jul 14 05:48:37 PM PDT 24
Finished Jul 14 05:48:42 PM PDT 24
Peak memory 215716 kb
Host smart-8d60b480-b50f-4b19-b842-ced4dc888ff4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561306025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.561306025
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2210899678
Short name T973
Test name
Test status
Simulation time 4800188761 ps
CPU time 89.07 seconds
Started Jul 14 05:53:54 PM PDT 24
Finished Jul 14 05:55:24 PM PDT 24
Peak memory 264040 kb
Host smart-bc5b068e-bde1-4779-8e86-29d2eecc91d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210899678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2210899678
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1423311494
Short name T261
Test name
Test status
Simulation time 1262627696 ps
CPU time 27.34 seconds
Started Jul 14 05:56:16 PM PDT 24
Finished Jul 14 05:56:44 PM PDT 24
Peak memory 239076 kb
Host smart-8e887ea0-cb2c-4295-9ecb-d96ef6241224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423311494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1423311494
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3969843768
Short name T297
Test name
Test status
Simulation time 1782557582 ps
CPU time 15.41 seconds
Started Jul 14 05:56:59 PM PDT 24
Finished Jul 14 05:57:15 PM PDT 24
Peak memory 233660 kb
Host smart-77ae71fa-ff5d-4cb9-8e5d-e3ac840f1801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969843768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3969843768
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2157257100
Short name T110
Test name
Test status
Simulation time 295383923 ps
CPU time 19.97 seconds
Started Jul 14 05:47:41 PM PDT 24
Finished Jul 14 05:48:01 PM PDT 24
Peak memory 215496 kb
Host smart-f0fec5f4-dbf0-485b-b343-88255a30708a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157257100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2157257100
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4035113826
Short name T171
Test name
Test status
Simulation time 1129408153 ps
CPU time 19.04 seconds
Started Jul 14 05:48:45 PM PDT 24
Finished Jul 14 05:49:04 PM PDT 24
Peak memory 215680 kb
Host smart-4b6deaaf-9c1e-4356-aeba-9a4a49c6a058
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035113826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.4035113826
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1587712841
Short name T321
Test name
Test status
Simulation time 30075153173 ps
CPU time 125.89 seconds
Started Jul 14 05:53:54 PM PDT 24
Finished Jul 14 05:56:01 PM PDT 24
Peak memory 242152 kb
Host smart-0c2d76ee-62e3-4c09-bdcc-c54d3b8bb90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587712841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1587712841
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3711400463
Short name T158
Test name
Test status
Simulation time 489358774365 ps
CPU time 353.23 seconds
Started Jul 14 05:55:22 PM PDT 24
Finished Jul 14 06:01:16 PM PDT 24
Peak memory 266260 kb
Host smart-51556160-ea9f-4705-8225-5a069a25f1b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711400463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3711400463
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2689549551
Short name T237
Test name
Test status
Simulation time 53856625439 ps
CPU time 511.38 seconds
Started Jul 14 05:51:53 PM PDT 24
Finished Jul 14 06:00:24 PM PDT 24
Peak memory 269312 kb
Host smart-133f0d24-2387-4b75-99f3-6e5eb9069bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689549551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2689549551
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2753457070
Short name T22
Test name
Test status
Simulation time 3291670185 ps
CPU time 5.82 seconds
Started Jul 14 05:54:46 PM PDT 24
Finished Jul 14 05:54:53 PM PDT 24
Peak memory 225728 kb
Host smart-6d7039a2-88cd-4a5f-b9d9-8ed9006ef006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753457070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2753457070
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4164465104
Short name T173
Test name
Test status
Simulation time 1195614997 ps
CPU time 20.42 seconds
Started Jul 14 05:48:24 PM PDT 24
Finished Jul 14 05:48:44 PM PDT 24
Peak memory 215452 kb
Host smart-41f153ad-fc57-48aa-a932-76381121f317
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164465104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4164465104
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.4140106815
Short name T319
Test name
Test status
Simulation time 6892317107 ps
CPU time 105.54 seconds
Started Jul 14 05:51:06 PM PDT 24
Finished Jul 14 05:52:53 PM PDT 24
Peak memory 256924 kb
Host smart-08f098ff-4a10-4644-8f3b-a94d9a514504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140106815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.4140106815
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4041229109
Short name T305
Test name
Test status
Simulation time 5569308900 ps
CPU time 50.77 seconds
Started Jul 14 05:51:07 PM PDT 24
Finished Jul 14 05:51:59 PM PDT 24
Peak memory 250228 kb
Host smart-cc7ade86-fd62-4e41-94fb-3f23d593a6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041229109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4041229109
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.201966082
Short name T278
Test name
Test status
Simulation time 46266538554 ps
CPU time 411.61 seconds
Started Jul 14 05:53:10 PM PDT 24
Finished Jul 14 06:00:02 PM PDT 24
Peak memory 264672 kb
Host smart-c8b0a4cd-33ff-4007-a269-c2a8390eefc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201966082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.201966082
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2890981830
Short name T282
Test name
Test status
Simulation time 1389033404 ps
CPU time 8.17 seconds
Started Jul 14 05:53:26 PM PDT 24
Finished Jul 14 05:53:35 PM PDT 24
Peak memory 225580 kb
Host smart-0be0cdc2-b3ca-40e7-a791-dc762c93761c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890981830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2890981830
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1414404698
Short name T132
Test name
Test status
Simulation time 31377131543 ps
CPU time 382.2 seconds
Started Jul 14 05:54:08 PM PDT 24
Finished Jul 14 06:00:32 PM PDT 24
Peak memory 274048 kb
Host smart-b752a1d1-653c-4256-8e36-70c9946847b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414404698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1414404698
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.988245058
Short name T274
Test name
Test status
Simulation time 39611260589 ps
CPU time 144.86 seconds
Started Jul 14 05:54:28 PM PDT 24
Finished Jul 14 05:56:54 PM PDT 24
Peak memory 257676 kb
Host smart-b53ce5fe-1136-421c-af32-751e2b8bba5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988245058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.988245058
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.249512287
Short name T296
Test name
Test status
Simulation time 25426606596 ps
CPU time 84.98 seconds
Started Jul 14 05:54:38 PM PDT 24
Finished Jul 14 05:56:04 PM PDT 24
Peak memory 233900 kb
Host smart-f5f93f30-b419-4c6b-859f-e363dffb5269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249512287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.249512287
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3819843949
Short name T154
Test name
Test status
Simulation time 40661051349 ps
CPU time 138.76 seconds
Started Jul 14 05:57:24 PM PDT 24
Finished Jul 14 05:59:43 PM PDT 24
Peak memory 251592 kb
Host smart-f6fe36ac-21de-4caa-91fb-2865195769ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819843949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3819843949
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1817258835
Short name T18
Test name
Test status
Simulation time 623740467 ps
CPU time 1.19 seconds
Started Jul 14 05:53:26 PM PDT 24
Finished Jul 14 05:53:28 PM PDT 24
Peak memory 207804 kb
Host smart-de30d1cb-8662-4444-8630-9b6be9a0b82a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817258835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1817258835
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_intercept.413778072
Short name T246
Test name
Test status
Simulation time 2333695117 ps
CPU time 13.17 seconds
Started Jul 14 05:53:44 PM PDT 24
Finished Jul 14 05:53:57 PM PDT 24
Peak memory 225560 kb
Host smart-1525445b-1921-42d0-8d59-ea2889d9f30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413778072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.413778072
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3711569053
Short name T88
Test name
Test status
Simulation time 21125741 ps
CPU time 0.94 seconds
Started Jul 14 05:47:09 PM PDT 24
Finished Jul 14 05:47:10 PM PDT 24
Peak memory 207060 kb
Host smart-f4f2a4db-d459-4557-9804-310a91c117f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711569053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3711569053
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.988313261
Short name T94
Test name
Test status
Simulation time 21983228278 ps
CPU time 167.56 seconds
Started Jul 14 05:53:46 PM PDT 24
Finished Jul 14 05:56:34 PM PDT 24
Peak memory 250192 kb
Host smart-0dcc7709-11f8-487c-a002-3d3f91a9c2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988313261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.988313261
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3426835834
Short name T1146
Test name
Test status
Simulation time 187727729 ps
CPU time 13.07 seconds
Started Jul 14 05:47:10 PM PDT 24
Finished Jul 14 05:47:24 PM PDT 24
Peak memory 207084 kb
Host smart-84483a60-647e-4f4b-aedd-b4bd336f49db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426835834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3426835834
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3309237397
Short name T1139
Test name
Test status
Simulation time 87382587 ps
CPU time 2.69 seconds
Started Jul 14 05:47:12 PM PDT 24
Finished Jul 14 05:47:15 PM PDT 24
Peak memory 217020 kb
Host smart-815518c5-2a6c-4d36-998b-c085417096cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309237397 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3309237397
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1866801803
Short name T1072
Test name
Test status
Simulation time 87930732 ps
CPU time 2.17 seconds
Started Jul 14 05:47:09 PM PDT 24
Finished Jul 14 05:47:12 PM PDT 24
Peak memory 215516 kb
Host smart-534b0ca1-564e-43b8-8fb2-f951e26b6771
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866801803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
866801803
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2855055719
Short name T1050
Test name
Test status
Simulation time 12675115 ps
CPU time 0.72 seconds
Started Jul 14 05:47:03 PM PDT 24
Finished Jul 14 05:47:04 PM PDT 24
Peak memory 204004 kb
Host smart-1ecfc71f-6bfc-44cd-b753-c590a82eee26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855055719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
855055719
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.805326069
Short name T1060
Test name
Test status
Simulation time 79174013 ps
CPU time 2.35 seconds
Started Jul 14 05:47:05 PM PDT 24
Finished Jul 14 05:47:08 PM PDT 24
Peak memory 215420 kb
Host smart-45e0a3ed-ca6d-49d4-aa8e-6de6ca136c56
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805326069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.805326069
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4260849371
Short name T1066
Test name
Test status
Simulation time 21555041 ps
CPU time 0.66 seconds
Started Jul 14 05:47:01 PM PDT 24
Finished Jul 14 05:47:02 PM PDT 24
Peak memory 203764 kb
Host smart-55324b9e-80f3-43ae-87ff-18d1155eb3cd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260849371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.4260849371
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1833713325
Short name T1084
Test name
Test status
Simulation time 170787016 ps
CPU time 2.79 seconds
Started Jul 14 05:47:11 PM PDT 24
Finished Jul 14 05:47:14 PM PDT 24
Peak memory 215468 kb
Host smart-cea35880-7f06-4b6b-be37-c7bae1b173e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833713325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1833713325
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1722378384
Short name T1127
Test name
Test status
Simulation time 600439280 ps
CPU time 2.85 seconds
Started Jul 14 05:46:58 PM PDT 24
Finished Jul 14 05:47:01 PM PDT 24
Peak memory 216828 kb
Host smart-ffef9107-8c64-451c-b439-3bbe24937239
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722378384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
722378384
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.160864386
Short name T1151
Test name
Test status
Simulation time 6710208221 ps
CPU time 21.59 seconds
Started Jul 14 05:46:59 PM PDT 24
Finished Jul 14 05:47:21 PM PDT 24
Peak memory 215552 kb
Host smart-4da1be36-8efe-4cbb-b5bb-9c44b17cb5c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160864386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.160864386
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2858587688
Short name T125
Test name
Test status
Simulation time 1294307809 ps
CPU time 23.29 seconds
Started Jul 14 05:47:26 PM PDT 24
Finished Jul 14 05:47:50 PM PDT 24
Peak memory 215492 kb
Host smart-bcca87a5-53b6-46be-8a10-7a48d5f73538
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858587688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2858587688
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3212249048
Short name T1030
Test name
Test status
Simulation time 613835853 ps
CPU time 13.18 seconds
Started Jul 14 05:47:24 PM PDT 24
Finished Jul 14 05:47:38 PM PDT 24
Peak memory 215628 kb
Host smart-667d6345-547e-4f30-9ec3-d87d75dab20f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212249048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3212249048
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1008264104
Short name T87
Test name
Test status
Simulation time 24337575 ps
CPU time 0.96 seconds
Started Jul 14 05:47:21 PM PDT 24
Finished Jul 14 05:47:22 PM PDT 24
Peak memory 206780 kb
Host smart-59cd5805-c834-4a21-a6fb-39eeb5ff3a0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008264104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1008264104
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3887773812
Short name T1103
Test name
Test status
Simulation time 328113147 ps
CPU time 1.69 seconds
Started Jul 14 05:47:27 PM PDT 24
Finished Jul 14 05:47:29 PM PDT 24
Peak memory 215552 kb
Host smart-39c7f7f1-9142-4e8d-ba76-0757115b87d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887773812 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3887773812
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3634050946
Short name T1062
Test name
Test status
Simulation time 78018734 ps
CPU time 1.25 seconds
Started Jul 14 05:47:19 PM PDT 24
Finished Jul 14 05:47:20 PM PDT 24
Peak memory 207300 kb
Host smart-0313bdf5-b166-4204-87fd-7efc6b413295
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634050946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
634050946
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.990879167
Short name T1117
Test name
Test status
Simulation time 15425556 ps
CPU time 0.7 seconds
Started Jul 14 05:47:20 PM PDT 24
Finished Jul 14 05:47:22 PM PDT 24
Peak memory 204292 kb
Host smart-460ffe46-3675-454f-b6ef-fda74c0d230f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990879167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.990879167
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3966829797
Short name T1116
Test name
Test status
Simulation time 173790401 ps
CPU time 1.89 seconds
Started Jul 14 05:47:16 PM PDT 24
Finished Jul 14 05:47:18 PM PDT 24
Peak memory 215492 kb
Host smart-a53c49a4-ed91-4950-9eb3-ed31881728c9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966829797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3966829797
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.5159724
Short name T1068
Test name
Test status
Simulation time 11046927 ps
CPU time 0.64 seconds
Started Jul 14 05:47:20 PM PDT 24
Finished Jul 14 05:47:22 PM PDT 24
Peak memory 203860 kb
Host smart-2650d9ae-3e3e-4655-aa9e-a79496e9c6c9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5159724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_w
alk.5159724
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1291377145
Short name T1113
Test name
Test status
Simulation time 60910786 ps
CPU time 1.96 seconds
Started Jul 14 05:47:26 PM PDT 24
Finished Jul 14 05:47:28 PM PDT 24
Peak memory 215488 kb
Host smart-695605f5-eb32-4a98-a596-a478d5cc8be8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291377145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1291377145
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.464254732
Short name T112
Test name
Test status
Simulation time 532637909 ps
CPU time 3.74 seconds
Started Jul 14 05:47:10 PM PDT 24
Finished Jul 14 05:47:14 PM PDT 24
Peak memory 215856 kb
Host smart-dbd2aac1-89cc-48d8-aea8-8f8bf5a86f95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464254732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.464254732
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2375699188
Short name T1137
Test name
Test status
Simulation time 8714864357 ps
CPU time 12.91 seconds
Started Jul 14 05:47:19 PM PDT 24
Finished Jul 14 05:47:32 PM PDT 24
Peak memory 215512 kb
Host smart-b45e7cb3-ffcb-4bde-9e3d-3670c55d807c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375699188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2375699188
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1989353101
Short name T121
Test name
Test status
Simulation time 142110396 ps
CPU time 1.87 seconds
Started Jul 14 05:48:25 PM PDT 24
Finished Jul 14 05:48:28 PM PDT 24
Peak memory 215412 kb
Host smart-556fe203-5fb5-4b8e-911d-7430692fba16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989353101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1989353101
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.860755138
Short name T1036
Test name
Test status
Simulation time 48947053 ps
CPU time 0.79 seconds
Started Jul 14 05:48:22 PM PDT 24
Finished Jul 14 05:48:23 PM PDT 24
Peak memory 203952 kb
Host smart-c37f1ff4-f24a-460c-ab0f-9419c115067e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860755138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.860755138
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3296772035
Short name T1109
Test name
Test status
Simulation time 181526838 ps
CPU time 4.2 seconds
Started Jul 14 05:48:24 PM PDT 24
Finished Jul 14 05:48:28 PM PDT 24
Peak memory 215380 kb
Host smart-1a833cee-edad-4ecf-9f0c-226e82e67962
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296772035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3296772035
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1772887724
Short name T108
Test name
Test status
Simulation time 1231816519 ps
CPU time 2.79 seconds
Started Jul 14 05:48:25 PM PDT 24
Finished Jul 14 05:48:28 PM PDT 24
Peak memory 215616 kb
Host smart-f5fa295b-b06b-439e-825e-1ef71135cb4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772887724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1772887724
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2663927242
Short name T1075
Test name
Test status
Simulation time 52640264 ps
CPU time 4 seconds
Started Jul 14 05:48:32 PM PDT 24
Finished Jul 14 05:48:36 PM PDT 24
Peak memory 217588 kb
Host smart-e39e555f-ab78-4d2e-9b1d-59e196713235
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663927242 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2663927242
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.294543540
Short name T123
Test name
Test status
Simulation time 29352323 ps
CPU time 1.87 seconds
Started Jul 14 05:48:23 PM PDT 24
Finished Jul 14 05:48:25 PM PDT 24
Peak memory 207236 kb
Host smart-338d3334-e092-4e17-a0a2-c441fd4a9143
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294543540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.294543540
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2687349133
Short name T1133
Test name
Test status
Simulation time 42079333 ps
CPU time 0.73 seconds
Started Jul 14 05:48:25 PM PDT 24
Finished Jul 14 05:48:26 PM PDT 24
Peak memory 203892 kb
Host smart-bc3203d7-eb03-4f54-a7bc-de97f23164f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687349133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2687349133
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3929768339
Short name T1063
Test name
Test status
Simulation time 123627735 ps
CPU time 1.91 seconds
Started Jul 14 05:48:31 PM PDT 24
Finished Jul 14 05:48:33 PM PDT 24
Peak memory 215496 kb
Host smart-bbf3e07d-fede-48df-a3f9-8557cefb1ddd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929768339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3929768339
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4263114303
Short name T1046
Test name
Test status
Simulation time 44322373 ps
CPU time 2.69 seconds
Started Jul 14 05:48:24 PM PDT 24
Finished Jul 14 05:48:27 PM PDT 24
Peak memory 215776 kb
Host smart-707cea7e-a63c-46ef-ad7b-e99b7b21ee67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263114303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
4263114303
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2753469730
Short name T1115
Test name
Test status
Simulation time 1226179716 ps
CPU time 9.15 seconds
Started Jul 14 05:48:27 PM PDT 24
Finished Jul 14 05:48:36 PM PDT 24
Peak memory 215396 kb
Host smart-5036c871-4d34-48a9-bb66-110adb74f7e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753469730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2753469730
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2667480769
Short name T1131
Test name
Test status
Simulation time 128353686 ps
CPU time 3.79 seconds
Started Jul 14 05:48:32 PM PDT 24
Finished Jul 14 05:48:36 PM PDT 24
Peak memory 217072 kb
Host smart-f1c4d7d5-40e4-4eea-a0f0-a0281fc90379
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667480769 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2667480769
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4289104454
Short name T119
Test name
Test status
Simulation time 195931787 ps
CPU time 1.5 seconds
Started Jul 14 05:48:30 PM PDT 24
Finished Jul 14 05:48:32 PM PDT 24
Peak memory 215424 kb
Host smart-84b4e2a4-b149-4979-81af-783c0d81fa51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289104454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4289104454
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3408017216
Short name T1038
Test name
Test status
Simulation time 48308665 ps
CPU time 0.74 seconds
Started Jul 14 05:48:32 PM PDT 24
Finished Jul 14 05:48:33 PM PDT 24
Peak memory 203948 kb
Host smart-f990ab4b-dd6e-4efe-aefd-177d7ded91c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408017216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3408017216
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3442655999
Short name T1049
Test name
Test status
Simulation time 65499176 ps
CPU time 3.83 seconds
Started Jul 14 05:48:32 PM PDT 24
Finished Jul 14 05:48:37 PM PDT 24
Peak memory 215392 kb
Host smart-02edb22c-444b-444b-abff-814685ed7797
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442655999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3442655999
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2041568115
Short name T1096
Test name
Test status
Simulation time 63613515 ps
CPU time 1.83 seconds
Started Jul 14 05:48:31 PM PDT 24
Finished Jul 14 05:48:33 PM PDT 24
Peak memory 215884 kb
Host smart-8cda4c8d-91f7-4648-9770-d16b9d0d858a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041568115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2041568115
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3328446692
Short name T145
Test name
Test status
Simulation time 345112927 ps
CPU time 8.89 seconds
Started Jul 14 05:48:32 PM PDT 24
Finished Jul 14 05:48:42 PM PDT 24
Peak memory 215336 kb
Host smart-56466a03-4f75-49d3-9091-f3eccf367b76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328446692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3328446692
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2589222371
Short name T149
Test name
Test status
Simulation time 159278498 ps
CPU time 3.86 seconds
Started Jul 14 05:48:39 PM PDT 24
Finished Jul 14 05:48:43 PM PDT 24
Peak memory 217264 kb
Host smart-5f1de6a6-9076-470b-ba73-0d46589f85df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589222371 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2589222371
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.268715648
Short name T137
Test name
Test status
Simulation time 71836447 ps
CPU time 1.42 seconds
Started Jul 14 05:48:40 PM PDT 24
Finished Jul 14 05:48:42 PM PDT 24
Peak memory 215420 kb
Host smart-1fff8eff-cd4c-477e-bc18-28c38e0325b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268715648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.268715648
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3780661071
Short name T1056
Test name
Test status
Simulation time 171054139 ps
CPU time 0.74 seconds
Started Jul 14 05:48:42 PM PDT 24
Finished Jul 14 05:48:43 PM PDT 24
Peak memory 204264 kb
Host smart-cd2e987e-464e-4ac3-b338-97eb1887a995
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780661071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3780661071
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.944858762
Short name T1095
Test name
Test status
Simulation time 313825351 ps
CPU time 4.67 seconds
Started Jul 14 05:48:42 PM PDT 24
Finished Jul 14 05:48:47 PM PDT 24
Peak memory 215764 kb
Host smart-6464b44c-e6a6-4438-845a-e96df2eaa4e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944858762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.944858762
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2941807320
Short name T1098
Test name
Test status
Simulation time 284401046 ps
CPU time 2.35 seconds
Started Jul 14 05:48:33 PM PDT 24
Finished Jul 14 05:48:36 PM PDT 24
Peak memory 215660 kb
Host smart-3aa79465-bd86-4f5a-9623-99c82f211762
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941807320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2941807320
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1474952065
Short name T176
Test name
Test status
Simulation time 618058106 ps
CPU time 12.72 seconds
Started Jul 14 05:48:39 PM PDT 24
Finished Jul 14 05:48:52 PM PDT 24
Peak memory 215808 kb
Host smart-1a593ae8-2c8a-4a3e-85ba-a94514faa773
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474952065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1474952065
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1571263162
Short name T1076
Test name
Test status
Simulation time 929899394 ps
CPU time 1.64 seconds
Started Jul 14 05:48:46 PM PDT 24
Finished Jul 14 05:48:48 PM PDT 24
Peak memory 215540 kb
Host smart-37f7e866-8237-4974-915d-b45cc948763c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571263162 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1571263162
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.137661884
Short name T127
Test name
Test status
Simulation time 100284540 ps
CPU time 2.59 seconds
Started Jul 14 05:48:45 PM PDT 24
Finished Jul 14 05:48:48 PM PDT 24
Peak memory 215540 kb
Host smart-25547c4f-d611-450d-9258-c48b351612f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137661884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.137661884
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3464764702
Short name T1089
Test name
Test status
Simulation time 16417338 ps
CPU time 0.74 seconds
Started Jul 14 05:48:44 PM PDT 24
Finished Jul 14 05:48:45 PM PDT 24
Peak memory 203956 kb
Host smart-ecbca3b0-2c69-46be-a2b4-b30e5d577f03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464764702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3464764702
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3088997798
Short name T1093
Test name
Test status
Simulation time 480785988 ps
CPU time 2.95 seconds
Started Jul 14 05:48:44 PM PDT 24
Finished Jul 14 05:48:47 PM PDT 24
Peak memory 215432 kb
Host smart-231ec034-4800-4223-a5b2-3784104adb10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088997798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3088997798
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2078226591
Short name T147
Test name
Test status
Simulation time 2710829092 ps
CPU time 15.51 seconds
Started Jul 14 05:48:42 PM PDT 24
Finished Jul 14 05:48:58 PM PDT 24
Peak memory 215796 kb
Host smart-9a3883e5-7fc3-48cc-92e1-bdd75830297d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078226591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2078226591
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2580542425
Short name T102
Test name
Test status
Simulation time 147083969 ps
CPU time 2.78 seconds
Started Jul 14 05:48:46 PM PDT 24
Finished Jul 14 05:48:49 PM PDT 24
Peak memory 217264 kb
Host smart-55d53245-fedb-48a3-b6d3-b266c1ce35ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580542425 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2580542425
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.966840247
Short name T1081
Test name
Test status
Simulation time 603215293 ps
CPU time 1.42 seconds
Started Jul 14 05:48:44 PM PDT 24
Finished Jul 14 05:48:46 PM PDT 24
Peak memory 215444 kb
Host smart-910c1915-f74f-4be1-9896-60e45a6579b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966840247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.966840247
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4128112129
Short name T1136
Test name
Test status
Simulation time 11538309 ps
CPU time 0.77 seconds
Started Jul 14 05:48:43 PM PDT 24
Finished Jul 14 05:48:44 PM PDT 24
Peak memory 203800 kb
Host smart-836a6519-8853-4b7b-97d7-d4a11947f2c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128112129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
4128112129
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3800231174
Short name T1107
Test name
Test status
Simulation time 671011720 ps
CPU time 2.03 seconds
Started Jul 14 05:48:45 PM PDT 24
Finished Jul 14 05:48:48 PM PDT 24
Peak memory 215448 kb
Host smart-f6e8b1fe-e6b5-4f70-b5b2-28cd154c5933
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800231174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3800231174
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3001619200
Short name T1102
Test name
Test status
Simulation time 74591695 ps
CPU time 2.12 seconds
Started Jul 14 05:48:46 PM PDT 24
Finished Jul 14 05:48:49 PM PDT 24
Peak memory 215720 kb
Host smart-1b79c710-641f-4a90-8063-f5f27c5a0a48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001619200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3001619200
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4148569262
Short name T114
Test name
Test status
Simulation time 27578534 ps
CPU time 1.55 seconds
Started Jul 14 05:48:56 PM PDT 24
Finished Jul 14 05:48:58 PM PDT 24
Peak memory 215592 kb
Host smart-56cd076a-3875-415d-a611-92811b5e0148
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148569262 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.4148569262
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3039772754
Short name T1147
Test name
Test status
Simulation time 221911993 ps
CPU time 2.78 seconds
Started Jul 14 05:48:51 PM PDT 24
Finished Jul 14 05:48:54 PM PDT 24
Peak memory 215504 kb
Host smart-d8108c25-8436-4886-a27d-916b0c64ad77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039772754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3039772754
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2857811493
Short name T1037
Test name
Test status
Simulation time 22940982 ps
CPU time 0.72 seconds
Started Jul 14 05:48:54 PM PDT 24
Finished Jul 14 05:48:55 PM PDT 24
Peak memory 203932 kb
Host smart-00e4c37d-2f8e-44df-a2be-c093304140c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857811493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2857811493
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1459751865
Short name T1130
Test name
Test status
Simulation time 98125167 ps
CPU time 1.6 seconds
Started Jul 14 05:48:53 PM PDT 24
Finished Jul 14 05:48:55 PM PDT 24
Peak memory 215428 kb
Host smart-ae7b935a-1713-4d3f-9f7d-f874c265f281
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459751865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1459751865
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.321187284
Short name T1134
Test name
Test status
Simulation time 48302708 ps
CPU time 3.42 seconds
Started Jul 14 05:48:46 PM PDT 24
Finished Jul 14 05:48:50 PM PDT 24
Peak memory 215680 kb
Host smart-eecdca83-dbf9-4da5-b981-007b34d48441
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321187284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.321187284
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1546046613
Short name T1079
Test name
Test status
Simulation time 50673115 ps
CPU time 3.43 seconds
Started Jul 14 05:48:52 PM PDT 24
Finished Jul 14 05:48:56 PM PDT 24
Peak memory 217380 kb
Host smart-5422cec7-0064-4f81-8d10-430fb760c9b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546046613 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1546046613
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3701563384
Short name T126
Test name
Test status
Simulation time 180744330 ps
CPU time 1.51 seconds
Started Jul 14 05:48:52 PM PDT 24
Finished Jul 14 05:48:53 PM PDT 24
Peak memory 207300 kb
Host smart-ced55d30-f032-47ba-bcfa-d246263d91b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701563384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3701563384
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3394793028
Short name T1059
Test name
Test status
Simulation time 25774691 ps
CPU time 0.76 seconds
Started Jul 14 05:48:53 PM PDT 24
Finished Jul 14 05:48:54 PM PDT 24
Peak memory 204228 kb
Host smart-c7788dd9-0ef7-4490-8ff0-13d4fc0b2bec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394793028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3394793028
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.705636530
Short name T1053
Test name
Test status
Simulation time 63295221 ps
CPU time 4.27 seconds
Started Jul 14 05:48:53 PM PDT 24
Finished Jul 14 05:48:58 PM PDT 24
Peak memory 215408 kb
Host smart-fdd213c5-b162-47f9-bd49-43b6f73afba2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705636530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.705636530
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3482945936
Short name T1104
Test name
Test status
Simulation time 740597162 ps
CPU time 4.31 seconds
Started Jul 14 05:48:56 PM PDT 24
Finished Jul 14 05:49:00 PM PDT 24
Peak memory 215968 kb
Host smart-740a343c-24f6-4181-adcb-e4de24806a12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482945936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3482945936
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2566218257
Short name T175
Test name
Test status
Simulation time 2156231306 ps
CPU time 14.36 seconds
Started Jul 14 05:48:52 PM PDT 24
Finished Jul 14 05:49:07 PM PDT 24
Peak memory 216036 kb
Host smart-2aecb1a5-1fce-4ab0-9eb2-cf67d3f2b065
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566218257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2566218257
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3455513464
Short name T1114
Test name
Test status
Simulation time 1763175310 ps
CPU time 4.04 seconds
Started Jul 14 05:49:02 PM PDT 24
Finished Jul 14 05:49:07 PM PDT 24
Peak memory 217876 kb
Host smart-3854274f-d270-46ca-b396-6560ad2297ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455513464 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3455513464
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2783686574
Short name T1043
Test name
Test status
Simulation time 20966386 ps
CPU time 1.32 seconds
Started Jul 14 05:49:00 PM PDT 24
Finished Jul 14 05:49:02 PM PDT 24
Peak memory 207332 kb
Host smart-297aa775-3726-4f08-a2f1-b30c7791bba2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783686574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2783686574
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2034707286
Short name T1135
Test name
Test status
Simulation time 16965703 ps
CPU time 0.76 seconds
Started Jul 14 05:48:54 PM PDT 24
Finished Jul 14 05:48:56 PM PDT 24
Peak memory 203868 kb
Host smart-fcd95203-ab82-41ca-8e8f-09a50d23bc85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034707286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2034707286
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2089722809
Short name T1042
Test name
Test status
Simulation time 204392044 ps
CPU time 3.83 seconds
Started Jul 14 05:49:00 PM PDT 24
Finished Jul 14 05:49:05 PM PDT 24
Peak memory 215368 kb
Host smart-af982ea7-e1b2-44f8-a519-6a4b8cb54f18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089722809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2089722809
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.294484330
Short name T170
Test name
Test status
Simulation time 2348922590 ps
CPU time 19.59 seconds
Started Jul 14 05:48:53 PM PDT 24
Finished Jul 14 05:49:13 PM PDT 24
Peak memory 215492 kb
Host smart-16d27aa7-c888-41a3-8fe5-0af425be8702
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294484330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.294484330
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1069715908
Short name T146
Test name
Test status
Simulation time 632468819 ps
CPU time 2.99 seconds
Started Jul 14 05:48:59 PM PDT 24
Finished Jul 14 05:49:02 PM PDT 24
Peak memory 216904 kb
Host smart-8c599ff5-a3e0-4e20-b4a6-267626922bf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069715908 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1069715908
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1422587412
Short name T124
Test name
Test status
Simulation time 250540210 ps
CPU time 2.65 seconds
Started Jul 14 05:48:58 PM PDT 24
Finished Jul 14 05:49:01 PM PDT 24
Peak memory 215456 kb
Host smart-6609e435-a9fb-4c96-ab82-8f2b645ddbf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422587412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1422587412
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.958113049
Short name T1071
Test name
Test status
Simulation time 13044039 ps
CPU time 0.71 seconds
Started Jul 14 05:49:00 PM PDT 24
Finished Jul 14 05:49:01 PM PDT 24
Peak memory 204136 kb
Host smart-7771fc15-1f56-43bd-b79e-ac4fa0ab9868
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958113049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.958113049
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3664428439
Short name T1041
Test name
Test status
Simulation time 29748784 ps
CPU time 1.8 seconds
Started Jul 14 05:49:00 PM PDT 24
Finished Jul 14 05:49:03 PM PDT 24
Peak memory 215504 kb
Host smart-76ec71d8-98af-4e2c-a371-25f3d194888e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664428439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3664428439
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3040909159
Short name T1092
Test name
Test status
Simulation time 248766249 ps
CPU time 1.35 seconds
Started Jul 14 05:49:00 PM PDT 24
Finished Jul 14 05:49:03 PM PDT 24
Peak memory 215660 kb
Host smart-ee65f11e-5380-400c-a077-b808ecbcbd5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040909159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3040909159
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1948193887
Short name T177
Test name
Test status
Simulation time 799217408 ps
CPU time 19.06 seconds
Started Jul 14 05:49:01 PM PDT 24
Finished Jul 14 05:49:21 PM PDT 24
Peak memory 215956 kb
Host smart-1f2fd897-d02f-4954-9dbc-9aba64ae757c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948193887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1948193887
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.816019224
Short name T1058
Test name
Test status
Simulation time 854951087 ps
CPU time 14.6 seconds
Started Jul 14 05:47:39 PM PDT 24
Finished Jul 14 05:47:54 PM PDT 24
Peak memory 215340 kb
Host smart-3621f6e2-78bd-42a9-a7dc-253385575f65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816019224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.816019224
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3302003099
Short name T1073
Test name
Test status
Simulation time 3605234945 ps
CPU time 26.21 seconds
Started Jul 14 05:47:40 PM PDT 24
Finished Jul 14 05:48:07 PM PDT 24
Peak memory 207264 kb
Host smart-1aebcd20-296a-48ca-a4df-0afde33c8cc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302003099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3302003099
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3052600029
Short name T86
Test name
Test status
Simulation time 26131162 ps
CPU time 0.95 seconds
Started Jul 14 05:47:32 PM PDT 24
Finished Jul 14 05:47:33 PM PDT 24
Peak memory 207040 kb
Host smart-b9af7059-f5e7-4df9-9577-f03e8c5e5fc1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052600029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3052600029
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2159042897
Short name T1124
Test name
Test status
Simulation time 102759605 ps
CPU time 2.07 seconds
Started Jul 14 05:47:42 PM PDT 24
Finished Jul 14 05:47:44 PM PDT 24
Peak memory 216528 kb
Host smart-d0e2666f-5881-40a3-a848-a026e08f7eab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159042897 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2159042897
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.18402876
Short name T1074
Test name
Test status
Simulation time 20111121 ps
CPU time 1.2 seconds
Started Jul 14 05:47:40 PM PDT 24
Finished Jul 14 05:47:42 PM PDT 24
Peak memory 207300 kb
Host smart-38f3068d-022d-4518-8b8d-03cb96f32ec7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18402876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.18402876
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.548522552
Short name T1085
Test name
Test status
Simulation time 14146935 ps
CPU time 0.72 seconds
Started Jul 14 05:47:33 PM PDT 24
Finished Jul 14 05:47:35 PM PDT 24
Peak memory 203948 kb
Host smart-20abdec9-7109-4a1b-9582-3468147188da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548522552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.548522552
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1603516136
Short name T1123
Test name
Test status
Simulation time 66933461 ps
CPU time 1.21 seconds
Started Jul 14 05:47:32 PM PDT 24
Finished Jul 14 05:47:34 PM PDT 24
Peak memory 215524 kb
Host smart-56bda75d-ab7f-44d8-8abe-b4b5240a79b3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603516136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1603516136
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3480104343
Short name T1140
Test name
Test status
Simulation time 17942826 ps
CPU time 0.64 seconds
Started Jul 14 05:47:34 PM PDT 24
Finished Jul 14 05:47:35 PM PDT 24
Peak memory 203740 kb
Host smart-4ba19207-e0c9-4867-8e67-6e07ca6b89c0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480104343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3480104343
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.186666560
Short name T151
Test name
Test status
Simulation time 137842748 ps
CPU time 3.25 seconds
Started Jul 14 05:47:40 PM PDT 24
Finished Jul 14 05:47:43 PM PDT 24
Peak memory 215488 kb
Host smart-b133677a-d9a9-47e4-938f-836d43db7601
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186666560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.186666560
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4590603
Short name T106
Test name
Test status
Simulation time 296738857 ps
CPU time 3.82 seconds
Started Jul 14 05:47:32 PM PDT 24
Finished Jul 14 05:47:37 PM PDT 24
Peak memory 215848 kb
Host smart-c2283877-9198-4596-b02e-b7520fa8116c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4590603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4590603
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4199395075
Short name T148
Test name
Test status
Simulation time 698679940 ps
CPU time 9.04 seconds
Started Jul 14 05:47:32 PM PDT 24
Finished Jul 14 05:47:41 PM PDT 24
Peak memory 216192 kb
Host smart-a2091cd6-9cae-4be3-a6c1-5190c6bc9fe5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199395075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.4199395075
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1379861448
Short name T1051
Test name
Test status
Simulation time 42618476 ps
CPU time 0.69 seconds
Started Jul 14 05:48:59 PM PDT 24
Finished Jul 14 05:49:00 PM PDT 24
Peak memory 204236 kb
Host smart-6f429d7c-d40d-4532-9fdb-b5613f95915b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379861448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1379861448
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4268459357
Short name T1144
Test name
Test status
Simulation time 41838153 ps
CPU time 0.71 seconds
Started Jul 14 05:48:59 PM PDT 24
Finished Jul 14 05:49:00 PM PDT 24
Peak memory 203884 kb
Host smart-a3e5e35f-8bcc-45e1-8fef-b4d56741e067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268459357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4268459357
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.914188549
Short name T1052
Test name
Test status
Simulation time 40814436 ps
CPU time 0.71 seconds
Started Jul 14 05:49:01 PM PDT 24
Finished Jul 14 05:49:02 PM PDT 24
Peak memory 204236 kb
Host smart-a9bd5123-3385-4ac1-912a-59aec75fbeba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914188549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.914188549
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2548439839
Short name T1033
Test name
Test status
Simulation time 84929642 ps
CPU time 0.78 seconds
Started Jul 14 05:49:04 PM PDT 24
Finished Jul 14 05:49:05 PM PDT 24
Peak memory 203980 kb
Host smart-7a48c8e4-a862-4fbc-9958-8be2e8bd8198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548439839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2548439839
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4292943363
Short name T1112
Test name
Test status
Simulation time 19302766 ps
CPU time 0.78 seconds
Started Jul 14 05:49:02 PM PDT 24
Finished Jul 14 05:49:04 PM PDT 24
Peak memory 203928 kb
Host smart-00dd0606-010d-463a-b0df-a5551c064379
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292943363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4292943363
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2328905514
Short name T1070
Test name
Test status
Simulation time 22951929 ps
CPU time 0.81 seconds
Started Jul 14 05:49:01 PM PDT 24
Finished Jul 14 05:49:02 PM PDT 24
Peak memory 203976 kb
Host smart-a85e3b46-4519-4436-a173-a69123bdb602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328905514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2328905514
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.130835473
Short name T1069
Test name
Test status
Simulation time 12744011 ps
CPU time 0.76 seconds
Started Jul 14 05:49:07 PM PDT 24
Finished Jul 14 05:49:08 PM PDT 24
Peak memory 204148 kb
Host smart-96e4fa9b-26ec-4644-9f32-6fee34515f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130835473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.130835473
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4142118283
Short name T1080
Test name
Test status
Simulation time 47007094 ps
CPU time 0.74 seconds
Started Jul 14 05:49:06 PM PDT 24
Finished Jul 14 05:49:07 PM PDT 24
Peak memory 203952 kb
Host smart-4f83344c-70ef-400e-9bf7-c25ea901c03e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142118283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4142118283
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1093557751
Short name T1061
Test name
Test status
Simulation time 123032073 ps
CPU time 0.73 seconds
Started Jul 14 05:49:07 PM PDT 24
Finished Jul 14 05:49:09 PM PDT 24
Peak memory 204240 kb
Host smart-fa43ac56-ec35-4c64-bd4a-065a7cf3ffd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093557751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1093557751
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3226930504
Short name T1149
Test name
Test status
Simulation time 21942438 ps
CPU time 0.72 seconds
Started Jul 14 05:49:07 PM PDT 24
Finished Jul 14 05:49:08 PM PDT 24
Peak memory 203976 kb
Host smart-7f73a4db-d665-4211-b299-ff5b21cba970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226930504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3226930504
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.377353077
Short name T1091
Test name
Test status
Simulation time 2854543830 ps
CPU time 25.03 seconds
Started Jul 14 05:47:46 PM PDT 24
Finished Jul 14 05:48:11 PM PDT 24
Peak memory 215420 kb
Host smart-f7fab0dc-dd48-4a3e-8d0e-090e110c43ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377353077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.377353077
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.807970913
Short name T1148
Test name
Test status
Simulation time 5508336899 ps
CPU time 41.52 seconds
Started Jul 14 05:47:50 PM PDT 24
Finished Jul 14 05:48:32 PM PDT 24
Peak memory 207488 kb
Host smart-541724d5-8b24-4015-8046-3bb5efa65aa9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807970913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.807970913
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2885539487
Short name T89
Test name
Test status
Simulation time 37080955 ps
CPU time 1.17 seconds
Started Jul 14 05:47:49 PM PDT 24
Finished Jul 14 05:47:50 PM PDT 24
Peak memory 207200 kb
Host smart-de047dde-61e8-46a6-980c-56b46923f302
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885539487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2885539487
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3782792838
Short name T1077
Test name
Test status
Simulation time 64954237 ps
CPU time 2.71 seconds
Started Jul 14 05:47:47 PM PDT 24
Finished Jul 14 05:47:50 PM PDT 24
Peak memory 216552 kb
Host smart-e212a9c6-f915-480e-9fd5-3f10cc306e70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782792838 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3782792838
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4113599139
Short name T1119
Test name
Test status
Simulation time 98841592 ps
CPU time 2.96 seconds
Started Jul 14 05:47:46 PM PDT 24
Finished Jul 14 05:47:49 PM PDT 24
Peak memory 215480 kb
Host smart-1d3a09a1-9ad1-4103-a149-df01d3b45717
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113599139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
113599139
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3124468034
Short name T1097
Test name
Test status
Simulation time 29164255 ps
CPU time 0.72 seconds
Started Jul 14 05:47:40 PM PDT 24
Finished Jul 14 05:47:41 PM PDT 24
Peak memory 203912 kb
Host smart-2518b6ad-cf8a-4fcf-96f4-44e13dab0728
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124468034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
124468034
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2537383809
Short name T122
Test name
Test status
Simulation time 84548797 ps
CPU time 2.06 seconds
Started Jul 14 05:47:48 PM PDT 24
Finished Jul 14 05:47:51 PM PDT 24
Peak memory 215412 kb
Host smart-cce19c92-6bc2-4a97-9f04-9838f8c58f00
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537383809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2537383809
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2129722092
Short name T1125
Test name
Test status
Simulation time 10291345 ps
CPU time 0.68 seconds
Started Jul 14 05:47:47 PM PDT 24
Finished Jul 14 05:47:48 PM PDT 24
Peak memory 203880 kb
Host smart-6bfb7097-b97f-4361-9cb6-6fff0703ff57
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129722092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2129722092
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3579986837
Short name T1090
Test name
Test status
Simulation time 140968557 ps
CPU time 3 seconds
Started Jul 14 05:47:49 PM PDT 24
Finished Jul 14 05:47:52 PM PDT 24
Peak memory 215364 kb
Host smart-cf19ae6f-cf87-48cb-a800-fe8530fdb1c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579986837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3579986837
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1115420008
Short name T109
Test name
Test status
Simulation time 285541641 ps
CPU time 3.55 seconds
Started Jul 14 05:47:41 PM PDT 24
Finished Jul 14 05:47:45 PM PDT 24
Peak memory 215684 kb
Host smart-a06df062-ad9a-4b8a-ae79-02d79985fd16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115420008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
115420008
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1205731275
Short name T1132
Test name
Test status
Simulation time 28660209 ps
CPU time 0.77 seconds
Started Jul 14 05:49:09 PM PDT 24
Finished Jul 14 05:49:10 PM PDT 24
Peak memory 203856 kb
Host smart-fc0b5da6-9fad-4a36-bac5-e25c2a8cb721
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205731275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1205731275
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.978970476
Short name T1055
Test name
Test status
Simulation time 18926513 ps
CPU time 0.75 seconds
Started Jul 14 05:49:04 PM PDT 24
Finished Jul 14 05:49:05 PM PDT 24
Peak memory 203976 kb
Host smart-e692f0a7-19a3-4467-a8e9-5abf84d38171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978970476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.978970476
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.529699622
Short name T1108
Test name
Test status
Simulation time 14975004 ps
CPU time 0.73 seconds
Started Jul 14 05:49:07 PM PDT 24
Finished Jul 14 05:49:08 PM PDT 24
Peak memory 203972 kb
Host smart-7c2332f9-5159-48e9-89dd-d7a1debd711a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529699622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.529699622
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3526643352
Short name T1039
Test name
Test status
Simulation time 15763416 ps
CPU time 0.78 seconds
Started Jul 14 05:49:06 PM PDT 24
Finished Jul 14 05:49:07 PM PDT 24
Peak memory 204212 kb
Host smart-83b163bd-38bb-4421-a906-56586bef14b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526643352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3526643352
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1643986203
Short name T1082
Test name
Test status
Simulation time 17323956 ps
CPU time 0.67 seconds
Started Jul 14 05:49:05 PM PDT 24
Finished Jul 14 05:49:06 PM PDT 24
Peak memory 203828 kb
Host smart-f3668b5c-d151-49db-84dc-6e5c07a2095d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643986203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1643986203
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.675771860
Short name T1032
Test name
Test status
Simulation time 15001042 ps
CPU time 0.74 seconds
Started Jul 14 05:49:05 PM PDT 24
Finished Jul 14 05:49:06 PM PDT 24
Peak memory 203984 kb
Host smart-3d21cf60-facc-48c4-8ae2-b027de686721
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675771860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.675771860
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2974932197
Short name T1040
Test name
Test status
Simulation time 15307528 ps
CPU time 0.73 seconds
Started Jul 14 05:49:08 PM PDT 24
Finished Jul 14 05:49:10 PM PDT 24
Peak memory 204184 kb
Host smart-1f052c12-42c9-4d47-b766-8bc0e0528c52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974932197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2974932197
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.976102806
Short name T1048
Test name
Test status
Simulation time 30898011 ps
CPU time 0.72 seconds
Started Jul 14 05:49:06 PM PDT 24
Finished Jul 14 05:49:08 PM PDT 24
Peak memory 204252 kb
Host smart-eeb8fa1b-1d15-487e-bebb-505c30fc9418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976102806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.976102806
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.878395444
Short name T1067
Test name
Test status
Simulation time 41434668 ps
CPU time 0.72 seconds
Started Jul 14 05:49:05 PM PDT 24
Finished Jul 14 05:49:07 PM PDT 24
Peak memory 203932 kb
Host smart-dcddd16b-e9f3-4913-a1c3-8a47ff7cdd5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878395444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.878395444
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1388493202
Short name T1034
Test name
Test status
Simulation time 16943552 ps
CPU time 0.77 seconds
Started Jul 14 05:49:07 PM PDT 24
Finished Jul 14 05:49:09 PM PDT 24
Peak memory 204256 kb
Host smart-9d2feded-7aa5-4620-93d1-53f654fb1ba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388493202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1388493202
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4169763767
Short name T1044
Test name
Test status
Simulation time 593406997 ps
CPU time 7.81 seconds
Started Jul 14 05:48:03 PM PDT 24
Finished Jul 14 05:48:12 PM PDT 24
Peak memory 207040 kb
Host smart-962cecf8-ab83-4580-b9ae-b1523ccbef06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169763767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.4169763767
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2368588671
Short name T118
Test name
Test status
Simulation time 2473347788 ps
CPU time 34.78 seconds
Started Jul 14 05:47:54 PM PDT 24
Finished Jul 14 05:48:30 PM PDT 24
Peak memory 215364 kb
Host smart-cf429b99-c95c-46df-9907-f9ada40fe010
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368588671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2368588671
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1637263700
Short name T1129
Test name
Test status
Simulation time 16881861 ps
CPU time 0.95 seconds
Started Jul 14 05:47:53 PM PDT 24
Finished Jul 14 05:47:55 PM PDT 24
Peak memory 207060 kb
Host smart-56706742-7231-4fe0-b247-eb972762a492
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637263700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1637263700
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2218835805
Short name T1145
Test name
Test status
Simulation time 1390022206 ps
CPU time 4.02 seconds
Started Jul 14 05:48:05 PM PDT 24
Finished Jul 14 05:48:09 PM PDT 24
Peak memory 218044 kb
Host smart-463a2978-e90a-4410-86c9-ad6276a1fd74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218835805 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2218835805
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.724274638
Short name T120
Test name
Test status
Simulation time 124928861 ps
CPU time 1.45 seconds
Started Jul 14 05:47:55 PM PDT 24
Finished Jul 14 05:47:57 PM PDT 24
Peak memory 207272 kb
Host smart-fa0d8133-b84d-4d84-8a7a-5a5398ed9ac0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724274638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.724274638
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3904067213
Short name T1106
Test name
Test status
Simulation time 125846465 ps
CPU time 0.75 seconds
Started Jul 14 05:47:54 PM PDT 24
Finished Jul 14 05:47:55 PM PDT 24
Peak memory 203928 kb
Host smart-0a9b1193-8a52-4bb3-8d0a-0e7ff45cc99b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904067213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
904067213
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1877577275
Short name T128
Test name
Test status
Simulation time 56688137 ps
CPU time 1.27 seconds
Started Jul 14 05:47:54 PM PDT 24
Finished Jul 14 05:47:56 PM PDT 24
Peak memory 215444 kb
Host smart-95ce2384-ad05-4726-a0f3-591876ba736a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877577275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1877577275
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2142103073
Short name T1118
Test name
Test status
Simulation time 11061741 ps
CPU time 0.68 seconds
Started Jul 14 05:47:54 PM PDT 24
Finished Jul 14 05:47:55 PM PDT 24
Peak memory 204188 kb
Host smart-c0dfa5e8-581a-47b6-9c9a-084e5a0611cb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142103073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2142103073
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.50379656
Short name T1054
Test name
Test status
Simulation time 168709904 ps
CPU time 3.04 seconds
Started Jul 14 05:48:03 PM PDT 24
Finished Jul 14 05:48:06 PM PDT 24
Peak memory 215520 kb
Host smart-c49dce6f-65aa-4a70-8257-7210a8cfb14c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50379656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_same_csr_outstanding.50379656
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3120807124
Short name T105
Test name
Test status
Simulation time 151877406 ps
CPU time 3.64 seconds
Started Jul 14 05:47:45 PM PDT 24
Finished Jul 14 05:47:49 PM PDT 24
Peak memory 215632 kb
Host smart-60fe3862-fc24-4baa-8030-dd288bbf34f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120807124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
120807124
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2234218594
Short name T104
Test name
Test status
Simulation time 865149820 ps
CPU time 22.61 seconds
Started Jul 14 05:47:52 PM PDT 24
Finished Jul 14 05:48:15 PM PDT 24
Peak memory 215804 kb
Host smart-9626c72d-7abb-4653-b117-95397cd31804
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234218594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2234218594
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2248438502
Short name T1047
Test name
Test status
Simulation time 11731261 ps
CPU time 0.73 seconds
Started Jul 14 05:49:05 PM PDT 24
Finished Jul 14 05:49:06 PM PDT 24
Peak memory 204264 kb
Host smart-ac2feeab-95aa-470a-b19a-c54504999d19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248438502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2248438502
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2946861939
Short name T1150
Test name
Test status
Simulation time 16445612 ps
CPU time 0.77 seconds
Started Jul 14 05:49:12 PM PDT 24
Finished Jul 14 05:49:13 PM PDT 24
Peak memory 204248 kb
Host smart-de35890d-0e8d-49fa-bc97-c4aaf569d481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946861939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2946861939
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1282364875
Short name T1087
Test name
Test status
Simulation time 25359639 ps
CPU time 0.77 seconds
Started Jul 14 05:49:13 PM PDT 24
Finished Jul 14 05:49:14 PM PDT 24
Peak memory 203976 kb
Host smart-d1713012-c8c1-4928-93ad-c0173ff67350
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282364875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1282364875
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1161939142
Short name T1094
Test name
Test status
Simulation time 25952970 ps
CPU time 0.77 seconds
Started Jul 14 05:49:14 PM PDT 24
Finished Jul 14 05:49:16 PM PDT 24
Peak memory 203964 kb
Host smart-e9984f5b-beb9-43cd-9b78-d5955b6238c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161939142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1161939142
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2121418080
Short name T1078
Test name
Test status
Simulation time 14371643 ps
CPU time 0.69 seconds
Started Jul 14 05:49:15 PM PDT 24
Finished Jul 14 05:49:16 PM PDT 24
Peak memory 203788 kb
Host smart-bc6feb5b-3076-456c-bea5-dd8164b5dad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121418080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2121418080
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4155099425
Short name T1045
Test name
Test status
Simulation time 11864174 ps
CPU time 0.77 seconds
Started Jul 14 05:49:13 PM PDT 24
Finished Jul 14 05:49:14 PM PDT 24
Peak memory 203988 kb
Host smart-baee41e3-3007-428d-8345-04b0e164dc36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155099425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
4155099425
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1912378731
Short name T1121
Test name
Test status
Simulation time 35984369 ps
CPU time 0.77 seconds
Started Jul 14 05:49:12 PM PDT 24
Finished Jul 14 05:49:14 PM PDT 24
Peak memory 203980 kb
Host smart-8c701531-355f-488f-9bf5-023d7b09694d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912378731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1912378731
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1041878807
Short name T1099
Test name
Test status
Simulation time 14244908 ps
CPU time 0.73 seconds
Started Jul 14 05:49:12 PM PDT 24
Finished Jul 14 05:49:13 PM PDT 24
Peak memory 204272 kb
Host smart-6a96cc7c-33fd-4b54-ac70-c633c2c4b384
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041878807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1041878807
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.830306835
Short name T1083
Test name
Test status
Simulation time 86133506 ps
CPU time 0.72 seconds
Started Jul 14 05:49:12 PM PDT 24
Finished Jul 14 05:49:14 PM PDT 24
Peak memory 203972 kb
Host smart-c7a009c7-fa66-43eb-98b4-1c0bdc4b40e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830306835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.830306835
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1291418064
Short name T1064
Test name
Test status
Simulation time 13025677 ps
CPU time 0.74 seconds
Started Jul 14 05:49:14 PM PDT 24
Finished Jul 14 05:49:16 PM PDT 24
Peak memory 203976 kb
Host smart-96622c2d-a742-4f65-9ec1-2e7ebfb45561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291418064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1291418064
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1476026981
Short name T1143
Test name
Test status
Simulation time 57438380 ps
CPU time 4.28 seconds
Started Jul 14 05:48:04 PM PDT 24
Finished Jul 14 05:48:09 PM PDT 24
Peak memory 218576 kb
Host smart-22832d41-1489-4e8c-9155-39b6fdb66167
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476026981 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1476026981
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2360611681
Short name T1128
Test name
Test status
Simulation time 106102821 ps
CPU time 2 seconds
Started Jul 14 05:48:03 PM PDT 24
Finished Jul 14 05:48:06 PM PDT 24
Peak memory 215448 kb
Host smart-e874d4a7-ee58-46df-8aae-954cc91d2016
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360611681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
360611681
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.524297351
Short name T1101
Test name
Test status
Simulation time 173451309 ps
CPU time 0.76 seconds
Started Jul 14 05:48:03 PM PDT 24
Finished Jul 14 05:48:04 PM PDT 24
Peak memory 203956 kb
Host smart-b797a7d5-b098-434d-a874-18a0f2955022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524297351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.524297351
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3343667940
Short name T1035
Test name
Test status
Simulation time 456100252 ps
CPU time 3.38 seconds
Started Jul 14 05:48:00 PM PDT 24
Finished Jul 14 05:48:04 PM PDT 24
Peak memory 215384 kb
Host smart-896e8e27-a223-427a-a2aa-cb2d885bbebe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343667940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3343667940
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4292603349
Short name T1057
Test name
Test status
Simulation time 34591837 ps
CPU time 2.05 seconds
Started Jul 14 05:48:04 PM PDT 24
Finished Jul 14 05:48:06 PM PDT 24
Peak memory 215660 kb
Host smart-2dfed44a-6b8b-45cc-afd5-4631a3a2b2f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292603349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.4
292603349
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3201324336
Short name T172
Test name
Test status
Simulation time 1315189147 ps
CPU time 18.27 seconds
Started Jul 14 05:48:04 PM PDT 24
Finished Jul 14 05:48:23 PM PDT 24
Peak memory 215544 kb
Host smart-bccea10e-31ff-4186-9ffb-e7b9b8cf559d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201324336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3201324336
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1463819531
Short name T1086
Test name
Test status
Simulation time 69470300 ps
CPU time 2.55 seconds
Started Jul 14 05:48:11 PM PDT 24
Finished Jul 14 05:48:14 PM PDT 24
Peak memory 217932 kb
Host smart-c6d6874c-f625-4641-8430-19ff5cfe87f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463819531 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1463819531
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1280855937
Short name T150
Test name
Test status
Simulation time 81872837 ps
CPU time 2.06 seconds
Started Jul 14 05:48:09 PM PDT 24
Finished Jul 14 05:48:11 PM PDT 24
Peak memory 207304 kb
Host smart-c5c69480-eaa4-4e11-95b3-0d709e12070d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280855937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
280855937
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.760586644
Short name T1122
Test name
Test status
Simulation time 13510658 ps
CPU time 0.73 seconds
Started Jul 14 05:48:10 PM PDT 24
Finished Jul 14 05:48:11 PM PDT 24
Peak memory 203908 kb
Host smart-e73666a5-646f-4089-995a-d316cd364a8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760586644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.760586644
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1657223696
Short name T1088
Test name
Test status
Simulation time 30747876 ps
CPU time 1.95 seconds
Started Jul 14 05:48:08 PM PDT 24
Finished Jul 14 05:48:11 PM PDT 24
Peak memory 215460 kb
Host smart-c593f2ac-3585-4b28-856f-4a1c2071914b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657223696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1657223696
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.596444022
Short name T103
Test name
Test status
Simulation time 706196900 ps
CPU time 3.95 seconds
Started Jul 14 05:48:09 PM PDT 24
Finished Jul 14 05:48:13 PM PDT 24
Peak memory 215624 kb
Host smart-9896a416-179b-4da3-8e74-fa856359bd41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596444022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.596444022
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2493973497
Short name T174
Test name
Test status
Simulation time 2163916491 ps
CPU time 6.89 seconds
Started Jul 14 05:48:09 PM PDT 24
Finished Jul 14 05:48:17 PM PDT 24
Peak memory 215468 kb
Host smart-c9921d0c-9add-4c98-a67f-dd21286d28f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493973497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2493973497
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.112361845
Short name T101
Test name
Test status
Simulation time 141975897 ps
CPU time 2.83 seconds
Started Jul 14 05:48:10 PM PDT 24
Finished Jul 14 05:48:14 PM PDT 24
Peak memory 216500 kb
Host smart-ccddd08c-6b18-4fcf-8736-5daabedf6b75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112361845 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.112361845
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1700308314
Short name T1065
Test name
Test status
Simulation time 35790670 ps
CPU time 1.25 seconds
Started Jul 14 05:48:10 PM PDT 24
Finished Jul 14 05:48:11 PM PDT 24
Peak memory 215516 kb
Host smart-0ce68459-1646-414d-a95a-a4fab83504b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700308314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
700308314
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1527964806
Short name T1031
Test name
Test status
Simulation time 285551610 ps
CPU time 0.74 seconds
Started Jul 14 05:48:13 PM PDT 24
Finished Jul 14 05:48:15 PM PDT 24
Peak memory 204268 kb
Host smart-611e1aae-c85a-4e2d-bff0-40a0ba058c6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527964806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
527964806
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.161750016
Short name T136
Test name
Test status
Simulation time 306002635 ps
CPU time 2.96 seconds
Started Jul 14 05:48:11 PM PDT 24
Finished Jul 14 05:48:14 PM PDT 24
Peak memory 215468 kb
Host smart-b0ab75ec-3808-4af0-9b61-0c2f010d9b6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161750016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.161750016
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.4285394920
Short name T1105
Test name
Test status
Simulation time 247637607 ps
CPU time 2.32 seconds
Started Jul 14 05:48:13 PM PDT 24
Finished Jul 14 05:48:16 PM PDT 24
Peak memory 215748 kb
Host smart-7ef03617-e65b-4e75-a982-8772a52a05c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285394920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.4
285394920
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.53758098
Short name T1120
Test name
Test status
Simulation time 1322634498 ps
CPU time 7.73 seconds
Started Jul 14 05:48:10 PM PDT 24
Finished Jul 14 05:48:18 PM PDT 24
Peak memory 216724 kb
Host smart-9717aa86-77c4-4d1c-938a-5f4dca540ea5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53758098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_t
l_intg_err.53758098
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3120787297
Short name T1111
Test name
Test status
Simulation time 42437208 ps
CPU time 1.58 seconds
Started Jul 14 05:48:18 PM PDT 24
Finished Jul 14 05:48:20 PM PDT 24
Peak memory 215428 kb
Host smart-c1098adf-68c7-4646-9c0e-f7e5a8f5b546
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120787297 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3120787297
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1245142597
Short name T1142
Test name
Test status
Simulation time 102560816 ps
CPU time 1.85 seconds
Started Jul 14 05:48:18 PM PDT 24
Finished Jul 14 05:48:21 PM PDT 24
Peak memory 215736 kb
Host smart-615d53b1-c1f2-4b11-906b-7d185b7e12d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245142597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
245142597
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3635690019
Short name T1029
Test name
Test status
Simulation time 32090974 ps
CPU time 0.73 seconds
Started Jul 14 05:48:17 PM PDT 24
Finished Jul 14 05:48:18 PM PDT 24
Peak memory 203956 kb
Host smart-40b24f85-69cc-40e6-91c7-a66a8dfbf936
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635690019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
635690019
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2762502926
Short name T1138
Test name
Test status
Simulation time 236300381 ps
CPU time 3.86 seconds
Started Jul 14 05:48:18 PM PDT 24
Finished Jul 14 05:48:23 PM PDT 24
Peak memory 215444 kb
Host smart-506ead5b-c9f2-4af7-a12a-d70cb8f492f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762502926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2762502926
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1964341121
Short name T99
Test name
Test status
Simulation time 334338197 ps
CPU time 3.86 seconds
Started Jul 14 05:48:18 PM PDT 24
Finished Jul 14 05:48:22 PM PDT 24
Peak memory 215628 kb
Host smart-c64b74a8-9926-4f07-a3e3-da0f9a562c1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964341121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
964341121
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2398955316
Short name T98
Test name
Test status
Simulation time 1102936837 ps
CPU time 7.71 seconds
Started Jul 14 05:48:18 PM PDT 24
Finished Jul 14 05:48:26 PM PDT 24
Peak memory 215796 kb
Host smart-fb7f2d33-64f6-47e4-8e51-0c269ebe2d70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398955316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2398955316
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.280008734
Short name T165
Test name
Test status
Simulation time 58866406 ps
CPU time 1.7 seconds
Started Jul 14 05:48:25 PM PDT 24
Finished Jul 14 05:48:27 PM PDT 24
Peak memory 215420 kb
Host smart-2cb88cb9-8978-4f71-9eb3-8476bb992f60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280008734 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.280008734
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.448701401
Short name T1141
Test name
Test status
Simulation time 158037302 ps
CPU time 1.86 seconds
Started Jul 14 05:48:23 PM PDT 24
Finished Jul 14 05:48:25 PM PDT 24
Peak memory 207276 kb
Host smart-ece2e1e4-c093-4d7e-b4e7-7d7994feb127
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448701401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.448701401
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.634188586
Short name T1100
Test name
Test status
Simulation time 49937855 ps
CPU time 0.77 seconds
Started Jul 14 05:48:27 PM PDT 24
Finished Jul 14 05:48:28 PM PDT 24
Peak memory 204264 kb
Host smart-8c2fd681-8101-45a9-92c9-9828bb69d356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634188586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.634188586
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.34770539
Short name T1110
Test name
Test status
Simulation time 28817575 ps
CPU time 1.82 seconds
Started Jul 14 05:48:22 PM PDT 24
Finished Jul 14 05:48:25 PM PDT 24
Peak memory 207240 kb
Host smart-f84ed6e6-973d-44c1-a12d-592071c68508
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34770539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi
_device_same_csr_outstanding.34770539
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2155885832
Short name T1126
Test name
Test status
Simulation time 819072443 ps
CPU time 2.24 seconds
Started Jul 14 05:48:21 PM PDT 24
Finished Jul 14 05:48:24 PM PDT 24
Peak memory 216712 kb
Host smart-1d1f867d-a87b-4527-a529-96bf18aceab5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155885832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
155885832
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3729312728
Short name T111
Test name
Test status
Simulation time 710985148 ps
CPU time 19.23 seconds
Started Jul 14 05:48:20 PM PDT 24
Finished Jul 14 05:48:39 PM PDT 24
Peak memory 215568 kb
Host smart-d711ad93-9744-4fba-8f97-718eaa247b6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729312728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3729312728
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2835980492
Short name T891
Test name
Test status
Simulation time 14806721 ps
CPU time 0.79 seconds
Started Jul 14 05:51:09 PM PDT 24
Finished Jul 14 05:51:10 PM PDT 24
Peak memory 206360 kb
Host smart-89db8cf3-34da-4d31-b471-5ac981537bf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835980492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
835980492
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1157893549
Short name T878
Test name
Test status
Simulation time 92427465 ps
CPU time 3.03 seconds
Started Jul 14 05:51:02 PM PDT 24
Finished Jul 14 05:51:05 PM PDT 24
Peak memory 233740 kb
Host smart-00f4fd43-6fbf-4729-b8a1-ac8a03efd0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157893549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1157893549
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2881562811
Short name T371
Test name
Test status
Simulation time 19598508 ps
CPU time 0.83 seconds
Started Jul 14 05:51:01 PM PDT 24
Finished Jul 14 05:51:02 PM PDT 24
Peak memory 206356 kb
Host smart-70fd221a-0621-40e8-afc2-d7d6ba77598a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881562811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2881562811
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2155115273
Short name T563
Test name
Test status
Simulation time 1928301983 ps
CPU time 9.01 seconds
Started Jul 14 05:51:01 PM PDT 24
Finished Jul 14 05:51:10 PM PDT 24
Peak memory 250188 kb
Host smart-7585763b-be8d-444a-8bf5-eef1925eeaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155115273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2155115273
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2509187632
Short name T500
Test name
Test status
Simulation time 30407792279 ps
CPU time 258.87 seconds
Started Jul 14 05:50:59 PM PDT 24
Finished Jul 14 05:55:19 PM PDT 24
Peak memory 250400 kb
Host smart-8f2eff3b-49d4-4108-bce2-fdd28589a2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509187632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2509187632
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.494069954
Short name T659
Test name
Test status
Simulation time 133023058 ps
CPU time 4.09 seconds
Started Jul 14 05:50:59 PM PDT 24
Finished Jul 14 05:51:04 PM PDT 24
Peak memory 225476 kb
Host smart-0a18790e-fe7b-4ea7-95a9-49c49bbc0ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494069954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.494069954
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.290512771
Short name T774
Test name
Test status
Simulation time 41788519033 ps
CPU time 286.37 seconds
Started Jul 14 05:50:59 PM PDT 24
Finished Jul 14 05:55:45 PM PDT 24
Peak memory 255972 kb
Host smart-b9b7edc3-8bba-492d-aa4f-04674d9f08b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290512771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
290512771
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.340186974
Short name T840
Test name
Test status
Simulation time 1588999570 ps
CPU time 7.18 seconds
Started Jul 14 05:51:01 PM PDT 24
Finished Jul 14 05:51:09 PM PDT 24
Peak memory 225556 kb
Host smart-094733a2-ea7e-44ff-8bbf-3a8e4a09b936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340186974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.340186974
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.889019223
Short name T226
Test name
Test status
Simulation time 1817882251 ps
CPU time 11.03 seconds
Started Jul 14 05:51:01 PM PDT 24
Finished Jul 14 05:51:13 PM PDT 24
Peak memory 233760 kb
Host smart-f4685de4-567e-4e34-bab5-066deacab7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889019223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.889019223
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3710428970
Short name T717
Test name
Test status
Simulation time 481387890 ps
CPU time 5.37 seconds
Started Jul 14 05:50:58 PM PDT 24
Finished Jul 14 05:51:04 PM PDT 24
Peak memory 225552 kb
Host smart-efd7e0c7-9cfc-41a9-b67d-116d573a2d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710428970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3710428970
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.4212252068
Short name T581
Test name
Test status
Simulation time 3136220983 ps
CPU time 10.58 seconds
Started Jul 14 05:51:01 PM PDT 24
Finished Jul 14 05:51:12 PM PDT 24
Peak memory 225636 kb
Host smart-e0bd22e9-bb83-412a-afb3-f106ea58a7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212252068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4212252068
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.4043802372
Short name T821
Test name
Test status
Simulation time 10947833647 ps
CPU time 15.71 seconds
Started Jul 14 05:51:00 PM PDT 24
Finished Jul 14 05:51:16 PM PDT 24
Peak memory 220408 kb
Host smart-0676c15c-df4f-4937-8d6b-7ea25ef6db8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4043802372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.4043802372
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2720595920
Short name T160
Test name
Test status
Simulation time 17301778095 ps
CPU time 14.49 seconds
Started Jul 14 05:51:01 PM PDT 24
Finished Jul 14 05:51:16 PM PDT 24
Peak memory 217824 kb
Host smart-2a3c4e19-bd62-4f79-ba96-fd48e67d996e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720595920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2720595920
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.481793757
Short name T676
Test name
Test status
Simulation time 20666006813 ps
CPU time 11.32 seconds
Started Jul 14 05:51:00 PM PDT 24
Finished Jul 14 05:51:12 PM PDT 24
Peak memory 217428 kb
Host smart-24209090-2dfb-42f8-9d33-250696ca1b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481793757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.481793757
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.453844219
Short name T351
Test name
Test status
Simulation time 72349163 ps
CPU time 1.44 seconds
Started Jul 14 05:50:59 PM PDT 24
Finished Jul 14 05:51:01 PM PDT 24
Peak memory 217360 kb
Host smart-8142fc5e-46ec-439d-b90e-07bb1f50f60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453844219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.453844219
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2166569185
Short name T91
Test name
Test status
Simulation time 83443043 ps
CPU time 0.85 seconds
Started Jul 14 05:50:59 PM PDT 24
Finished Jul 14 05:51:01 PM PDT 24
Peak memory 206880 kb
Host smart-30601a07-daa6-4f7f-8b6a-6a77abde0620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166569185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2166569185
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.630909387
Short name T845
Test name
Test status
Simulation time 917032904 ps
CPU time 5 seconds
Started Jul 14 05:51:01 PM PDT 24
Finished Jul 14 05:51:07 PM PDT 24
Peak memory 225580 kb
Host smart-92742d8e-a1f8-4d50-bc38-e04c97a24b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630909387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.630909387
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1790830946
Short name T497
Test name
Test status
Simulation time 12308716 ps
CPU time 0.75 seconds
Started Jul 14 05:51:17 PM PDT 24
Finished Jul 14 05:51:18 PM PDT 24
Peak memory 206004 kb
Host smart-1cd8e0e6-aca3-49fe-ad42-4d233f489c8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790830946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
790830946
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1940228742
Short name T718
Test name
Test status
Simulation time 179898125 ps
CPU time 2.23 seconds
Started Jul 14 05:51:06 PM PDT 24
Finished Jul 14 05:51:09 PM PDT 24
Peak memory 224264 kb
Host smart-ac0fe8eb-d9ad-44cc-b4a6-5897363f681b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940228742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1940228742
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.21051796
Short name T900
Test name
Test status
Simulation time 59629682 ps
CPU time 0.84 seconds
Started Jul 14 05:51:08 PM PDT 24
Finished Jul 14 05:51:09 PM PDT 24
Peak memory 207492 kb
Host smart-a0e43dc6-b544-4012-a6a2-dee1e03eb3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21051796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.21051796
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3803087281
Short name T193
Test name
Test status
Simulation time 6869529879 ps
CPU time 72.94 seconds
Started Jul 14 05:51:18 PM PDT 24
Finished Jul 14 05:52:32 PM PDT 24
Peak memory 257484 kb
Host smart-ff1eecab-dd3b-4966-be6a-aaf453459694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803087281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3803087281
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2414422329
Short name T533
Test name
Test status
Simulation time 11888112405 ps
CPU time 189.66 seconds
Started Jul 14 05:51:16 PM PDT 24
Finished Jul 14 05:54:27 PM PDT 24
Peak memory 265284 kb
Host smart-ce8dfcb7-c21f-4fe4-84f1-1593f4062565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414422329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2414422329
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1857125920
Short name T285
Test name
Test status
Simulation time 7098089988 ps
CPU time 68.75 seconds
Started Jul 14 05:51:17 PM PDT 24
Finished Jul 14 05:52:27 PM PDT 24
Peak memory 253412 kb
Host smart-908526c8-7a24-4723-824b-5a6279ec6cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857125920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1857125920
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3978465380
Short name T975
Test name
Test status
Simulation time 27005136343 ps
CPU time 58.89 seconds
Started Jul 14 05:51:07 PM PDT 24
Finished Jul 14 05:52:06 PM PDT 24
Peak memory 250280 kb
Host smart-6957a068-7c01-40bf-99f8-a602c571cdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978465380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3978465380
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.293337225
Short name T380
Test name
Test status
Simulation time 2068968436 ps
CPU time 5.78 seconds
Started Jul 14 05:51:08 PM PDT 24
Finished Jul 14 05:51:14 PM PDT 24
Peak memory 225444 kb
Host smart-f3c1115b-bf4f-429a-93e6-6278b254b912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293337225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.293337225
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3347373466
Short name T688
Test name
Test status
Simulation time 379583369 ps
CPU time 6.8 seconds
Started Jul 14 05:51:07 PM PDT 24
Finished Jul 14 05:51:15 PM PDT 24
Peak memory 225424 kb
Host smart-39df1991-e429-4720-ae6f-6e51d66491c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347373466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3347373466
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1370636598
Short name T972
Test name
Test status
Simulation time 15741581 ps
CPU time 1.06 seconds
Started Jul 14 05:51:06 PM PDT 24
Finished Jul 14 05:51:08 PM PDT 24
Peak memory 218868 kb
Host smart-03ba3240-9875-4e94-888c-3687fc55007c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370636598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1370636598
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1062606506
Short name T931
Test name
Test status
Simulation time 117040700 ps
CPU time 2.58 seconds
Started Jul 14 05:51:08 PM PDT 24
Finished Jul 14 05:51:11 PM PDT 24
Peak memory 233448 kb
Host smart-610dae34-f95f-4109-9f79-a609fe555dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062606506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1062606506
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4085119218
Short name T190
Test name
Test status
Simulation time 18971611726 ps
CPU time 18.49 seconds
Started Jul 14 05:51:06 PM PDT 24
Finished Jul 14 05:51:26 PM PDT 24
Peak memory 241544 kb
Host smart-66d000e0-b3e3-4ee1-9f78-dbdeda24f75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085119218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4085119218
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1974169605
Short name T806
Test name
Test status
Simulation time 190200545 ps
CPU time 4.74 seconds
Started Jul 14 05:51:06 PM PDT 24
Finished Jul 14 05:51:12 PM PDT 24
Peak memory 221176 kb
Host smart-7d1602f5-7e3d-4f5b-afe3-0cb4b407f39b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1974169605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1974169605
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2639402942
Short name T76
Test name
Test status
Simulation time 180760336 ps
CPU time 1 seconds
Started Jul 14 05:51:18 PM PDT 24
Finished Jul 14 05:51:20 PM PDT 24
Peak memory 236320 kb
Host smart-251df994-1f3b-4bd3-81c1-2d3845f083a6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639402942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2639402942
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2707152835
Short name T182
Test name
Test status
Simulation time 49273497254 ps
CPU time 377.44 seconds
Started Jul 14 05:51:17 PM PDT 24
Finished Jul 14 05:57:36 PM PDT 24
Peak memory 252420 kb
Host smart-ba7b57f5-436b-466f-b9e9-95f6815de7a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707152835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2707152835
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1563463573
Short name T560
Test name
Test status
Simulation time 4066593931 ps
CPU time 17.31 seconds
Started Jul 14 05:51:08 PM PDT 24
Finished Jul 14 05:51:26 PM PDT 24
Peak memory 217568 kb
Host smart-c7558045-26ac-4454-b656-23e638d1b633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563463573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1563463573
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2491182905
Short name T680
Test name
Test status
Simulation time 4766304066 ps
CPU time 7.41 seconds
Started Jul 14 05:51:07 PM PDT 24
Finished Jul 14 05:51:15 PM PDT 24
Peak memory 217456 kb
Host smart-0281de2c-659f-4145-aa2b-2a44e5bdda39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491182905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2491182905
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1355105195
Short name T1021
Test name
Test status
Simulation time 123807279 ps
CPU time 2.04 seconds
Started Jul 14 05:51:07 PM PDT 24
Finished Jul 14 05:51:10 PM PDT 24
Peak memory 217328 kb
Host smart-0cd3d0b8-1d0c-4ec6-b2ba-28fe8bf0a901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355105195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1355105195
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2638500874
Short name T387
Test name
Test status
Simulation time 69658995 ps
CPU time 0.82 seconds
Started Jul 14 05:51:09 PM PDT 24
Finished Jul 14 05:51:11 PM PDT 24
Peak memory 206980 kb
Host smart-4ff6a45e-e7b4-4d8e-88c9-581739c788ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638500874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2638500874
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3004499068
Short name T1013
Test name
Test status
Simulation time 2362320862 ps
CPU time 4.07 seconds
Started Jul 14 05:51:07 PM PDT 24
Finished Jul 14 05:51:12 PM PDT 24
Peak memory 233820 kb
Host smart-286c55cd-6f7a-4a50-b098-9b44d1595946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004499068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3004499068
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2201408417
Short name T426
Test name
Test status
Simulation time 15420574 ps
CPU time 0.72 seconds
Started Jul 14 05:52:27 PM PDT 24
Finished Jul 14 05:52:28 PM PDT 24
Peak memory 206348 kb
Host smart-4cd9fb70-6f72-4a6a-abf9-a9eb3a079069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201408417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2201408417
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2314130537
Short name T917
Test name
Test status
Simulation time 242417591 ps
CPU time 4.55 seconds
Started Jul 14 05:52:15 PM PDT 24
Finished Jul 14 05:52:20 PM PDT 24
Peak memory 225440 kb
Host smart-cd8b5c05-f5ec-4fa0-9f40-03fe364074c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314130537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2314130537
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3111270441
Short name T866
Test name
Test status
Simulation time 15266637 ps
CPU time 0.79 seconds
Started Jul 14 05:52:12 PM PDT 24
Finished Jul 14 05:52:14 PM PDT 24
Peak memory 207840 kb
Host smart-ba5fb4bf-7cbb-4a61-8aed-811c5bfb792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111270441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3111270441
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.715171864
Short name T684
Test name
Test status
Simulation time 181793806758 ps
CPU time 226.25 seconds
Started Jul 14 05:52:17 PM PDT 24
Finished Jul 14 05:56:04 PM PDT 24
Peak memory 256404 kb
Host smart-35d2ce50-ab30-4b59-af4a-0d9cb1601dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715171864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.715171864
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2422960396
Short name T260
Test name
Test status
Simulation time 60648893536 ps
CPU time 160.32 seconds
Started Jul 14 05:52:28 PM PDT 24
Finished Jul 14 05:55:08 PM PDT 24
Peak memory 274924 kb
Host smart-2e120a16-75b1-435a-8c0e-a2c01b6657c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422960396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2422960396
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2156697377
Short name T490
Test name
Test status
Simulation time 100735207830 ps
CPU time 220.82 seconds
Started Jul 14 05:52:26 PM PDT 24
Finished Jul 14 05:56:07 PM PDT 24
Peak memory 257144 kb
Host smart-5f303bb4-cddf-4bd8-965c-25f247fdeba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156697377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2156697377
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3725463966
Short name T1024
Test name
Test status
Simulation time 9549834957 ps
CPU time 54.65 seconds
Started Jul 14 05:52:15 PM PDT 24
Finished Jul 14 05:53:11 PM PDT 24
Peak memory 233800 kb
Host smart-5c1c36dc-ab65-4a03-a6f3-2477a7c902b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725463966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3725463966
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.4104482133
Short name T681
Test name
Test status
Simulation time 5678234221 ps
CPU time 42.03 seconds
Started Jul 14 05:52:20 PM PDT 24
Finished Jul 14 05:53:02 PM PDT 24
Peak memory 237064 kb
Host smart-0a4df567-cac9-419b-92f0-e0127913c363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104482133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.4104482133
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2009192597
Short name T189
Test name
Test status
Simulation time 21376768344 ps
CPU time 14.4 seconds
Started Jul 14 05:52:16 PM PDT 24
Finished Jul 14 05:52:31 PM PDT 24
Peak memory 233768 kb
Host smart-eaafd4b7-fa29-4f4f-9664-5072cd1805c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009192597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2009192597
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1060839845
Short name T63
Test name
Test status
Simulation time 8889864551 ps
CPU time 87.87 seconds
Started Jul 14 05:52:25 PM PDT 24
Finished Jul 14 05:53:54 PM PDT 24
Peak memory 250040 kb
Host smart-6e9c4fce-b02b-496e-9d7b-27cefad2393f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060839845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1060839845
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3789071862
Short name T408
Test name
Test status
Simulation time 96503492 ps
CPU time 1.01 seconds
Started Jul 14 05:52:09 PM PDT 24
Finished Jul 14 05:52:10 PM PDT 24
Peak memory 218948 kb
Host smart-ab8b9421-5b90-411c-90fe-5573ee653dcc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789071862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3789071862
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.345183897
Short name T851
Test name
Test status
Simulation time 2492613856 ps
CPU time 10.16 seconds
Started Jul 14 05:52:18 PM PDT 24
Finished Jul 14 05:52:28 PM PDT 24
Peak memory 242004 kb
Host smart-76a038a1-c8ae-4a68-b399-0a4f484c807b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345183897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.345183897
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1395736364
Short name T623
Test name
Test status
Simulation time 12996830159 ps
CPU time 8.02 seconds
Started Jul 14 05:52:15 PM PDT 24
Finished Jul 14 05:52:23 PM PDT 24
Peak memory 225612 kb
Host smart-07aa24d9-1daf-4fc9-84ee-693e1be04120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395736364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1395736364
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2353130447
Short name T1000
Test name
Test status
Simulation time 2989023135 ps
CPU time 17.49 seconds
Started Jul 14 05:52:17 PM PDT 24
Finished Jul 14 05:52:35 PM PDT 24
Peak memory 223160 kb
Host smart-9c281cff-b06c-490d-81bf-85568b9e0d3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2353130447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2353130447
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.445558049
Short name T17
Test name
Test status
Simulation time 59875084270 ps
CPU time 231.97 seconds
Started Jul 14 05:52:24 PM PDT 24
Finished Jul 14 05:56:17 PM PDT 24
Peak memory 252980 kb
Host smart-09b025c4-ddf9-4a88-bfa1-c609a5d97c14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445558049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.445558049
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.389909018
Short name T969
Test name
Test status
Simulation time 13325859 ps
CPU time 0.76 seconds
Started Jul 14 05:52:18 PM PDT 24
Finished Jul 14 05:52:19 PM PDT 24
Peak memory 206612 kb
Host smart-ca2f8be0-21c5-4e4c-86e8-c53dee21e66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389909018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.389909018
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2690259328
Short name T907
Test name
Test status
Simulation time 936571477 ps
CPU time 6.16 seconds
Started Jul 14 05:52:16 PM PDT 24
Finished Jul 14 05:52:23 PM PDT 24
Peak memory 217364 kb
Host smart-9a85c9ad-8e2f-4ae2-80e2-2f6167622cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690259328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2690259328
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2790476598
Short name T561
Test name
Test status
Simulation time 36507838 ps
CPU time 1.63 seconds
Started Jul 14 05:52:16 PM PDT 24
Finished Jul 14 05:52:18 PM PDT 24
Peak memory 217328 kb
Host smart-81f245a5-0271-4f8b-a89d-d30df648661f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790476598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2790476598
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.646285999
Short name T846
Test name
Test status
Simulation time 86981468 ps
CPU time 0.83 seconds
Started Jul 14 05:52:15 PM PDT 24
Finished Jul 14 05:52:16 PM PDT 24
Peak memory 206908 kb
Host smart-b58e5c02-484a-4e73-829e-16fc362aa7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646285999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.646285999
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.605464291
Short name T820
Test name
Test status
Simulation time 371963269 ps
CPU time 2.4 seconds
Started Jul 14 05:52:16 PM PDT 24
Finished Jul 14 05:52:18 PM PDT 24
Peak memory 225048 kb
Host smart-7f0f545a-3ad2-4611-af97-21107f810fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605464291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.605464291
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2720258633
Short name T1006
Test name
Test status
Simulation time 30714838 ps
CPU time 0.69 seconds
Started Jul 14 05:52:33 PM PDT 24
Finished Jul 14 05:52:34 PM PDT 24
Peak memory 206656 kb
Host smart-d7735d99-a469-496d-98c2-d9a8484e417c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720258633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2720258633
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3382740922
Short name T526
Test name
Test status
Simulation time 69060157 ps
CPU time 3.08 seconds
Started Jul 14 05:52:33 PM PDT 24
Finished Jul 14 05:52:37 PM PDT 24
Peak memory 233636 kb
Host smart-4d7ae502-1154-4fd5-9487-b08f593b0e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382740922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3382740922
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3622526622
Short name T601
Test name
Test status
Simulation time 17532265 ps
CPU time 0.78 seconds
Started Jul 14 05:52:28 PM PDT 24
Finished Jul 14 05:52:29 PM PDT 24
Peak memory 207504 kb
Host smart-ff03be6a-3e7c-4308-871d-3ef3fa3fef28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622526622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3622526622
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1030314097
Short name T203
Test name
Test status
Simulation time 26859297696 ps
CPU time 185.56 seconds
Started Jul 14 05:52:35 PM PDT 24
Finished Jul 14 05:55:41 PM PDT 24
Peak memory 252864 kb
Host smart-7577e926-d408-4ab8-aac5-a7b7ab21a732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030314097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1030314097
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1003154015
Short name T417
Test name
Test status
Simulation time 6367043960 ps
CPU time 70.69 seconds
Started Jul 14 05:52:33 PM PDT 24
Finished Jul 14 05:53:44 PM PDT 24
Peak memory 258516 kb
Host smart-6b944dc9-3bf2-4dc5-92cc-2fc351ad893a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003154015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1003154015
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.4186699860
Short name T767
Test name
Test status
Simulation time 42223488667 ps
CPU time 212.25 seconds
Started Jul 14 05:52:40 PM PDT 24
Finished Jul 14 05:56:13 PM PDT 24
Peak memory 264720 kb
Host smart-45d64efd-2869-4f0d-84e3-bc68ef1de116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186699860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.4186699860
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1801109232
Short name T669
Test name
Test status
Simulation time 519073037 ps
CPU time 6.61 seconds
Started Jul 14 05:52:34 PM PDT 24
Finished Jul 14 05:52:41 PM PDT 24
Peak memory 241236 kb
Host smart-9944b1bf-809f-4b6e-8151-19199cd7e6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801109232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1801109232
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3558323407
Short name T991
Test name
Test status
Simulation time 6456228936 ps
CPU time 77.98 seconds
Started Jul 14 05:52:33 PM PDT 24
Finished Jul 14 05:53:52 PM PDT 24
Peak memory 267396 kb
Host smart-381ba931-f81e-478c-b45c-52f3a672130e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558323407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3558323407
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2524492254
Short name T636
Test name
Test status
Simulation time 405697305 ps
CPU time 7.46 seconds
Started Jul 14 05:52:24 PM PDT 24
Finished Jul 14 05:52:32 PM PDT 24
Peak memory 233652 kb
Host smart-ef7afbfd-3d82-4569-afc0-1c892e7d5ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524492254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2524492254
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.4145172428
Short name T622
Test name
Test status
Simulation time 3234090816 ps
CPU time 27.73 seconds
Started Jul 14 05:52:25 PM PDT 24
Finished Jul 14 05:52:53 PM PDT 24
Peak memory 225628 kb
Host smart-3ec67ece-34fb-4513-9703-c6563fe5d162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145172428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.4145172428
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1131429526
Short name T966
Test name
Test status
Simulation time 25015310 ps
CPU time 1.03 seconds
Started Jul 14 05:52:32 PM PDT 24
Finished Jul 14 05:52:33 PM PDT 24
Peak memory 217628 kb
Host smart-f12164b4-9057-444f-ac61-cfe16ad70b6c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131429526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1131429526
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1592104773
Short name T254
Test name
Test status
Simulation time 6577566145 ps
CPU time 20 seconds
Started Jul 14 05:52:28 PM PDT 24
Finished Jul 14 05:52:48 PM PDT 24
Peak memory 233840 kb
Host smart-cbf68b8b-5ab8-402e-8a60-57cfb0e5ad8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592104773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1592104773
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3679383649
Short name T12
Test name
Test status
Simulation time 12831546569 ps
CPU time 16.08 seconds
Started Jul 14 05:52:27 PM PDT 24
Finished Jul 14 05:52:43 PM PDT 24
Peak memory 252252 kb
Host smart-84440942-aba8-4f33-bae1-37e72afa5d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679383649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3679383649
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.921449537
Short name T945
Test name
Test status
Simulation time 991407357 ps
CPU time 11.65 seconds
Started Jul 14 05:52:33 PM PDT 24
Finished Jul 14 05:52:45 PM PDT 24
Peak memory 220320 kb
Host smart-224cbf85-b5f7-407c-a5b0-f8dfc6a87098
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=921449537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.921449537
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3040972610
Short name T932
Test name
Test status
Simulation time 3254708100 ps
CPU time 16.02 seconds
Started Jul 14 05:52:27 PM PDT 24
Finished Jul 14 05:52:43 PM PDT 24
Peak memory 217692 kb
Host smart-f6532069-de55-49a8-91da-8be4f51dc592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040972610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3040972610
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.457115839
Short name T574
Test name
Test status
Simulation time 2952595318 ps
CPU time 11.86 seconds
Started Jul 14 05:52:25 PM PDT 24
Finished Jul 14 05:52:37 PM PDT 24
Peak memory 217472 kb
Host smart-571962a9-4594-493d-8d31-a6b5c49e599a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457115839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.457115839
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.81799631
Short name T863
Test name
Test status
Simulation time 686975896 ps
CPU time 1.94 seconds
Started Jul 14 05:52:26 PM PDT 24
Finished Jul 14 05:52:29 PM PDT 24
Peak memory 217264 kb
Host smart-b131b8b2-c8f5-49b6-a221-a02fc7731a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81799631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.81799631
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1158493976
Short name T456
Test name
Test status
Simulation time 42941984 ps
CPU time 0.79 seconds
Started Jul 14 05:52:26 PM PDT 24
Finished Jul 14 05:52:28 PM PDT 24
Peak memory 206928 kb
Host smart-4da49793-201c-49f7-ab36-dd894a8a8b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158493976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1158493976
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.510357972
Short name T205
Test name
Test status
Simulation time 251227086 ps
CPU time 2.96 seconds
Started Jul 14 05:52:35 PM PDT 24
Finished Jul 14 05:52:38 PM PDT 24
Peak memory 233800 kb
Host smart-ad2bd369-a070-4a7d-9951-ce3d8a63e200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510357972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.510357972
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1242146645
Short name T805
Test name
Test status
Simulation time 12705780 ps
CPU time 0.71 seconds
Started Jul 14 05:52:43 PM PDT 24
Finished Jul 14 05:52:44 PM PDT 24
Peak memory 206256 kb
Host smart-6903b8ce-5e27-4391-9d2f-953ee449bc88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242146645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1242146645
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1866010082
Short name T543
Test name
Test status
Simulation time 28768914 ps
CPU time 2.65 seconds
Started Jul 14 05:52:42 PM PDT 24
Finished Jul 14 05:52:45 PM PDT 24
Peak memory 233500 kb
Host smart-bb5faa3b-a17c-4736-990d-85242c8670cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866010082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1866010082
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.4098236075
Short name T719
Test name
Test status
Simulation time 18105268 ps
CPU time 0.8 seconds
Started Jul 14 05:52:34 PM PDT 24
Finished Jul 14 05:52:36 PM PDT 24
Peak memory 207412 kb
Host smart-266afb41-1769-40e5-b288-26811700db46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098236075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4098236075
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3198485113
Short name T666
Test name
Test status
Simulation time 2585039404 ps
CPU time 29.44 seconds
Started Jul 14 05:52:42 PM PDT 24
Finished Jul 14 05:53:12 PM PDT 24
Peak memory 250324 kb
Host smart-20eb497b-f66d-4e00-a4b0-4556e4838343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198485113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3198485113
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.4075805865
Short name T288
Test name
Test status
Simulation time 65700601531 ps
CPU time 595.44 seconds
Started Jul 14 05:52:42 PM PDT 24
Finished Jul 14 06:02:39 PM PDT 24
Peak memory 251436 kb
Host smart-8f5195bd-cb3d-4cd3-8fbd-3c08b4ebec2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075805865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.4075805865
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.284288416
Short name T183
Test name
Test status
Simulation time 13972982574 ps
CPU time 92.5 seconds
Started Jul 14 05:52:41 PM PDT 24
Finished Jul 14 05:54:14 PM PDT 24
Peak memory 251528 kb
Host smart-6095547a-cddd-400f-ac84-9cb74d4241a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284288416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.284288416
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.585831136
Short name T691
Test name
Test status
Simulation time 121514936 ps
CPU time 2.99 seconds
Started Jul 14 05:52:43 PM PDT 24
Finished Jul 14 05:52:46 PM PDT 24
Peak memory 225564 kb
Host smart-f596d9e1-1f2d-403e-98eb-707be35d5794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585831136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.585831136
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.4040032580
Short name T424
Test name
Test status
Simulation time 696829436 ps
CPU time 8.29 seconds
Started Jul 14 05:52:34 PM PDT 24
Finished Jul 14 05:52:42 PM PDT 24
Peak memory 233784 kb
Host smart-3f66aee5-7b40-4195-857a-137f9b061205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040032580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.4040032580
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1786045356
Short name T1018
Test name
Test status
Simulation time 5036677664 ps
CPU time 43.53 seconds
Started Jul 14 05:52:32 PM PDT 24
Finished Jul 14 05:53:15 PM PDT 24
Peak memory 240732 kb
Host smart-0dac6980-4ed9-47b6-8d4c-12029fc71dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786045356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1786045356
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2999124199
Short name T974
Test name
Test status
Simulation time 35776839 ps
CPU time 1.09 seconds
Started Jul 14 05:52:35 PM PDT 24
Finished Jul 14 05:52:37 PM PDT 24
Peak memory 217624 kb
Host smart-39fed130-3c28-479d-a14d-5442449a3d84
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999124199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2999124199
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.4137424151
Short name T283
Test name
Test status
Simulation time 15502393814 ps
CPU time 13.54 seconds
Started Jul 14 05:52:33 PM PDT 24
Finished Jul 14 05:52:47 PM PDT 24
Peak memory 225584 kb
Host smart-c5a349e7-7cc6-49ed-98ad-8647daf71703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137424151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.4137424151
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.4120259573
Short name T967
Test name
Test status
Simulation time 1402333247 ps
CPU time 7.55 seconds
Started Jul 14 05:52:38 PM PDT 24
Finished Jul 14 05:52:46 PM PDT 24
Peak memory 225552 kb
Host smart-db75c69d-c186-4f26-a057-54fdb33a5dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120259573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.4120259573
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1262716458
Short name T609
Test name
Test status
Simulation time 4440046682 ps
CPU time 9.38 seconds
Started Jul 14 05:52:40 PM PDT 24
Finished Jul 14 05:52:49 PM PDT 24
Peak memory 220320 kb
Host smart-430c7ba1-362c-478d-bd1f-8b2b99c87bab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1262716458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1262716458
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2042071880
Short name T476
Test name
Test status
Simulation time 12703333 ps
CPU time 0.73 seconds
Started Jul 14 05:52:34 PM PDT 24
Finished Jul 14 05:52:36 PM PDT 24
Peak memory 206896 kb
Host smart-60ec53bf-7c6f-46dc-a409-02c2e5e58394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042071880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2042071880
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2094246129
Short name T677
Test name
Test status
Simulation time 5554728956 ps
CPU time 17.33 seconds
Started Jul 14 05:52:32 PM PDT 24
Finished Jul 14 05:52:50 PM PDT 24
Peak memory 217484 kb
Host smart-fc6c1b59-7586-4185-9949-6a4654163082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094246129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2094246129
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1162432631
Short name T631
Test name
Test status
Simulation time 238250825 ps
CPU time 2.82 seconds
Started Jul 14 05:52:36 PM PDT 24
Finished Jul 14 05:52:39 PM PDT 24
Peak memory 217348 kb
Host smart-bb4e438e-4c84-47cf-91de-b51680dab7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162432631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1162432631
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2522022889
Short name T553
Test name
Test status
Simulation time 26636801 ps
CPU time 0.84 seconds
Started Jul 14 05:52:40 PM PDT 24
Finished Jul 14 05:52:41 PM PDT 24
Peak memory 206956 kb
Host smart-c59ff159-2b24-442b-abf0-37daa9cf9725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522022889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2522022889
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1261212935
Short name T833
Test name
Test status
Simulation time 21003361137 ps
CPU time 26.25 seconds
Started Jul 14 05:52:35 PM PDT 24
Finished Jul 14 05:53:01 PM PDT 24
Peak memory 225712 kb
Host smart-68d03bc3-941e-434b-8809-a95098f75c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261212935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1261212935
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1744267761
Short name T451
Test name
Test status
Simulation time 169138831 ps
CPU time 2.36 seconds
Started Jul 14 05:52:48 PM PDT 24
Finished Jul 14 05:52:51 PM PDT 24
Peak memory 233764 kb
Host smart-285ca006-da1a-453e-8866-7bfe3f0a8445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744267761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1744267761
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.793246156
Short name T600
Test name
Test status
Simulation time 95471812 ps
CPU time 0.78 seconds
Started Jul 14 05:52:43 PM PDT 24
Finished Jul 14 05:52:44 PM PDT 24
Peak memory 207488 kb
Host smart-adc35525-0e33-4f62-a27e-e6b4121c376c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793246156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.793246156
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3479175793
Short name T904
Test name
Test status
Simulation time 6627557128 ps
CPU time 30.8 seconds
Started Jul 14 05:52:48 PM PDT 24
Finished Jul 14 05:53:20 PM PDT 24
Peak memory 258304 kb
Host smart-9220c820-f423-448e-b1e7-fd5e4832e1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479175793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3479175793
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.4129925144
Short name T227
Test name
Test status
Simulation time 4818738442 ps
CPU time 128.29 seconds
Started Jul 14 05:52:47 PM PDT 24
Finished Jul 14 05:54:55 PM PDT 24
Peak memory 266776 kb
Host smart-de9f3ef0-1d73-4928-802b-1cce495364df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129925144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.4129925144
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2948714064
Short name T787
Test name
Test status
Simulation time 10690333137 ps
CPU time 48.29 seconds
Started Jul 14 05:52:49 PM PDT 24
Finished Jul 14 05:53:37 PM PDT 24
Peak memory 234340 kb
Host smart-d0f2ff53-bf07-4c8e-b86f-777c733bcf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948714064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2948714064
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3907573732
Short name T46
Test name
Test status
Simulation time 119972668372 ps
CPU time 207.14 seconds
Started Jul 14 05:52:53 PM PDT 24
Finished Jul 14 05:56:21 PM PDT 24
Peak memory 254164 kb
Host smart-2ff89c64-dafb-4162-98a5-8616819d4ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907573732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3907573732
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3851153969
Short name T457
Test name
Test status
Simulation time 205310073 ps
CPU time 2.77 seconds
Started Jul 14 05:52:41 PM PDT 24
Finished Jul 14 05:52:45 PM PDT 24
Peak memory 233712 kb
Host smart-70834ab8-7e38-4377-a131-08945e61a84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851153969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3851153969
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.279522502
Short name T897
Test name
Test status
Simulation time 7652120545 ps
CPU time 75.83 seconds
Started Jul 14 05:52:51 PM PDT 24
Finished Jul 14 05:54:08 PM PDT 24
Peak memory 241876 kb
Host smart-64aed906-726c-4775-88d0-8ea0f16a358e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279522502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.279522502
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.264112919
Short name T42
Test name
Test status
Simulation time 63869091 ps
CPU time 1.04 seconds
Started Jul 14 05:52:41 PM PDT 24
Finished Jul 14 05:52:43 PM PDT 24
Peak memory 218876 kb
Host smart-48718469-f4bc-4f9c-8e5f-4fe2d4e0a8d0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264112919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.264112919
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1255517912
Short name T838
Test name
Test status
Simulation time 5245244996 ps
CPU time 16.27 seconds
Started Jul 14 05:52:42 PM PDT 24
Finished Jul 14 05:52:58 PM PDT 24
Peak memory 235840 kb
Host smart-af160081-be21-4547-8349-f92dc82db7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255517912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1255517912
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3699009710
Short name T1002
Test name
Test status
Simulation time 340645852 ps
CPU time 2.94 seconds
Started Jul 14 05:52:41 PM PDT 24
Finished Jul 14 05:52:44 PM PDT 24
Peak memory 233700 kb
Host smart-c40683c0-ac78-4546-9491-d71208f7f0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699009710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3699009710
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.143171337
Short name T527
Test name
Test status
Simulation time 1154848665 ps
CPU time 6.81 seconds
Started Jul 14 05:52:48 PM PDT 24
Finished Jul 14 05:52:56 PM PDT 24
Peak memory 220080 kb
Host smart-b8bafe77-6192-4472-85de-9c3a741a7751
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=143171337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.143171337
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3721438617
Short name T8
Test name
Test status
Simulation time 6625759565 ps
CPU time 8.75 seconds
Started Jul 14 05:52:41 PM PDT 24
Finished Jul 14 05:52:50 PM PDT 24
Peak memory 217444 kb
Host smart-cb52cce7-2655-431a-8f6d-e3b75ced6a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721438617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3721438617
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.413554761
Short name T361
Test name
Test status
Simulation time 5438413338 ps
CPU time 4.71 seconds
Started Jul 14 05:52:42 PM PDT 24
Finished Jul 14 05:52:48 PM PDT 24
Peak memory 217624 kb
Host smart-15020c47-051e-4b21-9a01-f5c48bfa8d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413554761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.413554761
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3788672938
Short name T760
Test name
Test status
Simulation time 140642576 ps
CPU time 1.07 seconds
Started Jul 14 05:52:42 PM PDT 24
Finished Jul 14 05:52:44 PM PDT 24
Peak memory 208952 kb
Host smart-ac667097-fd1f-459c-9a56-95e3369f56bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788672938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3788672938
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1684504620
Short name T626
Test name
Test status
Simulation time 83467529 ps
CPU time 0.96 seconds
Started Jul 14 05:52:40 PM PDT 24
Finished Jul 14 05:52:42 PM PDT 24
Peak memory 206936 kb
Host smart-f821e592-0a06-4beb-b72f-7d9139c6ea50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684504620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1684504620
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1039045426
Short name T429
Test name
Test status
Simulation time 1647992194 ps
CPU time 7.81 seconds
Started Jul 14 05:52:49 PM PDT 24
Finished Jul 14 05:52:57 PM PDT 24
Peak memory 233644 kb
Host smart-0d388557-b9df-49c8-8a8a-234f1dc6de18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039045426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1039045426
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.33185695
Short name T955
Test name
Test status
Simulation time 18360236 ps
CPU time 0.73 seconds
Started Jul 14 05:52:56 PM PDT 24
Finished Jul 14 05:52:57 PM PDT 24
Peak memory 206288 kb
Host smart-01b34e6b-8c61-472e-9fa7-9dc7e10430ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33185695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.33185695
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2955644489
Short name T266
Test name
Test status
Simulation time 1838107557 ps
CPU time 6.35 seconds
Started Jul 14 05:52:54 PM PDT 24
Finished Jul 14 05:53:02 PM PDT 24
Peak memory 233752 kb
Host smart-d607a54d-52cc-450e-8c44-4775df8bbac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955644489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2955644489
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.233162483
Short name T778
Test name
Test status
Simulation time 46915948 ps
CPU time 0.78 seconds
Started Jul 14 05:52:53 PM PDT 24
Finished Jul 14 05:52:54 PM PDT 24
Peak memory 207844 kb
Host smart-cccd6460-17ab-48b7-890a-555241bcb331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233162483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.233162483
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1625468751
Short name T470
Test name
Test status
Simulation time 176519163591 ps
CPU time 175.07 seconds
Started Jul 14 05:52:56 PM PDT 24
Finished Jul 14 05:55:52 PM PDT 24
Peak memory 242032 kb
Host smart-5b096096-f019-492a-abc9-9c2e8edf75e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625468751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1625468751
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.123926221
Short name T289
Test name
Test status
Simulation time 31411876661 ps
CPU time 294.7 seconds
Started Jul 14 05:52:55 PM PDT 24
Finished Jul 14 05:57:50 PM PDT 24
Peak memory 257092 kb
Host smart-f52e9ac6-8e6d-4b7f-bfce-7bdfa5b773e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123926221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.123926221
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1691084404
Short name T765
Test name
Test status
Simulation time 8947794548 ps
CPU time 57.81 seconds
Started Jul 14 05:52:58 PM PDT 24
Finished Jul 14 05:53:56 PM PDT 24
Peak memory 250268 kb
Host smart-36c08bab-a57e-41cf-8cf8-945c03ab63ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691084404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1691084404
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.4178275355
Short name T520
Test name
Test status
Simulation time 10607505180 ps
CPU time 41.43 seconds
Started Jul 14 05:52:56 PM PDT 24
Finished Jul 14 05:53:39 PM PDT 24
Peak memory 235976 kb
Host smart-97b9951a-6537-49a8-94eb-218b0aa94765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178275355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4178275355
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.4000403470
Short name T1023
Test name
Test status
Simulation time 80373988393 ps
CPU time 163.59 seconds
Started Jul 14 05:52:57 PM PDT 24
Finished Jul 14 05:55:41 PM PDT 24
Peak memory 251472 kb
Host smart-e2e3e3b3-209a-43b1-aac4-bd4d1ea5c1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000403470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.4000403470
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1226024524
Short name T210
Test name
Test status
Simulation time 3304499442 ps
CPU time 6.11 seconds
Started Jul 14 05:52:56 PM PDT 24
Finished Jul 14 05:53:03 PM PDT 24
Peak memory 233852 kb
Host smart-df703555-64c3-4870-b88f-f7b957dff7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226024524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1226024524
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1231264289
Short name T374
Test name
Test status
Simulation time 9691874460 ps
CPU time 84.28 seconds
Started Jul 14 05:52:57 PM PDT 24
Finished Jul 14 05:54:22 PM PDT 24
Peak memory 233836 kb
Host smart-c7f6f8f8-4f26-474e-b254-99f47f90e49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231264289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1231264289
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.4065968665
Short name T807
Test name
Test status
Simulation time 33142203 ps
CPU time 1.1 seconds
Started Jul 14 05:52:50 PM PDT 24
Finished Jul 14 05:52:51 PM PDT 24
Peak memory 217580 kb
Host smart-115ee45e-2300-4468-9180-083d304b62dc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065968665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.4065968665
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2782536287
Short name T458
Test name
Test status
Simulation time 1184087285 ps
CPU time 5.14 seconds
Started Jul 14 05:52:56 PM PDT 24
Finished Jul 14 05:53:02 PM PDT 24
Peak memory 233716 kb
Host smart-c1b9b3aa-b34f-4d12-b69e-8708ee55966b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782536287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2782536287
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3190185922
Short name T454
Test name
Test status
Simulation time 319876754 ps
CPU time 5.73 seconds
Started Jul 14 05:52:55 PM PDT 24
Finished Jul 14 05:53:01 PM PDT 24
Peak memory 233732 kb
Host smart-d5c7b08b-1a35-4df4-9795-177641e821b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190185922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3190185922
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.135152531
Short name T564
Test name
Test status
Simulation time 1428085631 ps
CPU time 14.45 seconds
Started Jul 14 05:52:58 PM PDT 24
Finished Jul 14 05:53:13 PM PDT 24
Peak memory 224084 kb
Host smart-345eabdc-cd37-4724-a39c-58beb8a44793
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=135152531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.135152531
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2744157410
Short name T494
Test name
Test status
Simulation time 83459516 ps
CPU time 0.97 seconds
Started Jul 14 05:52:56 PM PDT 24
Finished Jul 14 05:52:58 PM PDT 24
Peak memory 207468 kb
Host smart-28276489-5cf2-433d-b20c-2590c766134e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744157410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2744157410
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2226738964
Short name T731
Test name
Test status
Simulation time 2519471042 ps
CPU time 7.88 seconds
Started Jul 14 05:52:54 PM PDT 24
Finished Jul 14 05:53:02 PM PDT 24
Peak memory 220700 kb
Host smart-f3ddbd88-1ae4-4f0b-b62a-cd7ef7da3e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226738964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2226738964
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2317357120
Short name T750
Test name
Test status
Simulation time 6988851037 ps
CPU time 12.23 seconds
Started Jul 14 05:52:47 PM PDT 24
Finished Jul 14 05:53:00 PM PDT 24
Peak memory 217488 kb
Host smart-aee2d2cb-9db8-454f-8df3-2d7ea588327f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317357120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2317357120
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1010642358
Short name T644
Test name
Test status
Simulation time 20912759 ps
CPU time 0.94 seconds
Started Jul 14 05:52:53 PM PDT 24
Finished Jul 14 05:52:54 PM PDT 24
Peak memory 208180 kb
Host smart-367501d2-d951-47c7-ae40-3b7617789ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010642358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1010642358
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1159237629
Short name T721
Test name
Test status
Simulation time 156239561 ps
CPU time 0.98 seconds
Started Jul 14 05:52:46 PM PDT 24
Finished Jul 14 05:52:48 PM PDT 24
Peak memory 207972 kb
Host smart-01136dc0-afdf-426a-9a50-c42eb93ae039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159237629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1159237629
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1571622895
Short name T861
Test name
Test status
Simulation time 1827608698 ps
CPU time 4.06 seconds
Started Jul 14 05:52:53 PM PDT 24
Finished Jul 14 05:52:58 PM PDT 24
Peak memory 225512 kb
Host smart-f6e5ee6d-b2b9-4f73-96e6-6be44bbd689b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571622895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1571622895
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3492166697
Short name T355
Test name
Test status
Simulation time 12158276 ps
CPU time 0.71 seconds
Started Jul 14 05:53:09 PM PDT 24
Finished Jul 14 05:53:10 PM PDT 24
Peak memory 205784 kb
Host smart-835b1bda-c23f-4f24-a412-1ace282bde7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492166697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3492166697
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2073855059
Short name T359
Test name
Test status
Simulation time 2378398966 ps
CPU time 13.15 seconds
Started Jul 14 05:53:03 PM PDT 24
Finished Jul 14 05:53:16 PM PDT 24
Peak memory 225664 kb
Host smart-a390f747-d0d9-4c59-aabd-3b142b39d0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073855059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2073855059
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3340465313
Short name T909
Test name
Test status
Simulation time 16852118 ps
CPU time 0.8 seconds
Started Jul 14 05:52:56 PM PDT 24
Finished Jul 14 05:52:58 PM PDT 24
Peak memory 207692 kb
Host smart-c1fbcd1f-1aea-4173-88d9-53e072272bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340465313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3340465313
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3614612901
Short name T951
Test name
Test status
Simulation time 5948290280 ps
CPU time 31.07 seconds
Started Jul 14 05:53:08 PM PDT 24
Finished Jul 14 05:53:40 PM PDT 24
Peak memory 238772 kb
Host smart-c40fe407-8c1d-4c8e-ae21-bbc970f30f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614612901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3614612901
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3187362904
Short name T422
Test name
Test status
Simulation time 1769681294 ps
CPU time 24.27 seconds
Started Jul 14 05:53:10 PM PDT 24
Finished Jul 14 05:53:35 PM PDT 24
Peak memory 237740 kb
Host smart-69639557-f7a2-4ce9-acd3-d67280430dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187362904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3187362904
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.650511084
Short name T301
Test name
Test status
Simulation time 598296712 ps
CPU time 11.17 seconds
Started Jul 14 05:53:05 PM PDT 24
Finished Jul 14 05:53:16 PM PDT 24
Peak memory 241788 kb
Host smart-ea6a58da-783f-4fa3-a4ca-e470537c51fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650511084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.650511084
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1128303570
Short name T47
Test name
Test status
Simulation time 64690471088 ps
CPU time 52.21 seconds
Started Jul 14 05:53:05 PM PDT 24
Finished Jul 14 05:53:58 PM PDT 24
Peak memory 250164 kb
Host smart-20f17bcb-7863-495b-967d-62f663c7a88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128303570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1128303570
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.749992901
Short name T771
Test name
Test status
Simulation time 87137480 ps
CPU time 2.47 seconds
Started Jul 14 05:53:04 PM PDT 24
Finished Jul 14 05:53:07 PM PDT 24
Peak memory 225388 kb
Host smart-de14074f-23e1-43cb-ad71-c6385cbd5971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749992901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.749992901
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.369252187
Short name T827
Test name
Test status
Simulation time 373011558 ps
CPU time 5.52 seconds
Started Jul 14 05:53:05 PM PDT 24
Finished Jul 14 05:53:11 PM PDT 24
Peak memory 233592 kb
Host smart-d9a3d1f5-65db-4d6a-a356-dec79973b286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369252187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.369252187
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1863262162
Short name T910
Test name
Test status
Simulation time 16048144 ps
CPU time 1.01 seconds
Started Jul 14 05:52:56 PM PDT 24
Finished Jul 14 05:52:58 PM PDT 24
Peak memory 217656 kb
Host smart-dfa4d295-3ec6-4e3c-830b-7d813bb05635
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863262162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1863262162
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1726513703
Short name T914
Test name
Test status
Simulation time 66357843 ps
CPU time 2.77 seconds
Started Jul 14 05:53:01 PM PDT 24
Finished Jul 14 05:53:04 PM PDT 24
Peak memory 225504 kb
Host smart-119cdb60-9bf6-4c3b-8239-62e76a825a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726513703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1726513703
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3694104635
Short name T922
Test name
Test status
Simulation time 288740476 ps
CPU time 2.31 seconds
Started Jul 14 05:53:00 PM PDT 24
Finished Jul 14 05:53:03 PM PDT 24
Peak memory 224896 kb
Host smart-e6f5869e-ab16-470a-b81e-102382a68133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694104635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3694104635
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2130317193
Short name T413
Test name
Test status
Simulation time 17483417078 ps
CPU time 11.2 seconds
Started Jul 14 05:53:03 PM PDT 24
Finished Jul 14 05:53:14 PM PDT 24
Peak memory 224196 kb
Host smart-caf8ea2c-ea6d-4644-970c-af5aa867bf09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2130317193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2130317193
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1899945231
Short name T306
Test name
Test status
Simulation time 2569957195 ps
CPU time 26.93 seconds
Started Jul 14 05:53:04 PM PDT 24
Finished Jul 14 05:53:32 PM PDT 24
Peak memory 217388 kb
Host smart-3b319dba-ac5e-4fbe-b845-5f41721f5331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899945231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1899945231
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2381027646
Short name T438
Test name
Test status
Simulation time 7185182764 ps
CPU time 9.98 seconds
Started Jul 14 05:52:54 PM PDT 24
Finished Jul 14 05:53:05 PM PDT 24
Peak memory 217440 kb
Host smart-2fb5235a-f468-49e0-a868-d74fb9e0ada5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381027646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2381027646
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3592104114
Short name T477
Test name
Test status
Simulation time 95608282 ps
CPU time 1.55 seconds
Started Jul 14 05:53:01 PM PDT 24
Finished Jul 14 05:53:03 PM PDT 24
Peak memory 217340 kb
Host smart-9bab560d-5da2-44e9-826d-ae08da1c0486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592104114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3592104114
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2429811038
Short name T871
Test name
Test status
Simulation time 15457212 ps
CPU time 0.71 seconds
Started Jul 14 05:53:03 PM PDT 24
Finished Jul 14 05:53:04 PM PDT 24
Peak memory 206864 kb
Host smart-b58cc094-0fe4-4876-b943-f279df66e7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429811038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2429811038
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.59070003
Short name T705
Test name
Test status
Simulation time 1733344112 ps
CPU time 9.02 seconds
Started Jul 14 05:53:04 PM PDT 24
Finished Jul 14 05:53:13 PM PDT 24
Peak memory 225544 kb
Host smart-6d0d32e5-e11a-452a-919b-ed21934bdbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59070003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.59070003
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.4172592038
Short name T488
Test name
Test status
Simulation time 36957633 ps
CPU time 0.72 seconds
Started Jul 14 05:53:15 PM PDT 24
Finished Jul 14 05:53:16 PM PDT 24
Peak memory 206280 kb
Host smart-e85686d1-aac4-4b4d-b352-62446cada0e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172592038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
4172592038
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2740983235
Short name T404
Test name
Test status
Simulation time 1991354984 ps
CPU time 12.9 seconds
Started Jul 14 05:53:09 PM PDT 24
Finished Jul 14 05:53:22 PM PDT 24
Peak memory 233636 kb
Host smart-b0583747-719a-4a6a-8554-c5c133193f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740983235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2740983235
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.898457000
Short name T345
Test name
Test status
Simulation time 64681592 ps
CPU time 0.74 seconds
Started Jul 14 05:53:12 PM PDT 24
Finished Jul 14 05:53:13 PM PDT 24
Peak memory 207828 kb
Host smart-6ce7664d-578b-4f05-b60a-cb2acb6cdec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898457000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.898457000
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.4196504936
Short name T571
Test name
Test status
Simulation time 47441295555 ps
CPU time 172.69 seconds
Started Jul 14 05:53:17 PM PDT 24
Finished Jul 14 05:56:10 PM PDT 24
Peak memory 254232 kb
Host smart-48dca305-6aa4-4084-9465-f22a5c33e571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196504936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.4196504936
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1794225078
Short name T218
Test name
Test status
Simulation time 19642489803 ps
CPU time 220.88 seconds
Started Jul 14 05:53:19 PM PDT 24
Finished Jul 14 05:57:00 PM PDT 24
Peak memory 257664 kb
Host smart-bb9278b4-971f-4921-ad9b-63a18211fa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794225078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1794225078
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2715388077
Short name T211
Test name
Test status
Simulation time 15958856204 ps
CPU time 191.46 seconds
Started Jul 14 05:53:18 PM PDT 24
Finished Jul 14 05:56:30 PM PDT 24
Peak memory 266172 kb
Host smart-5ac3601d-0f5f-4fbd-8764-df5e709da464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715388077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2715388077
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2845801433
Short name T302
Test name
Test status
Simulation time 921108158 ps
CPU time 21.39 seconds
Started Jul 14 05:53:09 PM PDT 24
Finished Jul 14 05:53:31 PM PDT 24
Peak memory 236848 kb
Host smart-4f0c8774-afc9-4235-bcd1-2b577e74e2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845801433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2845801433
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.275641469
Short name T185
Test name
Test status
Simulation time 1695191480 ps
CPU time 41.65 seconds
Started Jul 14 05:53:09 PM PDT 24
Finished Jul 14 05:53:50 PM PDT 24
Peak memory 251384 kb
Host smart-5f3c7e3a-973a-4682-ad49-12b06362bb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275641469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.275641469
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4080514080
Short name T569
Test name
Test status
Simulation time 562984040 ps
CPU time 8.24 seconds
Started Jul 14 05:53:10 PM PDT 24
Finished Jul 14 05:53:18 PM PDT 24
Peak memory 225732 kb
Host smart-0150cfed-5c54-4241-a8df-8df13f2c3146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080514080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4080514080
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2046943746
Short name T667
Test name
Test status
Simulation time 3357017313 ps
CPU time 10.67 seconds
Started Jul 14 05:53:13 PM PDT 24
Finished Jul 14 05:53:24 PM PDT 24
Peak memory 239944 kb
Host smart-5fe6491d-1b93-445c-a4a5-16bae7b355bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046943746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2046943746
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3499971113
Short name T934
Test name
Test status
Simulation time 97983169 ps
CPU time 1.01 seconds
Started Jul 14 05:53:10 PM PDT 24
Finished Jul 14 05:53:11 PM PDT 24
Peak memory 218844 kb
Host smart-1b8722b1-2d12-4b91-8573-c7334502e8a7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499971113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3499971113
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.893954659
Short name T737
Test name
Test status
Simulation time 4085080509 ps
CPU time 7.18 seconds
Started Jul 14 05:53:10 PM PDT 24
Finished Jul 14 05:53:18 PM PDT 24
Peak memory 225608 kb
Host smart-cc7bd6c8-34a6-494b-870c-0e5cfcec0f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893954659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.893954659
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2948304613
Short name T800
Test name
Test status
Simulation time 653244513 ps
CPU time 3.72 seconds
Started Jul 14 05:53:10 PM PDT 24
Finished Jul 14 05:53:14 PM PDT 24
Peak memory 225540 kb
Host smart-422ae61a-dea1-4e95-a8eb-7f36c5108f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948304613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2948304613
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2258862854
Short name T928
Test name
Test status
Simulation time 783960138 ps
CPU time 5.54 seconds
Started Jul 14 05:53:15 PM PDT 24
Finished Jul 14 05:53:21 PM PDT 24
Peak memory 223164 kb
Host smart-f2b1074f-d1ec-411f-b222-7184fb18d91f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2258862854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2258862854
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.957747950
Short name T788
Test name
Test status
Simulation time 22538521371 ps
CPU time 146.08 seconds
Started Jul 14 05:53:17 PM PDT 24
Finished Jul 14 05:55:43 PM PDT 24
Peak memory 257860 kb
Host smart-b9b29821-e2cb-433c-8ec4-ab7c810a44e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957747950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.957747950
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.146430938
Short name T402
Test name
Test status
Simulation time 7410145262 ps
CPU time 20.89 seconds
Started Jul 14 05:53:10 PM PDT 24
Finished Jul 14 05:53:32 PM PDT 24
Peak memory 217588 kb
Host smart-3da2275e-97e4-4de4-b32a-f535413f92ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146430938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.146430938
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3271250537
Short name T617
Test name
Test status
Simulation time 1295595357 ps
CPU time 3.52 seconds
Started Jul 14 05:53:09 PM PDT 24
Finished Jul 14 05:53:13 PM PDT 24
Peak memory 217236 kb
Host smart-7337fd3b-f7d6-4e35-b658-a89f1b0ac4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271250537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3271250537
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2413252348
Short name T501
Test name
Test status
Simulation time 108209415 ps
CPU time 1.84 seconds
Started Jul 14 05:53:12 PM PDT 24
Finished Jul 14 05:53:15 PM PDT 24
Peak memory 217260 kb
Host smart-6d311115-14e3-49ce-a59a-21b3b61a9305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413252348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2413252348
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.233751554
Short name T343
Test name
Test status
Simulation time 147390266 ps
CPU time 0.83 seconds
Started Jul 14 05:53:10 PM PDT 24
Finished Jul 14 05:53:12 PM PDT 24
Peak memory 206848 kb
Host smart-1d933887-3bdf-480d-a764-837b7d3de5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233751554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.233751554
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3497998418
Short name T235
Test name
Test status
Simulation time 408735595 ps
CPU time 2.45 seconds
Started Jul 14 05:53:10 PM PDT 24
Finished Jul 14 05:53:14 PM PDT 24
Peak memory 225568 kb
Host smart-5bc491ea-7316-42e4-be61-608258b001be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497998418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3497998418
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2925787707
Short name T908
Test name
Test status
Simulation time 14129992 ps
CPU time 0.72 seconds
Started Jul 14 05:53:25 PM PDT 24
Finished Jul 14 05:53:26 PM PDT 24
Peak memory 206368 kb
Host smart-1d3321e9-bedf-4845-bbfb-947e0d423b63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925787707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2925787707
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1257167700
Short name T559
Test name
Test status
Simulation time 113798733 ps
CPU time 2.47 seconds
Started Jul 14 05:53:28 PM PDT 24
Finished Jul 14 05:53:31 PM PDT 24
Peak memory 225540 kb
Host smart-5a828019-2920-4bb9-82ab-4cb712033310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257167700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1257167700
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.243328010
Short name T700
Test name
Test status
Simulation time 12793809 ps
CPU time 0.73 seconds
Started Jul 14 05:53:17 PM PDT 24
Finished Jul 14 05:53:18 PM PDT 24
Peak memory 206680 kb
Host smart-1a7fea21-87da-471d-9536-c34752b78a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243328010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.243328010
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.169546697
Short name T85
Test name
Test status
Simulation time 6486548292 ps
CPU time 88.57 seconds
Started Jul 14 05:53:29 PM PDT 24
Finished Jul 14 05:54:58 PM PDT 24
Peak memory 250260 kb
Host smart-41b03549-d1b2-4aa7-9af7-31a49c4d153c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169546697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.169546697
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2501496848
Short name T532
Test name
Test status
Simulation time 331809721 ps
CPU time 4.75 seconds
Started Jul 14 05:53:26 PM PDT 24
Finished Jul 14 05:53:31 PM PDT 24
Peak memory 225564 kb
Host smart-d12bc340-b2ff-404f-bbc4-0fe285ca07a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501496848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2501496848
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3635815949
Short name T549
Test name
Test status
Simulation time 188344071 ps
CPU time 0.83 seconds
Started Jul 14 05:53:26 PM PDT 24
Finished Jul 14 05:53:28 PM PDT 24
Peak memory 217108 kb
Host smart-dd39cbe0-3e03-4b0b-b288-f71f3fecbefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635815949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3635815949
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2027499523
Short name T163
Test name
Test status
Simulation time 753029573 ps
CPU time 3.96 seconds
Started Jul 14 05:53:23 PM PDT 24
Finished Jul 14 05:53:27 PM PDT 24
Peak memory 233688 kb
Host smart-6db8ff87-f834-4a30-8f94-0b79a2b64a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027499523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2027499523
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.795643792
Short name T606
Test name
Test status
Simulation time 2543560055 ps
CPU time 13.97 seconds
Started Jul 14 05:53:26 PM PDT 24
Finished Jul 14 05:53:41 PM PDT 24
Peak memory 225708 kb
Host smart-364cf3c4-3c39-470a-b8d5-3dd977ba1017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795643792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.795643792
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1053075763
Short name T587
Test name
Test status
Simulation time 94079509 ps
CPU time 1.08 seconds
Started Jul 14 05:53:17 PM PDT 24
Finished Jul 14 05:53:19 PM PDT 24
Peak memory 217664 kb
Host smart-df5491a2-c08f-4c3f-b500-ff75144d2220
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053075763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1053075763
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.828139625
Short name T388
Test name
Test status
Simulation time 2222761478 ps
CPU time 8.4 seconds
Started Jul 14 05:53:18 PM PDT 24
Finished Jul 14 05:53:27 PM PDT 24
Peak memory 233852 kb
Host smart-46f8d7b7-22d8-4863-afa1-ed17f2604dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828139625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.828139625
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2954920277
Short name T228
Test name
Test status
Simulation time 206625532 ps
CPU time 2.89 seconds
Started Jul 14 05:53:15 PM PDT 24
Finished Jul 14 05:53:19 PM PDT 24
Peak memory 233732 kb
Host smart-010efe57-45a1-436f-9ea3-4ab047200182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954920277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2954920277
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3920039258
Short name T899
Test name
Test status
Simulation time 2227572758 ps
CPU time 13.46 seconds
Started Jul 14 05:53:24 PM PDT 24
Finished Jul 14 05:53:38 PM PDT 24
Peak memory 222872 kb
Host smart-06469127-4540-4857-801e-43c1958a2ed8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3920039258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3920039258
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2091755155
Short name T577
Test name
Test status
Simulation time 5555325973 ps
CPU time 33.65 seconds
Started Jul 14 05:53:16 PM PDT 24
Finished Jul 14 05:53:50 PM PDT 24
Peak memory 217532 kb
Host smart-fa417c47-43a6-43aa-96be-00c2940b900b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091755155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2091755155
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.271440723
Short name T958
Test name
Test status
Simulation time 812410132 ps
CPU time 6.23 seconds
Started Jul 14 05:53:17 PM PDT 24
Finished Jul 14 05:53:24 PM PDT 24
Peak memory 217344 kb
Host smart-a65c7523-78af-4199-921c-7d5a558e281f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271440723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.271440723
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3826423487
Short name T26
Test name
Test status
Simulation time 351807324 ps
CPU time 1.2 seconds
Started Jul 14 05:53:18 PM PDT 24
Finished Jul 14 05:53:19 PM PDT 24
Peak memory 208744 kb
Host smart-85b0d42d-72db-4562-af50-b7c30a6ed4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826423487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3826423487
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.291250142
Short name T699
Test name
Test status
Simulation time 286789841 ps
CPU time 0.84 seconds
Started Jul 14 05:53:15 PM PDT 24
Finished Jul 14 05:53:16 PM PDT 24
Peak memory 207200 kb
Host smart-d3b4abb1-1e30-4727-aad3-4cd65a2d601f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291250142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.291250142
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.4079553324
Short name T1007
Test name
Test status
Simulation time 23872714550 ps
CPU time 20.42 seconds
Started Jul 14 05:53:25 PM PDT 24
Finished Jul 14 05:53:46 PM PDT 24
Peak memory 233840 kb
Host smart-79762f1b-d052-429c-9a18-b7c17a0a2a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079553324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4079553324
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1573231361
Short name T342
Test name
Test status
Simulation time 14259185 ps
CPU time 0.72 seconds
Started Jul 14 05:53:33 PM PDT 24
Finished Jul 14 05:53:34 PM PDT 24
Peak memory 205652 kb
Host smart-f9b0b142-e17f-4ee8-87cf-2d89c947ad27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573231361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1573231361
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4042305369
Short name T236
Test name
Test status
Simulation time 621620365 ps
CPU time 6.11 seconds
Started Jul 14 05:53:33 PM PDT 24
Finished Jul 14 05:53:39 PM PDT 24
Peak memory 225472 kb
Host smart-6c6594ac-1b05-42fe-a773-a230900fef11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042305369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4042305369
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2474171347
Short name T521
Test name
Test status
Simulation time 19774149 ps
CPU time 0.79 seconds
Started Jul 14 05:53:26 PM PDT 24
Finished Jul 14 05:53:27 PM PDT 24
Peak memory 207808 kb
Host smart-f2a88dbf-8b4b-4ad2-9734-c3bf638cb4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474171347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2474171347
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2767901707
Short name T206
Test name
Test status
Simulation time 2427543881 ps
CPU time 7.42 seconds
Started Jul 14 05:53:32 PM PDT 24
Finished Jul 14 05:53:40 PM PDT 24
Peak memory 225700 kb
Host smart-bb073e35-832c-4be1-b4e6-98abad60f6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767901707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2767901707
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2336877961
Short name T782
Test name
Test status
Simulation time 12226520028 ps
CPU time 71.61 seconds
Started Jul 14 05:53:34 PM PDT 24
Finished Jul 14 05:54:46 PM PDT 24
Peak memory 258604 kb
Host smart-f2dd66f1-545e-4fd5-905e-46e58fd9987f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336877961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2336877961
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1806774309
Short name T1010
Test name
Test status
Simulation time 27724748115 ps
CPU time 272.64 seconds
Started Jul 14 05:53:34 PM PDT 24
Finished Jul 14 05:58:07 PM PDT 24
Peak memory 264408 kb
Host smart-ad2b927d-ff59-4482-9fe1-18298b162d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806774309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1806774309
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1938727430
Short name T987
Test name
Test status
Simulation time 6228588267 ps
CPU time 26 seconds
Started Jul 14 05:53:31 PM PDT 24
Finished Jul 14 05:53:57 PM PDT 24
Peak memory 233784 kb
Host smart-2a09624b-015d-4c69-a3c2-845fa8aa3abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938727430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1938727430
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.4168675930
Short name T655
Test name
Test status
Simulation time 68843544328 ps
CPU time 118.54 seconds
Started Jul 14 05:53:31 PM PDT 24
Finished Jul 14 05:55:31 PM PDT 24
Peak memory 250220 kb
Host smart-5c8e9b98-d848-442e-8126-74386eea0463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168675930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.4168675930
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3491995986
Short name T81
Test name
Test status
Simulation time 683364322 ps
CPU time 7.03 seconds
Started Jul 14 05:53:34 PM PDT 24
Finished Jul 14 05:53:42 PM PDT 24
Peak memory 225532 kb
Host smart-8c9e1c86-27b7-46c3-9236-130277cedc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491995986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3491995986
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1867948217
Short name T82
Test name
Test status
Simulation time 4360889486 ps
CPU time 31.94 seconds
Started Jul 14 05:53:31 PM PDT 24
Finished Jul 14 05:54:03 PM PDT 24
Peak memory 235280 kb
Host smart-3de1b365-f44f-41a2-a8c8-c5a125d1f1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867948217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1867948217
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1553464302
Short name T930
Test name
Test status
Simulation time 29239690 ps
CPU time 1.08 seconds
Started Jul 14 05:53:26 PM PDT 24
Finished Jul 14 05:53:28 PM PDT 24
Peak memory 218908 kb
Host smart-90a67dea-5d2c-4728-9523-cf0efd6715c3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553464302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1553464302
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.578677284
Short name T242
Test name
Test status
Simulation time 510546618 ps
CPU time 2.72 seconds
Started Jul 14 05:53:23 PM PDT 24
Finished Jul 14 05:53:27 PM PDT 24
Peak memory 225564 kb
Host smart-7d312528-989d-449e-bd9b-1a2be5383554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578677284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.578677284
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3191103445
Short name T492
Test name
Test status
Simulation time 868286195 ps
CPU time 4.99 seconds
Started Jul 14 05:53:32 PM PDT 24
Finished Jul 14 05:53:37 PM PDT 24
Peak memory 220196 kb
Host smart-9dd3a03e-33ef-4bec-9f0e-54a458d70b8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3191103445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3191103445
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3792715611
Short name T747
Test name
Test status
Simulation time 72363499936 ps
CPU time 675.18 seconds
Started Jul 14 05:53:32 PM PDT 24
Finished Jul 14 06:04:48 PM PDT 24
Peak memory 266712 kb
Host smart-bba5f743-4fa9-429f-b70a-588292e97fd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792715611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3792715611
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.397386909
Short name T309
Test name
Test status
Simulation time 5813519974 ps
CPU time 17.88 seconds
Started Jul 14 05:53:26 PM PDT 24
Finished Jul 14 05:53:45 PM PDT 24
Peak memory 217796 kb
Host smart-aa2871c8-8f38-4596-8409-980bc0b27b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397386909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.397386909
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2795070496
Short name T347
Test name
Test status
Simulation time 894768076 ps
CPU time 4.07 seconds
Started Jul 14 05:53:25 PM PDT 24
Finished Jul 14 05:53:29 PM PDT 24
Peak memory 217292 kb
Host smart-0be92799-8a21-46ad-801d-96a113a5b1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795070496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2795070496
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3707678342
Short name T602
Test name
Test status
Simulation time 122402462 ps
CPU time 1.74 seconds
Started Jul 14 05:53:26 PM PDT 24
Finished Jul 14 05:53:29 PM PDT 24
Peak memory 217344 kb
Host smart-9a5b8e83-7038-4ce6-86d6-c7adab88f77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707678342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3707678342
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2503965973
Short name T84
Test name
Test status
Simulation time 141498693 ps
CPU time 0.74 seconds
Started Jul 14 05:53:25 PM PDT 24
Finished Jul 14 05:53:26 PM PDT 24
Peak memory 206924 kb
Host smart-da639afd-8a30-4a84-8233-02fa4acd13f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503965973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2503965973
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2376885865
Short name T629
Test name
Test status
Simulation time 1881479502 ps
CPU time 6.4 seconds
Started Jul 14 05:53:32 PM PDT 24
Finished Jul 14 05:53:39 PM PDT 24
Peak memory 233752 kb
Host smart-d5f2ccaa-cfcc-41a7-9407-b122f8b0298c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376885865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2376885865
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.691652484
Short name T517
Test name
Test status
Simulation time 25331554 ps
CPU time 0.73 seconds
Started Jul 14 05:53:42 PM PDT 24
Finished Jul 14 05:53:44 PM PDT 24
Peak memory 206324 kb
Host smart-0f427ba9-fe4a-4b83-aa7d-719e330f2d63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691652484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.691652484
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1830288317
Short name T326
Test name
Test status
Simulation time 560957437 ps
CPU time 3.19 seconds
Started Jul 14 05:53:40 PM PDT 24
Finished Jul 14 05:53:44 PM PDT 24
Peak memory 233772 kb
Host smart-795eccd9-a133-4b2f-903d-c13189187b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830288317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1830288317
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2410099743
Short name T693
Test name
Test status
Simulation time 80517796 ps
CPU time 0.76 seconds
Started Jul 14 05:53:33 PM PDT 24
Finished Jul 14 05:53:34 PM PDT 24
Peak memory 206424 kb
Host smart-bd8f806a-78f4-45c4-a9c1-218025a1a3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410099743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2410099743
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3755863367
Short name T257
Test name
Test status
Simulation time 2830489653 ps
CPU time 51.1 seconds
Started Jul 14 05:53:43 PM PDT 24
Finished Jul 14 05:54:35 PM PDT 24
Peak memory 238120 kb
Host smart-61c2d9e4-dd3f-4f74-9dea-e60ecf1bbbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755863367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3755863367
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1917034923
Short name T541
Test name
Test status
Simulation time 10719878243 ps
CPU time 20.63 seconds
Started Jul 14 05:53:40 PM PDT 24
Finished Jul 14 05:54:01 PM PDT 24
Peak memory 225796 kb
Host smart-da15d606-f86d-4f74-8cb8-8b3ce792690b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917034923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1917034923
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.333612913
Short name T502
Test name
Test status
Simulation time 1960178831 ps
CPU time 39.27 seconds
Started Jul 14 05:53:41 PM PDT 24
Finished Jul 14 05:54:21 PM PDT 24
Peak memory 258008 kb
Host smart-b1621cd2-e64e-42bf-b9ab-0ca7f61ed527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333612913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.333612913
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1217973793
Short name T940
Test name
Test status
Simulation time 845524188 ps
CPU time 13.82 seconds
Started Jul 14 05:53:43 PM PDT 24
Finished Jul 14 05:53:57 PM PDT 24
Peak memory 225484 kb
Host smart-99c75361-0e7f-4050-a779-4a7651c7a464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217973793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1217973793
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.225212488
Short name T180
Test name
Test status
Simulation time 129383131713 ps
CPU time 217.92 seconds
Started Jul 14 05:53:43 PM PDT 24
Finished Jul 14 05:57:21 PM PDT 24
Peak memory 264928 kb
Host smart-a48acf9a-9f28-41dd-8ea8-a0e9e3dbef25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225212488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds
.225212488
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.310723978
Short name T516
Test name
Test status
Simulation time 303712557 ps
CPU time 5.95 seconds
Started Jul 14 05:53:40 PM PDT 24
Finished Jul 14 05:53:47 PM PDT 24
Peak memory 225428 kb
Host smart-d419be08-bad3-4d5f-b152-2ac35c4eaa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310723978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.310723978
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3104825882
Short name T649
Test name
Test status
Simulation time 46071964 ps
CPU time 1.02 seconds
Started Jul 14 05:53:32 PM PDT 24
Finished Jul 14 05:53:33 PM PDT 24
Peak memory 217604 kb
Host smart-a43e400b-fd46-4cbf-afcf-8f5a8f0884c5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104825882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3104825882
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1851603422
Short name T748
Test name
Test status
Simulation time 14040921587 ps
CPU time 37.15 seconds
Started Jul 14 05:53:42 PM PDT 24
Finished Jul 14 05:54:20 PM PDT 24
Peak memory 234828 kb
Host smart-6071d661-ebdc-4635-843a-d398e1acf168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851603422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1851603422
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1193223333
Short name T220
Test name
Test status
Simulation time 8535726993 ps
CPU time 12.51 seconds
Started Jul 14 05:53:41 PM PDT 24
Finished Jul 14 05:53:54 PM PDT 24
Peak memory 233944 kb
Host smart-11c18743-d1ed-4be4-ae40-4b115456bc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193223333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1193223333
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3187803461
Short name T678
Test name
Test status
Simulation time 2793969157 ps
CPU time 6.84 seconds
Started Jul 14 05:53:41 PM PDT 24
Finished Jul 14 05:53:49 PM PDT 24
Peak memory 222188 kb
Host smart-e0ab18d4-13bb-4862-b9bf-3f1213e2d387
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3187803461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3187803461
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2887892243
Short name T19
Test name
Test status
Simulation time 60277243 ps
CPU time 1.08 seconds
Started Jul 14 05:53:43 PM PDT 24
Finished Jul 14 05:53:44 PM PDT 24
Peak memory 216608 kb
Host smart-d1395383-5e4b-478f-85e6-083db92ca322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887892243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2887892243
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.691513793
Short name T736
Test name
Test status
Simulation time 3354674373 ps
CPU time 18.83 seconds
Started Jul 14 05:53:42 PM PDT 24
Finished Jul 14 05:54:01 PM PDT 24
Peak memory 217364 kb
Host smart-8d94d16e-b848-4d0e-9538-c5e4283337cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691513793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.691513793
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.361735413
Short name T881
Test name
Test status
Simulation time 1098412014 ps
CPU time 2.67 seconds
Started Jul 14 05:53:39 PM PDT 24
Finished Jul 14 05:53:42 PM PDT 24
Peak memory 217316 kb
Host smart-3033e614-33c5-4e45-b13b-e238e7fd72a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361735413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.361735413
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.46369264
Short name T320
Test name
Test status
Simulation time 703201557 ps
CPU time 2.64 seconds
Started Jul 14 05:53:42 PM PDT 24
Finished Jul 14 05:53:45 PM PDT 24
Peak memory 217280 kb
Host smart-3e55b4ec-4bc0-41a6-a924-21f094188e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46369264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.46369264
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2541939576
Short name T850
Test name
Test status
Simulation time 70994546 ps
CPU time 0.79 seconds
Started Jul 14 05:53:39 PM PDT 24
Finished Jul 14 05:53:40 PM PDT 24
Peak memory 206868 kb
Host smart-0f0bab30-e133-4376-bb4d-c31c55d506f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541939576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2541939576
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.203158700
Short name T414
Test name
Test status
Simulation time 7341116968 ps
CPU time 26.29 seconds
Started Jul 14 05:53:42 PM PDT 24
Finished Jul 14 05:54:09 PM PDT 24
Peak memory 250268 kb
Host smart-9a1842ac-b141-4a0e-abf9-b0ba3e109241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203158700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.203158700
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2122813694
Short name T645
Test name
Test status
Simulation time 23152243 ps
CPU time 0.69 seconds
Started Jul 14 05:51:16 PM PDT 24
Finished Jul 14 05:51:17 PM PDT 24
Peak memory 206332 kb
Host smart-0e79efca-b24c-46db-89b6-7c88468cadaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122813694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
122813694
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3236527977
Short name T116
Test name
Test status
Simulation time 141851972 ps
CPU time 4.66 seconds
Started Jul 14 05:51:18 PM PDT 24
Finished Jul 14 05:51:24 PM PDT 24
Peak memory 233764 kb
Host smart-25173f29-4de8-436b-b9b3-d6c615082192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236527977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3236527977
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2118761307
Short name T916
Test name
Test status
Simulation time 19296355 ps
CPU time 0.78 seconds
Started Jul 14 05:51:14 PM PDT 24
Finished Jul 14 05:51:15 PM PDT 24
Peak memory 207476 kb
Host smart-13e790a1-9e80-4de0-ac29-84dbe6c0b7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118761307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2118761307
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1178992701
Short name T432
Test name
Test status
Simulation time 14205651790 ps
CPU time 94.94 seconds
Started Jul 14 05:51:17 PM PDT 24
Finished Jul 14 05:52:53 PM PDT 24
Peak memory 241988 kb
Host smart-687c9a27-483a-413a-b51a-af902a67e7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178992701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1178992701
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2890398698
Short name T743
Test name
Test status
Simulation time 157151401735 ps
CPU time 290.29 seconds
Started Jul 14 05:51:16 PM PDT 24
Finished Jul 14 05:56:07 PM PDT 24
Peak memory 250536 kb
Host smart-44274458-8a26-41a1-9f2a-29b26b4e4aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890398698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2890398698
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2906024030
Short name T304
Test name
Test status
Simulation time 1193255998 ps
CPU time 4.74 seconds
Started Jul 14 05:51:14 PM PDT 24
Finished Jul 14 05:51:19 PM PDT 24
Peak memory 235772 kb
Host smart-b90723f4-8c88-4380-afb7-6e1871cfd48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906024030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2906024030
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1830238444
Short name T887
Test name
Test status
Simulation time 61339240142 ps
CPU time 61.77 seconds
Started Jul 14 05:51:17 PM PDT 24
Finished Jul 14 05:52:20 PM PDT 24
Peak memory 242056 kb
Host smart-7bfebb4c-6b09-4413-9949-77d237a2d5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830238444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1830238444
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1574773356
Short name T882
Test name
Test status
Simulation time 671695007 ps
CPU time 6.06 seconds
Started Jul 14 05:51:17 PM PDT 24
Finished Jul 14 05:51:24 PM PDT 24
Peak memory 233636 kb
Host smart-3bf3557a-ccfa-4cae-9e8c-5a165c5d97a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574773356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1574773356
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.210632337
Short name T493
Test name
Test status
Simulation time 3364825257 ps
CPU time 26.54 seconds
Started Jul 14 05:51:19 PM PDT 24
Finished Jul 14 05:51:46 PM PDT 24
Peak memory 225648 kb
Host smart-d81e7560-6a5c-4dee-a031-10e19d863961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210632337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.210632337
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2774041698
Short name T43
Test name
Test status
Simulation time 67376571 ps
CPU time 1.1 seconds
Started Jul 14 05:51:15 PM PDT 24
Finished Jul 14 05:51:16 PM PDT 24
Peak memory 217628 kb
Host smart-02f958fe-3eea-469c-955c-977f719a2d14
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774041698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2774041698
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3096366834
Short name T552
Test name
Test status
Simulation time 312785811 ps
CPU time 4.93 seconds
Started Jul 14 05:51:17 PM PDT 24
Finished Jul 14 05:51:23 PM PDT 24
Peak memory 225472 kb
Host smart-7b3ee6e7-fdec-4b81-a460-bcda6fef051d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096366834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3096366834
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1226411128
Short name T673
Test name
Test status
Simulation time 72031187 ps
CPU time 2.31 seconds
Started Jul 14 05:51:15 PM PDT 24
Finished Jul 14 05:51:18 PM PDT 24
Peak memory 224068 kb
Host smart-d077db07-45cd-4f5a-a32d-e973f1f57bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226411128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1226411128
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1999156411
Short name T394
Test name
Test status
Simulation time 488000244 ps
CPU time 5.13 seconds
Started Jul 14 05:51:16 PM PDT 24
Finished Jul 14 05:51:22 PM PDT 24
Peak memory 224092 kb
Host smart-7c550e8f-eda7-41c7-b318-5890d8624571
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1999156411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1999156411
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.119065125
Short name T73
Test name
Test status
Simulation time 439096370 ps
CPU time 1.24 seconds
Started Jul 14 05:51:18 PM PDT 24
Finished Jul 14 05:51:20 PM PDT 24
Peak memory 236776 kb
Host smart-76cd909a-15c9-48ef-85b0-822ac07b7ba0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119065125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.119065125
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1517073302
Short name T431
Test name
Test status
Simulation time 1668432253 ps
CPU time 17.98 seconds
Started Jul 14 05:51:15 PM PDT 24
Finished Jul 14 05:51:34 PM PDT 24
Peak memory 240156 kb
Host smart-c7a209f9-3d4e-4dbd-adab-bbbb597ca738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517073302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1517073302
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3557046146
Short name T567
Test name
Test status
Simulation time 72576443521 ps
CPU time 45.43 seconds
Started Jul 14 05:51:17 PM PDT 24
Finished Jul 14 05:52:04 PM PDT 24
Peak memory 217376 kb
Host smart-43d6afea-54e8-4e35-ae1a-cdd2af9bf5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557046146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3557046146
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1967094500
Short name T369
Test name
Test status
Simulation time 495364887 ps
CPU time 3.98 seconds
Started Jul 14 05:51:18 PM PDT 24
Finished Jul 14 05:51:23 PM PDT 24
Peak memory 217324 kb
Host smart-8d006cf3-5d6b-4cc7-b26e-682cacc80c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967094500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1967094500
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.453328691
Short name T970
Test name
Test status
Simulation time 262537243 ps
CPU time 5.16 seconds
Started Jul 14 05:51:16 PM PDT 24
Finished Jul 14 05:51:22 PM PDT 24
Peak memory 217388 kb
Host smart-ff5b0dcf-f8ad-41e5-8759-b7e1d19c4d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453328691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.453328691
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2034701281
Short name T590
Test name
Test status
Simulation time 94844184 ps
CPU time 0.68 seconds
Started Jul 14 05:51:15 PM PDT 24
Finished Jul 14 05:51:16 PM PDT 24
Peak memory 206432 kb
Host smart-ab67f48d-8024-47b6-bb31-a31096dda1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034701281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2034701281
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1310245728
Short name T495
Test name
Test status
Simulation time 5512603131 ps
CPU time 25.88 seconds
Started Jul 14 05:51:15 PM PDT 24
Finished Jul 14 05:51:42 PM PDT 24
Peak memory 250152 kb
Host smart-e6ad588d-ab26-4874-9c9d-077e65c004fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310245728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1310245728
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1432910641
Short name T979
Test name
Test status
Simulation time 13855610 ps
CPU time 0.75 seconds
Started Jul 14 05:53:55 PM PDT 24
Finished Jul 14 05:53:57 PM PDT 24
Peak memory 206364 kb
Host smart-42751fed-b888-46fd-9d45-8d20faf21f9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432910641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1432910641
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1299467895
Short name T802
Test name
Test status
Simulation time 30764309 ps
CPU time 2.19 seconds
Started Jul 14 05:53:48 PM PDT 24
Finished Jul 14 05:53:51 PM PDT 24
Peak memory 224604 kb
Host smart-4e8d3d5d-2286-4a0d-bb32-e01fcc858719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299467895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1299467895
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.4003080151
Short name T594
Test name
Test status
Simulation time 13545108 ps
CPU time 0.76 seconds
Started Jul 14 05:53:40 PM PDT 24
Finished Jul 14 05:53:42 PM PDT 24
Peak memory 207500 kb
Host smart-8934befb-3d98-4561-8360-9d952058eb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003080151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.4003080151
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.590859747
Short name T742
Test name
Test status
Simulation time 1588845117 ps
CPU time 8.64 seconds
Started Jul 14 05:53:45 PM PDT 24
Finished Jul 14 05:53:54 PM PDT 24
Peak memory 234776 kb
Host smart-2ed35cb1-465e-4ff8-9f55-f9e4488a9ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590859747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.590859747
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1800506113
Short name T420
Test name
Test status
Simulation time 6565931363 ps
CPU time 16.02 seconds
Started Jul 14 05:53:48 PM PDT 24
Finished Jul 14 05:54:05 PM PDT 24
Peak memory 225700 kb
Host smart-ddf4b237-81ac-4c2a-bb43-52dcf84ea179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800506113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1800506113
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1304765380
Short name T925
Test name
Test status
Simulation time 974180978 ps
CPU time 5.21 seconds
Started Jul 14 05:53:48 PM PDT 24
Finished Jul 14 05:53:54 PM PDT 24
Peak memory 225536 kb
Host smart-fa19fc22-a532-4b98-99a4-f893c4e89947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304765380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1304765380
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.717208066
Short name T425
Test name
Test status
Simulation time 1726236960 ps
CPU time 20.41 seconds
Started Jul 14 05:53:46 PM PDT 24
Finished Jul 14 05:54:07 PM PDT 24
Peak memory 240384 kb
Host smart-e88b618e-5dec-4bf0-89f4-7821ee88f184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717208066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.717208066
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1468565364
Short name T752
Test name
Test status
Simulation time 453671652 ps
CPU time 7.63 seconds
Started Jul 14 05:53:45 PM PDT 24
Finished Jul 14 05:53:53 PM PDT 24
Peak memory 233724 kb
Host smart-c36ca2a7-4b63-4ec2-a0d1-070c985afbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468565364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1468565364
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3076022596
Short name T836
Test name
Test status
Simulation time 3279328313 ps
CPU time 8.63 seconds
Started Jul 14 05:53:49 PM PDT 24
Finished Jul 14 05:53:58 PM PDT 24
Peak memory 233852 kb
Host smart-875fc802-7d73-4f7c-bb49-daecead21b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076022596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3076022596
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3231184617
Short name T144
Test name
Test status
Simulation time 330708715 ps
CPU time 5.49 seconds
Started Jul 14 05:53:47 PM PDT 24
Finished Jul 14 05:53:54 PM PDT 24
Peak memory 223420 kb
Host smart-b07cc88f-b074-4174-a1c3-e8825c5d817b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3231184617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3231184617
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.135440719
Short name T287
Test name
Test status
Simulation time 133554657220 ps
CPU time 344.96 seconds
Started Jul 14 05:53:56 PM PDT 24
Finished Jul 14 05:59:42 PM PDT 24
Peak memory 283752 kb
Host smart-b5f8ecc6-c7b6-45c5-85d6-bfd98af69025
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135440719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.135440719
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3343411555
Short name T415
Test name
Test status
Simulation time 9224852256 ps
CPU time 49.18 seconds
Started Jul 14 05:53:41 PM PDT 24
Finished Jul 14 05:54:31 PM PDT 24
Peak memory 217476 kb
Host smart-8e029250-a12e-49a7-a070-50b2987fccc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343411555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3343411555
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1744289283
Short name T810
Test name
Test status
Simulation time 8363897436 ps
CPU time 7.23 seconds
Started Jul 14 05:53:43 PM PDT 24
Finished Jul 14 05:53:51 PM PDT 24
Peak memory 217440 kb
Host smart-0cc288b9-97a8-449c-a20d-a5200579952c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744289283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1744289283
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1876360896
Short name T452
Test name
Test status
Simulation time 47888076 ps
CPU time 1.01 seconds
Started Jul 14 05:53:48 PM PDT 24
Finished Jul 14 05:53:50 PM PDT 24
Peak memory 208940 kb
Host smart-aa7a28f1-4bd1-4908-9ecf-d37a909ec9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876360896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1876360896
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2337676934
Short name T751
Test name
Test status
Simulation time 562471867 ps
CPU time 0.83 seconds
Started Jul 14 05:53:48 PM PDT 24
Finished Jul 14 05:53:49 PM PDT 24
Peak memory 207932 kb
Host smart-99e7d036-491d-433b-95a2-26a52c9c090b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337676934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2337676934
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2590966630
Short name T1017
Test name
Test status
Simulation time 1056590601 ps
CPU time 10.65 seconds
Started Jul 14 05:53:46 PM PDT 24
Finished Jul 14 05:53:57 PM PDT 24
Peak memory 253928 kb
Host smart-46880ebd-c3f2-4248-949d-fcc6149733a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590966630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2590966630
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1816437336
Short name T499
Test name
Test status
Simulation time 26637225 ps
CPU time 0.71 seconds
Started Jul 14 05:53:57 PM PDT 24
Finished Jul 14 05:53:59 PM PDT 24
Peak memory 205640 kb
Host smart-cad033fc-33e2-4a49-880b-1a43d4956404
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816437336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1816437336
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.17919388
Short name T1005
Test name
Test status
Simulation time 107468843 ps
CPU time 2.32 seconds
Started Jul 14 05:53:54 PM PDT 24
Finished Jul 14 05:53:57 PM PDT 24
Peak memory 233484 kb
Host smart-9c7a3509-5b44-408b-957b-3359ccdc8e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17919388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.17919388
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1713984242
Short name T360
Test name
Test status
Simulation time 32650318 ps
CPU time 0.79 seconds
Started Jul 14 05:53:55 PM PDT 24
Finished Jul 14 05:53:57 PM PDT 24
Peak memory 207736 kb
Host smart-887f7da4-95d7-4aee-8c98-fc6983c51571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713984242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1713984242
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1737953733
Short name T777
Test name
Test status
Simulation time 12969572614 ps
CPU time 133.23 seconds
Started Jul 14 05:53:52 PM PDT 24
Finished Jul 14 05:56:06 PM PDT 24
Peak memory 257656 kb
Host smart-a5c898cf-1088-4825-aba3-c6482685c737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737953733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1737953733
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3103275393
Short name T496
Test name
Test status
Simulation time 4359765403 ps
CPU time 50.64 seconds
Started Jul 14 05:53:54 PM PDT 24
Finished Jul 14 05:54:46 PM PDT 24
Peak memory 242388 kb
Host smart-ad59ffaf-5a92-4bb0-a389-7372fa4c0879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103275393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3103275393
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3359404031
Short name T447
Test name
Test status
Simulation time 285121541 ps
CPU time 2.71 seconds
Started Jul 14 05:53:55 PM PDT 24
Finished Jul 14 05:53:59 PM PDT 24
Peak memory 225776 kb
Host smart-6117daf1-6063-482c-845a-64686c19b226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359404031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3359404031
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2007150339
Short name T867
Test name
Test status
Simulation time 28661527390 ps
CPU time 49.65 seconds
Started Jul 14 05:53:57 PM PDT 24
Finished Jul 14 05:54:47 PM PDT 24
Peak memory 250132 kb
Host smart-3ec90ab6-11f1-4e39-8dd5-fb5ace827202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007150339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2007150339
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3947198630
Short name T858
Test name
Test status
Simulation time 900833432 ps
CPU time 12.82 seconds
Started Jul 14 05:53:55 PM PDT 24
Finished Jul 14 05:54:09 PM PDT 24
Peak memory 233764 kb
Host smart-a5e18b2a-8e10-4f90-aeb0-b659f4dc4192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947198630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3947198630
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1602951720
Short name T195
Test name
Test status
Simulation time 41728580903 ps
CPU time 104.8 seconds
Started Jul 14 05:53:56 PM PDT 24
Finished Jul 14 05:55:42 PM PDT 24
Peak memory 250244 kb
Host smart-629b4680-a2f0-4e89-882c-74b7002f79ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602951720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1602951720
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1626324027
Short name T556
Test name
Test status
Simulation time 117370289 ps
CPU time 2.52 seconds
Started Jul 14 05:53:52 PM PDT 24
Finished Jul 14 05:53:55 PM PDT 24
Peak memory 233360 kb
Host smart-2ec223fd-1c77-4d00-bbee-53a8ecbd64e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626324027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1626324027
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.485323702
Short name T38
Test name
Test status
Simulation time 1922492661 ps
CPU time 10.63 seconds
Started Jul 14 05:53:54 PM PDT 24
Finished Jul 14 05:54:06 PM PDT 24
Peak memory 241372 kb
Host smart-2a8633de-740c-4433-a0ac-1fac113c6bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485323702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.485323702
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2185495035
Short name T816
Test name
Test status
Simulation time 1012078731 ps
CPU time 4.69 seconds
Started Jul 14 05:53:56 PM PDT 24
Finished Jul 14 05:54:01 PM PDT 24
Peak memory 222880 kb
Host smart-e4715096-a7c7-4f18-a70b-5c34c2de86d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2185495035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2185495035
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2106276683
Short name T593
Test name
Test status
Simulation time 48589702 ps
CPU time 0.98 seconds
Started Jul 14 05:53:56 PM PDT 24
Finished Jul 14 05:53:58 PM PDT 24
Peak memory 207856 kb
Host smart-7c888e70-f2e9-41df-9114-8233d27e608a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106276683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2106276683
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3099987872
Short name T905
Test name
Test status
Simulation time 4648187625 ps
CPU time 21.8 seconds
Started Jul 14 05:53:56 PM PDT 24
Finished Jul 14 05:54:19 PM PDT 24
Peak memory 220040 kb
Host smart-b12e62ca-f300-4566-a85c-4485c693cb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099987872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3099987872
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.4259424712
Short name T401
Test name
Test status
Simulation time 5533387973 ps
CPU time 5.32 seconds
Started Jul 14 05:53:55 PM PDT 24
Finished Jul 14 05:54:02 PM PDT 24
Peak memory 217396 kb
Host smart-41e377ba-cd97-48e8-854e-d4c847472895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259424712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.4259424712
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1405423010
Short name T159
Test name
Test status
Simulation time 158733922 ps
CPU time 2.67 seconds
Started Jul 14 05:53:53 PM PDT 24
Finished Jul 14 05:53:58 PM PDT 24
Peak memory 217380 kb
Host smart-855f27f0-fb78-4089-999c-66b0888e1d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405423010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1405423010
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.427341737
Short name T538
Test name
Test status
Simulation time 66932841 ps
CPU time 0.73 seconds
Started Jul 14 05:53:56 PM PDT 24
Finished Jul 14 05:53:58 PM PDT 24
Peak memory 206820 kb
Host smart-8739b1f0-879d-4494-8695-ad78feeb6907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427341737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.427341737
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2484828874
Short name T199
Test name
Test status
Simulation time 3634810575 ps
CPU time 9.89 seconds
Started Jul 14 05:53:55 PM PDT 24
Finished Jul 14 05:54:06 PM PDT 24
Peak memory 225896 kb
Host smart-60b1dea7-8a1c-4306-b20e-75e9351ee34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484828874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2484828874
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.4180525566
Short name T993
Test name
Test status
Simulation time 36538932 ps
CPU time 0.71 seconds
Started Jul 14 05:54:09 PM PDT 24
Finished Jul 14 05:54:10 PM PDT 24
Peak memory 205792 kb
Host smart-86b5bfcc-3858-4604-a65e-fd61ddd7a643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180525566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
4180525566
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1075671370
Short name T390
Test name
Test status
Simulation time 362702538 ps
CPU time 3.7 seconds
Started Jul 14 05:54:03 PM PDT 24
Finished Jul 14 05:54:08 PM PDT 24
Peak memory 225576 kb
Host smart-651392da-57f2-4134-a4af-5cf15551ad29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075671370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1075671370
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1899079361
Short name T357
Test name
Test status
Simulation time 64526967 ps
CPU time 0.76 seconds
Started Jul 14 05:54:00 PM PDT 24
Finished Jul 14 05:54:02 PM PDT 24
Peak memory 207808 kb
Host smart-d5a8895e-5397-432f-aee6-e1b5c8a7ba53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899079361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1899079361
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3212537264
Short name T284
Test name
Test status
Simulation time 33063095860 ps
CPU time 61.1 seconds
Started Jul 14 05:54:07 PM PDT 24
Finished Jul 14 05:55:09 PM PDT 24
Peak memory 250232 kb
Host smart-66c1944c-55ed-47a2-88ae-0c3eef025ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212537264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3212537264
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.334320577
Short name T207
Test name
Test status
Simulation time 36866592543 ps
CPU time 366.17 seconds
Started Jul 14 05:54:06 PM PDT 24
Finished Jul 14 06:00:13 PM PDT 24
Peak memory 251608 kb
Host smart-9eb3ddc2-6144-4a64-a001-4c26fa35b0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334320577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.334320577
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.494506175
Short name T522
Test name
Test status
Simulation time 748931150 ps
CPU time 7.72 seconds
Started Jul 14 05:54:02 PM PDT 24
Finished Jul 14 05:54:10 PM PDT 24
Peak memory 234716 kb
Host smart-86b99fb7-985d-43a4-b2dc-56585aa85be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494506175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.494506175
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3170893256
Short name T349
Test name
Test status
Simulation time 32647578 ps
CPU time 0.73 seconds
Started Jul 14 05:54:07 PM PDT 24
Finished Jul 14 05:54:08 PM PDT 24
Peak memory 216880 kb
Host smart-73eb03f9-a1ac-4fcb-8230-a2c874bbc5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170893256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3170893256
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1780030096
Short name T625
Test name
Test status
Simulation time 555347799 ps
CPU time 8.53 seconds
Started Jul 14 05:54:03 PM PDT 24
Finished Jul 14 05:54:12 PM PDT 24
Peak memory 233772 kb
Host smart-aba3e575-f2b9-4365-9987-714a50b0facd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780030096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1780030096
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3270524717
Short name T812
Test name
Test status
Simulation time 3080464568 ps
CPU time 14.55 seconds
Started Jul 14 05:54:01 PM PDT 24
Finished Jul 14 05:54:16 PM PDT 24
Peak memory 235368 kb
Host smart-ba84a162-70e7-4b0d-920a-4a2db445220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270524717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3270524717
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2274008453
Short name T281
Test name
Test status
Simulation time 4465228357 ps
CPU time 11.13 seconds
Started Jul 14 05:54:03 PM PDT 24
Finished Jul 14 05:54:15 PM PDT 24
Peak memory 225704 kb
Host smart-53ab721b-aafa-4c69-af68-6e3f70bfa896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274008453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2274008453
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2642742061
Short name T129
Test name
Test status
Simulation time 253672925 ps
CPU time 3.23 seconds
Started Jul 14 05:54:02 PM PDT 24
Finished Jul 14 05:54:06 PM PDT 24
Peak memory 225596 kb
Host smart-5620f934-cbc1-48b8-b2c7-e84f6ca7a075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642742061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2642742061
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1813123977
Short name T686
Test name
Test status
Simulation time 85810280 ps
CPU time 3.67 seconds
Started Jul 14 05:54:09 PM PDT 24
Finished Jul 14 05:54:14 PM PDT 24
Peak memory 223868 kb
Host smart-a4520e73-8a63-4b29-a972-96a414616475
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1813123977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1813123977
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3473076409
Short name T854
Test name
Test status
Simulation time 28802532128 ps
CPU time 266.64 seconds
Started Jul 14 05:54:06 PM PDT 24
Finished Jul 14 05:58:33 PM PDT 24
Peak memory 250552 kb
Host smart-cdd1f711-e408-44e0-bc13-2c25cc2bf56b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473076409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3473076409
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2788199931
Short name T310
Test name
Test status
Simulation time 261223523 ps
CPU time 4.93 seconds
Started Jul 14 05:54:00 PM PDT 24
Finished Jul 14 05:54:06 PM PDT 24
Peak memory 217360 kb
Host smart-e2502751-31ba-48f3-a375-d161fad56536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788199931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2788199931
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4286663198
Short name T161
Test name
Test status
Simulation time 9535038529 ps
CPU time 14.11 seconds
Started Jul 14 05:54:00 PM PDT 24
Finished Jul 14 05:54:15 PM PDT 24
Peak memory 217416 kb
Host smart-3704b764-8720-4e3f-abdb-32fb0895d545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286663198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4286663198
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.565554868
Short name T474
Test name
Test status
Simulation time 62189511 ps
CPU time 3.25 seconds
Started Jul 14 05:54:00 PM PDT 24
Finished Jul 14 05:54:04 PM PDT 24
Peak memory 217288 kb
Host smart-a000e4ca-9eac-45c6-bbb1-c75133bf5d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565554868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.565554868
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2490886261
Short name T544
Test name
Test status
Simulation time 260006247 ps
CPU time 0.92 seconds
Started Jul 14 05:54:01 PM PDT 24
Finished Jul 14 05:54:03 PM PDT 24
Peak memory 206920 kb
Host smart-a0ccebb3-e26f-4419-859a-8ffef0dbfa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490886261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2490886261
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.922903116
Short name T162
Test name
Test status
Simulation time 327347602 ps
CPU time 2.22 seconds
Started Jul 14 05:54:10 PM PDT 24
Finished Jul 14 05:54:13 PM PDT 24
Peak memory 225528 kb
Host smart-6b0e1068-6b15-4e31-b0a6-797bc8f6a531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922903116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.922903116
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3659262016
Short name T857
Test name
Test status
Simulation time 12988109 ps
CPU time 0.73 seconds
Started Jul 14 05:54:16 PM PDT 24
Finished Jul 14 05:54:17 PM PDT 24
Peak memory 205788 kb
Host smart-fed520ad-c8dd-4778-99bb-a726dcb54d09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659262016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3659262016
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1813745500
Short name T378
Test name
Test status
Simulation time 1666686078 ps
CPU time 9.95 seconds
Started Jul 14 05:54:09 PM PDT 24
Finished Jul 14 05:54:20 PM PDT 24
Peak memory 233756 kb
Host smart-c0aa1445-a651-44b0-b888-46bd59c27d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813745500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1813745500
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.286174499
Short name T558
Test name
Test status
Simulation time 17968138 ps
CPU time 0.77 seconds
Started Jul 14 05:54:11 PM PDT 24
Finished Jul 14 05:54:12 PM PDT 24
Peak memory 207468 kb
Host smart-24d4daa9-7660-43ee-98a7-c455fe611f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286174499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.286174499
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.594006093
Short name T286
Test name
Test status
Simulation time 5760454528 ps
CPU time 86.83 seconds
Started Jul 14 05:54:09 PM PDT 24
Finished Jul 14 05:55:36 PM PDT 24
Peak memory 254780 kb
Host smart-8150d98c-d205-4016-80ff-5f60bea23a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594006093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.594006093
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1609952374
Short name T706
Test name
Test status
Simulation time 12986614024 ps
CPU time 128.87 seconds
Started Jul 14 05:54:08 PM PDT 24
Finished Jul 14 05:56:17 PM PDT 24
Peak memory 251332 kb
Host smart-7505768d-abc6-426d-a31b-580925a54af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609952374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1609952374
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1169475120
Short name T135
Test name
Test status
Simulation time 118336972267 ps
CPU time 314.99 seconds
Started Jul 14 05:54:13 PM PDT 24
Finished Jul 14 05:59:28 PM PDT 24
Peak memory 257144 kb
Host smart-b6257a81-1729-474d-b30b-4c24ea1317ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169475120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1169475120
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.962004692
Short name T652
Test name
Test status
Simulation time 1222722936 ps
CPU time 11.25 seconds
Started Jul 14 05:54:12 PM PDT 24
Finished Jul 14 05:54:23 PM PDT 24
Peak memory 236760 kb
Host smart-a235863a-fe09-4601-9891-2c5b082b6a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962004692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.962004692
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3960763775
Short name T938
Test name
Test status
Simulation time 296575916392 ps
CPU time 310.49 seconds
Started Jul 14 05:54:09 PM PDT 24
Finished Jul 14 05:59:20 PM PDT 24
Peak memory 272084 kb
Host smart-664c10d0-99a5-4441-87cd-6ef1cf532e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960763775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3960763775
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1202931323
Short name T641
Test name
Test status
Simulation time 1247880268 ps
CPU time 12.52 seconds
Started Jul 14 05:54:09 PM PDT 24
Finished Jul 14 05:54:22 PM PDT 24
Peak memory 233748 kb
Host smart-22e07580-1cd4-4bd0-9249-92c1fb9df94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202931323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1202931323
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2337728825
Short name T591
Test name
Test status
Simulation time 631798554 ps
CPU time 4.2 seconds
Started Jul 14 05:54:08 PM PDT 24
Finished Jul 14 05:54:13 PM PDT 24
Peak memory 234436 kb
Host smart-17fd4010-7c56-4e28-8b4e-9ab070d640f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337728825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2337728825
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2449845068
Short name T710
Test name
Test status
Simulation time 649147992 ps
CPU time 4.49 seconds
Started Jul 14 05:54:07 PM PDT 24
Finished Jul 14 05:54:12 PM PDT 24
Peak memory 225468 kb
Host smart-3084e6b8-7d22-417c-bfb1-8afbaa2521ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449845068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2449845068
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3473015318
Short name T534
Test name
Test status
Simulation time 626248100 ps
CPU time 8.18 seconds
Started Jul 14 05:54:07 PM PDT 24
Finished Jul 14 05:54:16 PM PDT 24
Peak memory 241432 kb
Host smart-359b87ed-31a7-489c-a11d-438e0fbf9b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473015318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3473015318
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1273904624
Short name T599
Test name
Test status
Simulation time 7604752280 ps
CPU time 8.2 seconds
Started Jul 14 05:54:08 PM PDT 24
Finished Jul 14 05:54:17 PM PDT 24
Peak memory 221576 kb
Host smart-105e8081-4222-4927-9edf-b01637f72825
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1273904624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1273904624
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1011923284
Short name T230
Test name
Test status
Simulation time 1007616390117 ps
CPU time 771.55 seconds
Started Jul 14 05:54:07 PM PDT 24
Finished Jul 14 06:06:59 PM PDT 24
Peak memory 266768 kb
Host smart-8b73d9de-5110-4c55-8b57-7e8a5b10a233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011923284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1011923284
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3334247873
Short name T468
Test name
Test status
Simulation time 17427912 ps
CPU time 0.72 seconds
Started Jul 14 05:54:08 PM PDT 24
Finished Jul 14 05:54:09 PM PDT 24
Peak memory 207164 kb
Host smart-20066cbb-4a93-4fb0-a6f2-64ebf680c670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334247873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3334247873
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2454587864
Short name T464
Test name
Test status
Simulation time 12321212 ps
CPU time 0.77 seconds
Started Jul 14 05:54:07 PM PDT 24
Finished Jul 14 05:54:09 PM PDT 24
Peak memory 206660 kb
Host smart-da17dc28-b7c1-4d61-92b4-5c82eb3b2bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454587864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2454587864
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1573683387
Short name T512
Test name
Test status
Simulation time 87994095 ps
CPU time 1.04 seconds
Started Jul 14 05:54:08 PM PDT 24
Finished Jul 14 05:54:10 PM PDT 24
Peak memory 208924 kb
Host smart-fe8886cf-3e1e-43e0-9546-8eba62f27ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573683387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1573683387
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1437196154
Short name T638
Test name
Test status
Simulation time 266973057 ps
CPU time 0.95 seconds
Started Jul 14 05:54:09 PM PDT 24
Finished Jul 14 05:54:10 PM PDT 24
Peak memory 206960 kb
Host smart-aada5259-58d4-49a6-8c51-e3538a7e6281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437196154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1437196154
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2622668902
Short name T738
Test name
Test status
Simulation time 111014243349 ps
CPU time 28.39 seconds
Started Jul 14 05:54:07 PM PDT 24
Finished Jul 14 05:54:36 PM PDT 24
Peak memory 236908 kb
Host smart-a60b0a66-e1fb-4add-bc2b-7d0a31f854af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622668902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2622668902
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1525154555
Short name T513
Test name
Test status
Simulation time 127151813 ps
CPU time 0.7 seconds
Started Jul 14 05:54:21 PM PDT 24
Finished Jul 14 05:54:22 PM PDT 24
Peak memory 206696 kb
Host smart-0cb92c22-1e8f-48c6-8302-b1cec8fad0a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525154555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1525154555
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.4275005638
Short name T268
Test name
Test status
Simulation time 167908494 ps
CPU time 2.71 seconds
Started Jul 14 05:54:15 PM PDT 24
Finished Jul 14 05:54:18 PM PDT 24
Peak memory 225512 kb
Host smart-33332f41-1711-4098-936a-b6a635e19a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275005638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.4275005638
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.551895179
Short name T651
Test name
Test status
Simulation time 20852131 ps
CPU time 0.79 seconds
Started Jul 14 05:54:16 PM PDT 24
Finished Jul 14 05:54:17 PM PDT 24
Peak memory 207740 kb
Host smart-038287f7-bd96-4720-94b2-e6955d6ba86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551895179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.551895179
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3523687772
Short name T640
Test name
Test status
Simulation time 35227238632 ps
CPU time 77.32 seconds
Started Jul 14 05:54:15 PM PDT 24
Finished Jul 14 05:55:33 PM PDT 24
Peak memory 241968 kb
Host smart-d1756fbd-8b61-4f8f-95be-ad77877d988c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523687772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3523687772
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1347312822
Short name T395
Test name
Test status
Simulation time 15431967241 ps
CPU time 41.79 seconds
Started Jul 14 05:54:21 PM PDT 24
Finished Jul 14 05:55:04 PM PDT 24
Peak memory 218820 kb
Host smart-3fefbb37-b2e0-48b8-9c6f-9a304cad557c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347312822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1347312822
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3534208085
Short name T382
Test name
Test status
Simulation time 5361431368 ps
CPU time 37.92 seconds
Started Jul 14 05:54:21 PM PDT 24
Finished Jul 14 05:54:59 PM PDT 24
Peak memory 237444 kb
Host smart-441c029f-1561-4db1-b2f4-9f71ce44f9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534208085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3534208085
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1618424643
Short name T427
Test name
Test status
Simulation time 8013983182 ps
CPU time 104.12 seconds
Started Jul 14 05:54:15 PM PDT 24
Finished Jul 14 05:55:59 PM PDT 24
Peak memory 242076 kb
Host smart-fefe8db3-7561-4d41-8838-173ea62a7d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618424643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1618424643
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3424579839
Short name T575
Test name
Test status
Simulation time 1740936343 ps
CPU time 10.16 seconds
Started Jul 14 05:54:16 PM PDT 24
Finished Jul 14 05:54:27 PM PDT 24
Peak memory 240560 kb
Host smart-e5b666c3-771b-4a54-97ea-4873c531de81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424579839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3424579839
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2743727075
Short name T445
Test name
Test status
Simulation time 3841685297 ps
CPU time 8.53 seconds
Started Jul 14 05:54:16 PM PDT 24
Finished Jul 14 05:54:25 PM PDT 24
Peak memory 225656 kb
Host smart-7760a88b-d18a-45db-bd8a-6c7e9c7f418b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743727075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2743727075
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2042773289
Short name T79
Test name
Test status
Simulation time 32750354 ps
CPU time 2.39 seconds
Started Jul 14 05:54:18 PM PDT 24
Finished Jul 14 05:54:21 PM PDT 24
Peak memory 233484 kb
Host smart-4a6e185c-4750-41a7-b5ab-8b68833fd552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042773289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2042773289
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3630991815
Short name T605
Test name
Test status
Simulation time 477579055 ps
CPU time 6.9 seconds
Started Jul 14 05:54:15 PM PDT 24
Finished Jul 14 05:54:22 PM PDT 24
Peak memory 241664 kb
Host smart-cb3124b0-1b79-4e11-b533-741c44318311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630991815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3630991815
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2631416480
Short name T860
Test name
Test status
Simulation time 17025216790 ps
CPU time 13.1 seconds
Started Jul 14 05:54:16 PM PDT 24
Finished Jul 14 05:54:30 PM PDT 24
Peak memory 234220 kb
Host smart-49022ee7-e704-4f6a-b924-408daa7fe66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631416480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2631416480
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1989150985
Short name T504
Test name
Test status
Simulation time 381842626 ps
CPU time 5.36 seconds
Started Jul 14 05:54:14 PM PDT 24
Finished Jul 14 05:54:20 PM PDT 24
Peak memory 224064 kb
Host smart-9a1018f3-a0df-4209-ad97-66227f22895c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1989150985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1989150985
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1945922264
Short name T784
Test name
Test status
Simulation time 15996763503 ps
CPU time 20.77 seconds
Started Jul 14 05:54:16 PM PDT 24
Finished Jul 14 05:54:37 PM PDT 24
Peak memory 217456 kb
Host smart-d7c39a0a-bc99-4d1a-a259-1bfa939a2f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945922264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1945922264
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2298278865
Short name T460
Test name
Test status
Simulation time 2989175099 ps
CPU time 3.27 seconds
Started Jul 14 05:54:16 PM PDT 24
Finished Jul 14 05:54:20 PM PDT 24
Peak memory 217456 kb
Host smart-70b67122-bd89-4555-8ba9-7678507de6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298278865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2298278865
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2488456008
Short name T323
Test name
Test status
Simulation time 211866402 ps
CPU time 1.11 seconds
Started Jul 14 05:54:16 PM PDT 24
Finished Jul 14 05:54:18 PM PDT 24
Peak memory 208768 kb
Host smart-2a110c0a-1fbd-4efd-8c38-aa4d979b5b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488456008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2488456008
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1400494548
Short name T327
Test name
Test status
Simulation time 44885757 ps
CPU time 0.69 seconds
Started Jul 14 05:54:15 PM PDT 24
Finished Jul 14 05:54:16 PM PDT 24
Peak memory 206476 kb
Host smart-04cb27f6-794b-482e-85a5-11287accaf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400494548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1400494548
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2846203393
Short name T215
Test name
Test status
Simulation time 69261590 ps
CPU time 2.43 seconds
Started Jul 14 05:54:16 PM PDT 24
Finished Jul 14 05:54:19 PM PDT 24
Peak memory 225448 kb
Host smart-353da678-9953-4b85-badb-cfb3a0701165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846203393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2846203393
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.278624989
Short name T583
Test name
Test status
Simulation time 72028889 ps
CPU time 0.73 seconds
Started Jul 14 05:54:28 PM PDT 24
Finished Jul 14 05:54:29 PM PDT 24
Peak memory 205708 kb
Host smart-4fcf411d-aefe-4b6b-8578-d4df7be846e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278624989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.278624989
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3300651369
Short name T834
Test name
Test status
Simulation time 385506766 ps
CPU time 3.54 seconds
Started Jul 14 05:54:39 PM PDT 24
Finished Jul 14 05:54:43 PM PDT 24
Peak memory 225452 kb
Host smart-e1fc0a49-5a52-4f5c-9fe4-dd3e9a4058bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300651369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3300651369
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3844782610
Short name T994
Test name
Test status
Simulation time 104480529 ps
CPU time 0.75 seconds
Started Jul 14 05:54:20 PM PDT 24
Finished Jul 14 05:54:21 PM PDT 24
Peak memory 207532 kb
Host smart-b49ea09b-ad60-49eb-a20b-31878090984a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844782610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3844782610
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1566267242
Short name T53
Test name
Test status
Simulation time 35128622570 ps
CPU time 296.93 seconds
Started Jul 14 05:54:38 PM PDT 24
Finished Jul 14 05:59:36 PM PDT 24
Peak memory 274460 kb
Host smart-904ec72e-d985-42e2-acee-564223091d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566267242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1566267242
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.4220906213
Short name T80
Test name
Test status
Simulation time 21467193451 ps
CPU time 245.55 seconds
Started Jul 14 05:54:30 PM PDT 24
Finished Jul 14 05:58:36 PM PDT 24
Peak memory 253640 kb
Host smart-65f6fa90-5160-4b99-888f-c9f1ded08d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220906213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.4220906213
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2459391326
Short name T849
Test name
Test status
Simulation time 421062517 ps
CPU time 3.11 seconds
Started Jul 14 05:54:30 PM PDT 24
Finished Jul 14 05:54:34 PM PDT 24
Peak memory 225528 kb
Host smart-835b7af8-fb00-4321-8c24-598bccf43f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459391326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2459391326
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2260409785
Short name T763
Test name
Test status
Simulation time 1495404616 ps
CPU time 18.6 seconds
Started Jul 14 05:54:27 PM PDT 24
Finished Jul 14 05:54:46 PM PDT 24
Peak memory 250116 kb
Host smart-9a324a83-b0b9-4d57-a3b0-db19dd2a09a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260409785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2260409785
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2186078352
Short name T482
Test name
Test status
Simulation time 61864544 ps
CPU time 2.31 seconds
Started Jul 14 05:54:22 PM PDT 24
Finished Jul 14 05:54:25 PM PDT 24
Peak memory 233456 kb
Host smart-3325ab77-11b1-44b7-b1dc-d377785c760e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186078352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2186078352
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3438286945
Short name T340
Test name
Test status
Simulation time 7969836778 ps
CPU time 23.95 seconds
Started Jul 14 05:54:21 PM PDT 24
Finished Jul 14 05:54:46 PM PDT 24
Peak memory 238396 kb
Host smart-f6e05e58-ec58-4dc5-9f74-44f4f34c694e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438286945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3438286945
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2456443298
Short name T674
Test name
Test status
Simulation time 4920753437 ps
CPU time 16.63 seconds
Started Jul 14 05:54:23 PM PDT 24
Finished Jul 14 05:54:40 PM PDT 24
Peak memory 233872 kb
Host smart-2d1d4ff4-0c29-4be1-a93c-c594b3293e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456443298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2456443298
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1061904569
Short name T924
Test name
Test status
Simulation time 1706780675 ps
CPU time 6.82 seconds
Started Jul 14 05:54:24 PM PDT 24
Finished Jul 14 05:54:31 PM PDT 24
Peak memory 225580 kb
Host smart-e00b90fc-7e02-464b-8876-aa84cffe27d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061904569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1061904569
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.530162132
Short name T446
Test name
Test status
Simulation time 77761292 ps
CPU time 3.48 seconds
Started Jul 14 05:54:30 PM PDT 24
Finished Jul 14 05:54:34 PM PDT 24
Peak memory 220308 kb
Host smart-3ed440a6-e785-4251-985b-e1d54e9ad614
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=530162132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.530162132
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2112535029
Short name T204
Test name
Test status
Simulation time 40400221376 ps
CPU time 358.86 seconds
Started Jul 14 05:54:30 PM PDT 24
Finished Jul 14 06:00:29 PM PDT 24
Peak memory 274724 kb
Host smart-968d6eca-7743-48ca-9d2d-9ffa4569bde9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112535029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2112535029
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.248042129
Short name T317
Test name
Test status
Simulation time 7783586344 ps
CPU time 23.95 seconds
Started Jul 14 05:54:23 PM PDT 24
Finished Jul 14 05:54:47 PM PDT 24
Peak memory 217448 kb
Host smart-3ff340f0-2e10-4893-88a5-68337258715e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248042129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.248042129
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3562637762
Short name T164
Test name
Test status
Simulation time 267445873 ps
CPU time 1.5 seconds
Started Jul 14 05:54:21 PM PDT 24
Finished Jul 14 05:54:23 PM PDT 24
Peak memory 208780 kb
Host smart-d0687c68-0326-4ef6-a573-00726cd950fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562637762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3562637762
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.639277995
Short name T635
Test name
Test status
Simulation time 215811807 ps
CPU time 1.71 seconds
Started Jul 14 05:54:23 PM PDT 24
Finished Jul 14 05:54:26 PM PDT 24
Peak memory 217320 kb
Host smart-e653e13d-f4a3-4ef1-b883-12818be36a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639277995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.639277995
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1143530466
Short name T896
Test name
Test status
Simulation time 87989710 ps
CPU time 0.83 seconds
Started Jul 14 05:54:23 PM PDT 24
Finished Jul 14 05:54:24 PM PDT 24
Peak memory 206964 kb
Host smart-9eb149ff-7f02-4d45-a27b-f09f0ad26e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143530466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1143530466
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1625791773
Short name T181
Test name
Test status
Simulation time 4652618954 ps
CPU time 6.89 seconds
Started Jul 14 05:54:31 PM PDT 24
Finished Jul 14 05:54:38 PM PDT 24
Peak memory 241012 kb
Host smart-101b7034-0919-49c3-be9c-5a62cd0fd694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625791773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1625791773
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3968040688
Short name T980
Test name
Test status
Simulation time 42973949 ps
CPU time 0.77 seconds
Started Jul 14 05:54:38 PM PDT 24
Finished Jul 14 05:54:40 PM PDT 24
Peak memory 206280 kb
Host smart-fd6274b7-cf31-43ae-bc75-fab650a56716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968040688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3968040688
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2193777037
Short name T957
Test name
Test status
Simulation time 33463010 ps
CPU time 2.52 seconds
Started Jul 14 05:54:40 PM PDT 24
Finished Jul 14 05:54:43 PM PDT 24
Peak memory 233664 kb
Host smart-2ac0113d-dff9-47f4-96ab-7d6e78aac223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193777037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2193777037
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2831086635
Short name T565
Test name
Test status
Simulation time 19841835 ps
CPU time 0.83 seconds
Started Jul 14 05:54:32 PM PDT 24
Finished Jul 14 05:54:33 PM PDT 24
Peak memory 207420 kb
Host smart-3da47bb3-8581-4763-a0d0-e5fdddbb5a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831086635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2831086635
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1349443210
Short name T698
Test name
Test status
Simulation time 7262869302 ps
CPU time 70.81 seconds
Started Jul 14 05:54:36 PM PDT 24
Finished Jul 14 05:55:47 PM PDT 24
Peak memory 242404 kb
Host smart-413e423e-ef09-4c30-995b-0cf021b50919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349443210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1349443210
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.4097263215
Short name T607
Test name
Test status
Simulation time 15819835677 ps
CPU time 61.76 seconds
Started Jul 14 05:54:36 PM PDT 24
Finished Jul 14 05:55:38 PM PDT 24
Peak memory 252348 kb
Host smart-91628e7d-a5d3-4c60-ae58-95e0454a1884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097263215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.4097263215
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2105738898
Short name T243
Test name
Test status
Simulation time 10251674559 ps
CPU time 77.9 seconds
Started Jul 14 05:54:38 PM PDT 24
Finished Jul 14 05:55:57 PM PDT 24
Peak memory 233952 kb
Host smart-090fe625-4b3b-4289-bad9-c218983dfc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105738898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2105738898
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3025945552
Short name T303
Test name
Test status
Simulation time 6165746570 ps
CPU time 22.91 seconds
Started Jul 14 05:54:38 PM PDT 24
Finished Jul 14 05:55:02 PM PDT 24
Peak memory 225676 kb
Host smart-29bcebdc-0aaa-484c-b2b4-53102be21701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025945552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3025945552
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.743043485
Short name T809
Test name
Test status
Simulation time 33745763643 ps
CPU time 69.66 seconds
Started Jul 14 05:54:37 PM PDT 24
Finished Jul 14 05:55:47 PM PDT 24
Peak memory 251124 kb
Host smart-a3173b6e-9e5b-4969-9981-30a0c6626ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743043485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.743043485
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4103062125
Short name T875
Test name
Test status
Simulation time 12677906577 ps
CPU time 33.58 seconds
Started Jul 14 05:54:37 PM PDT 24
Finished Jul 14 05:55:11 PM PDT 24
Peak memory 225696 kb
Host smart-7b21a275-4570-46b3-a322-f4dd6cc69dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103062125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4103062125
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.569104479
Short name T450
Test name
Test status
Simulation time 48589465581 ps
CPU time 119.77 seconds
Started Jul 14 05:54:37 PM PDT 24
Finished Jul 14 05:56:37 PM PDT 24
Peak memory 225644 kb
Host smart-328d79e0-6e59-4604-8df4-4dfbf51a5ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569104479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.569104479
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.19453782
Short name T50
Test name
Test status
Simulation time 15891980903 ps
CPU time 18.43 seconds
Started Jul 14 05:54:29 PM PDT 24
Finished Jul 14 05:54:48 PM PDT 24
Peak memory 233880 kb
Host smart-8c73d67e-20cf-457c-82e1-ab27455a9673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19453782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.19453782
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2978918684
Short name T213
Test name
Test status
Simulation time 858144984 ps
CPU time 9.06 seconds
Started Jul 14 05:54:29 PM PDT 24
Finished Jul 14 05:54:38 PM PDT 24
Peak memory 234664 kb
Host smart-e90673e3-f5f9-42de-b72c-4ca44330f2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978918684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2978918684
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1252360111
Short name T365
Test name
Test status
Simulation time 476570804 ps
CPU time 6.84 seconds
Started Jul 14 05:54:42 PM PDT 24
Finished Jul 14 05:54:49 PM PDT 24
Peak memory 223304 kb
Host smart-112500fa-91c1-4b4a-8b39-bfbe77c1379f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1252360111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1252360111
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.4079599114
Short name T741
Test name
Test status
Simulation time 4315059420 ps
CPU time 13.06 seconds
Started Jul 14 05:54:29 PM PDT 24
Finished Jul 14 05:54:42 PM PDT 24
Peak memory 217524 kb
Host smart-2a43d789-b762-4aeb-b171-a14cb38ba41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079599114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.4079599114
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3921688955
Short name T437
Test name
Test status
Simulation time 10600799862 ps
CPU time 18.39 seconds
Started Jul 14 05:54:29 PM PDT 24
Finished Jul 14 05:54:47 PM PDT 24
Peak memory 217488 kb
Host smart-46bcc0c5-f0fc-4ff2-a0db-881e7d994a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921688955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3921688955
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3343201860
Short name T726
Test name
Test status
Simulation time 480962801 ps
CPU time 4.17 seconds
Started Jul 14 05:54:28 PM PDT 24
Finished Jul 14 05:54:33 PM PDT 24
Peak memory 217376 kb
Host smart-e7ff1de4-3a20-4218-a6b9-dd57d6fbb093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343201860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3343201860
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.4133684426
Short name T485
Test name
Test status
Simulation time 28356227 ps
CPU time 0.76 seconds
Started Jul 14 05:54:30 PM PDT 24
Finished Jul 14 05:54:32 PM PDT 24
Peak memory 206808 kb
Host smart-1064326f-e5fc-4677-abec-3b78caf864fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133684426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4133684426
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1791305442
Short name T214
Test name
Test status
Simulation time 1549489590 ps
CPU time 5.35 seconds
Started Jul 14 05:54:38 PM PDT 24
Finished Jul 14 05:54:44 PM PDT 24
Peak memory 233768 kb
Host smart-f1444e98-5f9e-4305-956d-3fbc029ef836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791305442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1791305442
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1299784580
Short name T746
Test name
Test status
Simulation time 102164739 ps
CPU time 0.78 seconds
Started Jul 14 05:54:45 PM PDT 24
Finished Jul 14 05:54:46 PM PDT 24
Peak memory 205784 kb
Host smart-d897f000-9e80-4b16-bd2a-5a8b4cae65af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299784580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1299784580
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2135443916
Short name T943
Test name
Test status
Simulation time 263322167 ps
CPU time 3.49 seconds
Started Jul 14 05:54:42 PM PDT 24
Finished Jul 14 05:54:46 PM PDT 24
Peak memory 233736 kb
Host smart-1b95f38e-0884-42ff-bad0-d94980b49c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135443916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2135443916
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3831073533
Short name T463
Test name
Test status
Simulation time 20345825 ps
CPU time 0.83 seconds
Started Jul 14 05:54:37 PM PDT 24
Finished Jul 14 05:54:38 PM PDT 24
Peak memory 207796 kb
Host smart-beb2f87f-9e70-425f-b1bb-8cc028904dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831073533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3831073533
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.628431657
Short name T712
Test name
Test status
Simulation time 89767752474 ps
CPU time 158.69 seconds
Started Jul 14 05:54:43 PM PDT 24
Finished Jul 14 05:57:22 PM PDT 24
Peak memory 250168 kb
Host smart-08f970e3-5426-45cb-8ec8-86a491648065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628431657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.628431657
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3699167076
Short name T39
Test name
Test status
Simulation time 146685861425 ps
CPU time 307.84 seconds
Started Jul 14 05:54:43 PM PDT 24
Finished Jul 14 05:59:52 PM PDT 24
Peak memory 270532 kb
Host smart-bcd6713d-b442-474b-a86f-1ddaae57aa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699167076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3699167076
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.885815238
Short name T255
Test name
Test status
Simulation time 8787450985 ps
CPU time 111.96 seconds
Started Jul 14 05:54:42 PM PDT 24
Finished Jul 14 05:56:34 PM PDT 24
Peak memory 255296 kb
Host smart-e0e55e4b-0c4f-46df-94f7-b98ac66e05bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885815238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.885815238
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4157183433
Short name T363
Test name
Test status
Simulation time 957040454 ps
CPU time 11.16 seconds
Started Jul 14 05:54:40 PM PDT 24
Finished Jul 14 05:54:52 PM PDT 24
Peak memory 225500 kb
Host smart-040f062f-5fbd-4d39-9885-87ff27857534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157183433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4157183433
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1387988484
Short name T668
Test name
Test status
Simulation time 778383897 ps
CPU time 8.14 seconds
Started Jul 14 05:54:38 PM PDT 24
Finished Jul 14 05:54:47 PM PDT 24
Peak memory 240544 kb
Host smart-dfacebf2-bf88-49f4-a4f3-7887a2fd43f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387988484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1387988484
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2847179702
Short name T229
Test name
Test status
Simulation time 115487250 ps
CPU time 2.84 seconds
Started Jul 14 05:54:37 PM PDT 24
Finished Jul 14 05:54:40 PM PDT 24
Peak memory 225508 kb
Host smart-42249212-4bb9-435f-a6ea-2655c8e94ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847179702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2847179702
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1266381984
Short name T187
Test name
Test status
Simulation time 102899230 ps
CPU time 2.93 seconds
Started Jul 14 05:54:38 PM PDT 24
Finished Jul 14 05:54:42 PM PDT 24
Peak memory 233728 kb
Host smart-169210a8-57f6-49c6-9973-2940a2b15cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266381984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1266381984
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.136452940
Short name T143
Test name
Test status
Simulation time 9098845854 ps
CPU time 21.51 seconds
Started Jul 14 05:54:38 PM PDT 24
Finished Jul 14 05:55:00 PM PDT 24
Peak memory 220304 kb
Host smart-3e79a709-8ed9-4ce4-abaa-21190206c718
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=136452940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.136452940
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2951022300
Short name T16
Test name
Test status
Simulation time 4415441009 ps
CPU time 19.93 seconds
Started Jul 14 05:54:46 PM PDT 24
Finished Jul 14 05:55:07 PM PDT 24
Peak memory 226012 kb
Host smart-564262d7-617e-4ce0-806f-7d84799d28a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951022300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2951022300
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3469892565
Short name T839
Test name
Test status
Simulation time 31523901126 ps
CPU time 40.14 seconds
Started Jul 14 05:54:38 PM PDT 24
Finished Jul 14 05:55:19 PM PDT 24
Peak memory 217432 kb
Host smart-cf255dd2-ebb9-4267-9e47-bb6402e441bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469892565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3469892565
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4124559025
Short name T822
Test name
Test status
Simulation time 252362828 ps
CPU time 2.5 seconds
Started Jul 14 05:54:38 PM PDT 24
Finished Jul 14 05:54:42 PM PDT 24
Peak memory 217320 kb
Host smart-57a7f956-8ac9-415c-9a3a-28d3d0dedb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124559025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4124559025
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1618749089
Short name T828
Test name
Test status
Simulation time 32919284 ps
CPU time 1.15 seconds
Started Jul 14 05:54:38 PM PDT 24
Finished Jul 14 05:54:40 PM PDT 24
Peak memory 208872 kb
Host smart-38913867-9351-4b31-928a-6ef318932178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618749089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1618749089
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2588965559
Short name T1014
Test name
Test status
Simulation time 56804729 ps
CPU time 0.83 seconds
Started Jul 14 05:54:37 PM PDT 24
Finished Jul 14 05:54:38 PM PDT 24
Peak memory 206900 kb
Host smart-6db79314-335f-4414-95c5-529fb872058a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588965559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2588965559
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3848059051
Short name T971
Test name
Test status
Simulation time 17546818120 ps
CPU time 15.57 seconds
Started Jul 14 05:54:37 PM PDT 24
Finished Jul 14 05:54:53 PM PDT 24
Peak memory 225632 kb
Host smart-441f444b-c5ae-4d5b-9bd2-b0ce51c2e84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848059051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3848059051
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1385995850
Short name T459
Test name
Test status
Simulation time 15125075 ps
CPU time 0.74 seconds
Started Jul 14 05:54:50 PM PDT 24
Finished Jul 14 05:54:52 PM PDT 24
Peak memory 206704 kb
Host smart-1ddddad0-fbbd-4435-a3af-da539e8d3aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385995850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1385995850
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3009054143
Short name T722
Test name
Test status
Simulation time 44743013 ps
CPU time 0.75 seconds
Started Jul 14 05:54:46 PM PDT 24
Finished Jul 14 05:54:48 PM PDT 24
Peak memory 206448 kb
Host smart-e5766b91-8822-4ae8-846b-150532e1c692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009054143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3009054143
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.518141332
Short name T197
Test name
Test status
Simulation time 3319051670 ps
CPU time 20.51 seconds
Started Jul 14 05:54:44 PM PDT 24
Finished Jul 14 05:55:05 PM PDT 24
Peak memory 250264 kb
Host smart-27b7d97d-3717-468c-a38c-22c023802456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518141332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.518141332
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2186963294
Short name T489
Test name
Test status
Simulation time 83171926924 ps
CPU time 142.12 seconds
Started Jul 14 05:54:43 PM PDT 24
Finished Jul 14 05:57:06 PM PDT 24
Peak memory 261928 kb
Host smart-e29c135b-0bdf-4410-8881-d301198323d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186963294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2186963294
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2204013542
Short name T942
Test name
Test status
Simulation time 6722484169 ps
CPU time 47.56 seconds
Started Jul 14 05:54:54 PM PDT 24
Finished Jul 14 05:55:42 PM PDT 24
Peak memory 250272 kb
Host smart-bcd5bf5f-153b-43bd-8460-0005dbb8915e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204013542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2204013542
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1355411579
Short name T711
Test name
Test status
Simulation time 971752568 ps
CPU time 6.69 seconds
Started Jul 14 05:54:45 PM PDT 24
Finished Jul 14 05:54:53 PM PDT 24
Peak memory 225748 kb
Host smart-863ae513-097c-49e1-a030-5308204d303b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355411579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1355411579
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1527853941
Short name T93
Test name
Test status
Simulation time 47458806048 ps
CPU time 186.44 seconds
Started Jul 14 05:54:45 PM PDT 24
Finished Jul 14 05:57:53 PM PDT 24
Peak memory 250284 kb
Host smart-47e1007f-7bd0-4024-bc54-13fe0002958e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527853941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1527853941
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3525427422
Short name T221
Test name
Test status
Simulation time 1968433752 ps
CPU time 12.39 seconds
Started Jul 14 05:54:43 PM PDT 24
Finished Jul 14 05:54:56 PM PDT 24
Peak memory 225428 kb
Host smart-06fe0b11-18ad-492a-9e3e-053ae17abcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525427422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3525427422
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3342360837
Short name T400
Test name
Test status
Simulation time 121279457 ps
CPU time 2.83 seconds
Started Jul 14 05:54:44 PM PDT 24
Finished Jul 14 05:54:47 PM PDT 24
Peak memory 225480 kb
Host smart-a2c5cbb8-777b-4b7c-bfdb-8e83177b3a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342360837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3342360837
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1894910655
Short name T376
Test name
Test status
Simulation time 1318167482 ps
CPU time 4.26 seconds
Started Jul 14 05:54:46 PM PDT 24
Finished Jul 14 05:54:51 PM PDT 24
Peak memory 225504 kb
Host smart-a4f71fe6-805f-4220-aa52-8f913bc219a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894910655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1894910655
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2183294872
Short name T723
Test name
Test status
Simulation time 1619790569 ps
CPU time 9.09 seconds
Started Jul 14 05:54:47 PM PDT 24
Finished Jul 14 05:54:57 PM PDT 24
Peak memory 233648 kb
Host smart-422c72e0-4567-43c5-b31f-81cba823a825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183294872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2183294872
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1635329408
Short name T138
Test name
Test status
Simulation time 1248152064 ps
CPU time 13.32 seconds
Started Jul 14 05:54:45 PM PDT 24
Finished Jul 14 05:54:59 PM PDT 24
Peak memory 223272 kb
Host smart-54718162-37e2-4818-a45a-c2299ad38bc2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1635329408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1635329408
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.399554482
Short name T258
Test name
Test status
Simulation time 77399925523 ps
CPU time 407.97 seconds
Started Jul 14 05:54:52 PM PDT 24
Finished Jul 14 06:01:40 PM PDT 24
Peak memory 266524 kb
Host smart-18763f42-092d-4e90-af11-714895632d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399554482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.399554482
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.951911312
Short name T779
Test name
Test status
Simulation time 983076025 ps
CPU time 9.04 seconds
Started Jul 14 05:54:46 PM PDT 24
Finished Jul 14 05:54:56 PM PDT 24
Peak memory 217408 kb
Host smart-a067c382-40a6-46c4-9cbf-c1c8f46d7e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951911312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.951911312
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2626377209
Short name T353
Test name
Test status
Simulation time 27692576 ps
CPU time 0.82 seconds
Started Jul 14 05:54:45 PM PDT 24
Finished Jul 14 05:54:46 PM PDT 24
Peak memory 206612 kb
Host smart-16ce864b-3923-4df2-88eb-8b0303418aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626377209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2626377209
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1778571094
Short name T624
Test name
Test status
Simulation time 1131229978 ps
CPU time 2.77 seconds
Started Jul 14 05:54:46 PM PDT 24
Finished Jul 14 05:54:50 PM PDT 24
Peak memory 217368 kb
Host smart-1280df07-d250-4c58-8939-d8941cfa9c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778571094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1778571094
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.295523839
Short name T67
Test name
Test status
Simulation time 33034538 ps
CPU time 0.76 seconds
Started Jul 14 05:54:47 PM PDT 24
Finished Jul 14 05:54:48 PM PDT 24
Peak memory 206908 kb
Host smart-119ccb5b-9348-4af2-bbb5-66baaefd005c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295523839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.295523839
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3693932572
Short name T919
Test name
Test status
Simulation time 30813440145 ps
CPU time 26.38 seconds
Started Jul 14 05:54:46 PM PDT 24
Finished Jul 14 05:55:13 PM PDT 24
Peak memory 233836 kb
Host smart-4afa55fd-788b-4501-8bb8-cbf0bddac266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693932572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3693932572
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2474496346
Short name T440
Test name
Test status
Simulation time 16008960 ps
CPU time 0.72 seconds
Started Jul 14 05:55:01 PM PDT 24
Finished Jul 14 05:55:02 PM PDT 24
Peak memory 206248 kb
Host smart-1d0efcd2-5fff-45ff-83f0-2155e82b655e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474496346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2474496346
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2167543784
Short name T251
Test name
Test status
Simulation time 82922139 ps
CPU time 2.43 seconds
Started Jul 14 05:54:54 PM PDT 24
Finished Jul 14 05:54:57 PM PDT 24
Peak memory 225564 kb
Host smart-11358600-a224-4d3a-965c-2ca2444f18b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167543784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2167543784
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.99709075
Short name T830
Test name
Test status
Simulation time 15918978 ps
CPU time 0.81 seconds
Started Jul 14 05:54:52 PM PDT 24
Finished Jul 14 05:54:54 PM PDT 24
Peak memory 207492 kb
Host smart-3c46c539-52a0-4030-91c8-7458df2bbc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99709075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.99709075
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2692994268
Short name T657
Test name
Test status
Simulation time 224067622609 ps
CPU time 235.24 seconds
Started Jul 14 05:55:00 PM PDT 24
Finished Jul 14 05:58:55 PM PDT 24
Peak memory 250296 kb
Host smart-e784d0b5-a069-48d2-b949-5494f80f5fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692994268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2692994268
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2983757171
Short name T732
Test name
Test status
Simulation time 23896475863 ps
CPU time 54.48 seconds
Started Jul 14 05:55:01 PM PDT 24
Finished Jul 14 05:55:56 PM PDT 24
Peak memory 250732 kb
Host smart-e42380f1-65ed-4d67-8f8e-9425ce01984e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983757171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2983757171
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2538786887
Short name T318
Test name
Test status
Simulation time 74728442354 ps
CPU time 220.56 seconds
Started Jul 14 05:54:58 PM PDT 24
Finished Jul 14 05:58:39 PM PDT 24
Peak memory 255860 kb
Host smart-503d9899-1f2b-40cc-93f6-4012a17633f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538786887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2538786887
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3535834696
Short name T299
Test name
Test status
Simulation time 153482917 ps
CPU time 5.88 seconds
Started Jul 14 05:54:53 PM PDT 24
Finished Jul 14 05:54:59 PM PDT 24
Peak memory 225548 kb
Host smart-7a5967da-b79f-44ce-9a4e-6d411ea89c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535834696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3535834696
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2159896569
Short name T510
Test name
Test status
Simulation time 82796590693 ps
CPU time 158.53 seconds
Started Jul 14 05:54:58 PM PDT 24
Finished Jul 14 05:57:37 PM PDT 24
Peak memory 250220 kb
Host smart-a291a468-efba-481a-8780-d1393c2b54f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159896569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2159896569
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.186049249
Short name T92
Test name
Test status
Simulation time 352131822 ps
CPU time 5.21 seconds
Started Jul 14 05:54:49 PM PDT 24
Finished Jul 14 05:54:55 PM PDT 24
Peak memory 225544 kb
Host smart-ba90b1b9-4069-4a3e-8287-cb71982d10d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186049249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.186049249
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.201398257
Short name T23
Test name
Test status
Simulation time 5127571374 ps
CPU time 39.9 seconds
Started Jul 14 05:54:52 PM PDT 24
Finished Jul 14 05:55:33 PM PDT 24
Peak memory 225672 kb
Host smart-3b4475de-162e-44cd-982d-01877ed7497c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201398257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.201398257
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1533168487
Short name T621
Test name
Test status
Simulation time 8428420147 ps
CPU time 12.4 seconds
Started Jul 14 05:54:51 PM PDT 24
Finished Jul 14 05:55:04 PM PDT 24
Peak memory 233884 kb
Host smart-5a7f877d-9d72-4c3a-9b07-b18bcf562a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533168487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1533168487
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.127221306
Short name T259
Test name
Test status
Simulation time 211275211 ps
CPU time 3.45 seconds
Started Jul 14 05:54:52 PM PDT 24
Finished Jul 14 05:54:56 PM PDT 24
Peak memory 233700 kb
Host smart-2f0352f7-11fb-453e-9831-f60c37d5ea89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127221306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.127221306
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2453970512
Short name T419
Test name
Test status
Simulation time 1070085537 ps
CPU time 4.01 seconds
Started Jul 14 05:55:01 PM PDT 24
Finished Jul 14 05:55:06 PM PDT 24
Peak memory 223620 kb
Host smart-a0757e36-675c-4bf6-81c8-af771cd766e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2453970512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2453970512
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3779865167
Short name T1004
Test name
Test status
Simulation time 448399441732 ps
CPU time 638.01 seconds
Started Jul 14 05:55:00 PM PDT 24
Finished Jul 14 06:05:39 PM PDT 24
Peak memory 270980 kb
Host smart-954cd855-480f-41a5-9b24-32a4a14ddbbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779865167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3779865167
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1768528023
Short name T632
Test name
Test status
Simulation time 877101533 ps
CPU time 3.65 seconds
Started Jul 14 05:54:54 PM PDT 24
Finished Jul 14 05:54:58 PM PDT 24
Peak memory 219276 kb
Host smart-99aae164-035b-4bee-947c-05faa0b3fb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768528023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1768528023
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2942674286
Short name T1027
Test name
Test status
Simulation time 2614656899 ps
CPU time 8.5 seconds
Started Jul 14 05:54:53 PM PDT 24
Finished Jul 14 05:55:02 PM PDT 24
Peak memory 217400 kb
Host smart-dd2e8d06-e357-4c85-a787-2887286dcfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942674286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2942674286
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3222730246
Short name T397
Test name
Test status
Simulation time 71816930 ps
CPU time 0.82 seconds
Started Jul 14 05:54:53 PM PDT 24
Finished Jul 14 05:54:54 PM PDT 24
Peak memory 206956 kb
Host smart-b7c1c302-145a-4bea-8702-84f4729d3ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222730246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3222730246
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.617192166
Short name T90
Test name
Test status
Simulation time 193158079 ps
CPU time 0.93 seconds
Started Jul 14 05:54:50 PM PDT 24
Finished Jul 14 05:54:52 PM PDT 24
Peak memory 206860 kb
Host smart-f9b9825d-1b67-4340-b5f2-14d8d3929779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617192166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.617192166
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3610175110
Short name T225
Test name
Test status
Simulation time 30639747271 ps
CPU time 17.62 seconds
Started Jul 14 05:54:49 PM PDT 24
Finished Jul 14 05:55:07 PM PDT 24
Peak memory 233880 kb
Host smart-ae648937-8bdc-46ae-a24d-29520f1371e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610175110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3610175110
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1472501943
Short name T915
Test name
Test status
Simulation time 14315634 ps
CPU time 0.73 seconds
Started Jul 14 05:51:27 PM PDT 24
Finished Jul 14 05:51:29 PM PDT 24
Peak memory 206268 kb
Host smart-c5359afa-7f0a-4b9c-a204-8474262fede2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472501943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
472501943
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1077102669
Short name T630
Test name
Test status
Simulation time 221878922 ps
CPU time 2.42 seconds
Started Jul 14 05:51:23 PM PDT 24
Finished Jul 14 05:51:26 PM PDT 24
Peak memory 233768 kb
Host smart-e84197ea-d128-4132-b03d-9f3922f8d6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077102669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1077102669
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2977516383
Short name T628
Test name
Test status
Simulation time 15865958 ps
CPU time 0.76 seconds
Started Jul 14 05:51:18 PM PDT 24
Finished Jul 14 05:51:19 PM PDT 24
Peak memory 207532 kb
Host smart-69f87534-617b-439a-b727-cbbd961f82f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977516383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2977516383
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2138045506
Short name T412
Test name
Test status
Simulation time 272817822653 ps
CPU time 109.37 seconds
Started Jul 14 05:51:24 PM PDT 24
Finished Jul 14 05:53:14 PM PDT 24
Peak memory 250332 kb
Host smart-f36cb3ae-4e72-45c8-a0e1-a74df8b3ddf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138045506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2138045506
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.906832795
Short name T776
Test name
Test status
Simulation time 4478803219 ps
CPU time 66.21 seconds
Started Jul 14 05:51:27 PM PDT 24
Finished Jul 14 05:52:34 PM PDT 24
Peak memory 238420 kb
Host smart-c7cb18ae-787c-45e1-8320-ab455b4cdbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906832795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.906832795
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2642197001
Short name T279
Test name
Test status
Simulation time 119055083042 ps
CPU time 443.69 seconds
Started Jul 14 05:51:24 PM PDT 24
Finished Jul 14 05:58:49 PM PDT 24
Peak memory 241796 kb
Host smart-be4dfc19-5269-40d8-aff0-c95b78fe38cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642197001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2642197001
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1129170708
Short name T740
Test name
Test status
Simulation time 185945113 ps
CPU time 3.36 seconds
Started Jul 14 05:51:26 PM PDT 24
Finished Jul 14 05:51:30 PM PDT 24
Peak memory 233672 kb
Host smart-20e9088b-1b46-4b28-b210-1b92675e46d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129170708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1129170708
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1967582828
Short name T192
Test name
Test status
Simulation time 16281102612 ps
CPU time 60.33 seconds
Started Jul 14 05:51:26 PM PDT 24
Finished Jul 14 05:52:27 PM PDT 24
Peak memory 266408 kb
Host smart-2f5d52ab-3871-4cc0-b461-338b6fc160ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967582828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1967582828
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1384302169
Short name T895
Test name
Test status
Simulation time 1202788404 ps
CPU time 15.39 seconds
Started Jul 14 05:51:21 PM PDT 24
Finished Jul 14 05:51:37 PM PDT 24
Peak memory 225532 kb
Host smart-a744d66d-975a-4ba8-8b9d-631932809395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384302169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1384302169
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2331469261
Short name T483
Test name
Test status
Simulation time 1187048703 ps
CPU time 15.72 seconds
Started Jul 14 05:51:22 PM PDT 24
Finished Jul 14 05:51:39 PM PDT 24
Peak memory 233696 kb
Host smart-db23147d-5bd1-4f0f-998f-05dc813d94d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331469261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2331469261
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2957761104
Short name T697
Test name
Test status
Simulation time 17472953 ps
CPU time 0.99 seconds
Started Jul 14 05:51:17 PM PDT 24
Finished Jul 14 05:51:19 PM PDT 24
Peak memory 218860 kb
Host smart-b7ba7028-de5d-4e96-9d58-f02bff1ea42a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957761104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2957761104
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.4179003585
Short name T618
Test name
Test status
Simulation time 12729943621 ps
CPU time 25.47 seconds
Started Jul 14 05:51:25 PM PDT 24
Finished Jul 14 05:51:51 PM PDT 24
Peak memory 233848 kb
Host smart-d880a257-bb6e-4f9e-b14e-03c40e8797bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179003585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.4179003585
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3342935684
Short name T224
Test name
Test status
Simulation time 478936462 ps
CPU time 3.91 seconds
Started Jul 14 05:51:25 PM PDT 24
Finished Jul 14 05:51:30 PM PDT 24
Peak memory 233752 kb
Host smart-11450dd4-ca9e-4753-9875-8f6cf0fee95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342935684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3342935684
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1834816427
Short name T826
Test name
Test status
Simulation time 307461695 ps
CPU time 4.34 seconds
Started Jul 14 05:51:22 PM PDT 24
Finished Jul 14 05:51:27 PM PDT 24
Peak memory 224176 kb
Host smart-d0b72e0a-2024-40be-8b75-86426be15f02
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1834816427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1834816427
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3850795670
Short name T75
Test name
Test status
Simulation time 54386389 ps
CPU time 1.1 seconds
Started Jul 14 05:51:24 PM PDT 24
Finished Jul 14 05:51:26 PM PDT 24
Peak memory 236376 kb
Host smart-f6334045-e123-447c-9ac3-78e48d39c9f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850795670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3850795670
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2280671709
Short name T557
Test name
Test status
Simulation time 50442148481 ps
CPU time 241.22 seconds
Started Jul 14 05:51:24 PM PDT 24
Finished Jul 14 05:55:26 PM PDT 24
Peak memory 252876 kb
Host smart-8ffd8393-7446-49a2-9719-749424f466cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280671709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2280671709
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3806866172
Short name T35
Test name
Test status
Simulation time 3835272330 ps
CPU time 14.82 seconds
Started Jul 14 05:51:16 PM PDT 24
Finished Jul 14 05:51:32 PM PDT 24
Peak memory 217676 kb
Host smart-b67659ee-0aeb-4096-911e-01184b0beb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806866172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3806866172
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2955222231
Short name T444
Test name
Test status
Simulation time 21262108900 ps
CPU time 15.84 seconds
Started Jul 14 05:51:15 PM PDT 24
Finished Jul 14 05:51:32 PM PDT 24
Peak memory 217400 kb
Host smart-e7a69f30-faf2-4439-9fcc-507dbc531139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955222231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2955222231
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1604066809
Short name T589
Test name
Test status
Simulation time 621377346 ps
CPU time 2.56 seconds
Started Jul 14 05:51:23 PM PDT 24
Finished Jul 14 05:51:26 PM PDT 24
Peak memory 217280 kb
Host smart-2dd20cff-3137-4334-8359-1326cec29afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604066809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1604066809
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.4235464086
Short name T1
Test name
Test status
Simulation time 92186280 ps
CPU time 1.03 seconds
Started Jul 14 05:51:21 PM PDT 24
Finished Jul 14 05:51:22 PM PDT 24
Peak memory 207960 kb
Host smart-52586483-44e4-4364-9835-8348a19ef3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235464086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.4235464086
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2038251208
Short name T603
Test name
Test status
Simulation time 758517977 ps
CPU time 5.93 seconds
Started Jul 14 05:51:22 PM PDT 24
Finished Jul 14 05:51:29 PM PDT 24
Peak memory 225564 kb
Host smart-8e53efea-7d48-4d73-805e-895e07308255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038251208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2038251208
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3626858539
Short name T473
Test name
Test status
Simulation time 34631229 ps
CPU time 0.74 seconds
Started Jul 14 05:55:08 PM PDT 24
Finished Jul 14 05:55:09 PM PDT 24
Peak memory 205788 kb
Host smart-dbe8a63f-15ce-4a17-a5f6-feac83cd4653
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626858539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3626858539
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2706444699
Short name T442
Test name
Test status
Simulation time 7461081597 ps
CPU time 32.51 seconds
Started Jul 14 05:54:59 PM PDT 24
Finished Jul 14 05:55:32 PM PDT 24
Peak memory 225612 kb
Host smart-3413fe68-ea28-4c3c-a501-574d7ba70684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706444699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2706444699
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3066439632
Short name T862
Test name
Test status
Simulation time 127824745 ps
CPU time 0.83 seconds
Started Jul 14 05:55:02 PM PDT 24
Finished Jul 14 05:55:03 PM PDT 24
Peak memory 207832 kb
Host smart-b880cc71-53ff-4ce9-bdc7-12b6f22314e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066439632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3066439632
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3563794816
Short name T78
Test name
Test status
Simulation time 240460264777 ps
CPU time 390.74 seconds
Started Jul 14 05:54:59 PM PDT 24
Finished Jul 14 06:01:30 PM PDT 24
Peak memory 250284 kb
Host smart-6cccec90-b0be-4d5a-835e-bb0a7f528cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563794816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3563794816
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.491829369
Short name T768
Test name
Test status
Simulation time 2575129777 ps
CPU time 28.21 seconds
Started Jul 14 05:55:05 PM PDT 24
Finished Jul 14 05:55:33 PM PDT 24
Peak memory 249624 kb
Host smart-deffb523-5d14-4644-9380-52ee30a07c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491829369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.491829369
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2262730022
Short name T525
Test name
Test status
Simulation time 17127964456 ps
CPU time 75.6 seconds
Started Jul 14 05:55:07 PM PDT 24
Finished Jul 14 05:56:23 PM PDT 24
Peak memory 237420 kb
Host smart-ff7d48b9-4702-4330-ae56-9e3061ac48b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262730022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2262730022
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3976781126
Short name T933
Test name
Test status
Simulation time 3858157526 ps
CPU time 28.94 seconds
Started Jul 14 05:55:01 PM PDT 24
Finished Jul 14 05:55:30 PM PDT 24
Peak memory 233848 kb
Host smart-89cdc18b-c0ef-43af-8810-b16acc096715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976781126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3976781126
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.46288394
Short name T715
Test name
Test status
Simulation time 18511934292 ps
CPU time 48.8 seconds
Started Jul 14 05:55:02 PM PDT 24
Finished Jul 14 05:55:51 PM PDT 24
Peak memory 252536 kb
Host smart-cedce070-d93c-4931-92d3-cb9f586b72bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46288394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.46288394
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2642870332
Short name T976
Test name
Test status
Simulation time 4774926657 ps
CPU time 11.25 seconds
Started Jul 14 05:55:00 PM PDT 24
Finished Jul 14 05:55:12 PM PDT 24
Peak memory 229364 kb
Host smart-198b1242-812b-4f6d-8739-4ecce27ec4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642870332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2642870332
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3266348864
Short name T498
Test name
Test status
Simulation time 121500156 ps
CPU time 2.17 seconds
Started Jul 14 05:55:00 PM PDT 24
Finished Jul 14 05:55:03 PM PDT 24
Peak memory 225556 kb
Host smart-1626f47b-8b63-4106-9ada-f647fc0050a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266348864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3266348864
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1497569530
Short name T200
Test name
Test status
Simulation time 1278105262 ps
CPU time 5.38 seconds
Started Jul 14 05:55:00 PM PDT 24
Finished Jul 14 05:55:06 PM PDT 24
Peak memory 233684 kb
Host smart-4f9117d5-151c-49d2-a295-1b2c24469a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497569530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1497569530
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1702983849
Short name T433
Test name
Test status
Simulation time 742670070 ps
CPU time 4.67 seconds
Started Jul 14 05:55:01 PM PDT 24
Finished Jul 14 05:55:07 PM PDT 24
Peak memory 233788 kb
Host smart-820470e6-0a6f-44a2-9721-19385e311527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702983849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1702983849
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3058004999
Short name T1016
Test name
Test status
Simulation time 4039740223 ps
CPU time 11.76 seconds
Started Jul 14 05:54:57 PM PDT 24
Finished Jul 14 05:55:09 PM PDT 24
Peak memory 224328 kb
Host smart-075471a3-9c10-48c3-90d2-a1b134fa8a6d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3058004999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3058004999
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1134233731
Short name T157
Test name
Test status
Simulation time 38416635132 ps
CPU time 49.89 seconds
Started Jul 14 05:55:08 PM PDT 24
Finished Jul 14 05:55:58 PM PDT 24
Peak memory 237140 kb
Host smart-0a3ae351-aaf0-4a22-86d5-37ec8667eed8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134233731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1134233731
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1939442633
Short name T648
Test name
Test status
Simulation time 608476776 ps
CPU time 6.04 seconds
Started Jul 14 05:55:01 PM PDT 24
Finished Jul 14 05:55:08 PM PDT 24
Peak memory 217404 kb
Host smart-9fa1c938-fb08-4c4d-9b04-e466cbc5496c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939442633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1939442633
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2927066081
Short name T959
Test name
Test status
Simulation time 6455711392 ps
CPU time 6 seconds
Started Jul 14 05:55:00 PM PDT 24
Finished Jul 14 05:55:06 PM PDT 24
Peak memory 217372 kb
Host smart-b2e0633d-bfcf-420a-af2f-e1a1717aeae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927066081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2927066081
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4154045304
Short name T714
Test name
Test status
Simulation time 500033850 ps
CPU time 2.37 seconds
Started Jul 14 05:54:58 PM PDT 24
Finished Jul 14 05:55:01 PM PDT 24
Peak memory 217244 kb
Host smart-8f0fdef7-df0a-408d-a8ad-4666616419a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154045304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4154045304
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1367345591
Short name T814
Test name
Test status
Simulation time 28563154 ps
CPU time 0.86 seconds
Started Jul 14 05:55:00 PM PDT 24
Finished Jul 14 05:55:02 PM PDT 24
Peak memory 206936 kb
Host smart-e61942db-9605-4c6a-bd2b-716e95b6526f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367345591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1367345591
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3527774669
Short name T515
Test name
Test status
Simulation time 437253510 ps
CPU time 3.87 seconds
Started Jul 14 05:55:00 PM PDT 24
Finished Jul 14 05:55:05 PM PDT 24
Peak memory 225548 kb
Host smart-4a330952-ab48-4040-8aab-3ab3c2e75c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527774669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3527774669
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1510934156
Short name T475
Test name
Test status
Simulation time 29457705 ps
CPU time 0.71 seconds
Started Jul 14 05:55:14 PM PDT 24
Finished Jul 14 05:55:15 PM PDT 24
Peak memory 205696 kb
Host smart-f1413160-114b-4f22-8e9c-9c5625a352fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510934156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1510934156
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2951147117
Short name T462
Test name
Test status
Simulation time 624246462 ps
CPU time 5.5 seconds
Started Jul 14 05:55:13 PM PDT 24
Finished Jul 14 05:55:19 PM PDT 24
Peak memory 225488 kb
Host smart-e39eaae8-9cd6-4637-be7e-e116e406e1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951147117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2951147117
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2037176094
Short name T831
Test name
Test status
Simulation time 64468042 ps
CPU time 0.77 seconds
Started Jul 14 05:55:06 PM PDT 24
Finished Jul 14 05:55:07 PM PDT 24
Peak memory 206812 kb
Host smart-54fd3ccd-4d47-498f-b28e-8fa930e0450a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037176094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2037176094
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1157934901
Short name T789
Test name
Test status
Simulation time 59574167953 ps
CPU time 229.87 seconds
Started Jul 14 05:55:15 PM PDT 24
Finished Jul 14 05:59:05 PM PDT 24
Peak memory 253404 kb
Host smart-4f1757bf-8632-4194-8ed8-5fb2f797942c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157934901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1157934901
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.683304931
Short name T410
Test name
Test status
Simulation time 3384542744 ps
CPU time 50.7 seconds
Started Jul 14 05:55:13 PM PDT 24
Finished Jul 14 05:56:04 PM PDT 24
Peak memory 254408 kb
Host smart-78e945fd-8f87-4331-b796-7a0fd1df0eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683304931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.683304931
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1098298679
Short name T368
Test name
Test status
Simulation time 9462843965 ps
CPU time 47.78 seconds
Started Jul 14 05:55:16 PM PDT 24
Finished Jul 14 05:56:04 PM PDT 24
Peak memory 258412 kb
Host smart-4cd3d94b-0bc9-4db0-8360-cac17df661b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098298679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1098298679
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1667642724
Short name T139
Test name
Test status
Simulation time 738478980 ps
CPU time 10.66 seconds
Started Jul 14 05:55:13 PM PDT 24
Finished Jul 14 05:55:25 PM PDT 24
Peak memory 241924 kb
Host smart-8bcc88ad-b1d4-4d0c-917c-c40d7153eb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667642724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1667642724
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2052512283
Short name T886
Test name
Test status
Simulation time 23233627098 ps
CPU time 86.9 seconds
Started Jul 14 05:55:16 PM PDT 24
Finished Jul 14 05:56:43 PM PDT 24
Peak memory 244096 kb
Host smart-b6bdbd0d-5dc4-4188-99a7-8949c3c028ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052512283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2052512283
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1658481430
Short name T249
Test name
Test status
Simulation time 93132043 ps
CPU time 4.06 seconds
Started Jul 14 05:55:08 PM PDT 24
Finished Jul 14 05:55:12 PM PDT 24
Peak memory 233736 kb
Host smart-e24ef43a-bf11-4192-8c86-7ff0d2f4cffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658481430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1658481430
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.209877857
Short name T772
Test name
Test status
Simulation time 1316602179 ps
CPU time 6.8 seconds
Started Jul 14 05:55:15 PM PDT 24
Finished Jul 14 05:55:22 PM PDT 24
Peak memory 233592 kb
Host smart-cafe2831-21d8-4709-9774-faf39f771571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209877857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.209877857
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3528993484
Short name T291
Test name
Test status
Simulation time 4396260327 ps
CPU time 2.97 seconds
Started Jul 14 05:55:06 PM PDT 24
Finished Jul 14 05:55:09 PM PDT 24
Peak memory 233752 kb
Host smart-4441fdc5-5273-48f0-9563-b2a899e0ffad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528993484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3528993484
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.923966134
Short name T529
Test name
Test status
Simulation time 1318334618 ps
CPU time 9.53 seconds
Started Jul 14 05:55:08 PM PDT 24
Finished Jul 14 05:55:18 PM PDT 24
Peak memory 233724 kb
Host smart-aeb0dff2-8d6d-41c8-970c-8d1dbb146de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923966134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.923966134
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4282816804
Short name T935
Test name
Test status
Simulation time 2545908062 ps
CPU time 11.37 seconds
Started Jul 14 05:55:13 PM PDT 24
Finished Jul 14 05:55:25 PM PDT 24
Peak memory 220544 kb
Host smart-52fc748a-f6a5-4f9a-ae12-0d7c609fd0d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4282816804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4282816804
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1839703965
Short name T219
Test name
Test status
Simulation time 49306125532 ps
CPU time 100.88 seconds
Started Jul 14 05:55:13 PM PDT 24
Finished Jul 14 05:56:55 PM PDT 24
Peak memory 242012 kb
Host smart-e221f8fa-6caa-49e8-b3d3-37fe42a0dd1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839703965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1839703965
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2828835082
Short name T316
Test name
Test status
Simulation time 3201895388 ps
CPU time 17.9 seconds
Started Jul 14 05:55:07 PM PDT 24
Finished Jul 14 05:55:25 PM PDT 24
Peak memory 217440 kb
Host smart-2c85a3e1-74cf-45ba-bf75-5d7243047a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828835082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2828835082
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1329032513
Short name T685
Test name
Test status
Simulation time 28567815 ps
CPU time 0.76 seconds
Started Jul 14 05:55:08 PM PDT 24
Finished Jul 14 05:55:09 PM PDT 24
Peak memory 206524 kb
Host smart-e0ae3457-0e66-42f5-a68f-e7b5bfe79975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329032513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1329032513
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.561456667
Short name T539
Test name
Test status
Simulation time 70605912 ps
CPU time 1.03 seconds
Started Jul 14 05:55:04 PM PDT 24
Finished Jul 14 05:55:05 PM PDT 24
Peak memory 208540 kb
Host smart-830d68c5-6bff-408f-8c70-22a01e16933e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561456667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.561456667
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2557305156
Short name T912
Test name
Test status
Simulation time 12474927 ps
CPU time 0.72 seconds
Started Jul 14 05:55:06 PM PDT 24
Finished Jul 14 05:55:08 PM PDT 24
Peak memory 206960 kb
Host smart-e847e6ff-2acf-40fe-b42c-d093f8d4e914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557305156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2557305156
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.439495357
Short name T198
Test name
Test status
Simulation time 1090635640 ps
CPU time 7.92 seconds
Started Jul 14 05:55:14 PM PDT 24
Finished Jul 14 05:55:22 PM PDT 24
Peak memory 241972 kb
Host smart-8691cded-bf62-4cee-a636-bc706cb5b65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439495357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.439495357
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.189422924
Short name T406
Test name
Test status
Simulation time 52419734 ps
CPU time 0.72 seconds
Started Jul 14 05:55:20 PM PDT 24
Finished Jul 14 05:55:22 PM PDT 24
Peak memory 206360 kb
Host smart-f0b43dbe-0c1a-4c8f-af3a-6baed2827cb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189422924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.189422924
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1300654058
Short name T727
Test name
Test status
Simulation time 123747857 ps
CPU time 3.52 seconds
Started Jul 14 05:55:23 PM PDT 24
Finished Jul 14 05:55:27 PM PDT 24
Peak memory 233748 kb
Host smart-da914be1-835c-41ac-adbd-69a83d85587a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300654058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1300654058
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2703737084
Short name T385
Test name
Test status
Simulation time 48800109 ps
CPU time 0.75 seconds
Started Jul 14 05:55:17 PM PDT 24
Finished Jul 14 05:55:18 PM PDT 24
Peak memory 206824 kb
Host smart-1a952295-93fb-4a37-9d23-06c6a0ac8c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703737084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2703737084
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2799236622
Short name T568
Test name
Test status
Simulation time 18037663920 ps
CPU time 30.58 seconds
Started Jul 14 05:55:20 PM PDT 24
Finished Jul 14 05:55:51 PM PDT 24
Peak memory 256596 kb
Host smart-ce6595ce-949f-40b8-b611-e77f52323011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799236622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2799236622
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1161898518
Short name T664
Test name
Test status
Simulation time 9547348927 ps
CPU time 92.29 seconds
Started Jul 14 05:55:22 PM PDT 24
Finished Jul 14 05:56:56 PM PDT 24
Peak memory 256756 kb
Host smart-267824ee-c2b2-4b88-9f00-8f0c66b02f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161898518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1161898518
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2163290754
Short name T481
Test name
Test status
Simulation time 176633598838 ps
CPU time 168.27 seconds
Started Jul 14 05:55:24 PM PDT 24
Finished Jul 14 05:58:13 PM PDT 24
Peak memory 255420 kb
Host smart-fd949b34-c8db-4d14-8207-123d124dc2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163290754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2163290754
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3085904606
Short name T300
Test name
Test status
Simulation time 1638464310 ps
CPU time 15.78 seconds
Started Jul 14 05:55:20 PM PDT 24
Finished Jul 14 05:55:36 PM PDT 24
Peak memory 250140 kb
Host smart-3aa0c539-b413-4163-9364-79de39b418c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085904606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3085904606
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1865859315
Short name T453
Test name
Test status
Simulation time 4195990664 ps
CPU time 21.34 seconds
Started Jul 14 05:55:23 PM PDT 24
Finished Jul 14 05:55:45 PM PDT 24
Peak memory 238024 kb
Host smart-22edfcf3-a479-4cdd-a926-2a49effd0206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865859315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1865859315
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.542218456
Short name T665
Test name
Test status
Simulation time 49612759 ps
CPU time 2.37 seconds
Started Jul 14 05:55:22 PM PDT 24
Finished Jul 14 05:55:25 PM PDT 24
Peak memory 225568 kb
Host smart-6a8ff3a2-8260-4cd9-bab4-5c9cb12deda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542218456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.542218456
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.61039890
Short name T77
Test name
Test status
Simulation time 10540769892 ps
CPU time 88.48 seconds
Started Jul 14 05:55:21 PM PDT 24
Finished Jul 14 05:56:50 PM PDT 24
Peak memory 240016 kb
Host smart-999d7575-22f8-416c-b5e6-51a8e44cc61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61039890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.61039890
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.156983076
Short name T941
Test name
Test status
Simulation time 1637773125 ps
CPU time 4.81 seconds
Started Jul 14 05:55:22 PM PDT 24
Finished Jul 14 05:55:28 PM PDT 24
Peak memory 233664 kb
Host smart-62ae617f-1d6a-4e82-b2a8-a0be5f2f7ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156983076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.156983076
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2976190241
Short name T588
Test name
Test status
Simulation time 39921988170 ps
CPU time 15.22 seconds
Started Jul 14 05:55:23 PM PDT 24
Finished Jul 14 05:55:39 PM PDT 24
Peak memory 233852 kb
Host smart-23488127-faf0-411f-b405-7725b2ecade9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976190241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2976190241
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2171978069
Short name T989
Test name
Test status
Simulation time 640324418 ps
CPU time 8.07 seconds
Started Jul 14 05:55:23 PM PDT 24
Finished Jul 14 05:55:32 PM PDT 24
Peak memory 221828 kb
Host smart-78c9bcfe-2caf-40b9-98db-1ab263cb7193
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2171978069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2171978069
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.425890370
Short name T480
Test name
Test status
Simulation time 1739600012 ps
CPU time 4.4 seconds
Started Jul 14 05:55:13 PM PDT 24
Finished Jul 14 05:55:17 PM PDT 24
Peak memory 217440 kb
Host smart-837e119b-e272-4717-9154-2525874ce75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425890370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.425890370
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.142772086
Short name T550
Test name
Test status
Simulation time 172933371 ps
CPU time 1.58 seconds
Started Jul 14 05:55:15 PM PDT 24
Finished Jul 14 05:55:17 PM PDT 24
Peak memory 208908 kb
Host smart-d36a5252-9064-4f39-8d96-5e2c0a9a0dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142772086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.142772086
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2891973898
Short name T27
Test name
Test status
Simulation time 72329421 ps
CPU time 1.88 seconds
Started Jul 14 05:55:20 PM PDT 24
Finished Jul 14 05:55:22 PM PDT 24
Peak memory 217328 kb
Host smart-ecd2f092-2dfa-4007-8eb5-a90cdb81a118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891973898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2891973898
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1860381714
Short name T370
Test name
Test status
Simulation time 78718925 ps
CPU time 0.73 seconds
Started Jul 14 05:55:20 PM PDT 24
Finished Jul 14 05:55:21 PM PDT 24
Peak memory 206920 kb
Host smart-6a8d7bee-1178-451d-90fc-6ccef641e9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860381714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1860381714
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.762268603
Short name T997
Test name
Test status
Simulation time 1579741863 ps
CPU time 4.28 seconds
Started Jul 14 05:55:22 PM PDT 24
Finished Jul 14 05:55:27 PM PDT 24
Peak memory 225504 kb
Host smart-bdb47eb5-e661-47c2-a58a-19f37bf3a8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762268603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.762268603
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1340784222
Short name T614
Test name
Test status
Simulation time 12384583 ps
CPU time 0.73 seconds
Started Jul 14 05:55:34 PM PDT 24
Finished Jul 14 05:55:35 PM PDT 24
Peak memory 206364 kb
Host smart-5cacec29-7449-4c91-b847-1f59d980acab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340784222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1340784222
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.896356912
Short name T1001
Test name
Test status
Simulation time 2530605674 ps
CPU time 10.31 seconds
Started Jul 14 05:55:27 PM PDT 24
Finished Jul 14 05:55:38 PM PDT 24
Peak memory 233852 kb
Host smart-f9b98cc8-0508-41f6-a34b-ec2aa525bb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896356912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.896356912
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.215919977
Short name T701
Test name
Test status
Simulation time 13340965 ps
CPU time 0.78 seconds
Started Jul 14 05:55:22 PM PDT 24
Finished Jul 14 05:55:24 PM PDT 24
Peak memory 207476 kb
Host smart-da4c9b60-1556-4e09-8feb-4eb92e4e270b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215919977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.215919977
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1671961442
Short name T546
Test name
Test status
Simulation time 26742695874 ps
CPU time 75.73 seconds
Started Jul 14 05:55:29 PM PDT 24
Finished Jul 14 05:56:45 PM PDT 24
Peak memory 253576 kb
Host smart-3d82c6df-c2fa-4058-bf6b-0f6aa60e0c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671961442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1671961442
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1565284980
Short name T322
Test name
Test status
Simulation time 56114649676 ps
CPU time 288.49 seconds
Started Jul 14 05:55:29 PM PDT 24
Finished Jul 14 06:00:18 PM PDT 24
Peak memory 254124 kb
Host smart-741b1522-0406-47dd-91a2-c10d38034a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565284980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1565284980
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2817566496
Short name T707
Test name
Test status
Simulation time 3999781971 ps
CPU time 22.1 seconds
Started Jul 14 05:55:29 PM PDT 24
Finished Jul 14 05:55:51 PM PDT 24
Peak memory 241432 kb
Host smart-58dd703a-dcc9-48ab-b98f-e2ac5c7a6ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817566496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2817566496
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.29000204
Short name T885
Test name
Test status
Simulation time 6039691001 ps
CPU time 12.78 seconds
Started Jul 14 05:55:29 PM PDT 24
Finished Jul 14 05:55:42 PM PDT 24
Peak memory 225700 kb
Host smart-cc523c22-5025-4699-9902-212b9b89e101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29000204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.29000204
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1670009988
Short name T178
Test name
Test status
Simulation time 55151550902 ps
CPU time 233.69 seconds
Started Jul 14 05:55:29 PM PDT 24
Finished Jul 14 05:59:23 PM PDT 24
Peak memory 250484 kb
Host smart-086d0b36-a06b-4412-b873-693654f298c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670009988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1670009988
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3965773221
Short name T3
Test name
Test status
Simulation time 5122675584 ps
CPU time 5.38 seconds
Started Jul 14 05:55:34 PM PDT 24
Finished Jul 14 05:55:40 PM PDT 24
Peak memory 225640 kb
Host smart-95fcfc20-6d34-476f-a0da-f5f825ce4e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965773221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3965773221
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.893333638
Short name T396
Test name
Test status
Simulation time 733662925 ps
CPU time 8.05 seconds
Started Jul 14 05:55:30 PM PDT 24
Finished Jul 14 05:55:39 PM PDT 24
Peak memory 233764 kb
Host smart-b8867bed-eaed-475b-a077-11486932b20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893333638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.893333638
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1879741552
Short name T253
Test name
Test status
Simulation time 60466395 ps
CPU time 2.33 seconds
Started Jul 14 05:55:31 PM PDT 24
Finished Jul 14 05:55:34 PM PDT 24
Peak memory 225472 kb
Host smart-7421c395-d447-4aaa-ae52-b3a6623869e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879741552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1879741552
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1632822469
Short name T331
Test name
Test status
Simulation time 354103915 ps
CPU time 2.31 seconds
Started Jul 14 05:55:31 PM PDT 24
Finished Jul 14 05:55:34 PM PDT 24
Peak memory 224932 kb
Host smart-8ab7b243-4e4b-454a-abef-a5ec24014365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632822469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1632822469
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1684562175
Short name T949
Test name
Test status
Simulation time 591239453 ps
CPU time 6.88 seconds
Started Jul 14 05:55:31 PM PDT 24
Finished Jul 14 05:55:39 PM PDT 24
Peak memory 219828 kb
Host smart-ff81878c-55eb-4714-ba73-a45dbf208925
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1684562175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1684562175
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3654420131
Short name T21
Test name
Test status
Simulation time 14424424263 ps
CPU time 118.25 seconds
Started Jul 14 05:55:28 PM PDT 24
Finished Jul 14 05:57:27 PM PDT 24
Peak memory 242216 kb
Host smart-c9760883-d8a8-40ed-a208-7c0fb2e7b7d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654420131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3654420131
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3200129959
Short name T769
Test name
Test status
Simulation time 5255332731 ps
CPU time 29.39 seconds
Started Jul 14 05:55:23 PM PDT 24
Finished Jul 14 05:55:53 PM PDT 24
Peak memory 217556 kb
Host smart-ef2514cf-3268-4080-9244-964ae8f5c15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200129959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3200129959
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.152310895
Short name T597
Test name
Test status
Simulation time 1966854742 ps
CPU time 3.4 seconds
Started Jul 14 05:55:19 PM PDT 24
Finished Jul 14 05:55:23 PM PDT 24
Peak memory 217312 kb
Host smart-4430c195-16b6-406b-8a32-95d9034bdbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152310895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.152310895
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1389486417
Short name T332
Test name
Test status
Simulation time 13590862 ps
CPU time 0.71 seconds
Started Jul 14 05:55:31 PM PDT 24
Finished Jul 14 05:55:32 PM PDT 24
Peak memory 206564 kb
Host smart-5eb83a7f-c711-4d36-b8a2-07c4e55b346e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389486417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1389486417
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2037743542
Short name T449
Test name
Test status
Simulation time 120830683 ps
CPU time 0.89 seconds
Started Jul 14 05:55:21 PM PDT 24
Finished Jul 14 05:55:22 PM PDT 24
Peak memory 206932 kb
Host smart-e151d155-3631-44c0-9458-c45f0c41bfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037743542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2037743542
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1604981797
Short name T233
Test name
Test status
Simulation time 217398656 ps
CPU time 4.22 seconds
Started Jul 14 05:55:28 PM PDT 24
Finished Jul 14 05:55:33 PM PDT 24
Peak memory 233764 kb
Host smart-249c1652-648d-45db-a1cd-f382752b9c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604981797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1604981797
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3565634017
Short name T903
Test name
Test status
Simulation time 64252628 ps
CPU time 0.74 seconds
Started Jul 14 05:55:44 PM PDT 24
Finished Jul 14 05:55:46 PM PDT 24
Peak memory 206652 kb
Host smart-ed2cded8-4eb0-47a1-bd85-873dac76474a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565634017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3565634017
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3410123974
Short name T753
Test name
Test status
Simulation time 568672595 ps
CPU time 3.4 seconds
Started Jul 14 05:55:32 PM PDT 24
Finished Jul 14 05:55:36 PM PDT 24
Peak memory 225380 kb
Host smart-c60fd5ce-8380-4a22-89ac-bce0504c8f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410123974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3410123974
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2512676981
Short name T338
Test name
Test status
Simulation time 67660164 ps
CPU time 0.76 seconds
Started Jul 14 05:55:30 PM PDT 24
Finished Jul 14 05:55:31 PM PDT 24
Peak memory 207480 kb
Host smart-e74fb86f-c660-4a6a-9262-23cf748ce343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512676981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2512676981
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3605765345
Short name T280
Test name
Test status
Simulation time 1449030110 ps
CPU time 13.3 seconds
Started Jul 14 05:55:33 PM PDT 24
Finished Jul 14 05:55:47 PM PDT 24
Peak memory 233712 kb
Host smart-747ff602-0f25-40d8-8d7b-24b71c136b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605765345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3605765345
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1077755019
Short name T754
Test name
Test status
Simulation time 48775740823 ps
CPU time 122.73 seconds
Started Jul 14 05:55:38 PM PDT 24
Finished Jul 14 05:57:41 PM PDT 24
Peak memory 258376 kb
Host smart-86c6c96c-dc1f-4850-8447-621cdf049be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077755019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1077755019
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2017846797
Short name T962
Test name
Test status
Simulation time 4378892111 ps
CPU time 119.28 seconds
Started Jul 14 05:55:36 PM PDT 24
Finished Jul 14 05:57:36 PM PDT 24
Peak memory 267892 kb
Host smart-80b5ba5b-ce5f-457c-8d33-dc3b2cb1a091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017846797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2017846797
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3417250887
Short name T956
Test name
Test status
Simulation time 277358650 ps
CPU time 7.02 seconds
Started Jul 14 05:55:35 PM PDT 24
Finished Jul 14 05:55:43 PM PDT 24
Peak memory 225600 kb
Host smart-bbd86835-c4f6-4871-97c3-891b62f53f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417250887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3417250887
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1507785227
Short name T95
Test name
Test status
Simulation time 1380422451 ps
CPU time 12.75 seconds
Started Jul 14 05:55:34 PM PDT 24
Finished Jul 14 05:55:47 PM PDT 24
Peak memory 225512 kb
Host smart-2929cb4e-a7de-4dcc-8a4a-94daf14fe8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507785227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1507785227
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.680735518
Short name T592
Test name
Test status
Simulation time 2010009406 ps
CPU time 5.35 seconds
Started Jul 14 05:55:36 PM PDT 24
Finished Jul 14 05:55:42 PM PDT 24
Peak memory 225504 kb
Host smart-7dd35d87-34e8-4d52-93ba-862207eb9bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680735518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.680735518
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1242233719
Short name T906
Test name
Test status
Simulation time 4144139407 ps
CPU time 42.94 seconds
Started Jul 14 05:55:36 PM PDT 24
Finished Jul 14 05:56:20 PM PDT 24
Peak memory 225668 kb
Host smart-bcbf249f-394a-484b-9bd1-0962e63107b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242233719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1242233719
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.923377405
Short name T920
Test name
Test status
Simulation time 5190381510 ps
CPU time 16.1 seconds
Started Jul 14 05:55:33 PM PDT 24
Finished Jul 14 05:55:50 PM PDT 24
Peak memory 233892 kb
Host smart-90221917-3dd5-4a7a-aaf3-a4f1ddc593ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923377405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.923377405
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2249176505
Short name T923
Test name
Test status
Simulation time 818147274 ps
CPU time 3.85 seconds
Started Jul 14 05:55:36 PM PDT 24
Finished Jul 14 05:55:41 PM PDT 24
Peak memory 225556 kb
Host smart-eb2c79c5-e543-45f6-a60e-3635a504f202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249176505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2249176505
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2558977820
Short name T761
Test name
Test status
Simulation time 640494007 ps
CPU time 4.58 seconds
Started Jul 14 05:55:37 PM PDT 24
Finished Jul 14 05:55:42 PM PDT 24
Peak memory 221216 kb
Host smart-7ceb3cf2-43cb-4e0f-81d1-ee0636343599
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2558977820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2558977820
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3120377439
Short name T275
Test name
Test status
Simulation time 53612728946 ps
CPU time 684.02 seconds
Started Jul 14 05:55:36 PM PDT 24
Finished Jul 14 06:07:01 PM PDT 24
Peak memory 307632 kb
Host smart-1527bc64-b938-4051-8e63-587a9599b1f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120377439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3120377439
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2174190703
Short name T572
Test name
Test status
Simulation time 14604823661 ps
CPU time 35.02 seconds
Started Jul 14 05:55:36 PM PDT 24
Finished Jul 14 05:56:12 PM PDT 24
Peak memory 217480 kb
Host smart-21c8de9e-377e-42bb-95ee-3c2b766ea336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174190703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2174190703
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3824535483
Short name T853
Test name
Test status
Simulation time 1388367445 ps
CPU time 7.27 seconds
Started Jul 14 05:55:28 PM PDT 24
Finished Jul 14 05:55:35 PM PDT 24
Peak memory 217292 kb
Host smart-d60d5a68-cf6e-4977-9efc-113388c7966c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824535483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3824535483
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2294965271
Short name T59
Test name
Test status
Simulation time 160073223 ps
CPU time 1.48 seconds
Started Jul 14 05:55:35 PM PDT 24
Finished Jul 14 05:55:37 PM PDT 24
Peak memory 217272 kb
Host smart-4859e90e-4d69-4f2b-89d4-761b84f41a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294965271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2294965271
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2144781531
Short name T584
Test name
Test status
Simulation time 54164226 ps
CPU time 0.86 seconds
Started Jul 14 05:55:32 PM PDT 24
Finished Jul 14 05:55:33 PM PDT 24
Peak memory 206880 kb
Host smart-3d8a3d7e-3620-4f2f-8f69-d55df39cca77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144781531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2144781531
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.763664766
Short name T240
Test name
Test status
Simulation time 946189939 ps
CPU time 5.72 seconds
Started Jul 14 05:55:36 PM PDT 24
Finished Jul 14 05:55:42 PM PDT 24
Peak memory 233776 kb
Host smart-e80626b4-a84f-46bf-a24d-a142cdaab451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763664766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.763664766
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1046388695
Short name T570
Test name
Test status
Simulation time 36663579 ps
CPU time 0.69 seconds
Started Jul 14 05:55:43 PM PDT 24
Finished Jul 14 05:55:44 PM PDT 24
Peak memory 206344 kb
Host smart-4658c094-9638-4965-a579-ad9c4e4a4158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046388695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1046388695
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.622963469
Short name T64
Test name
Test status
Simulation time 36411308 ps
CPU time 2.41 seconds
Started Jul 14 05:55:42 PM PDT 24
Finished Jul 14 05:55:45 PM PDT 24
Peak memory 233452 kb
Host smart-89e1ce5e-1739-47ab-bdec-b6f1f1fbc88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622963469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.622963469
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1954192672
Short name T418
Test name
Test status
Simulation time 16614276 ps
CPU time 0.73 seconds
Started Jul 14 05:55:44 PM PDT 24
Finished Jul 14 05:55:45 PM PDT 24
Peak memory 206832 kb
Host smart-d5731820-d906-458e-8366-dceee190fb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954192672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1954192672
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3284233189
Short name T926
Test name
Test status
Simulation time 6006679893 ps
CPU time 54.21 seconds
Started Jul 14 05:55:44 PM PDT 24
Finished Jul 14 05:56:40 PM PDT 24
Peak memory 233992 kb
Host smart-976eb618-a4a3-4258-8b14-2cad43b883fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284233189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3284233189
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1258900230
Short name T841
Test name
Test status
Simulation time 14710692241 ps
CPU time 141.64 seconds
Started Jul 14 05:55:44 PM PDT 24
Finished Jul 14 05:58:06 PM PDT 24
Peak memory 252720 kb
Host smart-c6d5e720-abfd-4261-8a0b-5728c87489e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258900230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1258900230
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3871677693
Short name T952
Test name
Test status
Simulation time 1212976701 ps
CPU time 21.04 seconds
Started Jul 14 05:55:45 PM PDT 24
Finished Jul 14 05:56:07 PM PDT 24
Peak memory 234820 kb
Host smart-14606d6e-99e0-4f8e-b9ec-8c851f47b414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871677693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3871677693
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.4015002987
Short name T661
Test name
Test status
Simulation time 1831134778 ps
CPU time 13.34 seconds
Started Jul 14 05:55:43 PM PDT 24
Finished Jul 14 05:55:57 PM PDT 24
Peak memory 225536 kb
Host smart-35e70226-f063-47b3-85f8-30ac0241468b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015002987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.4015002987
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3518404546
Short name T265
Test name
Test status
Simulation time 524046410 ps
CPU time 4.8 seconds
Started Jul 14 05:55:44 PM PDT 24
Finished Jul 14 05:55:50 PM PDT 24
Peak memory 225520 kb
Host smart-f76ef54f-2ba3-48f3-89f9-f1d8e797d236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518404546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3518404546
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.4178162963
Short name T97
Test name
Test status
Simulation time 457858684 ps
CPU time 8.76 seconds
Started Jul 14 05:55:43 PM PDT 24
Finished Jul 14 05:55:53 PM PDT 24
Peak memory 225488 kb
Host smart-38b1e529-b02d-4bfe-abba-1dd208a54d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178162963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4178162963
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2193858314
Short name T803
Test name
Test status
Simulation time 6765259751 ps
CPU time 11.5 seconds
Started Jul 14 05:55:43 PM PDT 24
Finished Jul 14 05:55:55 PM PDT 24
Peak memory 237608 kb
Host smart-67a45920-3d47-453d-85be-2b482eb17ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193858314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2193858314
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3020318652
Short name T239
Test name
Test status
Simulation time 8991088089 ps
CPU time 26.57 seconds
Started Jul 14 05:55:43 PM PDT 24
Finished Jul 14 05:56:11 PM PDT 24
Peak memory 252260 kb
Host smart-848e7e9a-f05e-4841-a944-0bbf5c0f67ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020318652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3020318652
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1874807242
Short name T405
Test name
Test status
Simulation time 4084168667 ps
CPU time 9.18 seconds
Started Jul 14 05:55:44 PM PDT 24
Finished Jul 14 05:55:54 PM PDT 24
Peak memory 224440 kb
Host smart-3b1b8e4a-6191-40be-af4a-6814a110d631
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1874807242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1874807242
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3002260309
Short name T484
Test name
Test status
Simulation time 13049817094 ps
CPU time 52.31 seconds
Started Jul 14 05:55:42 PM PDT 24
Finished Jul 14 05:56:35 PM PDT 24
Peak memory 241396 kb
Host smart-5104c09e-e04f-4c54-a798-0848359f33c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002260309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3002260309
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.910307309
Short name T586
Test name
Test status
Simulation time 9273608733 ps
CPU time 15.88 seconds
Started Jul 14 05:55:44 PM PDT 24
Finished Jul 14 05:56:01 PM PDT 24
Peak memory 217728 kb
Host smart-cd385055-ed6a-4c32-b224-586e70fd9a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910307309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.910307309
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1422985682
Short name T770
Test name
Test status
Simulation time 2093831370 ps
CPU time 11.01 seconds
Started Jul 14 05:55:45 PM PDT 24
Finished Jul 14 05:55:57 PM PDT 24
Peak memory 217324 kb
Host smart-a674ef39-aee5-425c-8203-8a6a6ab45cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422985682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1422985682
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1585687172
Short name T509
Test name
Test status
Simulation time 33440169 ps
CPU time 1.31 seconds
Started Jul 14 05:55:44 PM PDT 24
Finished Jul 14 05:55:46 PM PDT 24
Peak memory 217280 kb
Host smart-ad9068b2-b252-45e6-bda3-126ff70c876a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585687172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1585687172
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2105923401
Short name T852
Test name
Test status
Simulation time 194756186 ps
CPU time 0.94 seconds
Started Jul 14 05:55:43 PM PDT 24
Finished Jul 14 05:55:45 PM PDT 24
Peak memory 207284 kb
Host smart-64f220aa-0532-4c96-993e-12d61e924473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105923401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2105923401
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.433469522
Short name T855
Test name
Test status
Simulation time 16000391888 ps
CPU time 12.01 seconds
Started Jul 14 05:55:46 PM PDT 24
Finished Jul 14 05:55:58 PM PDT 24
Peak memory 233892 kb
Host smart-1a706cb2-c13e-49aa-9553-1fafe6961cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433469522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.433469522
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1433228237
Short name T954
Test name
Test status
Simulation time 24004995 ps
CPU time 0.72 seconds
Started Jul 14 05:55:59 PM PDT 24
Finished Jul 14 05:56:01 PM PDT 24
Peak memory 205804 kb
Host smart-01a18671-3f0c-4ba0-aa83-25b97e0b4ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433228237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1433228237
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3351626218
Short name T232
Test name
Test status
Simulation time 6603439844 ps
CPU time 8.27 seconds
Started Jul 14 05:55:50 PM PDT 24
Finished Jul 14 05:55:59 PM PDT 24
Peak memory 225556 kb
Host smart-daac7b2d-5bff-440d-b8da-2d8fb9a1a24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351626218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3351626218
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.842795280
Short name T68
Test name
Test status
Simulation time 13668318 ps
CPU time 0.88 seconds
Started Jul 14 05:55:44 PM PDT 24
Finished Jul 14 05:55:46 PM PDT 24
Peak memory 207704 kb
Host smart-e8e64b44-0562-43ca-9386-beedc8d402ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842795280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.842795280
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.192530770
Short name T995
Test name
Test status
Simulation time 47463074285 ps
CPU time 78.83 seconds
Started Jul 14 05:55:59 PM PDT 24
Finished Jul 14 05:57:19 PM PDT 24
Peak memory 253056 kb
Host smart-7d2036e0-7233-4701-8963-669ac7eabd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192530770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.192530770
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.267562229
Short name T362
Test name
Test status
Simulation time 3365414955 ps
CPU time 53.03 seconds
Started Jul 14 05:55:59 PM PDT 24
Finished Jul 14 05:56:53 PM PDT 24
Peak memory 253360 kb
Host smart-413fa67e-62e5-44d5-8de3-26fbafea3fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267562229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.267562229
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3499253416
Short name T815
Test name
Test status
Simulation time 12650191994 ps
CPU time 23.11 seconds
Started Jul 14 05:55:53 PM PDT 24
Finished Jul 14 05:56:16 PM PDT 24
Peak memory 242060 kb
Host smart-e685ce01-a4f8-4b83-bdfc-02c358a0594b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499253416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3499253416
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2083653093
Short name T1015
Test name
Test status
Simulation time 90257883734 ps
CPU time 155.48 seconds
Started Jul 14 05:55:53 PM PDT 24
Finished Jul 14 05:58:29 PM PDT 24
Peak memory 256044 kb
Host smart-8611b929-4a3c-4e7a-ad26-6b39f1d675ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083653093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2083653093
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1290697756
Short name T14
Test name
Test status
Simulation time 999704936 ps
CPU time 13.33 seconds
Started Jul 14 05:55:53 PM PDT 24
Finished Jul 14 05:56:07 PM PDT 24
Peak memory 225388 kb
Host smart-7c6bb9e9-0032-46ac-a408-df03e829f003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290697756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1290697756
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.612856650
Short name T507
Test name
Test status
Simulation time 12392081816 ps
CPU time 89.37 seconds
Started Jul 14 05:55:51 PM PDT 24
Finished Jul 14 05:57:20 PM PDT 24
Peak memory 241968 kb
Host smart-e2d5c5c4-e4bd-4166-9579-05a53473163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612856650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.612856650
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.911540268
Short name T786
Test name
Test status
Simulation time 184059663 ps
CPU time 2.17 seconds
Started Jul 14 05:55:53 PM PDT 24
Finished Jul 14 05:55:55 PM PDT 24
Peak memory 224076 kb
Host smart-337502c4-9d59-45a7-87cb-4118bddda849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911540268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.911540268
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3176126326
Short name T262
Test name
Test status
Simulation time 2077300427 ps
CPU time 5.81 seconds
Started Jul 14 05:55:52 PM PDT 24
Finished Jul 14 05:55:58 PM PDT 24
Peak memory 233776 kb
Host smart-ac2d9bce-ed0c-4bb3-a90e-773773c468ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176126326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3176126326
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3227211122
Short name T479
Test name
Test status
Simulation time 79300130 ps
CPU time 3.91 seconds
Started Jul 14 05:56:00 PM PDT 24
Finished Jul 14 05:56:04 PM PDT 24
Peak memory 220400 kb
Host smart-e32b9eb3-2d21-408e-9ea7-70155d01f47f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3227211122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3227211122
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2280361089
Short name T201
Test name
Test status
Simulation time 81476969484 ps
CPU time 584.5 seconds
Started Jul 14 05:55:59 PM PDT 24
Finished Jul 14 06:05:44 PM PDT 24
Peak memory 269772 kb
Host smart-adf86471-d87e-4981-8d7d-dfe560f2b662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280361089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2280361089
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2244850600
Short name T874
Test name
Test status
Simulation time 3311198723 ps
CPU time 30.75 seconds
Started Jul 14 05:55:44 PM PDT 24
Finished Jul 14 05:56:16 PM PDT 24
Peak memory 217804 kb
Host smart-3bd459bf-bad7-4db5-b724-082c57d43bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244850600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2244850600
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.441972983
Short name T373
Test name
Test status
Simulation time 624258427 ps
CPU time 4.32 seconds
Started Jul 14 05:55:44 PM PDT 24
Finished Jul 14 05:55:48 PM PDT 24
Peak memory 217348 kb
Host smart-231a36af-12b6-47b2-b6f9-43c1700d4ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441972983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.441972983
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3145301318
Short name T619
Test name
Test status
Simulation time 70596664 ps
CPU time 1.13 seconds
Started Jul 14 05:55:50 PM PDT 24
Finished Jul 14 05:55:52 PM PDT 24
Peak memory 208940 kb
Host smart-343df629-4503-4229-9d15-d8441eb570cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145301318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3145301318
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.4179796175
Short name T911
Test name
Test status
Simulation time 110569493 ps
CPU time 0.79 seconds
Started Jul 14 05:55:48 PM PDT 24
Finished Jul 14 05:55:50 PM PDT 24
Peak memory 206948 kb
Host smart-71f73216-cfbf-4f4e-b931-c9b623c0e052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179796175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.4179796175
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3473272270
Short name T421
Test name
Test status
Simulation time 5009190414 ps
CPU time 5.77 seconds
Started Jul 14 05:55:50 PM PDT 24
Finished Jul 14 05:55:56 PM PDT 24
Peak memory 225692 kb
Host smart-04dcf678-a679-4bd6-89bb-24551a13f00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473272270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3473272270
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.233396544
Short name T876
Test name
Test status
Simulation time 14980927 ps
CPU time 0.75 seconds
Started Jul 14 05:56:09 PM PDT 24
Finished Jul 14 05:56:10 PM PDT 24
Peak memory 206304 kb
Host smart-11c509fd-71f9-4829-9733-2529b774a8cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233396544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.233396544
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.798844077
Short name T1012
Test name
Test status
Simulation time 148932582 ps
CPU time 2.1 seconds
Started Jul 14 05:55:58 PM PDT 24
Finished Jul 14 05:56:01 PM PDT 24
Peak memory 225408 kb
Host smart-62c3a5c5-b55d-4446-9494-b2a1064f202a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798844077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.798844077
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1412368346
Short name T634
Test name
Test status
Simulation time 20356961 ps
CPU time 0.79 seconds
Started Jul 14 05:55:57 PM PDT 24
Finished Jul 14 05:55:58 PM PDT 24
Peak memory 207484 kb
Host smart-ffb44fcb-d6dc-49f9-845c-417c70f5813e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412368346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1412368346
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.28774515
Short name T168
Test name
Test status
Simulation time 3425881091 ps
CPU time 48.89 seconds
Started Jul 14 05:56:11 PM PDT 24
Finished Jul 14 05:57:00 PM PDT 24
Peak memory 257020 kb
Host smart-7dc5ea75-7bc2-4b97-886e-81d1ec662b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28774515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.28774515
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1357488240
Short name T792
Test name
Test status
Simulation time 3740745746 ps
CPU time 62.74 seconds
Started Jul 14 05:56:18 PM PDT 24
Finished Jul 14 05:57:22 PM PDT 24
Peak memory 255336 kb
Host smart-2c5aa07b-080d-4422-a090-1454931b0183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357488240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1357488240
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2133370568
Short name T627
Test name
Test status
Simulation time 1304802411 ps
CPU time 7.22 seconds
Started Jul 14 05:55:58 PM PDT 24
Finished Jul 14 05:56:06 PM PDT 24
Peak memory 231888 kb
Host smart-73fdefeb-61b7-46bb-b461-5ab619cbd87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133370568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2133370568
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1864830024
Short name T166
Test name
Test status
Simulation time 15251827055 ps
CPU time 133.38 seconds
Started Jul 14 05:55:59 PM PDT 24
Finished Jul 14 05:58:13 PM PDT 24
Peak memory 260040 kb
Host smart-730421e0-373c-4cdb-bbc7-0df54ff52779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864830024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1864830024
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3676971213
Short name T566
Test name
Test status
Simulation time 12390355632 ps
CPU time 28.65 seconds
Started Jul 14 05:56:00 PM PDT 24
Finished Jul 14 05:56:29 PM PDT 24
Peak memory 225608 kb
Host smart-7bd1787a-6ebb-457e-af9b-1ba44cafb4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676971213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3676971213
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.528812360
Short name T893
Test name
Test status
Simulation time 7364215300 ps
CPU time 36.16 seconds
Started Jul 14 05:55:59 PM PDT 24
Finished Jul 14 05:56:35 PM PDT 24
Peak memory 225512 kb
Host smart-e5b2ce5d-2107-405b-8148-a59fa2d0cf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528812360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.528812360
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1803074195
Short name T375
Test name
Test status
Simulation time 6918523822 ps
CPU time 7.71 seconds
Started Jul 14 05:56:03 PM PDT 24
Finished Jul 14 05:56:11 PM PDT 24
Peak memory 233872 kb
Host smart-2657b093-1a1b-4ba5-8006-af59e85350e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803074195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1803074195
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2535931733
Short name T642
Test name
Test status
Simulation time 1069222483 ps
CPU time 8.88 seconds
Started Jul 14 05:55:56 PM PDT 24
Finished Jul 14 05:56:05 PM PDT 24
Peak memory 233808 kb
Host smart-66207e7d-e16e-450c-bcb3-f40cc1348cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535931733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2535931733
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3577737884
Short name T4
Test name
Test status
Simulation time 3806848615 ps
CPU time 13.17 seconds
Started Jul 14 05:56:09 PM PDT 24
Finished Jul 14 05:56:22 PM PDT 24
Peak memory 223008 kb
Host smart-384b500d-f343-4fc1-95b1-de7a707f2379
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3577737884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3577737884
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1307330923
Short name T612
Test name
Test status
Simulation time 5340389108 ps
CPU time 30.69 seconds
Started Jul 14 05:55:59 PM PDT 24
Finished Jul 14 05:56:31 PM PDT 24
Peak memory 217404 kb
Host smart-e0aca085-3be9-4b79-b3ef-95be4f523cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307330923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1307330923
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3006503100
Short name T333
Test name
Test status
Simulation time 41677116 ps
CPU time 1.06 seconds
Started Jul 14 05:55:59 PM PDT 24
Finished Jul 14 05:56:01 PM PDT 24
Peak memory 206972 kb
Host smart-784df16c-4847-4750-9fb5-30ffaaa1c528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006503100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3006503100
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1945201079
Short name T817
Test name
Test status
Simulation time 350113859 ps
CPU time 3.57 seconds
Started Jul 14 05:56:02 PM PDT 24
Finished Jul 14 05:56:06 PM PDT 24
Peak memory 217368 kb
Host smart-d10c3d61-1c7c-470f-8542-ceb3a162ec12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945201079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1945201079
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2715113706
Short name T946
Test name
Test status
Simulation time 49337291 ps
CPU time 0.79 seconds
Started Jul 14 05:55:57 PM PDT 24
Finished Jul 14 05:55:58 PM PDT 24
Peak memory 206940 kb
Host smart-633d4246-fb33-4f2c-9bac-abca1ffc2c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715113706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2715113706
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2473145768
Short name T523
Test name
Test status
Simulation time 3232006020 ps
CPU time 7.71 seconds
Started Jul 14 05:56:00 PM PDT 24
Finished Jul 14 05:56:09 PM PDT 24
Peak memory 229296 kb
Host smart-a60603d5-8b9b-410a-b1fa-67019990787c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473145768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2473145768
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1346362782
Short name T24
Test name
Test status
Simulation time 67396945 ps
CPU time 0.72 seconds
Started Jul 14 05:56:19 PM PDT 24
Finished Jul 14 05:56:20 PM PDT 24
Peak memory 206696 kb
Host smart-8a33199f-f211-4b9a-88a6-59b0e4cfe36e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346362782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1346362782
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3782336347
Short name T1026
Test name
Test status
Simulation time 67160616 ps
CPU time 2.67 seconds
Started Jul 14 05:56:18 PM PDT 24
Finished Jul 14 05:56:22 PM PDT 24
Peak memory 233728 kb
Host smart-ef0b6558-52f4-4df0-ab15-e42c62530754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782336347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3782336347
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2859404495
Short name T947
Test name
Test status
Simulation time 172788885 ps
CPU time 0.81 seconds
Started Jul 14 05:56:09 PM PDT 24
Finished Jul 14 05:56:10 PM PDT 24
Peak memory 207516 kb
Host smart-eef488cb-0195-4b49-bc37-4e5057d2a9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859404495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2859404495
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2528526569
Short name T921
Test name
Test status
Simulation time 35159621 ps
CPU time 0.76 seconds
Started Jul 14 05:56:14 PM PDT 24
Finished Jul 14 05:56:16 PM PDT 24
Peak memory 216864 kb
Host smart-827d40ac-eff3-40e3-9d7d-60cd19e3392a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528526569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2528526569
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.139565829
Short name T682
Test name
Test status
Simulation time 9010316358 ps
CPU time 61.98 seconds
Started Jul 14 05:56:18 PM PDT 24
Finished Jul 14 05:57:20 PM PDT 24
Peak memory 253560 kb
Host smart-f910d302-6613-47d9-a7de-dcd0036842fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139565829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.139565829
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3747220824
Short name T996
Test name
Test status
Simulation time 3194619929 ps
CPU time 10.45 seconds
Started Jul 14 05:56:16 PM PDT 24
Finished Jul 14 05:56:27 PM PDT 24
Peak memory 225660 kb
Host smart-5a61c7a0-01a5-4e6b-a923-7b000e396251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747220824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3747220824
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.3387242277
Short name T277
Test name
Test status
Simulation time 2433217112 ps
CPU time 62.76 seconds
Started Jul 14 05:56:18 PM PDT 24
Finished Jul 14 05:57:21 PM PDT 24
Peak memory 267472 kb
Host smart-640a9763-af8e-4656-91ee-134dbcab77cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387242277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.3387242277
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.591532217
Short name T662
Test name
Test status
Simulation time 112609186 ps
CPU time 3.73 seconds
Started Jul 14 05:56:07 PM PDT 24
Finished Jul 14 05:56:11 PM PDT 24
Peak memory 225436 kb
Host smart-e32a86e5-4c92-4d52-ac1c-1403ed3695fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591532217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.591532217
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.271016346
Short name T724
Test name
Test status
Simulation time 1191563534 ps
CPU time 9.86 seconds
Started Jul 14 05:56:15 PM PDT 24
Finished Jul 14 05:56:25 PM PDT 24
Peak memory 233756 kb
Host smart-9a9bc725-c90e-4a7a-843b-2b8b21fe0d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271016346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.271016346
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3722804632
Short name T1011
Test name
Test status
Simulation time 10348549908 ps
CPU time 15.64 seconds
Started Jul 14 05:56:10 PM PDT 24
Finished Jul 14 05:56:26 PM PDT 24
Peak memory 233848 kb
Host smart-bec4f9c3-b2bf-4830-b6a4-f269e4c667c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722804632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3722804632
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2635022823
Short name T759
Test name
Test status
Simulation time 10620884748 ps
CPU time 9.93 seconds
Started Jul 14 05:56:07 PM PDT 24
Finished Jul 14 05:56:18 PM PDT 24
Peak memory 233852 kb
Host smart-2455e0ad-ad3e-4b65-90b2-05c3f49c47a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635022823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2635022823
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1500440761
Short name T140
Test name
Test status
Simulation time 262806258 ps
CPU time 3.29 seconds
Started Jul 14 05:56:15 PM PDT 24
Finished Jul 14 05:56:19 PM PDT 24
Peak memory 224252 kb
Host smart-f1554ae3-6990-4221-919a-6cc09fc3fde6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1500440761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1500440761
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2523374554
Short name T720
Test name
Test status
Simulation time 21288634479 ps
CPU time 133.46 seconds
Started Jul 14 05:56:16 PM PDT 24
Finished Jul 14 05:58:30 PM PDT 24
Peak memory 257608 kb
Host smart-a97b9da7-b8de-4812-ac38-a0dc7de72fb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523374554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2523374554
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1984297724
Short name T780
Test name
Test status
Simulation time 11107990918 ps
CPU time 27.5 seconds
Started Jul 14 05:56:06 PM PDT 24
Finished Jul 14 05:56:34 PM PDT 24
Peak memory 217440 kb
Host smart-c7957fc7-e4f4-48b2-ae06-ac0c258f9f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984297724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1984297724
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1726911645
Short name T508
Test name
Test status
Simulation time 265900589 ps
CPU time 2.08 seconds
Started Jul 14 05:56:11 PM PDT 24
Finished Jul 14 05:56:13 PM PDT 24
Peak memory 217332 kb
Host smart-d70eb639-0b22-44a2-81eb-72c84a01936c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726911645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1726911645
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1502850629
Short name T813
Test name
Test status
Simulation time 76601653 ps
CPU time 2.22 seconds
Started Jul 14 05:56:08 PM PDT 24
Finished Jul 14 05:56:11 PM PDT 24
Peak memory 217296 kb
Host smart-a8be4f8f-fe32-47de-9e53-28b5047ef0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502850629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1502850629
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1193309120
Short name T944
Test name
Test status
Simulation time 28879591 ps
CPU time 0.75 seconds
Started Jul 14 05:56:08 PM PDT 24
Finished Jul 14 05:56:09 PM PDT 24
Peak memory 206892 kb
Host smart-091ca5ae-c009-4968-b078-765ca5c5d8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193309120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1193309120
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3714956934
Short name T901
Test name
Test status
Simulation time 275576889 ps
CPU time 3.87 seconds
Started Jul 14 05:56:19 PM PDT 24
Finished Jul 14 05:56:23 PM PDT 24
Peak memory 233760 kb
Host smart-44deba60-d4bf-45d7-bc1a-63285603afdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714956934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3714956934
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3517797536
Short name T733
Test name
Test status
Simulation time 54465455 ps
CPU time 0.73 seconds
Started Jul 14 05:56:25 PM PDT 24
Finished Jul 14 05:56:27 PM PDT 24
Peak memory 206288 kb
Host smart-01f6aebc-f8d3-451e-abce-278f679ff07b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517797536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3517797536
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1072271663
Short name T263
Test name
Test status
Simulation time 165686171 ps
CPU time 3.21 seconds
Started Jul 14 05:56:18 PM PDT 24
Finished Jul 14 05:56:22 PM PDT 24
Peak memory 233788 kb
Host smart-e224157a-1d43-42b1-bbf0-9f0d4d19b9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072271663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1072271663
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2862939424
Short name T439
Test name
Test status
Simulation time 71066700 ps
CPU time 0.8 seconds
Started Jul 14 05:56:16 PM PDT 24
Finished Jul 14 05:56:18 PM PDT 24
Peak memory 207444 kb
Host smart-a58de8e4-8522-4b30-bd5c-f9e3bf2174d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862939424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2862939424
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3309559271
Short name T186
Test name
Test status
Simulation time 15201508488 ps
CPU time 47.83 seconds
Started Jul 14 05:56:13 PM PDT 24
Finished Jul 14 05:57:01 PM PDT 24
Peak memory 251980 kb
Host smart-a5bb8b5a-073a-4d2c-a11f-6afba7c372b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309559271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3309559271
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2403766380
Short name T505
Test name
Test status
Simulation time 137144473858 ps
CPU time 269.28 seconds
Started Jul 14 05:56:15 PM PDT 24
Finished Jul 14 06:00:45 PM PDT 24
Peak memory 250356 kb
Host smart-2b0aeb58-8de0-4aa1-9869-3e203a7ac777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403766380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2403766380
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3603605868
Short name T755
Test name
Test status
Simulation time 126978097305 ps
CPU time 625.85 seconds
Started Jul 14 05:56:22 PM PDT 24
Finished Jul 14 06:06:49 PM PDT 24
Peak memory 258460 kb
Host smart-24b3ce52-7efd-427a-8421-c6a11ec0147f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603605868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3603605868
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.4246894671
Short name T937
Test name
Test status
Simulation time 290305940 ps
CPU time 4.38 seconds
Started Jul 14 05:56:18 PM PDT 24
Finished Jul 14 05:56:23 PM PDT 24
Peak memory 233764 kb
Host smart-bc1e35e6-55a2-4948-a48a-2d4c4b08fd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246894671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4246894671
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2408811406
Short name T734
Test name
Test status
Simulation time 448519957889 ps
CPU time 246.1 seconds
Started Jul 14 05:56:15 PM PDT 24
Finished Jul 14 06:00:22 PM PDT 24
Peak memory 258000 kb
Host smart-c90d50e3-69c3-4cc7-b99f-bfe890679f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408811406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2408811406
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.4075680995
Short name T241
Test name
Test status
Simulation time 1124558932 ps
CPU time 13.39 seconds
Started Jul 14 05:56:18 PM PDT 24
Finished Jul 14 05:56:32 PM PDT 24
Peak memory 233780 kb
Host smart-cb622862-41f1-4260-a165-f559be5b5df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075680995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4075680995
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3233068096
Short name T25
Test name
Test status
Simulation time 1492413151 ps
CPU time 11.44 seconds
Started Jul 14 05:56:14 PM PDT 24
Finished Jul 14 05:56:26 PM PDT 24
Peak memory 233748 kb
Host smart-610df382-94c7-46e5-8a3e-695b31bbe693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233068096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3233068096
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3229183579
Short name T708
Test name
Test status
Simulation time 5172614796 ps
CPU time 16.63 seconds
Started Jul 14 05:56:18 PM PDT 24
Finished Jul 14 05:56:35 PM PDT 24
Peak memory 233888 kb
Host smart-79f05b2c-1806-49ca-b722-cd4e45fba192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229183579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3229183579
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3752840801
Short name T1008
Test name
Test status
Simulation time 3613874078 ps
CPU time 8.3 seconds
Started Jul 14 05:56:19 PM PDT 24
Finished Jul 14 05:56:28 PM PDT 24
Peak memory 233912 kb
Host smart-1447ca71-35aa-4707-95a7-3d08e15a24ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752840801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3752840801
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.931618235
Short name T354
Test name
Test status
Simulation time 3338010764 ps
CPU time 12.49 seconds
Started Jul 14 05:56:19 PM PDT 24
Finished Jul 14 05:56:32 PM PDT 24
Peak memory 219904 kb
Host smart-9fdb2aab-db45-417d-904f-dace92b1663f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=931618235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.931618235
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2474577096
Short name T45
Test name
Test status
Simulation time 1339578066 ps
CPU time 19.48 seconds
Started Jul 14 05:56:18 PM PDT 24
Finished Jul 14 05:56:37 PM PDT 24
Peak memory 217652 kb
Host smart-1b2a3f9e-6a79-4b9d-bec7-4d935edcbcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474577096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2474577096
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4223286547
Short name T757
Test name
Test status
Simulation time 2785225999 ps
CPU time 8.82 seconds
Started Jul 14 05:56:17 PM PDT 24
Finished Jul 14 05:56:27 PM PDT 24
Peak memory 217444 kb
Host smart-d3e958a7-c4b6-47bf-89a7-5e577776f9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223286547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4223286547
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3120500824
Short name T314
Test name
Test status
Simulation time 58436971 ps
CPU time 3.22 seconds
Started Jul 14 05:56:14 PM PDT 24
Finished Jul 14 05:56:17 PM PDT 24
Peak memory 217364 kb
Host smart-1ef85a19-cbfc-41b4-870a-e2407923d935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120500824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3120500824
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.200901761
Short name T865
Test name
Test status
Simulation time 47301635 ps
CPU time 0.76 seconds
Started Jul 14 05:56:19 PM PDT 24
Finished Jul 14 05:56:20 PM PDT 24
Peak memory 207288 kb
Host smart-c8af1f24-97f0-44da-a5ce-9279f824ca61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200901761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.200901761
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2559469030
Short name T823
Test name
Test status
Simulation time 9601891559 ps
CPU time 30.75 seconds
Started Jul 14 05:56:17 PM PDT 24
Finished Jul 14 05:56:48 PM PDT 24
Peak memory 233776 kb
Host smart-853da18b-29db-406f-be52-52db222539a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559469030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2559469030
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.953517469
Short name T71
Test name
Test status
Simulation time 140386821 ps
CPU time 0.77 seconds
Started Jul 14 05:51:32 PM PDT 24
Finished Jul 14 05:51:33 PM PDT 24
Peak memory 206352 kb
Host smart-6d55558b-2c49-4d84-9a8b-442bfb3476a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953517469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.953517469
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2192189322
Short name T2
Test name
Test status
Simulation time 720369914 ps
CPU time 5.67 seconds
Started Jul 14 05:51:25 PM PDT 24
Finished Jul 14 05:51:31 PM PDT 24
Peak memory 233784 kb
Host smart-edf7e67c-3a81-4437-98c9-9a3d54f7b928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192189322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2192189322
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3673344787
Short name T835
Test name
Test status
Simulation time 41434869 ps
CPU time 0.75 seconds
Started Jul 14 05:51:26 PM PDT 24
Finished Jul 14 05:51:28 PM PDT 24
Peak memory 206444 kb
Host smart-e858c605-d042-4d83-8af0-f11544d6af1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673344787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3673344787
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1143716676
Short name T208
Test name
Test status
Simulation time 26349359707 ps
CPU time 93.83 seconds
Started Jul 14 05:51:31 PM PDT 24
Finished Jul 14 05:53:06 PM PDT 24
Peak memory 250252 kb
Host smart-5ef80177-5114-4c8f-8e9e-6f97c1ee5879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143716676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1143716676
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.839332730
Short name T276
Test name
Test status
Simulation time 32554720767 ps
CPU time 153.17 seconds
Started Jul 14 05:51:30 PM PDT 24
Finished Jul 14 05:54:03 PM PDT 24
Peak memory 264560 kb
Host smart-02c87fa7-06c0-439b-8358-38812eb8788c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839332730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.839332730
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.713705049
Short name T133
Test name
Test status
Simulation time 57049472494 ps
CPU time 544.42 seconds
Started Jul 14 05:51:31 PM PDT 24
Finished Jul 14 06:00:36 PM PDT 24
Peak memory 258296 kb
Host smart-8c22d21f-1370-4c0d-afdf-3670b1dfb829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713705049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
713705049
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3868396281
Short name T844
Test name
Test status
Simulation time 5750357579 ps
CPU time 27.8 seconds
Started Jul 14 05:51:24 PM PDT 24
Finished Jul 14 05:51:52 PM PDT 24
Peak memory 250216 kb
Host smart-d6511a27-8bf0-497e-9641-0d5e5822e6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868396281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3868396281
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3890897693
Short name T245
Test name
Test status
Simulation time 15322895297 ps
CPU time 87.5 seconds
Started Jul 14 05:51:29 PM PDT 24
Finished Jul 14 05:52:57 PM PDT 24
Peak memory 249484 kb
Host smart-d609b7e6-936e-4e29-aca9-29b8fbb6c2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890897693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3890897693
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.4108377461
Short name T392
Test name
Test status
Simulation time 2315628748 ps
CPU time 5.43 seconds
Started Jul 14 05:51:24 PM PDT 24
Finished Jul 14 05:51:30 PM PDT 24
Peak memory 233940 kb
Host smart-3d59e74c-009a-4af1-bc15-2a7ee608cc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108377461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.4108377461
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1564186220
Short name T793
Test name
Test status
Simulation time 13953538778 ps
CPU time 40.72 seconds
Started Jul 14 05:51:22 PM PDT 24
Finished Jul 14 05:52:03 PM PDT 24
Peak memory 225624 kb
Host smart-93fdc10e-fc79-460c-92da-3c96e50cfc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564186220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1564186220
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3047306932
Short name T537
Test name
Test status
Simulation time 90230859 ps
CPU time 1.07 seconds
Started Jul 14 05:51:25 PM PDT 24
Finished Jul 14 05:51:27 PM PDT 24
Peak memory 217616 kb
Host smart-4c858ff5-ab06-4d5c-9845-7a0f7c9f643a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047306932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3047306932
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1212593361
Short name T889
Test name
Test status
Simulation time 3312775970 ps
CPU time 14.27 seconds
Started Jul 14 05:51:21 PM PDT 24
Finished Jul 14 05:51:35 PM PDT 24
Peak memory 233908 kb
Host smart-5b42ec17-8a43-41b1-b1e2-c2acdfa782c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212593361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1212593361
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.392175619
Short name T818
Test name
Test status
Simulation time 1266586153 ps
CPU time 15.89 seconds
Started Jul 14 05:51:27 PM PDT 24
Finished Jul 14 05:51:44 PM PDT 24
Peak memory 250944 kb
Host smart-026f386e-c15f-46b7-85b1-29c803f14038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392175619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.392175619
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3596062984
Short name T379
Test name
Test status
Simulation time 284246859 ps
CPU time 3.83 seconds
Started Jul 14 05:51:28 PM PDT 24
Finished Jul 14 05:51:33 PM PDT 24
Peak memory 224040 kb
Host smart-e399dbfc-3dc3-4ce4-aee1-24a57feab3a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3596062984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3596062984
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1126177440
Short name T74
Test name
Test status
Simulation time 34235809 ps
CPU time 1 seconds
Started Jul 14 05:51:31 PM PDT 24
Finished Jul 14 05:51:33 PM PDT 24
Peak memory 236344 kb
Host smart-a99fda72-526d-47df-a31d-d5ee8d1a47b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126177440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1126177440
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2776799646
Short name T156
Test name
Test status
Simulation time 74599448067 ps
CPU time 113.41 seconds
Started Jul 14 05:51:31 PM PDT 24
Finished Jul 14 05:53:25 PM PDT 24
Peak memory 250628 kb
Host smart-914ac9b1-07dd-42aa-af6f-e845ff4879f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776799646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2776799646
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.960847959
Short name T466
Test name
Test status
Simulation time 4596236623 ps
CPU time 9.26 seconds
Started Jul 14 05:51:22 PM PDT 24
Finished Jul 14 05:51:31 PM PDT 24
Peak memory 219420 kb
Host smart-db556d54-5854-4122-85de-0bbec5b70665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960847959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.960847959
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.4027320142
Short name T704
Test name
Test status
Simulation time 1185357328 ps
CPU time 7.54 seconds
Started Jul 14 05:51:22 PM PDT 24
Finished Jul 14 05:51:31 PM PDT 24
Peak memory 217240 kb
Host smart-8b5a71b7-d90b-4c3e-b008-a9dad7c21b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027320142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.4027320142
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1449789268
Short name T441
Test name
Test status
Simulation time 503112630 ps
CPU time 2.48 seconds
Started Jul 14 05:51:22 PM PDT 24
Finished Jul 14 05:51:25 PM PDT 24
Peak memory 217328 kb
Host smart-3537522b-421b-4524-b3d7-8adb10705f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449789268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1449789268
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1351744773
Short name T524
Test name
Test status
Simulation time 89082857 ps
CPU time 0.77 seconds
Started Jul 14 05:51:27 PM PDT 24
Finished Jul 14 05:51:28 PM PDT 24
Peak memory 206932 kb
Host smart-15a2db13-cc67-4c65-ac1e-6dc255690147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351744773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1351744773
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4149195087
Short name T486
Test name
Test status
Simulation time 68175268351 ps
CPU time 27.27 seconds
Started Jul 14 05:51:23 PM PDT 24
Finished Jul 14 05:51:50 PM PDT 24
Peak memory 242000 kb
Host smart-6abbfc52-090e-456c-883f-d70735094fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149195087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4149195087
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2357426237
Short name T554
Test name
Test status
Simulation time 14612161 ps
CPU time 0.71 seconds
Started Jul 14 05:56:31 PM PDT 24
Finished Jul 14 05:56:32 PM PDT 24
Peak memory 206700 kb
Host smart-2749bae8-b645-4a20-90f3-87a483450f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357426237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2357426237
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3062644615
Short name T595
Test name
Test status
Simulation time 2825354307 ps
CPU time 8.03 seconds
Started Jul 14 05:56:23 PM PDT 24
Finished Jul 14 05:56:32 PM PDT 24
Peak memory 225856 kb
Host smart-ce9b5e08-199d-4654-a8e2-fe8425e1a642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062644615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3062644615
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3361094568
Short name T695
Test name
Test status
Simulation time 85284245 ps
CPU time 0.83 seconds
Started Jul 14 05:56:24 PM PDT 24
Finished Jul 14 05:56:25 PM PDT 24
Peak memory 207492 kb
Host smart-74c1117d-f05d-4f4b-a5cf-f696e6159384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361094568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3361094568
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1329399059
Short name T271
Test name
Test status
Simulation time 227995076971 ps
CPU time 231.08 seconds
Started Jul 14 05:56:24 PM PDT 24
Finished Jul 14 06:00:15 PM PDT 24
Peak memory 258016 kb
Host smart-9d0cb1fc-2d33-49cd-bf10-7a19c153d7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329399059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1329399059
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1627660020
Short name T604
Test name
Test status
Simulation time 746372971 ps
CPU time 9.69 seconds
Started Jul 14 05:56:22 PM PDT 24
Finished Jul 14 05:56:32 PM PDT 24
Peak memory 222112 kb
Host smart-031741e3-06ca-4e72-a24d-6b173b46d4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627660020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1627660020
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1824176118
Short name T57
Test name
Test status
Simulation time 99769331910 ps
CPU time 149.44 seconds
Started Jul 14 05:56:21 PM PDT 24
Finished Jul 14 05:58:51 PM PDT 24
Peak memory 254272 kb
Host smart-7e7f6efa-fc18-45c2-a4c7-617833a4e7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824176118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1824176118
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1959631422
Short name T298
Test name
Test status
Simulation time 1294645108 ps
CPU time 23.75 seconds
Started Jul 14 05:56:21 PM PDT 24
Finished Jul 14 05:56:45 PM PDT 24
Peak memory 234420 kb
Host smart-d433637f-b99b-49fa-8bfd-14e9e9bb4666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959631422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1959631422
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1603478590
Short name T506
Test name
Test status
Simulation time 12117263845 ps
CPU time 25.54 seconds
Started Jul 14 05:56:26 PM PDT 24
Finished Jul 14 05:56:52 PM PDT 24
Peak memory 242088 kb
Host smart-d8515d17-4dd2-4953-a660-792934e53022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603478590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1603478590
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2003132190
Short name T766
Test name
Test status
Simulation time 932287770 ps
CPU time 10.15 seconds
Started Jul 14 05:56:25 PM PDT 24
Finished Jul 14 05:56:36 PM PDT 24
Peak memory 225544 kb
Host smart-81fdd21c-57e0-4208-bd11-2c13e63a9536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003132190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2003132190
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.347037947
Short name T785
Test name
Test status
Simulation time 91718582 ps
CPU time 3.2 seconds
Started Jul 14 05:56:23 PM PDT 24
Finished Jul 14 05:56:27 PM PDT 24
Peak memory 233800 kb
Host smart-2abf93ed-6363-42f4-a975-65df0b197d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347037947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.347037947
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.230405639
Short name T985
Test name
Test status
Simulation time 1113285571 ps
CPU time 2.91 seconds
Started Jul 14 05:56:21 PM PDT 24
Finished Jul 14 05:56:25 PM PDT 24
Peak memory 233752 kb
Host smart-5ee165d1-e39e-44b1-9df6-1224779f5606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230405639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.230405639
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2995633796
Short name T49
Test name
Test status
Simulation time 2033171652 ps
CPU time 11.18 seconds
Started Jul 14 05:56:23 PM PDT 24
Finished Jul 14 05:56:35 PM PDT 24
Peak memory 225532 kb
Host smart-01fdf5f3-48ef-4c3d-8984-7c74773f9781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995633796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2995633796
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4049866295
Short name T348
Test name
Test status
Simulation time 261829526 ps
CPU time 3.44 seconds
Started Jul 14 05:56:23 PM PDT 24
Finished Jul 14 05:56:27 PM PDT 24
Peak memory 224204 kb
Host smart-d4f8e060-9b5b-4591-8f5a-4ebaef2e1fc1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4049866295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4049866295
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3397221262
Short name T794
Test name
Test status
Simulation time 30122592512 ps
CPU time 296.26 seconds
Started Jul 14 05:56:23 PM PDT 24
Finished Jul 14 06:01:20 PM PDT 24
Peak memory 258492 kb
Host smart-e83c10ed-46d8-4b45-bc4c-8ffa554319cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397221262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3397221262
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3077152684
Short name T511
Test name
Test status
Simulation time 1249357242 ps
CPU time 19.67 seconds
Started Jul 14 05:56:22 PM PDT 24
Finished Jul 14 05:56:43 PM PDT 24
Peak memory 217340 kb
Host smart-78f2c95a-66f8-4914-ad68-ca9440faafca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077152684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3077152684
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1500066340
Short name T968
Test name
Test status
Simulation time 7727950236 ps
CPU time 18.1 seconds
Started Jul 14 05:56:31 PM PDT 24
Finished Jul 14 05:56:50 PM PDT 24
Peak memory 217436 kb
Host smart-5e3ab4d5-37db-4db2-9bbb-93570ab7b1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500066340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1500066340
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.152875462
Short name T888
Test name
Test status
Simulation time 78183842 ps
CPU time 2.18 seconds
Started Jul 14 05:56:32 PM PDT 24
Finished Jul 14 05:56:35 PM PDT 24
Peak memory 217320 kb
Host smart-2e2b00d3-1cc2-4f8d-9dba-fe04b9f3e2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152875462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.152875462
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2552668287
Short name T1019
Test name
Test status
Simulation time 36771021 ps
CPU time 0.85 seconds
Started Jul 14 05:56:25 PM PDT 24
Finished Jul 14 05:56:26 PM PDT 24
Peak memory 206936 kb
Host smart-ee9a94f4-d7da-44d0-8b21-2107807f5b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552668287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2552668287
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2464764110
Short name T535
Test name
Test status
Simulation time 236516810 ps
CPU time 2.32 seconds
Started Jul 14 05:56:22 PM PDT 24
Finished Jul 14 05:56:25 PM PDT 24
Peak memory 233480 kb
Host smart-82f5835a-45e0-47ae-9290-d113bc3a7ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464764110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2464764110
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.289066568
Short name T729
Test name
Test status
Simulation time 70593333 ps
CPU time 0.73 seconds
Started Jul 14 05:56:33 PM PDT 24
Finished Jul 14 05:56:34 PM PDT 24
Peak memory 206348 kb
Host smart-4c6d8f4a-45b7-48b5-b135-ab676cb85eb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289066568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.289066568
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2116365663
Short name T898
Test name
Test status
Simulation time 144956580 ps
CPU time 2.98 seconds
Started Jul 14 05:56:32 PM PDT 24
Finished Jul 14 05:56:35 PM PDT 24
Peak memory 225544 kb
Host smart-5c5688b1-5622-4669-bafa-bb1f1ea4eae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116365663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2116365663
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.959384776
Short name T69
Test name
Test status
Simulation time 14531420 ps
CPU time 0.75 seconds
Started Jul 14 05:56:22 PM PDT 24
Finished Jul 14 05:56:23 PM PDT 24
Peak memory 206464 kb
Host smart-43975d4c-78bf-4b8c-8767-6800db44aff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959384776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.959384776
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1902890802
Short name T672
Test name
Test status
Simulation time 2991875196 ps
CPU time 29.61 seconds
Started Jul 14 05:56:33 PM PDT 24
Finished Jul 14 05:57:03 PM PDT 24
Peak memory 250268 kb
Host smart-75a78057-4f77-4049-91a6-6f97fc5e4e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902890802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1902890802
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2798942400
Short name T883
Test name
Test status
Simulation time 16002881220 ps
CPU time 87 seconds
Started Jul 14 05:56:31 PM PDT 24
Finished Jul 14 05:57:58 PM PDT 24
Peak memory 258580 kb
Host smart-3e153b0a-e04b-46a2-9f6c-2804067e4906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798942400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2798942400
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.383447601
Short name T465
Test name
Test status
Simulation time 44132914333 ps
CPU time 40.05 seconds
Started Jul 14 05:56:32 PM PDT 24
Finished Jul 14 05:57:13 PM PDT 24
Peak memory 235564 kb
Host smart-dce3f900-58da-4323-b118-7a626b2aadbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383447601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.383447601
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2023347378
Short name T702
Test name
Test status
Simulation time 640768598 ps
CPU time 4.29 seconds
Started Jul 14 05:56:36 PM PDT 24
Finished Jul 14 05:56:41 PM PDT 24
Peak memory 225548 kb
Host smart-eb69716e-2353-4c86-a7f3-7360ec2ad9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023347378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2023347378
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.873110458
Short name T739
Test name
Test status
Simulation time 342146362958 ps
CPU time 248.93 seconds
Started Jul 14 05:56:33 PM PDT 24
Finished Jul 14 06:00:43 PM PDT 24
Peak memory 254960 kb
Host smart-e369c76b-1af2-4981-a982-83e1810dba3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873110458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.873110458
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1258604069
Short name T423
Test name
Test status
Simulation time 4885769068 ps
CPU time 6.25 seconds
Started Jul 14 05:56:31 PM PDT 24
Finished Jul 14 05:56:37 PM PDT 24
Peak memory 233824 kb
Host smart-3ba308ca-ce6b-4d91-a607-a917a2ba2840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258604069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1258604069
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4201010219
Short name T217
Test name
Test status
Simulation time 14468803524 ps
CPU time 125.37 seconds
Started Jul 14 05:56:26 PM PDT 24
Finished Jul 14 05:58:32 PM PDT 24
Peak memory 238220 kb
Host smart-f6f70878-1772-4393-bf16-96f3adfd0b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201010219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4201010219
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2870468766
Short name T658
Test name
Test status
Simulation time 31017127 ps
CPU time 1.98 seconds
Started Jul 14 05:56:25 PM PDT 24
Finished Jul 14 05:56:27 PM PDT 24
Peak memory 225228 kb
Host smart-5ead5cb2-135b-479d-9e86-04e9937c4487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870468766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2870468766
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2604486191
Short name T551
Test name
Test status
Simulation time 9730467900 ps
CPU time 3.67 seconds
Started Jul 14 05:56:23 PM PDT 24
Finished Jul 14 05:56:27 PM PDT 24
Peak memory 225852 kb
Host smart-22f2001b-2734-45eb-bb7f-71897b54c923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604486191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2604486191
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2114384108
Short name T615
Test name
Test status
Simulation time 542037619 ps
CPU time 6.25 seconds
Started Jul 14 05:56:34 PM PDT 24
Finished Jul 14 05:56:40 PM PDT 24
Peak memory 219904 kb
Host smart-f6bfdc42-bb60-4cc8-98d1-5a4b73f6b723
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2114384108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2114384108
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2339145230
Short name T808
Test name
Test status
Simulation time 33678615691 ps
CPU time 359.98 seconds
Started Jul 14 05:56:33 PM PDT 24
Finished Jul 14 06:02:34 PM PDT 24
Peak memory 271488 kb
Host smart-7ac7367e-5733-44cc-ad9d-6c42514152ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339145230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2339145230
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.951619919
Short name T580
Test name
Test status
Simulation time 17926040803 ps
CPU time 26.14 seconds
Started Jul 14 05:56:24 PM PDT 24
Finished Jul 14 05:56:50 PM PDT 24
Peak memory 217436 kb
Host smart-a58a84df-c46e-403f-a8f1-80ac42c8eed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951619919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.951619919
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1599152457
Short name T428
Test name
Test status
Simulation time 14816992269 ps
CPU time 12.4 seconds
Started Jul 14 05:56:31 PM PDT 24
Finished Jul 14 05:56:44 PM PDT 24
Peak memory 218612 kb
Host smart-bbafa7a5-2fd9-415e-b68b-69ab19b4f4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599152457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1599152457
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3297294382
Short name T315
Test name
Test status
Simulation time 479456500 ps
CPU time 1.07 seconds
Started Jul 14 05:56:25 PM PDT 24
Finished Jul 14 05:56:26 PM PDT 24
Peak memory 207964 kb
Host smart-c25d66cf-3e28-4e95-885d-61b3d8c9a1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297294382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3297294382
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1014121658
Short name T471
Test name
Test status
Simulation time 145372523 ps
CPU time 0.79 seconds
Started Jul 14 05:56:25 PM PDT 24
Finished Jul 14 05:56:27 PM PDT 24
Peak memory 206940 kb
Host smart-64c5c45f-be82-4a61-b309-b7a89e05189a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014121658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1014121658
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2027212413
Short name T713
Test name
Test status
Simulation time 22830365504 ps
CPU time 25.99 seconds
Started Jul 14 05:56:32 PM PDT 24
Finished Jul 14 05:56:58 PM PDT 24
Peak memory 250624 kb
Host smart-dd2d3aa5-d836-44e3-8602-f9ff6282329a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027212413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2027212413
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.282711991
Short name T409
Test name
Test status
Simulation time 26939863 ps
CPU time 0.74 seconds
Started Jul 14 05:56:38 PM PDT 24
Finished Jul 14 05:56:39 PM PDT 24
Peak memory 206332 kb
Host smart-f1a2562d-a275-49f6-97c1-e29cbc07b092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282711991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.282711991
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.496676764
Short name T514
Test name
Test status
Simulation time 102509288 ps
CPU time 2.32 seconds
Started Jul 14 05:56:37 PM PDT 24
Finished Jul 14 05:56:40 PM PDT 24
Peak memory 233400 kb
Host smart-b29d8b70-125c-4e68-bdce-9e4b2b683c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496676764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.496676764
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1953313789
Short name T639
Test name
Test status
Simulation time 51185400 ps
CPU time 0.78 seconds
Started Jul 14 05:56:34 PM PDT 24
Finished Jul 14 05:56:35 PM PDT 24
Peak memory 207504 kb
Host smart-a5da16d1-8862-45ca-aa63-a94f4bb857f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953313789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1953313789
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3120056690
Short name T986
Test name
Test status
Simulation time 3061630298 ps
CPU time 41.99 seconds
Started Jul 14 05:56:39 PM PDT 24
Finished Jul 14 05:57:21 PM PDT 24
Peak memory 238012 kb
Host smart-1acb6ec8-33f0-4813-b5a7-1ab6729baf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120056690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3120056690
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1401452034
Short name T963
Test name
Test status
Simulation time 34845393753 ps
CPU time 118.96 seconds
Started Jul 14 05:56:37 PM PDT 24
Finished Jul 14 05:58:37 PM PDT 24
Peak memory 269340 kb
Host smart-8677f0a2-e909-43a1-a4f3-cd4c26ace8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401452034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1401452034
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1423243990
Short name T311
Test name
Test status
Simulation time 4255756414 ps
CPU time 27.1 seconds
Started Jul 14 05:56:39 PM PDT 24
Finished Jul 14 05:57:07 PM PDT 24
Peak memory 218772 kb
Host smart-beeb9653-1304-40bf-8774-d99982cf346a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423243990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1423243990
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.928479074
Short name T531
Test name
Test status
Simulation time 2000076285 ps
CPU time 18.86 seconds
Started Jul 14 05:56:37 PM PDT 24
Finished Jul 14 05:56:57 PM PDT 24
Peak memory 233792 kb
Host smart-82f75202-6382-4b22-a324-6e594c64b5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928479074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.928479074
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3562088563
Short name T366
Test name
Test status
Simulation time 4420788581 ps
CPU time 32.56 seconds
Started Jul 14 05:56:39 PM PDT 24
Finished Jul 14 05:57:13 PM PDT 24
Peak memory 242096 kb
Host smart-dc11653e-c7e6-4d1b-9083-92124581d909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562088563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3562088563
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1893696688
Short name T984
Test name
Test status
Simulation time 108056749 ps
CPU time 2.34 seconds
Started Jul 14 05:56:39 PM PDT 24
Finished Jul 14 05:56:42 PM PDT 24
Peak memory 219560 kb
Host smart-54b87b19-5877-4671-85c6-a0951fd8a16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893696688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1893696688
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4139926505
Short name T801
Test name
Test status
Simulation time 20256605123 ps
CPU time 54.12 seconds
Started Jul 14 05:56:40 PM PDT 24
Finished Jul 14 05:57:35 PM PDT 24
Peak memory 233908 kb
Host smart-9abead44-fe34-4616-a284-53bb609bc630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139926505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4139926505
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2124474166
Short name T52
Test name
Test status
Simulation time 52598163931 ps
CPU time 16.15 seconds
Started Jul 14 05:56:40 PM PDT 24
Finished Jul 14 05:56:57 PM PDT 24
Peak memory 241916 kb
Host smart-390065fc-bafe-47d0-9276-9abb777a6d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124474166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2124474166
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.4164961929
Short name T981
Test name
Test status
Simulation time 30347361 ps
CPU time 2.08 seconds
Started Jul 14 05:56:34 PM PDT 24
Finished Jul 14 05:56:36 PM PDT 24
Peak memory 224976 kb
Host smart-ee88b504-eabb-402b-8a78-c11abe5ddc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164961929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.4164961929
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1621722042
Short name T948
Test name
Test status
Simulation time 422685917 ps
CPU time 4.04 seconds
Started Jul 14 05:56:39 PM PDT 24
Finished Jul 14 05:56:43 PM PDT 24
Peak memory 224032 kb
Host smart-0e195917-514f-44bc-98cd-11c295011daf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1621722042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1621722042
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3153142709
Short name T131
Test name
Test status
Simulation time 7779020279 ps
CPU time 80.64 seconds
Started Jul 14 05:56:40 PM PDT 24
Finished Jul 14 05:58:01 PM PDT 24
Peak memory 266748 kb
Host smart-6f46deb7-ca67-4ec0-910a-9af447cab5a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153142709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3153142709
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.366117445
Short name T528
Test name
Test status
Simulation time 245224039 ps
CPU time 4.49 seconds
Started Jul 14 05:56:31 PM PDT 24
Finished Jul 14 05:56:37 PM PDT 24
Peak memory 220920 kb
Host smart-878036bf-0aa5-445d-bde8-dbf39c839ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366117445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.366117445
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3164610564
Short name T339
Test name
Test status
Simulation time 233367579 ps
CPU time 1.68 seconds
Started Jul 14 05:56:31 PM PDT 24
Finished Jul 14 05:56:33 PM PDT 24
Peak memory 208868 kb
Host smart-ff84daff-3e61-46f9-9873-81ca82fff34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164610564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3164610564
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2339324558
Short name T478
Test name
Test status
Simulation time 19056983 ps
CPU time 1.06 seconds
Started Jul 14 05:56:32 PM PDT 24
Finished Jul 14 05:56:34 PM PDT 24
Peak memory 208912 kb
Host smart-70ce3cb3-5ede-4d79-8d08-5fc39474403a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339324558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2339324558
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1195340660
Short name T582
Test name
Test status
Simulation time 27685130 ps
CPU time 0.72 seconds
Started Jul 14 05:56:30 PM PDT 24
Finished Jul 14 05:56:31 PM PDT 24
Peak memory 207000 kb
Host smart-c0ba0b48-de03-4f6c-9ec8-6f1bac4235a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195340660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1195340660
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3109039824
Short name T670
Test name
Test status
Simulation time 16099214810 ps
CPU time 11.1 seconds
Started Jul 14 05:56:39 PM PDT 24
Finished Jul 14 05:56:50 PM PDT 24
Peak memory 233876 kb
Host smart-2c1c380a-bcea-4497-82af-7aedd67ab4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109039824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3109039824
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3151319405
Short name T341
Test name
Test status
Simulation time 36955729 ps
CPU time 0.71 seconds
Started Jul 14 05:56:50 PM PDT 24
Finished Jul 14 05:56:51 PM PDT 24
Peak memory 206388 kb
Host smart-6b70de09-2011-493e-8fa1-223d19d9888d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151319405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3151319405
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3012726947
Short name T796
Test name
Test status
Simulation time 281617412 ps
CPU time 4.57 seconds
Started Jul 14 05:56:39 PM PDT 24
Finished Jul 14 05:56:44 PM PDT 24
Peak memory 225484 kb
Host smart-88db9b7f-7fa3-4349-81eb-76c70578facd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012726947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3012726947
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2239165668
Short name T436
Test name
Test status
Simulation time 41919655 ps
CPU time 0.74 seconds
Started Jul 14 05:56:39 PM PDT 24
Finished Jul 14 05:56:41 PM PDT 24
Peak memory 207808 kb
Host smart-5db1ccb0-e0d5-4477-8c96-160aa08fbb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239165668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2239165668
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2530802394
Short name T696
Test name
Test status
Simulation time 1653120576 ps
CPU time 11.62 seconds
Started Jul 14 05:56:52 PM PDT 24
Finished Jul 14 05:57:04 PM PDT 24
Peak memory 251884 kb
Host smart-2bdf75f5-24f1-40b6-b399-c45a4a54d6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530802394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2530802394
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2000403202
Short name T37
Test name
Test status
Simulation time 15443000197 ps
CPU time 160.12 seconds
Started Jul 14 05:56:50 PM PDT 24
Finished Jul 14 05:59:31 PM PDT 24
Peak memory 266796 kb
Host smart-b64d43af-0541-4160-b1b9-5e4a64a1734e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000403202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2000403202
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3075287942
Short name T856
Test name
Test status
Simulation time 477673707 ps
CPU time 10.76 seconds
Started Jul 14 05:56:52 PM PDT 24
Finished Jul 14 05:57:03 PM PDT 24
Peak memory 233820 kb
Host smart-22c7434c-3261-441c-9f7c-ab9587061366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075287942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3075287942
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.439084489
Short name T337
Test name
Test status
Simulation time 2763927234 ps
CPU time 9.96 seconds
Started Jul 14 05:56:38 PM PDT 24
Finished Jul 14 05:56:49 PM PDT 24
Peak memory 225664 kb
Host smart-6d2348a5-fd50-4a7f-9d88-22805348af0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439084489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.439084489
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1107101707
Short name T223
Test name
Test status
Simulation time 107854410464 ps
CPU time 370.67 seconds
Started Jul 14 05:56:51 PM PDT 24
Finished Jul 14 06:03:02 PM PDT 24
Peak memory 250176 kb
Host smart-3044f0f6-f549-4ad7-8f6e-48482a15503f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107101707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1107101707
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1143541054
Short name T250
Test name
Test status
Simulation time 592778934 ps
CPU time 5.34 seconds
Started Jul 14 05:56:36 PM PDT 24
Finished Jul 14 05:56:42 PM PDT 24
Peak memory 233708 kb
Host smart-87531243-b9e5-4e2f-a788-0b1c9aefbd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143541054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1143541054
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.4086787513
Short name T596
Test name
Test status
Simulation time 4543416382 ps
CPU time 42.92 seconds
Started Jul 14 05:56:37 PM PDT 24
Finished Jul 14 05:57:20 PM PDT 24
Peak memory 233832 kb
Host smart-6f6808d3-f2ed-4aa4-9615-25eecfacccb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086787513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4086787513
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2829368074
Short name T837
Test name
Test status
Simulation time 2895607481 ps
CPU time 8.01 seconds
Started Jul 14 05:56:38 PM PDT 24
Finished Jul 14 05:56:47 PM PDT 24
Peak memory 225560 kb
Host smart-b23d6129-c4c0-47b3-acb2-86d87bca49c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829368074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2829368074
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3477192040
Short name T196
Test name
Test status
Simulation time 4093815729 ps
CPU time 13.02 seconds
Started Jul 14 05:56:38 PM PDT 24
Finished Jul 14 05:56:51 PM PDT 24
Peak memory 233920 kb
Host smart-22aa88eb-4d28-4880-890d-a075ecfec810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477192040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3477192040
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.487469892
Short name T892
Test name
Test status
Simulation time 543355625 ps
CPU time 4.24 seconds
Started Jul 14 05:56:50 PM PDT 24
Finished Jul 14 05:56:54 PM PDT 24
Peak memory 223608 kb
Host smart-11284608-2ff7-45f1-9a23-89aed9a9b9fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=487469892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.487469892
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1567992278
Short name T153
Test name
Test status
Simulation time 76240909 ps
CPU time 1.04 seconds
Started Jul 14 05:56:53 PM PDT 24
Finished Jul 14 05:56:54 PM PDT 24
Peak memory 208592 kb
Host smart-8822865c-270d-4d7d-a0df-51dd514eb86e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567992278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1567992278
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1784225650
Short name T799
Test name
Test status
Simulation time 1807662446 ps
CPU time 20.07 seconds
Started Jul 14 05:56:38 PM PDT 24
Finished Jul 14 05:56:59 PM PDT 24
Peak memory 217340 kb
Host smart-2eca4704-b294-4972-81de-dce245c2aec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784225650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1784225650
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3447719113
Short name T448
Test name
Test status
Simulation time 530525776 ps
CPU time 2.06 seconds
Started Jul 14 05:56:40 PM PDT 24
Finished Jul 14 05:56:43 PM PDT 24
Peak memory 208880 kb
Host smart-e0adde9c-202b-4436-aba7-9cb138789a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447719113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3447719113
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3569528391
Short name T455
Test name
Test status
Simulation time 367051469 ps
CPU time 1.23 seconds
Started Jul 14 05:56:40 PM PDT 24
Finished Jul 14 05:56:42 PM PDT 24
Peak memory 208868 kb
Host smart-5bd8b0c3-f7eb-4ca0-a38d-d89454221ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569528391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3569528391
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3772764021
Short name T545
Test name
Test status
Simulation time 120700756 ps
CPU time 0.85 seconds
Started Jul 14 05:56:39 PM PDT 24
Finished Jul 14 05:56:41 PM PDT 24
Peak memory 206892 kb
Host smart-826bd8b3-de8c-4a36-aa94-6f83354afea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772764021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3772764021
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2136978170
Short name T913
Test name
Test status
Simulation time 7929580723 ps
CPU time 10.41 seconds
Started Jul 14 05:56:39 PM PDT 24
Finished Jul 14 05:56:50 PM PDT 24
Peak memory 225652 kb
Host smart-24dd1835-3129-4240-a05f-5453f7898fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136978170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2136978170
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.358635802
Short name T848
Test name
Test status
Simulation time 18463657 ps
CPU time 0.77 seconds
Started Jul 14 05:56:59 PM PDT 24
Finished Jul 14 05:57:00 PM PDT 24
Peak memory 206340 kb
Host smart-9e712414-f7db-44a8-b6a2-01098b2eda69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358635802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.358635802
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2290753449
Short name T633
Test name
Test status
Simulation time 153972581 ps
CPU time 2.41 seconds
Started Jul 14 05:56:52 PM PDT 24
Finished Jul 14 05:56:55 PM PDT 24
Peak memory 225460 kb
Host smart-c2b6f7e0-359c-4e3c-8380-539b678a52f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290753449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2290753449
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2008796428
Short name T585
Test name
Test status
Simulation time 269192688 ps
CPU time 0.79 seconds
Started Jul 14 05:56:54 PM PDT 24
Finished Jul 14 05:56:55 PM PDT 24
Peak memory 206432 kb
Host smart-b233f09e-5077-4e51-8b1d-653cb93d3c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008796428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2008796428
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2049788952
Short name T999
Test name
Test status
Simulation time 1828434568 ps
CPU time 18.87 seconds
Started Jul 14 05:57:01 PM PDT 24
Finished Jul 14 05:57:20 PM PDT 24
Peak memory 252524 kb
Host smart-29360f2c-8e7d-4f8f-b9ee-cd3369102ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049788952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2049788952
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.541963309
Short name T61
Test name
Test status
Simulation time 26889310993 ps
CPU time 165.48 seconds
Started Jul 14 05:56:57 PM PDT 24
Finished Jul 14 05:59:43 PM PDT 24
Peak memory 253696 kb
Host smart-0ab25967-eafe-44ca-a472-aee1fbce98d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541963309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.541963309
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.509078323
Short name T929
Test name
Test status
Simulation time 1551574199 ps
CPU time 6.73 seconds
Started Jul 14 05:56:50 PM PDT 24
Finished Jul 14 05:56:57 PM PDT 24
Peak memory 233708 kb
Host smart-49dc3c9c-e079-4980-be76-34726a10195e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509078323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.509078323
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.860939214
Short name T1020
Test name
Test status
Simulation time 586745686 ps
CPU time 10.27 seconds
Started Jul 14 05:56:50 PM PDT 24
Finished Jul 14 05:57:01 PM PDT 24
Peak memory 225488 kb
Host smart-958064ab-c6db-4346-a509-ef6ec2244935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860939214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.860939214
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.452399753
Short name T683
Test name
Test status
Simulation time 1595606190 ps
CPU time 6.26 seconds
Started Jul 14 05:56:54 PM PDT 24
Finished Jul 14 05:57:01 PM PDT 24
Peak memory 233800 kb
Host smart-1774539a-08b3-4e09-bbd0-61d517b687af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452399753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.452399753
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3232273765
Short name T202
Test name
Test status
Simulation time 947679772 ps
CPU time 4.93 seconds
Started Jul 14 05:56:54 PM PDT 24
Finished Jul 14 05:57:00 PM PDT 24
Peak memory 225512 kb
Host smart-ce68ee24-7cab-4993-af31-34977583e59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232273765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3232273765
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3093582573
Short name T269
Test name
Test status
Simulation time 4605667284 ps
CPU time 8.53 seconds
Started Jul 14 05:56:53 PM PDT 24
Finished Jul 14 05:57:02 PM PDT 24
Peak memory 233848 kb
Host smart-2e356d92-c137-4610-af36-963b1e93190f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093582573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3093582573
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1873241930
Short name T15
Test name
Test status
Simulation time 852841477 ps
CPU time 5.14 seconds
Started Jul 14 05:56:51 PM PDT 24
Finished Jul 14 05:56:57 PM PDT 24
Peak memory 233688 kb
Host smart-6ea64d4b-b915-454f-941e-d6276d396883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873241930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1873241930
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2417188418
Short name T367
Test name
Test status
Simulation time 163525526 ps
CPU time 3.87 seconds
Started Jul 14 05:56:51 PM PDT 24
Finished Jul 14 05:56:55 PM PDT 24
Peak memory 223580 kb
Host smart-8ffc854f-1c76-4062-abdd-e80bd6b5fa6f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2417188418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2417188418
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2086951986
Short name T329
Test name
Test status
Simulation time 870435629 ps
CPU time 2.8 seconds
Started Jul 14 05:56:49 PM PDT 24
Finished Jul 14 05:56:52 PM PDT 24
Peak memory 217388 kb
Host smart-314b3edf-5189-4f5e-82ba-3356bd62e425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086951986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2086951986
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.451474923
Short name T873
Test name
Test status
Simulation time 1104984109 ps
CPU time 5.78 seconds
Started Jul 14 05:56:51 PM PDT 24
Finished Jul 14 05:56:57 PM PDT 24
Peak memory 217296 kb
Host smart-3b096214-fda6-4523-b217-1cbec9b07ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451474923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.451474923
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.497222821
Short name T364
Test name
Test status
Simulation time 165202862 ps
CPU time 0.93 seconds
Started Jul 14 05:56:51 PM PDT 24
Finished Jul 14 05:56:53 PM PDT 24
Peak memory 208868 kb
Host smart-2f04c35e-f1f7-4fda-ab83-338ebd6ab5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497222821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.497222821
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1657659996
Short name T358
Test name
Test status
Simulation time 98670945 ps
CPU time 0.81 seconds
Started Jul 14 05:56:55 PM PDT 24
Finished Jul 14 05:56:56 PM PDT 24
Peak memory 206940 kb
Host smart-ecac75da-0892-43f8-9197-c7a1fa15cf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657659996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1657659996
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2544317149
Short name T775
Test name
Test status
Simulation time 38654859 ps
CPU time 2.12 seconds
Started Jul 14 05:56:51 PM PDT 24
Finished Jul 14 05:56:54 PM PDT 24
Peak memory 225596 kb
Host smart-b993cc45-bbd8-4c7c-adb7-cc8d29a705ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544317149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2544317149
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2633936655
Short name T879
Test name
Test status
Simulation time 18186144 ps
CPU time 0.73 seconds
Started Jul 14 05:57:03 PM PDT 24
Finished Jul 14 05:57:04 PM PDT 24
Peak memory 206340 kb
Host smart-8d95c1b5-f823-4a7f-b24d-7d1277e3a41d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633936655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2633936655
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2354834534
Short name T764
Test name
Test status
Simulation time 60305736 ps
CPU time 3.33 seconds
Started Jul 14 05:57:00 PM PDT 24
Finished Jul 14 05:57:04 PM PDT 24
Peak memory 233696 kb
Host smart-0eda6389-ffa9-47cb-b127-f52cedc31e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354834534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2354834534
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2961955609
Short name T829
Test name
Test status
Simulation time 19632717 ps
CPU time 0.81 seconds
Started Jul 14 05:57:00 PM PDT 24
Finished Jul 14 05:57:02 PM PDT 24
Peak memory 207400 kb
Host smart-ed5fde5a-7bb4-4b83-a69d-0c271aa613a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961955609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2961955609
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3550630604
Short name T961
Test name
Test status
Simulation time 103019868621 ps
CPU time 210.18 seconds
Started Jul 14 05:57:04 PM PDT 24
Finished Jul 14 06:00:34 PM PDT 24
Peak memory 254988 kb
Host smart-05bd92bf-d6e0-464a-ab2d-164cd9b8eb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550630604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3550630604
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.415891074
Short name T783
Test name
Test status
Simulation time 22504495610 ps
CPU time 31.83 seconds
Started Jul 14 05:56:59 PM PDT 24
Finished Jul 14 05:57:32 PM PDT 24
Peak memory 218720 kb
Host smart-5a9bd6f6-f882-4296-8579-7fdba5655c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415891074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.415891074
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1467624419
Short name T555
Test name
Test status
Simulation time 17314040855 ps
CPU time 183.12 seconds
Started Jul 14 05:57:01 PM PDT 24
Finished Jul 14 06:00:05 PM PDT 24
Peak memory 250356 kb
Host smart-58b9d9cc-9031-469a-8d7f-3bfc62d0216a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467624419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1467624419
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.992172665
Short name T491
Test name
Test status
Simulation time 46059730977 ps
CPU time 164.15 seconds
Started Jul 14 05:56:59 PM PDT 24
Finished Jul 14 05:59:44 PM PDT 24
Peak memory 253628 kb
Host smart-20fa49ab-633a-49b8-8f71-9d4d4be855d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992172665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.992172665
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1159482927
Short name T1003
Test name
Test status
Simulation time 2372963579 ps
CPU time 8.12 seconds
Started Jul 14 05:57:01 PM PDT 24
Finished Jul 14 05:57:10 PM PDT 24
Peak memory 225540 kb
Host smart-c67840a9-e388-4fe8-be50-c65cee486871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159482927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1159482927
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2006886637
Short name T399
Test name
Test status
Simulation time 1857827687 ps
CPU time 17.09 seconds
Started Jul 14 05:57:03 PM PDT 24
Finished Jul 14 05:57:21 PM PDT 24
Peak memory 225564 kb
Host smart-c289d68d-71be-4cda-a31e-0e41f0c2478c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006886637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2006886637
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2476859424
Short name T325
Test name
Test status
Simulation time 119437557 ps
CPU time 2.66 seconds
Started Jul 14 05:57:00 PM PDT 24
Finished Jul 14 05:57:03 PM PDT 24
Peak memory 233396 kb
Host smart-778a49f3-931b-43db-8899-b934d1e20710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476859424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2476859424
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2239179026
Short name T194
Test name
Test status
Simulation time 991574898 ps
CPU time 8.1 seconds
Started Jul 14 05:57:01 PM PDT 24
Finished Jul 14 05:57:10 PM PDT 24
Peak memory 237008 kb
Host smart-f6faffbd-e0ee-427c-b386-2999269c0be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239179026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2239179026
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3197168013
Short name T391
Test name
Test status
Simulation time 1507697309 ps
CPU time 16.41 seconds
Started Jul 14 05:57:00 PM PDT 24
Finished Jul 14 05:57:18 PM PDT 24
Peak memory 224056 kb
Host smart-c7f403a4-5ee4-4efc-8061-53e61ab28d39
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3197168013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3197168013
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1078688516
Short name T248
Test name
Test status
Simulation time 55107023615 ps
CPU time 251.83 seconds
Started Jul 14 05:57:00 PM PDT 24
Finished Jul 14 06:01:12 PM PDT 24
Peak memory 238280 kb
Host smart-a2ddfc01-c8db-4532-9229-3117ea8dd3fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078688516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1078688516
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1139532101
Short name T393
Test name
Test status
Simulation time 266705376 ps
CPU time 3.05 seconds
Started Jul 14 05:56:58 PM PDT 24
Finished Jul 14 05:57:01 PM PDT 24
Peak memory 219724 kb
Host smart-f62e3b0b-634e-422d-8c1d-c39f03df4acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139532101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1139532101
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2225019679
Short name T443
Test name
Test status
Simulation time 18335263 ps
CPU time 0.74 seconds
Started Jul 14 05:57:02 PM PDT 24
Finished Jul 14 05:57:03 PM PDT 24
Peak memory 206544 kb
Host smart-c5ab1b9e-2fa6-4ec5-8115-b71fad19d05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225019679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2225019679
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.979217113
Short name T336
Test name
Test status
Simulation time 34229037 ps
CPU time 0.73 seconds
Started Jul 14 05:57:00 PM PDT 24
Finished Jul 14 05:57:02 PM PDT 24
Peak memory 206948 kb
Host smart-5efa6516-5c1b-475a-8430-3e5778a4aa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979217113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.979217113
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.438494050
Short name T709
Test name
Test status
Simulation time 20962632 ps
CPU time 0.78 seconds
Started Jul 14 05:57:01 PM PDT 24
Finished Jul 14 05:57:02 PM PDT 24
Peak memory 206948 kb
Host smart-93eceba9-9a3b-48fe-bfab-dcb270b6c9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438494050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.438494050
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1747477599
Short name T407
Test name
Test status
Simulation time 2224576748 ps
CPU time 10.31 seconds
Started Jul 14 05:56:59 PM PDT 24
Finished Jul 14 05:57:09 PM PDT 24
Peak memory 241892 kb
Host smart-fa2e7500-73ed-426a-8953-06b2f093b50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747477599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1747477599
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.279127845
Short name T372
Test name
Test status
Simulation time 38899750 ps
CPU time 0.77 seconds
Started Jul 14 05:57:13 PM PDT 24
Finished Jul 14 05:57:15 PM PDT 24
Peak memory 206388 kb
Host smart-654efab4-4ddb-4534-97b8-239456c4dde6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279127845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.279127845
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2150628084
Short name T877
Test name
Test status
Simulation time 967039583 ps
CPU time 9.53 seconds
Started Jul 14 05:57:10 PM PDT 24
Finished Jul 14 05:57:20 PM PDT 24
Peak memory 225508 kb
Host smart-22fb4e58-56b0-455b-a173-f480d176062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150628084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2150628084
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3681514919
Short name T384
Test name
Test status
Simulation time 16214379 ps
CPU time 0.76 seconds
Started Jul 14 05:56:59 PM PDT 24
Finished Jul 14 05:57:01 PM PDT 24
Peak memory 206760 kb
Host smart-feb34dca-bf3e-4ac8-a9d2-60cb75f18650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681514919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3681514919
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2448168619
Short name T292
Test name
Test status
Simulation time 51382277807 ps
CPU time 360.3 seconds
Started Jul 14 05:57:10 PM PDT 24
Finished Jul 14 06:03:11 PM PDT 24
Peak memory 265484 kb
Host smart-9b4c8a78-2598-4f94-b02c-eb14abacde30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448168619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2448168619
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2003005632
Short name T54
Test name
Test status
Simulation time 57679364893 ps
CPU time 288.96 seconds
Started Jul 14 05:57:07 PM PDT 24
Finished Jul 14 06:01:56 PM PDT 24
Peak memory 258596 kb
Host smart-ebc45c57-fa4d-4460-acfb-8eb14ba20a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003005632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2003005632
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1539640816
Short name T134
Test name
Test status
Simulation time 777693684302 ps
CPU time 667.22 seconds
Started Jul 14 05:57:08 PM PDT 24
Finished Jul 14 06:08:15 PM PDT 24
Peak memory 263548 kb
Host smart-6f94fa31-80ba-4b54-9634-9ae91f76759d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539640816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1539640816
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.66925827
Short name T728
Test name
Test status
Simulation time 3076037877 ps
CPU time 31.11 seconds
Started Jul 14 05:57:13 PM PDT 24
Finished Jul 14 05:57:45 PM PDT 24
Peak memory 241896 kb
Host smart-279b2a66-6602-4dc0-9830-bbbbcfa7c625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66925827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.66925827
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2711522667
Short name T894
Test name
Test status
Simulation time 849628720 ps
CPU time 9.31 seconds
Started Jul 14 05:57:09 PM PDT 24
Finished Jul 14 05:57:19 PM PDT 24
Peak memory 225772 kb
Host smart-8c7b8c55-912a-4320-9a86-0fca4e39f8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711522667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2711522667
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2327645147
Short name T472
Test name
Test status
Simulation time 420432952 ps
CPU time 3.5 seconds
Started Jul 14 05:57:14 PM PDT 24
Finished Jul 14 05:57:18 PM PDT 24
Peak memory 219844 kb
Host smart-99fee536-9229-4943-838c-b9ae8a4a6c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327645147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2327645147
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2853620872
Short name T646
Test name
Test status
Simulation time 135635040 ps
CPU time 2.67 seconds
Started Jul 14 05:57:09 PM PDT 24
Finished Jul 14 05:57:13 PM PDT 24
Peak memory 233700 kb
Host smart-b3f9a6d1-cc27-4a6f-8c1d-09e6a8860d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853620872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2853620872
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2841314523
Short name T191
Test name
Test status
Simulation time 23133080083 ps
CPU time 33.44 seconds
Started Jul 14 05:57:07 PM PDT 24
Finished Jul 14 05:57:41 PM PDT 24
Peak memory 233788 kb
Host smart-6c6448cf-c8a3-4cc9-96bc-732d6bf38dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841314523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2841314523
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1188727932
Short name T819
Test name
Test status
Simulation time 758016999 ps
CPU time 6.77 seconds
Started Jul 14 05:57:12 PM PDT 24
Finished Jul 14 05:57:19 PM PDT 24
Peak memory 240404 kb
Host smart-e96a1bf1-7752-4e9e-83f7-0d59c4eb3b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188727932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1188727932
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2244292018
Short name T142
Test name
Test status
Simulation time 325742916 ps
CPU time 4.83 seconds
Started Jul 14 05:57:10 PM PDT 24
Finished Jul 14 05:57:16 PM PDT 24
Peak memory 221104 kb
Host smart-8038beb4-13fe-44d1-9f20-5bb3c7d17ff1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2244292018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2244292018
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1729518435
Short name T377
Test name
Test status
Simulation time 34825587 ps
CPU time 0.87 seconds
Started Jul 14 05:57:13 PM PDT 24
Finished Jul 14 05:57:15 PM PDT 24
Peak memory 206544 kb
Host smart-14078d29-6eb1-459d-b007-7583831b29c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729518435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1729518435
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2007949925
Short name T773
Test name
Test status
Simulation time 1139296695 ps
CPU time 6.38 seconds
Started Jul 14 05:57:00 PM PDT 24
Finished Jul 14 05:57:07 PM PDT 24
Peak memory 217468 kb
Host smart-756040e5-6c91-49fc-b94e-62334247103f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007949925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2007949925
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.4152297722
Short name T647
Test name
Test status
Simulation time 17452873716 ps
CPU time 13.44 seconds
Started Jul 14 05:56:58 PM PDT 24
Finished Jul 14 05:57:12 PM PDT 24
Peak memory 217392 kb
Host smart-ec92741b-4e9d-4c39-b633-ebf82f25e0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152297722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.4152297722
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2034818380
Short name T716
Test name
Test status
Simulation time 106514187 ps
CPU time 1.19 seconds
Started Jul 14 05:57:07 PM PDT 24
Finished Jul 14 05:57:09 PM PDT 24
Peak memory 208968 kb
Host smart-354a849b-77e4-461e-bf2a-8563b975095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034818380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2034818380
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.4169104447
Short name T518
Test name
Test status
Simulation time 96553519 ps
CPU time 0.95 seconds
Started Jul 14 05:57:10 PM PDT 24
Finished Jul 14 05:57:12 PM PDT 24
Peak memory 207368 kb
Host smart-6da9bf5f-867e-45ad-851f-e734d3663a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169104447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4169104447
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.795842044
Short name T965
Test name
Test status
Simulation time 130072939 ps
CPU time 2.63 seconds
Started Jul 14 05:57:12 PM PDT 24
Finished Jul 14 05:57:16 PM PDT 24
Peak memory 233492 kb
Host smart-9b0c74c1-8e97-44d2-bea3-a0c4b26ce7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795842044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.795842044
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1620732282
Short name T70
Test name
Test status
Simulation time 113814056 ps
CPU time 0.72 seconds
Started Jul 14 05:57:15 PM PDT 24
Finished Jul 14 05:57:16 PM PDT 24
Peak memory 205716 kb
Host smart-f3f5e6ce-a6c7-44bf-ba26-74ec03a242cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620732282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1620732282
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.4106490591
Short name T608
Test name
Test status
Simulation time 3005540214 ps
CPU time 12.8 seconds
Started Jul 14 05:57:13 PM PDT 24
Finished Jul 14 05:57:27 PM PDT 24
Peak memory 225664 kb
Host smart-0b50be12-25da-405a-be2f-b0b7c14c60d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106490591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.4106490591
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.265017534
Short name T745
Test name
Test status
Simulation time 37046741 ps
CPU time 0.79 seconds
Started Jul 14 05:57:08 PM PDT 24
Finished Jul 14 05:57:10 PM PDT 24
Peak memory 207480 kb
Host smart-5f4a8396-14e3-4ff6-96cd-fc8095d93a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265017534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.265017534
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2876554673
Short name T643
Test name
Test status
Simulation time 10964642599 ps
CPU time 83.95 seconds
Started Jul 14 05:57:15 PM PDT 24
Finished Jul 14 05:58:40 PM PDT 24
Peak memory 251628 kb
Host smart-1bc56683-3e64-4afc-8c06-b90676f56fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876554673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2876554673
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3373622116
Short name T65
Test name
Test status
Simulation time 30590475396 ps
CPU time 235.58 seconds
Started Jul 14 05:57:16 PM PDT 24
Finished Jul 14 06:01:13 PM PDT 24
Peak memory 250360 kb
Host smart-2129ebf0-d27f-4d62-aa05-f8942d7a0c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373622116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3373622116
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3276834089
Short name T872
Test name
Test status
Simulation time 33428277749 ps
CPU time 330.95 seconds
Started Jul 14 05:57:17 PM PDT 24
Finished Jul 14 06:02:49 PM PDT 24
Peak memory 258068 kb
Host smart-53a5b3af-5be0-4718-940b-54432f3afecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276834089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3276834089
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1165658638
Short name T694
Test name
Test status
Simulation time 16786881775 ps
CPU time 56.42 seconds
Started Jul 14 05:57:13 PM PDT 24
Finished Jul 14 05:58:10 PM PDT 24
Peak memory 251236 kb
Host smart-1f7ca3fb-db91-472c-a724-4c109e47a520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165658638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1165658638
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3017013301
Short name T690
Test name
Test status
Simulation time 56284691279 ps
CPU time 120.07 seconds
Started Jul 14 05:57:18 PM PDT 24
Finished Jul 14 05:59:19 PM PDT 24
Peak memory 253388 kb
Host smart-f822e6fe-1c02-4864-bdd4-c49ac530caf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017013301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3017013301
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2692009559
Short name T487
Test name
Test status
Simulation time 115428355 ps
CPU time 4.17 seconds
Started Jul 14 05:57:09 PM PDT 24
Finished Jul 14 05:57:13 PM PDT 24
Peak memory 233748 kb
Host smart-6055d520-8d04-47ba-b700-541f3fce48eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692009559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2692009559
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1131731798
Short name T1009
Test name
Test status
Simulation time 4735657951 ps
CPU time 24.19 seconds
Started Jul 14 05:57:08 PM PDT 24
Finished Jul 14 05:57:33 PM PDT 24
Peak memory 225528 kb
Host smart-1eee7a68-eff0-4863-864b-31a7484bfc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131731798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1131731798
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.235774928
Short name T62
Test name
Test status
Simulation time 2423269261 ps
CPU time 9.53 seconds
Started Jul 14 05:57:13 PM PDT 24
Finished Jul 14 05:57:24 PM PDT 24
Peak memory 241820 kb
Host smart-6745d899-2ab3-48b3-863c-66e6ebda168a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235774928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.235774928
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4127408403
Short name T579
Test name
Test status
Simulation time 2051544725 ps
CPU time 10.27 seconds
Started Jul 14 05:57:10 PM PDT 24
Finished Jul 14 05:57:21 PM PDT 24
Peak memory 233736 kb
Host smart-42f322fd-a974-4b92-9b96-ad30b7d43dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127408403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4127408403
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3483413274
Short name T356
Test name
Test status
Simulation time 7069044975 ps
CPU time 15.93 seconds
Started Jul 14 05:57:21 PM PDT 24
Finished Jul 14 05:57:38 PM PDT 24
Peak memory 221840 kb
Host smart-abc01fee-4c3f-4519-a252-b8d369c5d7ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3483413274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3483413274
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3752874895
Short name T804
Test name
Test status
Simulation time 34201671122 ps
CPU time 194.63 seconds
Started Jul 14 05:57:20 PM PDT 24
Finished Jul 14 06:00:36 PM PDT 24
Peak memory 283144 kb
Host smart-a4a4e577-6103-4316-abdf-e26857cc89f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752874895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3752874895
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1667008583
Short name T671
Test name
Test status
Simulation time 3557266626 ps
CPU time 6.55 seconds
Started Jul 14 05:57:10 PM PDT 24
Finished Jul 14 05:57:17 PM PDT 24
Peak memory 217540 kb
Host smart-4ff68790-84ff-464b-9163-5a6406f2fec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667008583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1667008583
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3360366691
Short name T953
Test name
Test status
Simulation time 11815447 ps
CPU time 0.73 seconds
Started Jul 14 05:57:06 PM PDT 24
Finished Jul 14 05:57:07 PM PDT 24
Peak memory 206612 kb
Host smart-a4fb3446-9013-4baf-9eff-0cf3c7d660e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360366691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3360366691
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3672176439
Short name T864
Test name
Test status
Simulation time 46809030 ps
CPU time 1.04 seconds
Started Jul 14 05:57:09 PM PDT 24
Finished Jul 14 05:57:10 PM PDT 24
Peak memory 208272 kb
Host smart-13c1c693-3e65-45aa-ab4d-01f4ca6eee8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672176439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3672176439
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3484236829
Short name T988
Test name
Test status
Simulation time 139068851 ps
CPU time 0.81 seconds
Started Jul 14 05:57:06 PM PDT 24
Finished Jul 14 05:57:07 PM PDT 24
Peak memory 206944 kb
Host smart-6b1f715f-b93f-4d82-9435-23db05e1393f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484236829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3484236829
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1423922993
Short name T530
Test name
Test status
Simulation time 78652400 ps
CPU time 2.73 seconds
Started Jul 14 05:57:13 PM PDT 24
Finished Jul 14 05:57:17 PM PDT 24
Peak memory 233748 kb
Host smart-88fa5557-fc33-43ec-9977-da8e2e91fa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423922993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1423922993
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.983167657
Short name T346
Test name
Test status
Simulation time 12734784 ps
CPU time 0.72 seconds
Started Jul 14 05:57:24 PM PDT 24
Finished Jul 14 05:57:25 PM PDT 24
Peak memory 205764 kb
Host smart-cbfc87ed-8354-4cef-9faa-bc0ca8bba6f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983167657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.983167657
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2931434559
Short name T990
Test name
Test status
Simulation time 120182149 ps
CPU time 2.43 seconds
Started Jul 14 05:57:15 PM PDT 24
Finished Jul 14 05:57:18 PM PDT 24
Peak memory 233508 kb
Host smart-c4819be8-a20d-4174-a4f3-57c8c4be631b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931434559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2931434559
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2657746712
Short name T60
Test name
Test status
Simulation time 14262093 ps
CPU time 0.78 seconds
Started Jul 14 05:57:16 PM PDT 24
Finished Jul 14 05:57:17 PM PDT 24
Peak memory 206764 kb
Host smart-9a48f1b9-9b57-41c8-a522-fd315649161b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657746712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2657746712
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.361875013
Short name T744
Test name
Test status
Simulation time 66676175406 ps
CPU time 193.07 seconds
Started Jul 14 05:57:15 PM PDT 24
Finished Jul 14 06:00:29 PM PDT 24
Peak memory 258084 kb
Host smart-3d1c94cc-1966-4532-813d-9ac429575a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361875013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.361875013
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.68398581
Short name T859
Test name
Test status
Simulation time 155644782346 ps
CPU time 238.72 seconds
Started Jul 14 05:57:18 PM PDT 24
Finished Jul 14 06:01:18 PM PDT 24
Peak memory 250848 kb
Host smart-77aa90e1-6fdd-4e7f-ab19-702121cd13ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68398581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.68398581
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1217626263
Short name T7
Test name
Test status
Simulation time 4942300881 ps
CPU time 75.62 seconds
Started Jul 14 05:57:20 PM PDT 24
Finished Jul 14 05:58:37 PM PDT 24
Peak memory 253076 kb
Host smart-ccfb5794-e48a-4c0e-9391-496e99fe128f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217626263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1217626263
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.391307112
Short name T179
Test name
Test status
Simulation time 32861935068 ps
CPU time 101.25 seconds
Started Jul 14 05:57:16 PM PDT 24
Finished Jul 14 05:58:58 PM PDT 24
Peak memory 258440 kb
Host smart-186c6c61-459f-439d-93a3-dec0cf05473a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391307112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.391307112
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3594271368
Short name T467
Test name
Test status
Simulation time 285847454 ps
CPU time 3.97 seconds
Started Jul 14 05:57:17 PM PDT 24
Finished Jul 14 05:57:22 PM PDT 24
Peak memory 233676 kb
Host smart-c0d2f04a-2f90-4137-9154-b53912984641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594271368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3594271368
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.803457217
Short name T790
Test name
Test status
Simulation time 98205888 ps
CPU time 4.39 seconds
Started Jul 14 05:57:14 PM PDT 24
Finished Jul 14 05:57:19 PM PDT 24
Peak memory 233712 kb
Host smart-05d4ca1b-4b1b-454b-be64-69fe62a7ae9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803457217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.803457217
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3141738356
Short name T756
Test name
Test status
Simulation time 1358607616 ps
CPU time 9.17 seconds
Started Jul 14 05:57:16 PM PDT 24
Finished Jul 14 05:57:27 PM PDT 24
Peak memory 233756 kb
Host smart-cf575f56-02b2-4a3f-887b-167bc144bcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141738356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3141738356
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.4292495119
Short name T832
Test name
Test status
Simulation time 11483761703 ps
CPU time 11.84 seconds
Started Jul 14 05:57:16 PM PDT 24
Finished Jul 14 05:57:29 PM PDT 24
Peak memory 233860 kb
Host smart-d95f2c82-5405-4ba1-8227-3983a39264f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292495119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.4292495119
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3235997582
Short name T141
Test name
Test status
Simulation time 725957144 ps
CPU time 3.68 seconds
Started Jul 14 05:57:16 PM PDT 24
Finished Jul 14 05:57:21 PM PDT 24
Peak memory 219964 kb
Host smart-bb45c29a-a26e-432d-be2b-4a35635804e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3235997582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3235997582
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2192767388
Short name T312
Test name
Test status
Simulation time 1917015225 ps
CPU time 10.75 seconds
Started Jul 14 05:57:16 PM PDT 24
Finished Jul 14 05:57:28 PM PDT 24
Peak memory 217308 kb
Host smart-1fcf1985-11d5-4baf-a7d4-6a8979dbc378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192767388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2192767388
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2340228648
Short name T918
Test name
Test status
Simulation time 2621441240 ps
CPU time 2.94 seconds
Started Jul 14 05:57:16 PM PDT 24
Finished Jul 14 05:57:20 PM PDT 24
Peak memory 217480 kb
Host smart-66c6dd07-61b8-41b2-816a-1d2d6a77ea5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340228648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2340228648
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.666224040
Short name T435
Test name
Test status
Simulation time 1225036607 ps
CPU time 3.62 seconds
Started Jul 14 05:57:16 PM PDT 24
Finished Jul 14 05:57:21 PM PDT 24
Peak memory 217328 kb
Host smart-5ade8f58-ef16-446b-9b34-be4d1dd3c9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666224040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.666224040
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1553215325
Short name T939
Test name
Test status
Simulation time 56073617 ps
CPU time 0.91 seconds
Started Jul 14 05:57:15 PM PDT 24
Finished Jul 14 05:57:17 PM PDT 24
Peak memory 207356 kb
Host smart-4801da0e-b0c8-493b-9f6a-bc9f058abff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553215325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1553215325
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2178525234
Short name T811
Test name
Test status
Simulation time 88567407 ps
CPU time 2.98 seconds
Started Jul 14 05:57:15 PM PDT 24
Finished Jul 14 05:57:19 PM PDT 24
Peak memory 233764 kb
Host smart-07b9e202-14e1-4cbe-a29d-01f9f57fc7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178525234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2178525234
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1174551350
Short name T884
Test name
Test status
Simulation time 17368039 ps
CPU time 0.7 seconds
Started Jul 14 05:57:31 PM PDT 24
Finished Jul 14 05:57:32 PM PDT 24
Peak memory 206348 kb
Host smart-ec6bc7f0-0f27-47ef-80db-dfd5c61b5e08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174551350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1174551350
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.228831686
Short name T416
Test name
Test status
Simulation time 6072614805 ps
CPU time 7.75 seconds
Started Jul 14 05:57:25 PM PDT 24
Finished Jul 14 05:57:34 PM PDT 24
Peak memory 225712 kb
Host smart-d7739267-b394-4fad-9a2d-48383f103448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228831686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.228831686
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3289416673
Short name T334
Test name
Test status
Simulation time 54111608 ps
CPU time 0.8 seconds
Started Jul 14 05:57:29 PM PDT 24
Finished Jul 14 05:57:30 PM PDT 24
Peak memory 207468 kb
Host smart-54d7d7d0-9961-428f-8abb-adebb4eb9471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289416673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3289416673
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1390244654
Short name T293
Test name
Test status
Simulation time 3413749451 ps
CPU time 68.29 seconds
Started Jul 14 05:57:24 PM PDT 24
Finished Jul 14 05:58:33 PM PDT 24
Peak memory 253592 kb
Host smart-d95f92c9-71b3-49c6-8857-bfc03ee10dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390244654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1390244654
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1636933273
Short name T324
Test name
Test status
Simulation time 48316248625 ps
CPU time 161.51 seconds
Started Jul 14 05:57:21 PM PDT 24
Finished Jul 14 06:00:03 PM PDT 24
Peak memory 250428 kb
Host smart-388099b1-07e7-48a8-aa3e-8beb46809edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636933273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1636933273
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3057576975
Short name T542
Test name
Test status
Simulation time 329484239 ps
CPU time 4.82 seconds
Started Jul 14 05:57:23 PM PDT 24
Finished Jul 14 05:57:28 PM PDT 24
Peak memory 235048 kb
Host smart-e69756c3-841a-48c7-94cd-6b67c44d87bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057576975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3057576975
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2564555520
Short name T578
Test name
Test status
Simulation time 1609956227 ps
CPU time 18.82 seconds
Started Jul 14 05:57:23 PM PDT 24
Finished Jul 14 05:57:43 PM PDT 24
Peak memory 225556 kb
Host smart-f9f8cb75-14e3-49a7-91d8-1b6fb1accf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564555520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2564555520
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.348343263
Short name T842
Test name
Test status
Simulation time 13131284 ps
CPU time 0.75 seconds
Started Jul 14 05:57:23 PM PDT 24
Finished Jul 14 05:57:25 PM PDT 24
Peak memory 216900 kb
Host smart-04cef5e5-1f31-4909-8c8c-cfcaff17a522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348343263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.348343263
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3029426204
Short name T598
Test name
Test status
Simulation time 329375642 ps
CPU time 3.55 seconds
Started Jul 14 05:57:23 PM PDT 24
Finished Jul 14 05:57:28 PM PDT 24
Peak memory 229820 kb
Host smart-3e4d57f3-ced8-4c3b-8082-913f0d00909a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029426204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3029426204
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1424370422
Short name T519
Test name
Test status
Simulation time 9583038060 ps
CPU time 25.71 seconds
Started Jul 14 05:57:23 PM PDT 24
Finished Jul 14 05:57:50 PM PDT 24
Peak memory 225632 kb
Host smart-443c685b-4a9d-439f-83d1-1139ec1f39fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424370422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1424370422
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.836087371
Short name T56
Test name
Test status
Simulation time 104243142852 ps
CPU time 22.47 seconds
Started Jul 14 05:57:23 PM PDT 24
Finished Jul 14 05:57:46 PM PDT 24
Peak memory 241964 kb
Host smart-6c85e48e-fd94-4f14-97dd-3ff6081602b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836087371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.836087371
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.862634610
Short name T847
Test name
Test status
Simulation time 4554181153 ps
CPU time 15.87 seconds
Started Jul 14 05:57:25 PM PDT 24
Finished Jul 14 05:57:41 PM PDT 24
Peak memory 233804 kb
Host smart-902b0b05-6ad9-42f6-8288-19cb8ae6fa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862634610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.862634610
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.98942784
Short name T797
Test name
Test status
Simulation time 961264707 ps
CPU time 12.27 seconds
Started Jul 14 05:57:27 PM PDT 24
Finished Jul 14 05:57:41 PM PDT 24
Peak memory 221196 kb
Host smart-b9c4bcdf-0b76-41bf-beeb-aaea1fad5ec3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=98942784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direc
t.98942784
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3864414482
Short name T983
Test name
Test status
Simulation time 9149734013 ps
CPU time 36.68 seconds
Started Jul 14 05:57:30 PM PDT 24
Finished Jul 14 05:58:08 PM PDT 24
Peak memory 239664 kb
Host smart-dac1459b-7c42-4250-8574-b210ae5a6fc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864414482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3864414482
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.897925760
Short name T611
Test name
Test status
Simulation time 7097723793 ps
CPU time 27.83 seconds
Started Jul 14 05:57:24 PM PDT 24
Finished Jul 14 05:57:53 PM PDT 24
Peak memory 217376 kb
Host smart-c9703022-7f2b-4463-b13a-d32bf44a430f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897925760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.897925760
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3393876335
Short name T613
Test name
Test status
Simulation time 16828145933 ps
CPU time 13.17 seconds
Started Jul 14 05:57:25 PM PDT 24
Finished Jul 14 05:57:38 PM PDT 24
Peak memory 217440 kb
Host smart-1909a6d4-d439-47ec-a115-a722e096f044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393876335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3393876335
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.751599976
Short name T434
Test name
Test status
Simulation time 181623892 ps
CPU time 2.24 seconds
Started Jul 14 05:57:23 PM PDT 24
Finished Jul 14 05:57:26 PM PDT 24
Peak memory 217336 kb
Host smart-1c683e98-7e4d-4dd4-8202-888c2e94cf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751599976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.751599976
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.742490944
Short name T547
Test name
Test status
Simulation time 20882492 ps
CPU time 0.77 seconds
Started Jul 14 05:57:22 PM PDT 24
Finished Jul 14 05:57:23 PM PDT 24
Peak memory 206856 kb
Host smart-d1fdb325-dcc4-49dd-8241-b3e8c26b13ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742490944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.742490944
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1849067977
Short name T791
Test name
Test status
Simulation time 375744482 ps
CPU time 3.17 seconds
Started Jul 14 05:57:23 PM PDT 24
Finished Jul 14 05:57:27 PM PDT 24
Peak memory 233744 kb
Host smart-edc5c2f7-b8c7-4edb-a886-ab3eb09ead3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849067977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1849067977
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2193680354
Short name T381
Test name
Test status
Simulation time 30446841 ps
CPU time 0.71 seconds
Started Jul 14 05:51:37 PM PDT 24
Finished Jul 14 05:51:39 PM PDT 24
Peak memory 206244 kb
Host smart-0d74a751-1219-4b2c-ba79-bf18fd42a475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193680354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
193680354
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.29665405
Short name T398
Test name
Test status
Simulation time 733347955 ps
CPU time 8.36 seconds
Started Jul 14 05:51:37 PM PDT 24
Finished Jul 14 05:51:45 PM PDT 24
Peak memory 225544 kb
Host smart-cbe031fd-1f00-4b2f-aba9-69b64c9838be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29665405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.29665405
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.741930735
Short name T843
Test name
Test status
Simulation time 22869464 ps
CPU time 0.77 seconds
Started Jul 14 05:51:32 PM PDT 24
Finished Jul 14 05:51:34 PM PDT 24
Peak memory 207400 kb
Host smart-a36c525f-3672-4368-bfdb-5b298b833fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741930735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.741930735
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1341069543
Short name T169
Test name
Test status
Simulation time 1599885215 ps
CPU time 19.59 seconds
Started Jul 14 05:51:38 PM PDT 24
Finished Jul 14 05:51:58 PM PDT 24
Peak memory 241928 kb
Host smart-4222a966-b7d4-4727-9b4b-a283e4687292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341069543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1341069543
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3026585743
Short name T978
Test name
Test status
Simulation time 7550942612 ps
CPU time 55.28 seconds
Started Jul 14 05:51:37 PM PDT 24
Finished Jul 14 05:52:33 PM PDT 24
Peak memory 253612 kb
Host smart-8afe30d8-39e1-4d52-8433-7554306f75fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026585743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3026585743
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.898576500
Short name T992
Test name
Test status
Simulation time 3760084613 ps
CPU time 88.04 seconds
Started Jul 14 05:51:40 PM PDT 24
Finished Jul 14 05:53:09 PM PDT 24
Peak memory 266960 kb
Host smart-5dfe3cb4-36e4-4d43-b154-6a58ad83787a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898576500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
898576500
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2306285061
Short name T692
Test name
Test status
Simulation time 559309158 ps
CPU time 5.69 seconds
Started Jul 14 05:51:37 PM PDT 24
Finished Jul 14 05:51:43 PM PDT 24
Peak memory 236360 kb
Host smart-b645d9fd-7557-4efa-a0fb-6ed525ebddf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306285061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2306285061
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1610968901
Short name T637
Test name
Test status
Simulation time 132265944 ps
CPU time 0.76 seconds
Started Jul 14 05:51:39 PM PDT 24
Finished Jul 14 05:51:40 PM PDT 24
Peak memory 216832 kb
Host smart-e01d1ff5-3bde-41bd-ba4d-1d471289000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610968901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1610968901
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.626376752
Short name T1025
Test name
Test status
Simulation time 2850017327 ps
CPU time 8.26 seconds
Started Jul 14 05:51:37 PM PDT 24
Finished Jul 14 05:51:47 PM PDT 24
Peak memory 233904 kb
Host smart-0ad8d9a2-353f-4535-9114-a1c880bf50ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626376752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.626376752
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3532561434
Short name T386
Test name
Test status
Simulation time 5301574650 ps
CPU time 10.74 seconds
Started Jul 14 05:51:38 PM PDT 24
Finished Jul 14 05:51:49 PM PDT 24
Peak memory 225728 kb
Host smart-94b2d170-2d8a-4d35-8714-3f754889d76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532561434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3532561434
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.812472901
Short name T44
Test name
Test status
Simulation time 118205688 ps
CPU time 0.99 seconds
Started Jul 14 05:51:29 PM PDT 24
Finished Jul 14 05:51:31 PM PDT 24
Peak memory 218888 kb
Host smart-bba16213-56f7-471b-a475-3840ba91caca
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812472901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.812472901
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3117144793
Short name T270
Test name
Test status
Simulation time 690814460 ps
CPU time 10.03 seconds
Started Jul 14 05:51:31 PM PDT 24
Finished Jul 14 05:51:42 PM PDT 24
Peak memory 233772 kb
Host smart-c78ea7ba-91e4-45e3-84c4-109c8a7486cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117144793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3117144793
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3717881188
Short name T730
Test name
Test status
Simulation time 336278662 ps
CPU time 2.88 seconds
Started Jul 14 05:51:30 PM PDT 24
Finished Jul 14 05:51:34 PM PDT 24
Peak memory 233672 kb
Host smart-d099a4cf-7dde-44cf-8af8-acc3b7819d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717881188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3717881188
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.513282114
Short name T11
Test name
Test status
Simulation time 2079605144 ps
CPU time 5.8 seconds
Started Jul 14 05:51:38 PM PDT 24
Finished Jul 14 05:51:45 PM PDT 24
Peak memory 224136 kb
Host smart-440eb48e-bc47-4d12-89f6-cfe53a2d020a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=513282114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.513282114
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1891271396
Short name T936
Test name
Test status
Simulation time 5786602702 ps
CPU time 68.96 seconds
Started Jul 14 05:51:38 PM PDT 24
Finished Jul 14 05:52:48 PM PDT 24
Peak memory 250396 kb
Host smart-1c1108a4-2797-4a98-9653-19a133a82967
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891271396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1891271396
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1286154244
Short name T675
Test name
Test status
Simulation time 3572998087 ps
CPU time 10.06 seconds
Started Jul 14 05:51:29 PM PDT 24
Finished Jul 14 05:51:40 PM PDT 24
Peak memory 220928 kb
Host smart-dcef7802-a83e-437c-89b3-3519e1b3254e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286154244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1286154244
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1319788959
Short name T28
Test name
Test status
Simulation time 1014649033 ps
CPU time 2.9 seconds
Started Jul 14 05:51:30 PM PDT 24
Finished Jul 14 05:51:33 PM PDT 24
Peak memory 217292 kb
Host smart-70208e56-65c1-40f6-b43a-4769d23e33a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319788959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1319788959
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2465668684
Short name T10
Test name
Test status
Simulation time 441653497 ps
CPU time 2.28 seconds
Started Jul 14 05:51:29 PM PDT 24
Finished Jul 14 05:51:32 PM PDT 24
Peak memory 217320 kb
Host smart-f31d4eff-ab8c-4412-9c60-df5b1922d180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465668684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2465668684
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1620359252
Short name T548
Test name
Test status
Simulation time 60151470 ps
CPU time 0.92 seconds
Started Jul 14 05:51:28 PM PDT 24
Finished Jul 14 05:51:29 PM PDT 24
Peak memory 206908 kb
Host smart-b5aa3d42-a96b-4ae2-9382-f5587a2a3282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620359252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1620359252
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.4235051516
Short name T616
Test name
Test status
Simulation time 2726323762 ps
CPU time 7.71 seconds
Started Jul 14 05:51:36 PM PDT 24
Finished Jul 14 05:51:45 PM PDT 24
Peak memory 233844 kb
Host smart-13c8ddc8-76db-431b-a4e5-67a1abba74ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235051516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4235051516
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.4139092198
Short name T868
Test name
Test status
Simulation time 12774912 ps
CPU time 0.75 seconds
Started Jul 14 05:51:56 PM PDT 24
Finished Jul 14 05:51:57 PM PDT 24
Peak memory 206004 kb
Host smart-4697e5d3-3ae0-4bf2-b3d0-73c565c4795a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139092198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.4
139092198
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2405571862
Short name T244
Test name
Test status
Simulation time 583421217 ps
CPU time 3.65 seconds
Started Jul 14 05:51:45 PM PDT 24
Finished Jul 14 05:51:50 PM PDT 24
Peak memory 233776 kb
Host smart-a59f9496-7b53-4593-8060-c57ad04dcf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405571862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2405571862
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1666592892
Short name T610
Test name
Test status
Simulation time 53679651 ps
CPU time 0.77 seconds
Started Jul 14 05:51:37 PM PDT 24
Finished Jul 14 05:51:39 PM PDT 24
Peak memory 206816 kb
Host smart-a338dc65-cbd1-4519-a16c-4892fae33f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666592892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1666592892
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2298053496
Short name T184
Test name
Test status
Simulation time 71954056055 ps
CPU time 268.68 seconds
Started Jul 14 05:51:45 PM PDT 24
Finished Jul 14 05:56:15 PM PDT 24
Peak memory 251772 kb
Host smart-11e3e1ac-d1e4-407a-876d-038b14953008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298053496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2298053496
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1086607091
Short name T295
Test name
Test status
Simulation time 1616035615 ps
CPU time 6.41 seconds
Started Jul 14 05:51:47 PM PDT 24
Finished Jul 14 05:51:53 PM PDT 24
Peak memory 225560 kb
Host smart-0daa9738-fa6d-4799-a21a-3b6daa1d361e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086607091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1086607091
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2079986517
Short name T234
Test name
Test status
Simulation time 2014602558 ps
CPU time 44.69 seconds
Started Jul 14 05:51:45 PM PDT 24
Finished Jul 14 05:52:30 PM PDT 24
Peak memory 256388 kb
Host smart-94fa76e7-3722-4604-b11d-d86983d93985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079986517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2079986517
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2884574243
Short name T562
Test name
Test status
Simulation time 3309283593 ps
CPU time 9.12 seconds
Started Jul 14 05:51:50 PM PDT 24
Finished Jul 14 05:52:00 PM PDT 24
Peak memory 225664 kb
Host smart-a651b19a-9039-4310-9809-05f50baf4801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884574243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2884574243
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3297746248
Short name T267
Test name
Test status
Simulation time 1668694833 ps
CPU time 15.53 seconds
Started Jul 14 05:51:47 PM PDT 24
Finished Jul 14 05:52:03 PM PDT 24
Peak memory 241932 kb
Host smart-4baefab3-bbd0-419d-8f80-6e757d0e672d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297746248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3297746248
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2505322530
Short name T798
Test name
Test status
Simulation time 14901284 ps
CPU time 1.09 seconds
Started Jul 14 05:51:40 PM PDT 24
Finished Jul 14 05:51:41 PM PDT 24
Peak memory 217620 kb
Host smart-ad04fd5c-0ea9-4336-b183-304debb11cde
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505322530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2505322530
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1261256950
Short name T650
Test name
Test status
Simulation time 9255818251 ps
CPU time 14.53 seconds
Started Jul 14 05:51:44 PM PDT 24
Finished Jul 14 05:51:59 PM PDT 24
Peak memory 233796 kb
Host smart-3a6d7ace-3a0f-4b9b-bb99-159ce1bf9220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261256950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1261256950
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2945774886
Short name T188
Test name
Test status
Simulation time 1673734696 ps
CPU time 8.3 seconds
Started Jul 14 05:51:44 PM PDT 24
Finished Jul 14 05:51:52 PM PDT 24
Peak memory 249828 kb
Host smart-e02c36ed-7a53-4705-8ce8-2da4de52a5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945774886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2945774886
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3388399701
Short name T335
Test name
Test status
Simulation time 308618509 ps
CPU time 4.88 seconds
Started Jul 14 05:51:45 PM PDT 24
Finished Jul 14 05:51:51 PM PDT 24
Peak memory 224112 kb
Host smart-46fa36ba-ed00-444d-8e8b-cd0b84ddb210
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3388399701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3388399701
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3866801434
Short name T870
Test name
Test status
Simulation time 14810139816 ps
CPU time 78.93 seconds
Started Jul 14 05:51:52 PM PDT 24
Finished Jul 14 05:53:11 PM PDT 24
Peak memory 253332 kb
Host smart-b728cab7-aa71-4002-bd60-7ead381980a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866801434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3866801434
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1143046749
Short name T307
Test name
Test status
Simulation time 14562027268 ps
CPU time 37.77 seconds
Started Jul 14 05:51:40 PM PDT 24
Finished Jul 14 05:52:19 PM PDT 24
Peak memory 217476 kb
Host smart-eeb20d8e-10a8-4213-834b-0ce5f1165215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143046749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1143046749
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4158375906
Short name T83
Test name
Test status
Simulation time 1871786573 ps
CPU time 7.44 seconds
Started Jul 14 05:51:37 PM PDT 24
Finished Jul 14 05:51:46 PM PDT 24
Peak memory 217304 kb
Host smart-3145102f-537b-4416-93e8-ca770161ed43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158375906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4158375906
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.632831001
Short name T977
Test name
Test status
Simulation time 252535751 ps
CPU time 2.24 seconds
Started Jul 14 05:51:50 PM PDT 24
Finished Jul 14 05:51:53 PM PDT 24
Peak memory 217300 kb
Host smart-9a180e2c-a40c-45da-9a38-63d5229ad089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632831001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.632831001
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.532407565
Short name T960
Test name
Test status
Simulation time 76935553 ps
CPU time 0.97 seconds
Started Jul 14 05:51:40 PM PDT 24
Finished Jul 14 05:51:42 PM PDT 24
Peak memory 206940 kb
Host smart-40d586c7-b3d9-4ae6-a55c-75f51d892ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532407565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.532407565
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2812434237
Short name T350
Test name
Test status
Simulation time 229340507 ps
CPU time 4.12 seconds
Started Jul 14 05:51:48 PM PDT 24
Finished Jul 14 05:51:52 PM PDT 24
Peak memory 225560 kb
Host smart-8d03e99b-c6b5-4602-acf9-3b58cf6c11f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812434237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2812434237
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2201017259
Short name T890
Test name
Test status
Simulation time 25115297 ps
CPU time 0.71 seconds
Started Jul 14 05:52:04 PM PDT 24
Finished Jul 14 05:52:05 PM PDT 24
Peak memory 206392 kb
Host smart-1abcb566-1d1e-4881-a9df-1f5a6d1e1d8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201017259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
201017259
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3248798011
Short name T725
Test name
Test status
Simulation time 2184227790 ps
CPU time 6.45 seconds
Started Jul 14 05:51:56 PM PDT 24
Finished Jul 14 05:52:03 PM PDT 24
Peak memory 225660 kb
Host smart-9e6d5f0d-e0e7-482f-a09b-7d0e6612de1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248798011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3248798011
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.4075573209
Short name T503
Test name
Test status
Simulation time 69780856 ps
CPU time 0.75 seconds
Started Jul 14 05:51:54 PM PDT 24
Finished Jul 14 05:51:55 PM PDT 24
Peak memory 207524 kb
Host smart-6db23c26-ed6f-4c9e-a088-a9a8e9f38a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075573209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.4075573209
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1236019744
Short name T998
Test name
Test status
Simulation time 3678316506 ps
CPU time 12.5 seconds
Started Jul 14 05:51:53 PM PDT 24
Finished Jul 14 05:52:06 PM PDT 24
Peak memory 225652 kb
Host smart-612cb4c3-da5e-464a-989a-0e65c675d669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236019744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1236019744
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1488954548
Short name T653
Test name
Test status
Simulation time 224361405550 ps
CPU time 374.55 seconds
Started Jul 14 05:51:54 PM PDT 24
Finished Jul 14 05:58:09 PM PDT 24
Peak memory 253904 kb
Host smart-088f96cd-4d92-47ba-a416-d5d57d8f36dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488954548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1488954548
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2475734689
Short name T66
Test name
Test status
Simulation time 1740901187 ps
CPU time 18.42 seconds
Started Jul 14 05:51:54 PM PDT 24
Finished Jul 14 05:52:13 PM PDT 24
Peak memory 243412 kb
Host smart-bd9b0b6c-49fb-46e8-b341-dc16e5552a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475734689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2475734689
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3885979937
Short name T679
Test name
Test status
Simulation time 13045749761 ps
CPU time 125.96 seconds
Started Jul 14 05:51:56 PM PDT 24
Finished Jul 14 05:54:02 PM PDT 24
Peak memory 258200 kb
Host smart-f8644000-f830-4c86-8a43-44934c8d2a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885979937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3885979937
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2032215404
Short name T663
Test name
Test status
Simulation time 766088134 ps
CPU time 5.49 seconds
Started Jul 14 05:51:53 PM PDT 24
Finished Jul 14 05:51:59 PM PDT 24
Peak memory 233636 kb
Host smart-7df229a7-f64e-4ee6-be0d-a3927bb30cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032215404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2032215404
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.800089309
Short name T656
Test name
Test status
Simulation time 8551667198 ps
CPU time 28.75 seconds
Started Jul 14 05:51:54 PM PDT 24
Finished Jul 14 05:52:24 PM PDT 24
Peak memory 238612 kb
Host smart-9d5b6d3d-5453-41d3-8b5f-89ea91482862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800089309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.800089309
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1366599475
Short name T536
Test name
Test status
Simulation time 28790991 ps
CPU time 1.08 seconds
Started Jul 14 05:51:56 PM PDT 24
Finished Jul 14 05:51:57 PM PDT 24
Peak memory 217652 kb
Host smart-ecbdfc52-8348-4cef-9271-20bb0c2e9e86
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366599475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1366599475
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1037312022
Short name T795
Test name
Test status
Simulation time 985615758 ps
CPU time 5.59 seconds
Started Jul 14 05:51:55 PM PDT 24
Finished Jul 14 05:52:01 PM PDT 24
Peak memory 233756 kb
Host smart-31ce02e7-4151-4de0-b043-5d91c144bd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037312022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1037312022
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.4136034676
Short name T762
Test name
Test status
Simulation time 1591339720 ps
CPU time 8.04 seconds
Started Jul 14 05:51:55 PM PDT 24
Finished Jul 14 05:52:04 PM PDT 24
Peak memory 225620 kb
Host smart-63ba7911-755c-41f9-9eaf-0dbe424f6f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136034676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.4136034676
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1032117004
Short name T660
Test name
Test status
Simulation time 830371370 ps
CPU time 4.37 seconds
Started Jul 14 05:51:53 PM PDT 24
Finished Jul 14 05:51:58 PM PDT 24
Peak memory 221444 kb
Host smart-b545ca79-7a8f-4184-a406-3851f3b80101
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1032117004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1032117004
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1337009895
Short name T758
Test name
Test status
Simulation time 23544153059 ps
CPU time 120.26 seconds
Started Jul 14 05:51:56 PM PDT 24
Finished Jul 14 05:53:57 PM PDT 24
Peak memory 251364 kb
Host smart-ee8ed121-abef-42d1-8e09-8dc5d0535410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337009895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1337009895
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.446137774
Short name T313
Test name
Test status
Simulation time 4446059489 ps
CPU time 28.8 seconds
Started Jul 14 05:51:54 PM PDT 24
Finished Jul 14 05:52:23 PM PDT 24
Peak memory 217320 kb
Host smart-71f81c99-595b-4c74-b24e-6eb9ffedd31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446137774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.446137774
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2266840048
Short name T982
Test name
Test status
Simulation time 4809687065 ps
CPU time 15.3 seconds
Started Jul 14 05:51:51 PM PDT 24
Finished Jul 14 05:52:07 PM PDT 24
Peak memory 217396 kb
Host smart-a2494be0-0e50-4e64-b540-1a045e8db402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266840048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2266840048
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3491646398
Short name T469
Test name
Test status
Simulation time 60272787 ps
CPU time 1.27 seconds
Started Jul 14 05:51:52 PM PDT 24
Finished Jul 14 05:51:54 PM PDT 24
Peak memory 209016 kb
Host smart-cc6f794e-7ce0-4c90-8e97-4246f801b381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491646398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3491646398
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3859756322
Short name T576
Test name
Test status
Simulation time 21750782 ps
CPU time 0.81 seconds
Started Jul 14 05:51:52 PM PDT 24
Finished Jul 14 05:51:53 PM PDT 24
Peak memory 206956 kb
Host smart-2b6eab67-884f-493e-bdaf-3e1da20446ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859756322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3859756322
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.381281951
Short name T238
Test name
Test status
Simulation time 2274615413 ps
CPU time 9.68 seconds
Started Jul 14 05:51:52 PM PDT 24
Finished Jul 14 05:52:02 PM PDT 24
Peak memory 225604 kb
Host smart-6282288b-4ebf-458d-ba02-56c58baae49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381281951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.381281951
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.871990460
Short name T389
Test name
Test status
Simulation time 16231095 ps
CPU time 0.71 seconds
Started Jul 14 05:52:07 PM PDT 24
Finished Jul 14 05:52:08 PM PDT 24
Peak memory 205788 kb
Host smart-63d73c59-40b3-442e-a9dc-0ab242b76d86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871990460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.871990460
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2017807279
Short name T252
Test name
Test status
Simulation time 1585389717 ps
CPU time 10.84 seconds
Started Jul 14 05:52:01 PM PDT 24
Finished Jul 14 05:52:12 PM PDT 24
Peak memory 233620 kb
Host smart-a67f4634-63a4-4ff5-8421-9cab02aa2be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017807279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2017807279
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.339709532
Short name T9
Test name
Test status
Simulation time 13381527 ps
CPU time 0.71 seconds
Started Jul 14 05:52:03 PM PDT 24
Finished Jul 14 05:52:04 PM PDT 24
Peak memory 206440 kb
Host smart-28465393-9a65-44c3-b5b9-52fe46f0701f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339709532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.339709532
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.399345932
Short name T735
Test name
Test status
Simulation time 42149261125 ps
CPU time 97.91 seconds
Started Jul 14 05:52:03 PM PDT 24
Finished Jul 14 05:53:41 PM PDT 24
Peak memory 239932 kb
Host smart-47f452bc-1469-4b1b-9ab0-0779a27654c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399345932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.399345932
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2219864954
Short name T964
Test name
Test status
Simulation time 29332047591 ps
CPU time 90.18 seconds
Started Jul 14 05:52:03 PM PDT 24
Finished Jul 14 05:53:34 PM PDT 24
Peak memory 252684 kb
Host smart-89395ad6-9998-4a51-bb71-f474b44afb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219864954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2219864954
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2411616835
Short name T222
Test name
Test status
Simulation time 28358418453 ps
CPU time 237 seconds
Started Jul 14 05:52:04 PM PDT 24
Finished Jul 14 05:56:02 PM PDT 24
Peak memory 250364 kb
Host smart-1360fede-71bb-4df1-96c7-a9704ea11c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411616835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2411616835
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3717911649
Short name T294
Test name
Test status
Simulation time 430250578 ps
CPU time 5.16 seconds
Started Jul 14 05:52:02 PM PDT 24
Finished Jul 14 05:52:08 PM PDT 24
Peak memory 233744 kb
Host smart-f9c08de4-b3ec-409e-a493-45d31b9eb03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717911649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3717911649
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3673125912
Short name T403
Test name
Test status
Simulation time 11515419075 ps
CPU time 80.53 seconds
Started Jul 14 05:52:02 PM PDT 24
Finished Jul 14 05:53:23 PM PDT 24
Peak memory 258148 kb
Host smart-a0955256-860f-4599-a04e-d62c83ba0538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673125912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3673125912
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.178983271
Short name T1028
Test name
Test status
Simulation time 1334034184 ps
CPU time 5.57 seconds
Started Jul 14 05:52:01 PM PDT 24
Finished Jul 14 05:52:07 PM PDT 24
Peak memory 233752 kb
Host smart-3aade3b4-66d4-471d-b3d9-56ea9ab1490d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178983271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.178983271
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3677023584
Short name T703
Test name
Test status
Simulation time 9097571266 ps
CPU time 62.64 seconds
Started Jul 14 05:52:04 PM PDT 24
Finished Jul 14 05:53:07 PM PDT 24
Peak memory 242012 kb
Host smart-7b418bf4-06cd-422c-a1e4-c311d04be9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677023584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3677023584
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1130007788
Short name T927
Test name
Test status
Simulation time 74304327 ps
CPU time 0.98 seconds
Started Jul 14 05:52:03 PM PDT 24
Finished Jul 14 05:52:04 PM PDT 24
Peak memory 218932 kb
Host smart-e8654c32-aa01-49e5-8328-a522aa7b60d8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130007788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1130007788
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2872126467
Short name T620
Test name
Test status
Simulation time 7120323659 ps
CPU time 12.93 seconds
Started Jul 14 05:52:03 PM PDT 24
Finished Jul 14 05:52:17 PM PDT 24
Peak memory 250288 kb
Host smart-75fc95f3-fc4a-45ce-aa08-6a9c976357bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872126467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2872126467
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3458773192
Short name T36
Test name
Test status
Simulation time 1238882532 ps
CPU time 10.65 seconds
Started Jul 14 05:52:02 PM PDT 24
Finished Jul 14 05:52:13 PM PDT 24
Peak memory 241600 kb
Host smart-0fa0e5d5-56cb-44ee-bbec-6bdde770e5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458773192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3458773192
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.4175022516
Short name T880
Test name
Test status
Simulation time 5968916189 ps
CPU time 15.26 seconds
Started Jul 14 05:52:01 PM PDT 24
Finished Jul 14 05:52:17 PM PDT 24
Peak memory 220344 kb
Host smart-64802bba-8706-4ba5-abdb-9fe970742275
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4175022516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.4175022516
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3014656738
Short name T273
Test name
Test status
Simulation time 4425785096 ps
CPU time 113.38 seconds
Started Jul 14 05:52:09 PM PDT 24
Finished Jul 14 05:54:03 PM PDT 24
Peak memory 258592 kb
Host smart-c818c59f-4c5b-4852-afd9-b5944be13682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014656738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3014656738
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1078041995
Short name T950
Test name
Test status
Simulation time 6824216279 ps
CPU time 21.3 seconds
Started Jul 14 05:52:00 PM PDT 24
Finished Jul 14 05:52:22 PM PDT 24
Peak memory 217468 kb
Host smart-b6ca51a0-c2b1-4b16-89f1-b46714e2b417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078041995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1078041995
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.810392343
Short name T308
Test name
Test status
Simulation time 22452490507 ps
CPU time 17.09 seconds
Started Jul 14 05:52:02 PM PDT 24
Finished Jul 14 05:52:19 PM PDT 24
Peak memory 217448 kb
Host smart-ee8821c3-4dce-4953-8a91-a12fd2a227a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810392343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.810392343
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.912623536
Short name T330
Test name
Test status
Simulation time 63990009 ps
CPU time 1.42 seconds
Started Jul 14 05:51:59 PM PDT 24
Finished Jul 14 05:52:01 PM PDT 24
Peak memory 217236 kb
Host smart-d0e9359f-dcbc-452f-b65c-b2cbd8fb7889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912623536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.912623536
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.407475312
Short name T328
Test name
Test status
Simulation time 52737134 ps
CPU time 0.74 seconds
Started Jul 14 05:52:03 PM PDT 24
Finished Jul 14 05:52:05 PM PDT 24
Peak memory 206944 kb
Host smart-4835456c-ac09-46c1-bc13-a67baf7995fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407475312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.407475312
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1492645400
Short name T1022
Test name
Test status
Simulation time 305541204 ps
CPU time 4.13 seconds
Started Jul 14 05:51:59 PM PDT 24
Finished Jul 14 05:52:04 PM PDT 24
Peak memory 233756 kb
Host smart-f1f4696b-9f42-4f5d-bb9b-1743e936f9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492645400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1492645400
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2644558281
Short name T825
Test name
Test status
Simulation time 71987444 ps
CPU time 0.74 seconds
Started Jul 14 05:52:08 PM PDT 24
Finished Jul 14 05:52:09 PM PDT 24
Peak memory 206320 kb
Host smart-61c9fcdd-1d8f-42c6-ba26-bbaa1c01df65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644558281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
644558281
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3692980686
Short name T749
Test name
Test status
Simulation time 2040491739 ps
CPU time 12.36 seconds
Started Jul 14 05:52:09 PM PDT 24
Finished Jul 14 05:52:22 PM PDT 24
Peak memory 225512 kb
Host smart-1d3d902e-c085-4887-9368-1b6ff0056b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692980686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3692980686
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3417661231
Short name T344
Test name
Test status
Simulation time 75015264 ps
CPU time 0.78 seconds
Started Jul 14 05:52:08 PM PDT 24
Finished Jul 14 05:52:10 PM PDT 24
Peak memory 206368 kb
Host smart-b2975352-8c74-4a9d-a00f-dd77e9a0f105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417661231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3417661231
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.36180332
Short name T290
Test name
Test status
Simulation time 35620051899 ps
CPU time 82.43 seconds
Started Jul 14 05:52:10 PM PDT 24
Finished Jul 14 05:53:33 PM PDT 24
Peak memory 258468 kb
Host smart-9e23aed7-cdd6-4018-b299-92837e46704e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36180332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.36180332
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.721628062
Short name T272
Test name
Test status
Simulation time 9574892507 ps
CPU time 51.51 seconds
Started Jul 14 05:52:06 PM PDT 24
Finished Jul 14 05:52:57 PM PDT 24
Peak memory 250380 kb
Host smart-febe4a49-ec36-433e-9f30-2ddfba119d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721628062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.721628062
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4132601681
Short name T167
Test name
Test status
Simulation time 264245170666 ps
CPU time 182.06 seconds
Started Jul 14 05:52:09 PM PDT 24
Finished Jul 14 05:55:12 PM PDT 24
Peak memory 254220 kb
Host smart-3d9f5297-ec08-48f2-9af0-1f550f79dbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132601681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4132601681
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1891522124
Short name T654
Test name
Test status
Simulation time 1031894158 ps
CPU time 20.39 seconds
Started Jul 14 05:52:09 PM PDT 24
Finished Jul 14 05:52:30 PM PDT 24
Peak memory 233712 kb
Host smart-3a7a4b0b-5d10-4208-827e-ad5c768a5616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891522124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1891522124
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3553734105
Short name T383
Test name
Test status
Simulation time 12896686 ps
CPU time 0.73 seconds
Started Jul 14 05:52:09 PM PDT 24
Finished Jul 14 05:52:11 PM PDT 24
Peak memory 216808 kb
Host smart-0a3b6b56-0e20-4a8b-aead-869ff5c1e9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553734105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3553734105
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.967879303
Short name T212
Test name
Test status
Simulation time 21336353587 ps
CPU time 16.98 seconds
Started Jul 14 05:52:11 PM PDT 24
Finished Jul 14 05:52:29 PM PDT 24
Peak memory 225660 kb
Host smart-e3c2afc7-8903-4f05-9465-973b283722d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967879303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.967879303
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.529180338
Short name T573
Test name
Test status
Simulation time 1186160134 ps
CPU time 9.71 seconds
Started Jul 14 05:52:08 PM PDT 24
Finished Jul 14 05:52:18 PM PDT 24
Peak memory 225556 kb
Host smart-74120fa1-7d50-435f-98aa-187f06741a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529180338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.529180338
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2924655719
Short name T902
Test name
Test status
Simulation time 119015407 ps
CPU time 1.04 seconds
Started Jul 14 05:52:06 PM PDT 24
Finished Jul 14 05:52:08 PM PDT 24
Peak memory 217640 kb
Host smart-d073d11c-01fd-40b6-b46d-cc4daafcb24c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924655719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2924655719
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.638945367
Short name T540
Test name
Test status
Simulation time 7804567719 ps
CPU time 15.56 seconds
Started Jul 14 05:52:07 PM PDT 24
Finished Jul 14 05:52:23 PM PDT 24
Peak memory 249844 kb
Host smart-8c447e73-d8aa-4212-8f21-0b0eea46faf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638945367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
638945367
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1180128018
Short name T687
Test name
Test status
Simulation time 21572641971 ps
CPU time 16.85 seconds
Started Jul 14 05:52:09 PM PDT 24
Finished Jul 14 05:52:26 PM PDT 24
Peak memory 233916 kb
Host smart-af325a5d-1712-473c-865f-d54331829cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180128018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1180128018
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.847042730
Short name T411
Test name
Test status
Simulation time 925199358 ps
CPU time 7.3 seconds
Started Jul 14 05:52:10 PM PDT 24
Finished Jul 14 05:52:18 PM PDT 24
Peak memory 220360 kb
Host smart-d361a105-08d2-46a5-8c40-f278869c1b6f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=847042730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.847042730
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1057322307
Short name T869
Test name
Test status
Simulation time 1056547137 ps
CPU time 5.99 seconds
Started Jul 14 05:52:09 PM PDT 24
Finished Jul 14 05:52:15 PM PDT 24
Peak memory 217340 kb
Host smart-343b89f9-a81c-47d9-9473-8760995fdc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057322307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1057322307
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1703660495
Short name T430
Test name
Test status
Simulation time 42126252063 ps
CPU time 7.75 seconds
Started Jul 14 05:52:08 PM PDT 24
Finished Jul 14 05:52:16 PM PDT 24
Peak memory 217396 kb
Host smart-fd6bf276-4f91-4f2b-9a5f-6f515f9220c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703660495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1703660495
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.929843620
Short name T781
Test name
Test status
Simulation time 38799870 ps
CPU time 1.33 seconds
Started Jul 14 05:52:08 PM PDT 24
Finished Jul 14 05:52:10 PM PDT 24
Peak memory 217356 kb
Host smart-0dc2f1ee-bb75-47c9-8e91-0e214138865b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929843620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.929843620
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.4042988131
Short name T689
Test name
Test status
Simulation time 21836580 ps
CPU time 0.76 seconds
Started Jul 14 05:52:10 PM PDT 24
Finished Jul 14 05:52:11 PM PDT 24
Peak memory 206984 kb
Host smart-90fe3082-1d66-4daa-a7d7-c635b2a1834b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042988131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.4042988131
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2047200146
Short name T824
Test name
Test status
Simulation time 19615610340 ps
CPU time 21.84 seconds
Started Jul 14 05:52:07 PM PDT 24
Finished Jul 14 05:52:30 PM PDT 24
Peak memory 233884 kb
Host smart-7eff896d-7241-4c10-9e8f-6f09c3106113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047200146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2047200146
Directory /workspace/9.spi_device_upload/latest
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