Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2523082	1			T2	1		T3	1		T4	63
all_values[1]	2523082	1			T2	1		T3	1		T4	63
all_values[2]	2523082	1			T2	1		T3	1		T4	63
all_values[3]	2523082	1			T2	1		T3	1		T4	63
all_values[4]	2523082	1			T2	1		T3	1		T4	63
all_values[5]	2523082	1			T2	1		T3	1		T4	63
all_values[6]	2523082	1			T2	1		T3	1		T4	63
all_values[7]	2523082	1			T2	1		T3	1		T4	63

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19812968

1

T2

8

T3

8

T4

504

auto[1]

371688

1

T6

96

T8

16757

T14

19167

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20159944

1

T2

8

T3

8

T4

504

auto[1]

24712

1

T6

58

T8

351

T13

34

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2497973	1			T2	1		T3	1		T4	63
all_values[0]	auto[0]	auto[1]	11767	1			T6	2		T8	205		T13	34
all_values[0]	auto[1]	auto[0]	12982	1			T6	10		T8	3		T14	1
all_values[0]	auto[1]	auto[1]	360	1			T6	2		T8	7		T18	5
all_values[1]	auto[0]	auto[0]	2473710	1			T2	1		T3	1		T4	63
all_values[1]	auto[0]	auto[1]	7470	1			T6	4		T8	75		T14	2
all_values[1]	auto[1]	auto[0]	41620	1			T6	11		T8	4		T14	3825
all_values[1]	auto[1]	auto[1]	282	1			T6	2		T8	6		T14	8
all_values[2]	auto[0]	auto[0]	2460329	1			T2	1		T3	1		T4	63
all_values[2]	auto[0]	auto[1]	2864	1			T6	3		T8	9		T17	1
all_values[2]	auto[1]	auto[0]	59709	1			T6	6		T8	8347		T17	4
all_values[2]	auto[1]	auto[1]	180	1			T6	4		T8	8		T18	3
all_values[3]	auto[0]	auto[0]	2475871	1			T2	1		T3	1		T4	63
all_values[3]	auto[0]	auto[1]	194	1			T6	6		T8	9		T17	2
all_values[3]	auto[1]	auto[0]	46821	1			T6	4		T8	2		T14	3830
all_values[3]	auto[1]	auto[1]	196	1			T6	4		T8	3		T14	4
all_values[4]	auto[0]	auto[0]	2459849	1			T2	1		T3	1		T4	63
all_values[4]	auto[0]	auto[1]	173	1			T8	3		T18	5		T19	1
all_values[4]	auto[1]	auto[0]	62852	1			T6	7		T8	7		T17	2
all_values[4]	auto[1]	auto[1]	208	1			T6	5		T8	4		T17	2
all_values[5]	auto[0]	auto[0]	2481812	1			T2	1		T3	1		T4	63
all_values[5]	auto[0]	auto[1]	169	1			T6	3		T8	5		T18	3
all_values[5]	auto[1]	auto[0]	40918	1			T6	10		T8	8350		T14	3832
all_values[5]	auto[1]	auto[1]	183	1			T6	5		T8	3		T14	1
all_values[6]	auto[0]	auto[0]	2468722	1			T2	1		T3	1		T4	63
all_values[6]	auto[0]	auto[1]	166	1			T6	1		T8	6		T17	1
all_values[6]	auto[1]	auto[0]	54010	1			T6	7		T8	4		T14	3833
all_values[6]	auto[1]	auto[1]	184	1			T6	8		T8	5		T14	1
all_values[7]	auto[0]	auto[0]	2471740	1			T2	1		T3	1		T4	63
all_values[7]	auto[0]	auto[1]	159	1			T6	6		T8	3		T17	2
all_values[7]	auto[1]	auto[0]	51026	1			T6	8		T8	4		T14	3832
all_values[7]	auto[1]	auto[1]	157	1			T6	3		T18	4		T19	3