Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34888	1			T4	4		T5	2		T8	392
auto[SpiFlashAddrCfg]	7762	1			T3	2		T8	82		T13	25
auto[SpiFlashAddr3b]	9187	1			T4	2		T8	99		T11	2
auto[SpiFlashAddr4b]	7613	1			T3	2		T4	10		T8	75

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34036

1

T3

4

T4

16

T5

2

auto[1]

25414

1

T8

355

T13

40

T14

100

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31375

1

T4

4

T5

2

T8

336

auto[1]

28075

1

T3

4

T4

12

T8

312

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39432	1			T3	2		T4	6		T5	2
values[1]	1130	1			T8	9		T13	4		T14	3
values[2]	1456	1			T8	20		T13	2		T14	10
values[3]	1455	1			T4	6		T8	15		T13	3
values[4]	1529	1			T8	16		T13	3		T14	7
values[5]	1455	1			T3	2		T8	14		T14	20
values[6]	1423	1			T8	17		T13	5		T14	8
values[7]	1609	1			T8	10		T13	1		T14	9
values[8]	9961	1			T4	4		T8	124		T11	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31829

1

T3

4

T4

16

T5

2

auto[1]

27621

1

T8

330

T13

133

T14

125

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56220

1

T3

4

T4

16

T5

2

write

3230

1

T8

32

T13

9

T14

10

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19319

1

T3

2

T4

10

T8

205

valids[0x1]

40131

1

T3

2

T4

6

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1619	1			T4	2		T8	17		T14	10
internal_process_ops[0x5a]	1572	1			T4	2		T8	12		T13	3
internal_process_ops[0x05]	20937	1			T4	2		T5	2		T8	225
internal_process_ops[0x35]	1578	1			T8	28		T13	4		T14	6
internal_process_ops[0x15]	1602	1			T8	19		T13	3		T14	10
internal_process_ops[0x03]	1063	1			T8	8		T14	5		T39	2
internal_process_ops[0x0b]	1064	1			T8	10		T13	3		T14	2
internal_process_ops[0x3b]	1131	1			T8	12		T13	1		T14	1
internal_process_ops[0x6b]	1083	1			T3	2		T8	10		T13	1
internal_process_ops[0xbb]	1082	1			T8	10		T13	1		T14	4
internal_process_ops[0xeb]	1066	1			T8	8		T13	4		T14	5

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57848

1

T3

4

T4

16

T5

2

auto[1]

1602

1

T8

18

T13

7

T14

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57071

1

T3

4

T4

16

T5

2

auto[1]

2379

1

T8

28

T13

5

T14

7

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10535

1

T4

4

T5

2

T8

81

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6578

1

T8

66

T14

18

T37

5

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2213

1

T3

2

T8

21

T14

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1895

1

T8

29

T14

10

T37

3

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2536

1

T4

2

T8

24

T11

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2351

1

T8

38

T14

7

T37

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2157

1

T3

2

T4

10

T8

22

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1889

1

T8

25

T14

6

T37

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

105

1

T21

1

T51

2

T45

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

103

1

T43

2

T42

1

T44

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

105

1

T21

2

T43

1

T44

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

95

1

T42

2

T45

3

T31

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

95

1

T41

2

T21

1

T44

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

115

1

T8

1

T37

2

T43

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

91

1

T8

3

T14

3

T37

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

106

1

T8

3

T43

3

T42

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

119

1

T43

1

T173

2

T42

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

91

1

T21

2

T44

2

T45

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

99

1

T37

2

T43

1

T42

7

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

121

1

T8

2

T37

4

T42

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

108

1

T43

2

T42

1

T44

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

78

1

T8

2

T45

1

T32

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

118

1

T42

2

T45

5

T32

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

126

1

T8

1

T14

1

T21

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10442

1

T8

97

T13

68

T14

33

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6543

1

T8

141

T13

13

T14

17

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1451

1

T8

13

T13

10

T14

13

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1373

1

T8

10

T13

11

T14

17

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1716

1

T8

13

T13

5

T14

12

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1786

1

T8

19

T13

7

T14

18

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1377

1

T8

9

T13

6

T14

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1378

1

T8

8

T13

4

T14

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

88

1

T8

1

T17

4

T18

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

94

1

T8

2

T14

1

T18

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

102

1

T8

4

T17

1

T81

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

98

1

T18

5

T21

1

T81

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

111

1

T14

1

T17

2

T18

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

109

1

T13

2

T17

5

T18

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

99

1

T8

1

T21

2

T81

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

104

1

T8

1

T13

2

T21

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

88

1

T14

1

T81

2

T82

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

97

1

T8

3

T18

2

T90

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

91

1

T13

1

T18

1

T81

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

92

1

T82

1

T90

2

T174

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

109

1

T8

4

T13

1

T14

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

99

1

T13

1

T18

1

T175

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

100

1

T8

1

T18

1

T81

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

74

1

T8

3

T13

2

T17

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3853	1			T8	44		T14	18		T37	7
auto[0]	values[0]	valids[0x1]	16255	1			T3	2		T4	6		T5	2
auto[0]	values[1]	valids[0x1]	637	1			T8	8		T14	2		T37	1
auto[0]	values[2]	valids[0x0]	544	1			T8	5		T40	2		T37	4
auto[0]	values[2]	valids[0x1]	322	1			T8	7		T14	1		T120	2
auto[0]	values[3]	valids[0x0]	572	1			T4	6		T8	6		T14	1
auto[0]	values[3]	valids[0x1]	313	1			T8	3		T106	8		T21	3
auto[0]	values[4]	valids[0x0]	565	1			T8	9		T21	2		T43	4
auto[0]	values[4]	valids[0x1]	327	1			T8	4		T14	3		T21	3
auto[0]	values[5]	valids[0x0]	608	1			T3	2		T8	5		T14	6
auto[0]	values[5]	valids[0x1]	272	1			T8	5		T14	5		T176	2
auto[0]	values[6]	valids[0x0]	518	1			T8	7		T37	2		T120	4
auto[0]	values[6]	valids[0x1]	305	1			T8	2		T14	1		T21	5
auto[0]	values[7]	valids[0x0]	614	1			T8	7		T14	2		T15	2
auto[0]	values[7]	valids[0x1]	319	1			T8	2		T37	2		T21	1
auto[0]	values[8]	valids[0x0]	3657	1			T4	4		T8	52		T11	2
auto[0]	values[8]	valids[0x1]	2148	1			T8	28		T14	12		T37	7
auto[1]	values[0]	valids[0x0]	3785	1			T8	38		T13	16		T14	24
auto[1]	values[0]	valids[0x1]	15539	1			T8	217		T13	78		T14	35
auto[1]	values[1]	valids[0x1]	493	1			T8	1		T13	4		T14	1
auto[1]	values[2]	valids[0x0]	336	1			T8	6		T14	4		T17	3
auto[1]	values[2]	valids[0x1]	254	1			T8	2		T13	2		T14	5
auto[1]	values[3]	valids[0x0]	330	1			T8	4		T13	1		T14	6
auto[1]	values[3]	valids[0x1]	240	1			T8	2		T13	2		T14	1
auto[1]	values[4]	valids[0x0]	367	1			T8	2		T13	1		T14	3
auto[1]	values[4]	valids[0x1]	270	1			T8	1		T13	2		T14	1
auto[1]	values[5]	valids[0x0]	362	1			T8	3		T14	7		T18	1
auto[1]	values[5]	valids[0x1]	213	1			T8	1		T14	2		T81	2
auto[1]	values[6]	valids[0x0]	347	1			T8	4		T13	4		T14	5
auto[1]	values[6]	valids[0x1]	253	1			T8	4		T13	1		T14	2
auto[1]	values[7]	valids[0x0]	378	1			T8	1		T13	1		T14	5
auto[1]	values[7]	valids[0x1]	298	1			T14	2		T18	5		T21	1
auto[1]	values[8]	valids[0x0]	2483	1			T8	12		T13	14		T14	6
auto[1]	values[8]	valids[0x1]	1673	1			T8	32		T13	7		T14	16