Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3358077

1

T3

1

T4

5

T5

1774

auto[1]

33089

1

T8

208

T13

53

T14

20

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

852341

1

T3

1

T4

1

T5

1774

auto[1]

2538825

1

T4

4

T8

38302

T13

3699

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	621480	1			T3	1		T4	5		T5	385
auto[524288:1048575]	387094	1			T5	3		T8	3723		T14	789
auto[1048576:1572863]	405281	1			T8	2949		T13	1864		T14	3297
auto[1572864:2097151]	424437	1			T8	8224		T13	8		T14	2285
auto[2097152:2621439]	408911	1			T5	2		T8	7166		T14	3138
auto[2621440:3145727]	368192	1			T5	957		T8	2320		T14	1126
auto[3145728:3670015]	360514	1			T5	427		T8	6694		T13	108
auto[3670016:4194303]	415257	1			T8	1289		T13	265		T14	1404

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2572843

1

T3

1

T4

5

T5

13

auto[1]

818323

1

T5

1761

T8

5

T13

5

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2875050

1

T3

1

T4

5

T5

1774

auto[1]

516116

1

T8

4757

T13

393

T14

6059

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	201311	1			T3	1		T4	1		T5	385
auto[0]	auto[0]	auto[0:524287]	auto[1]	351201	1			T4	4		T8	5731		T13	1289
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	85651	1			T5	3		T8	10		T14	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	233053	1			T8	3700		T14	3		T39	133
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	56230	1			T8	7		T14	4		T119	5854
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	285752	1			T8	2882		T13	1864		T14	676
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	113742	1			T8	10		T13	1		T14	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	216563	1			T8	8152		T13	1		T176	2957
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	85391	1			T5	2		T8	9		T14	5
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	256077	1			T8	6873		T14	3129		T37	1469
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	101263	1			T5	957		T8	3		T14	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	200796	1			T8	2311		T14	1121		T39	476
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	85541	1			T5	427		T8	11		T13	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	212784	1			T8	3217		T13	107		T37	1715
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	110098	1			T8	3		T13	2		T14	5
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	254364	1			T8	513		T14	1398		T39	24
auto[0]	auto[1]	auto[0:524287]	auto[0]	1755	1			T18	3		T21	2		T42	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	62989	1			T8	256		T13	130		T18	513
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1877	1			T8	1		T14	2		T18	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	63080	1			T14	773		T18	1		T21	130
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1939	1			T14	1		T17	2		T43	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	58222	1			T14	2615		T17	1		T21	2475
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	686	1			T8	1		T14	1		T18	11
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	88778	1			T8	5		T14	2283		T18	666
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	584	1			T8	2		T18	3		T21	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	62794	1			T8	258		T18	2		T21	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	577	1			T8	2		T14	1		T18	6
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	60293	1			T8	4		T18	129		T90	512
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1211	1			T8	5		T14	4		T17	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	56388	1			T8	3452		T14	377		T17	420
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	493	1			T8	3		T13	3		T18	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	46594	1			T8	768		T13	260		T18	256
auto[1]	auto[0]	auto[0:524287]	auto[0]	555	1			T8	6		T13	4		T14	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2418	1			T8	39		T13	43		T18	65
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	392	1			T8	3		T14	1		T17	5
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2472	1			T8	9		T14	7		T17	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	301	1			T8	4		T14	1		T37	9
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1869	1			T8	56		T21	2		T43	6
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	435	1			T8	9		T13	1		T18	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2980	1			T8	47		T13	5		T18	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	374	1			T8	3		T14	1		T37	6
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2303	1			T8	21		T14	3		T21	8
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	420	1			T14	1		T37	11		T18	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	4030	1			T14	2		T37	204		T18	56
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	404	1			T8	2		T37	11		T18	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3630	1			T8	7		T37	514		T18	26
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	356	1			T8	1		T14	1		T17	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2294	1			T8	1		T17	2		T18	34
auto[1]	auto[1]	auto[0:524287]	auto[0]	103	1			T18	1		T90	5		T44	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	1148	1			T18	52		T90	3		T44	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	91	1			T18	1		T21	2		T42	4
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	478	1			T18	31		T21	2		T42	127
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	96	1			T17	1		T82	1		T45	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	872	1			T17	3		T82	23		T45	8
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	105	1			T18	1		T45	1		T32	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1148	1			T18	7		T32	6		T58	29
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	100	1			T18	2		T90	7		T44	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	1288	1			T18	116		T44	1		T31	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	89	1			T18	1		T90	2		T44	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	724	1			T18	44		T44	2		T31	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	74	1			T14	1		T21	2		T42	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	482	1			T14	1		T21	4		T42	6
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	97	1			T32	3		T174	1		T215	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	961	1			T32	16		T238	9		T243	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2036796	1			T3	1		T4	5		T5	13
auto[0]	auto[0]	auto[1]	813021	1			T5	1761		T8	2		T13	2
auto[0]	auto[1]	auto[0]	503621	1			T8	4757		T13	393		T14	6057
auto[0]	auto[1]	auto[1]	4639	1			T18	3		T42	3		T82	2
auto[1]	auto[0]	auto[0]	24694	1			T8	205		T13	50		T14	18
auto[1]	auto[0]	auto[1]	539	1			T8	3		T13	3		T37	4
auto[1]	auto[1]	auto[0]	7732	1			T14	2		T17	4		T18	256
auto[1]	auto[1]	auto[1]	124	1			T90	1		T44	1		T32	1