Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2523082	1			T2	1		T3	1		T4	63
all_pins[1]	2523082	1			T2	1		T3	1		T4	63
all_pins[2]	2523082	1			T2	1		T3	1		T4	63
all_pins[3]	2523082	1			T2	1		T3	1		T4	63
all_pins[4]	2523082	1			T2	1		T3	1		T4	63
all_pins[5]	2523082	1			T2	1		T3	1		T4	63
all_pins[6]	2523082	1			T2	1		T3	1		T4	63
all_pins[7]	2523082	1			T2	1		T3	1		T4	63

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20128544	1			T2	8		T3	8		T4	504
values[0x1]	56112	1			T6	33		T8	218		T14	4055
transitions[0x0=>0x1]	55310	1			T6	26		T8	206		T14	3834
transitions[0x1=>0x0]	55321	1			T6	27		T8	206		T14	3834

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2522715	1			T2	1		T3	1		T4	63
all_pins[0]	values[0x1]	367	1			T6	2		T8	7		T18	5
all_pins[0]	transitions[0x0=>0x1]	265	1			T6	2		T8	5		T18	2
all_pins[0]	transitions[0x1=>0x0]	199	1			T6	2		T8	4		T14	10
all_pins[1]	values[0x0]	2522781	1			T2	1		T3	1		T4	63
all_pins[1]	values[0x1]	301	1			T6	2		T8	6		T14	10
all_pins[1]	transitions[0x0=>0x1]	253	1			T6	2		T8	2		T14	10
all_pins[1]	transitions[0x1=>0x0]	139	1			T6	4		T8	7		T18	3
all_pins[2]	values[0x0]	2522895	1			T2	1		T3	1		T4	63
all_pins[2]	values[0x1]	187	1			T6	4		T8	11		T18	3
all_pins[2]	transitions[0x0=>0x1]	131	1			T6	4		T8	9		T18	3
all_pins[2]	transitions[0x1=>0x0]	140	1			T6	4		T8	1		T14	4
all_pins[3]	values[0x0]	2522886	1			T2	1		T3	1		T4	63
all_pins[3]	values[0x1]	196	1			T6	4		T8	3		T14	4
all_pins[3]	transitions[0x0=>0x1]	141	1			T6	2		T8	1		T14	4
all_pins[3]	transitions[0x1=>0x0]	153	1			T6	3		T8	2		T17	2
all_pins[4]	values[0x0]	2522874	1			T2	1		T3	1		T4	63
all_pins[4]	values[0x1]	208	1			T6	5		T8	4		T17	2
all_pins[4]	transitions[0x0=>0x1]	158	1			T6	3		T8	3		T17	1
all_pins[4]	transitions[0x1=>0x0]	1032	1			T6	3		T8	181		T14	223
all_pins[5]	values[0x0]	2522000	1			T2	1		T3	1		T4	63
all_pins[5]	values[0x1]	1082	1			T6	5		T8	182		T14	223
all_pins[5]	transitions[0x0=>0x1]	681	1			T6	4		T8	181		T14	2
all_pins[5]	transitions[0x1=>0x0]	53213	1			T6	7		T8	4		T14	3597
all_pins[6]	values[0x0]	2469468	1			T2	1		T3	1		T4	63
all_pins[6]	values[0x1]	53614	1			T6	8		T8	5		T14	3818
all_pins[6]	transitions[0x0=>0x1]	53565	1			T6	8		T8	5		T14	3818
all_pins[6]	transitions[0x1=>0x0]	108	1			T6	3		T18	4		T19	2
all_pins[7]	values[0x0]	2522925	1			T2	1		T3	1		T4	63
all_pins[7]	values[0x1]	157	1			T6	3		T18	4		T19	3
all_pins[7]	transitions[0x0=>0x1]	116	1			T6	1		T18	3		T19	3
all_pins[7]	transitions[0x1=>0x0]	337	1			T6	1		T8	7		T18	4