Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18255

1

T3

4

T4

16

T5

2

auto[1]

13574

1

T8

167

T14

45

T37

27

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4385	1			T4	16		T8	20		T14	28
values[1]	4025	1			T3	4		T8	100		T14	24
values[2]	3259	1			T8	65		T11	2		T21	62
values[3]	4164	1			T8	40		T37	20		T176	10
values[4]	4254	1			T8	50		T15	8		T167	12
values[5]	3762	1			T14	21		T48	4		T226	18
values[6]	3857	1			T8	23		T14	22		T40	12
values[7]	4123	1			T5	2		T8	20		T39	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3836	1			T8	20		T40	12		T37	20
values[1]	3736	1			T3	4		T21	69		T43	20
values[2]	3783	1			T8	24		T11	2		T21	58
values[3]	4087	1			T8	100		T14	28		T15	8
values[4]	3549	1			T14	24		T43	61		T44	43
values[5]	4178	1			T4	16		T5	2		T8	40
values[6]	4313	1			T8	73		T37	20		T96	10
values[7]	4347	1			T8	61		T14	43		T21	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	320	1			T51	46		T42	13		T160	11
auto[0]	values[0]	values[1]	321	1			T21	6		T43	10		T23	12
auto[0]	values[0]	values[2]	275	1			T21	52		T42	11		T230	4
auto[0]	values[0]	values[3]	212	1			T14	11		T23	15		T160	25
auto[0]	values[0]	values[4]	274	1			T44	8		T32	24		T23	12
auto[0]	values[0]	values[5]	265	1			T4	16		T8	10		T42	12
auto[0]	values[0]	values[6]	168	1			T42	7		T199	10		T244	8
auto[0]	values[0]	values[7]	436	1			T42	12		T45	35		T31	20
auto[0]	values[1]	values[0]	171	1			T43	14		T245	2		T197	9
auto[0]	values[1]	values[1]	207	1			T3	4		T44	9		T45	17
auto[0]	values[1]	values[2]	473	1			T32	28		T23	12		T194	9
auto[0]	values[1]	values[3]	255	1			T8	39		T197	16		T233	18
auto[0]	values[1]	values[4]	299	1			T14	12		T43	9		T44	10
auto[0]	values[1]	values[5]	308	1			T199	11		T234	11		T217	13
auto[0]	values[1]	values[6]	378	1			T8	11		T96	10		T197	7
auto[0]	values[1]	values[7]	279	1			T223	14		T210	58		T237	12
auto[0]	values[2]	values[0]	275	1			T23	13		T194	12		T217	13
auto[0]	values[2]	values[1]	237	1			T21	12		T42	12		T246	20
auto[0]	values[2]	values[2]	221	1			T8	13		T11	2		T42	8
auto[0]	values[2]	values[3]	132	1			T42	15		T223	10		T224	8
auto[0]	values[2]	values[4]	201	1			T23	9		T201	9		T161	11
auto[0]	values[2]	values[5]	215	1			T43	6		T221	18		T160	11
auto[0]	values[2]	values[6]	436	1			T21	15		T44	11		T247	4
auto[0]	values[2]	values[7]	328	1			T8	8		T197	50		T199	15
auto[0]	values[3]	values[0]	180	1			T37	12		T193	10		T220	14
auto[0]	values[3]	values[1]	237	1			T60	18		T194	10		T224	11
auto[0]	values[3]	values[2]	352	1			T89	8		T44	29		T248	6
auto[0]	values[3]	values[3]	330	1			T45	5		T240	7		T213	11
auto[0]	values[3]	values[4]	235	1			T45	19		T249	4		T193	15
auto[0]	values[3]	values[5]	399	1			T8	1		T176	10		T193	14
auto[0]	values[3]	values[6]	417	1			T21	13		T202	13		T214	8
auto[0]	values[3]	values[7]	248	1			T8	8		T43	14		T32	9
auto[0]	values[4]	values[0]	394	1			T220	26		T199	12		T195	9
auto[0]	values[4]	values[1]	300	1			T91	2		T250	38		T201	33
auto[0]	values[4]	values[2]	357	1			T42	14		T45	8		T61	20
auto[0]	values[4]	values[3]	271	1			T8	10		T15	8		T167	12
auto[0]	values[4]	values[4]	375	1			T32	6		T211	12		T194	13
auto[0]	values[4]	values[5]	382	1			T64	8		T44	15		T32	14
auto[0]	values[4]	values[6]	250	1			T8	23		T21	8		T227	4
auto[0]	values[4]	values[7]	198	1			T251	8		T197	81		T252	8
auto[0]	values[5]	values[0]	261	1			T226	18		T160	38		T236	6
auto[0]	values[5]	values[1]	378	1			T253	9		T213	11		T189	12
auto[0]	values[5]	values[2]	313	1			T43	14		T45	8		T254	20
auto[0]	values[5]	values[3]	383	1			T48	4		T42	10		T44	12
auto[0]	values[5]	values[4]	327	1			T43	17		T45	61		T32	11
auto[0]	values[5]	values[5]	182	1			T220	13		T199	6		T255	20
auto[0]	values[5]	values[6]	272	1			T45	8		T201	17		T256	22
auto[0]	values[5]	values[7]	205	1			T14	11		T23	13		T193	14
auto[0]	values[6]	values[0]	258	1			T40	12		T170	8		T106	24
auto[0]	values[6]	values[1]	213	1			T44	11		T32	15		T213	25
auto[0]	values[6]	values[2]	77	1			T257	2		T240	14		T258	4
auto[0]	values[6]	values[3]	232	1			T120	22		T32	18		T23	14
auto[0]	values[6]	values[4]	257	1			T223	17		T199	80		T203	13
auto[0]	values[6]	values[5]	193	1			T41	4		T173	10		T45	15
auto[0]	values[6]	values[6]	220	1			T8	16		T23	6		T194	24
auto[0]	values[6]	values[7]	339	1			T14	16		T43	16		T44	19
auto[0]	values[7]	values[0]	335	1			T8	12		T44	19		T23	15
auto[0]	values[7]	values[1]	295	1			T21	20		T44	9		T160	12
auto[0]	values[7]	values[2]	158	1			T42	13		T259	2		T260	10
auto[0]	values[7]	values[3]	402	1			T39	6		T261	2		T199	133
auto[0]	values[7]	values[4]	168	1			T228	13		T202	14		T212	16
auto[0]	values[7]	values[5]	329	1			T5	2		T37	12		T42	109
auto[0]	values[7]	values[6]	441	1			T37	9		T213	12		T203	16
auto[0]	values[7]	values[7]	406	1			T21	7		T43	57		T45	13
auto[1]	values[0]	values[0]	204	1			T42	10		T160	9		T262	20
auto[1]	values[0]	values[1]	221	1			T21	18		T43	10		T23	8
auto[1]	values[0]	values[2]	233	1			T21	6		T42	9		T197	32
auto[1]	values[0]	values[3]	291	1			T14	17		T23	9		T160	30
auto[1]	values[0]	values[4]	294	1			T44	12		T32	9		T23	9
auto[1]	values[0]	values[5]	211	1			T8	10		T42	8		T31	14
auto[1]	values[0]	values[6]	247	1			T42	20		T199	10		T244	12
auto[1]	values[0]	values[7]	413	1			T42	136		T45	19		T31	7
auto[1]	values[1]	values[0]	222	1			T43	6		T197	70		T195	11
auto[1]	values[1]	values[1]	180	1			T44	11		T45	4		T32	10
auto[1]	values[1]	values[2]	280	1			T32	8		T23	8		T194	11
auto[1]	values[1]	values[3]	190	1			T8	41		T197	4		T199	9
auto[1]	values[1]	values[4]	185	1			T14	12		T43	24		T44	13
auto[1]	values[1]	values[5]	186	1			T199	9		T234	9		T217	7
auto[1]	values[1]	values[6]	297	1			T8	9		T197	56		T231	11
auto[1]	values[1]	values[7]	115	1			T200	10		T223	11		T210	11
auto[1]	values[2]	values[0]	174	1			T23	7		T194	8		T217	7
auto[1]	values[2]	values[1]	102	1			T21	8		T42	8		T195	13
auto[1]	values[2]	values[2]	174	1			T8	11		T42	12		T263	2
auto[1]	values[2]	values[3]	128	1			T42	5		T223	41		T224	15
auto[1]	values[2]	values[4]	116	1			T23	11		T201	11		T161	9
auto[1]	values[2]	values[5]	135	1			T43	14		T160	9		T189	7
auto[1]	values[2]	values[6]	221	1			T21	27		T44	9		T160	7
auto[1]	values[2]	values[7]	164	1			T8	33		T197	6		T199	17
auto[1]	values[3]	values[0]	181	1			T37	8		T193	10		T220	6
auto[1]	values[3]	values[1]	150	1			T194	34		T224	10		T234	9
auto[1]	values[3]	values[2]	259	1			T44	27		T23	11		T202	7
auto[1]	values[3]	values[3]	243	1			T45	15		T240	13		T213	41
auto[1]	values[3]	values[4]	194	1			T45	9		T193	6		T264	2
auto[1]	values[3]	values[5]	205	1			T8	19		T193	7		T199	21
auto[1]	values[3]	values[6]	225	1			T21	10		T202	7		T214	14
auto[1]	values[3]	values[7]	309	1			T8	12		T43	6		T32	20
auto[1]	values[4]	values[0]	264	1			T220	5		T199	12		T195	11
auto[1]	values[4]	values[1]	209	1			T201	41		T265	7		T210	43
auto[1]	values[4]	values[2]	184	1			T42	26		T45	12		T197	8
auto[1]	values[4]	values[3]	289	1			T8	10		T44	4		T223	40
auto[1]	values[4]	values[4]	217	1			T32	31		T211	8		T194	7
auto[1]	values[4]	values[5]	300	1			T44	5		T32	7		T209	26
auto[1]	values[4]	values[6]	162	1			T8	7		T21	18		T194	7
auto[1]	values[4]	values[7]	102	1			T197	9		T198	5		T266	14
auto[1]	values[5]	values[0]	185	1			T160	7		T189	3		T190	29
auto[1]	values[5]	values[1]	172	1			T191	20		T253	16		T213	9
auto[1]	values[5]	values[2]	153	1			T43	8		T45	17		T161	9
auto[1]	values[5]	values[3]	225	1			T42	14		T44	11		T31	9
auto[1]	values[5]	values[4]	188	1			T43	11		T45	13		T32	19
auto[1]	values[5]	values[5]	217	1			T220	14		T199	14		T213	18
auto[1]	values[5]	values[6]	137	1			T45	12		T201	6		T260	10
auto[1]	values[5]	values[7]	164	1			T14	10		T23	7		T193	7
auto[1]	values[6]	values[0]	209	1			T21	12		T31	14		T32	13
auto[1]	values[6]	values[1]	342	1			T44	9		T32	14		T213	15
auto[1]	values[6]	values[2]	126	1			T240	6		T52	10		T267	5
auto[1]	values[6]	values[3]	227	1			T32	13		T23	45		T199	5
auto[1]	values[6]	values[4]	96	1			T223	12		T199	14		T203	7
auto[1]	values[6]	values[5]	499	1			T45	9		T195	5		T201	64
auto[1]	values[6]	values[6]	322	1			T8	7		T23	24		T194	43
auto[1]	values[6]	values[7]	247	1			T14	6		T43	5		T44	3
auto[1]	values[7]	values[0]	203	1			T8	8		T44	9		T23	6
auto[1]	values[7]	values[1]	172	1			T21	5		T44	15		T160	13
auto[1]	values[7]	values[2]	148	1			T42	7		T260	25		T240	9
auto[1]	values[7]	values[3]	277	1			T199	11		T234	25		T268	50
auto[1]	values[7]	values[4]	123	1			T228	7		T202	6		T269	10
auto[1]	values[7]	values[5]	152	1			T37	8		T42	8		T160	13
auto[1]	values[7]	values[6]	120	1			T37	11		T213	8		T203	6
auto[1]	values[7]	values[7]	394	1			T21	13		T43	25		T45	7