Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	444	1			T8	2		T14	2		T39	2
auto[ReadAddrCrossIntoMailbox]	321	1			T8	6		T14	3		T37	1
auto[ReadAddrCrossOutOfMailbox]	348	1			T8	6		T14	2		T106	4
auto[ReadAddrCrossAllMailbox]	240	1			T14	1		T21	3		T43	4
auto[ReadAddrOutsideMailbox]	3663	1			T3	2		T8	36		T14	3

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2413

1

T3

1

T8

24

T14

6

auto[1]

2603

1

T3

1

T8

26

T14

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	804	1			T8	7		T14	4		T39	2
read_ops[0x0b]	838	1			T8	9		T14	1		T120	2
read_ops[0x3b]	879	1			T8	9		T14	1		T40	6
read_ops[0x6b]	844	1			T3	2		T8	10		T14	1
read_ops[0xbb]	846	1			T8	8		T14	1		T15	2
read_ops[0xeb]	805	1			T8	7		T14	3		T37	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T39	1		T120	1		T21	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T14	1		T39	1		T120	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T14	1		T21	1		T43	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T197	1		T194	2		T195	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T8	1		T14	1		T32	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T42	1		T44	1		T161	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T21	1		T227	1		T31	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T43	2		T227	1		T42	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	278	1			T8	2		T37	1		T106	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	328	1			T8	4		T14	1		T37	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T8	1		T120	1		T106	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T120	1		T106	1		T43	3
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T8	1		T106	2		T31	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T8	2		T106	2		T195	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T106	1		T45	1		T220	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T106	1		T43	1		T45	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T223	1		T199	1		T237	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T21	1		T160	1		T194	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	314	1			T8	2		T14	1		T226	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	314	1			T8	3		T226	1		T43	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	45	1			T40	3		T120	3		T44	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T40	3		T37	1		T120	3
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T8	1		T21	1		T31	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T14	1		T43	1		T42	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T8	2		T21	1		T197	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	44	1			T32	1		T23	1		T197	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T42	1		T45	1		T32	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T43	1		T32	1		T23	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	284	1			T8	3		T21	3		T43	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	345	1			T8	3		T37	1		T21	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T120	1		T42	1		T160	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	50	1			T8	1		T37	3		T120	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T8	1		T42	3		T44	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T8	1		T44	1		T32	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T21	1		T45	1		T32	3
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T43	1		T32	2		T23	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T21	1		T42	1		T193	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T32	1		T234	3		T161	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T3	1		T8	2		T14	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	330	1			T3	1		T8	5		T15	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T14	1		T40	1		T106	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T40	1		T106	1		T43	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T45	2		T32	1		T23	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T31	1		T23	1		T270	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T8	2		T106	1		T42	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T8	1		T106	1		T45	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T45	2		T271	1		T234	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	30	1			T160	1		T271	1		T228	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	311	1			T8	1		T15	1		T37	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	293	1			T8	4		T15	1		T106	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T43	3		T32	1		T211	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T42	1		T206	1		T259	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T37	1		T21	1		T43	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T14	1		T43	1		T44	3
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T14	1		T44	1		T211	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T43	1		T44	1		T45	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T245	1		T44	1		T45	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T14	1		T43	1		T245	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	292	1			T8	5		T120	1		T226	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T8	2		T37	1		T120	1