Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3467	1			T8	40		T14	24		T39	6
values[1]	4301	1			T8	41		T11	2		T64	8
values[2]	4076	1			T8	20		T14	22		T120	22
values[3]	3694	1			T8	58		T37	40		T226	18
values[4]	4299	1			T3	4		T5	2		T8	50
values[5]	3768	1			T4	16		T8	20		T48	4
values[6]	4306	1			T8	65		T14	28		T170	8
values[7]	3918	1			T8	24		T15	8		T21	58

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4412	1			T8	61		T37	20		T21	62
values[1]	4095	1			T8	40		T11	2		T14	46
values[2]	4180	1			T8	23		T96	10		T226	18
values[3]	3769	1			T8	50		T15	8		T21	45
values[4]	3957	1			T8	80		T39	6		T43	40
values[5]	3671	1			T3	4		T4	16		T8	20
values[6]	3457	1			T5	2		T8	44		T14	28
values[7]	4288	1			T14	21		T37	20		T120	22

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30994

1

T3

4

T4

16

T5

2

auto[1]

835

1

T8

9

T14

1

T37

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	275	1			T44	53		T194	20		T228	20
auto[0]	values[0]	values[1]	426	1			T14	24		T199	20		T201	20
auto[0]	values[0]	values[2]	389	1			T42	20		T45	23		T247	4
auto[0]	values[0]	values[3]	418	1			T8	16		T21	25		T160	19
auto[0]	values[0]	values[4]	432	1			T8	20		T39	6		T23	20
auto[0]	values[0]	values[5]	486	1			T43	20		T32	20		T230	4
auto[0]	values[0]	values[6]	378	1			T176	10		T43	62		T23	20
auto[0]	values[0]	values[7]	579	1			T200	10		T216	12		T246	20
auto[0]	values[1]	values[0]	453	1			T8	40		T21	42		T224	20
auto[0]	values[1]	values[1]	620	1			T11	2		T44	20		T197	39
auto[0]	values[1]	values[2]	567	1			T21	30		T45	26		T92	16
auto[0]	values[1]	values[3]	727	1			T42	20		T45	20		T231	95
auto[0]	values[1]	values[4]	510	1			T173	10		T199	114		T242	26
auto[0]	values[1]	values[5]	557	1			T21	20		T194	44		T199	20
auto[0]	values[1]	values[6]	345	1			T249	4		T197	28		T234	20
auto[0]	values[1]	values[7]	443	1			T64	8		T21	21		T44	33
auto[0]	values[2]	values[0]	539	1			T8	20		T44	24		T32	66
auto[0]	values[2]	values[1]	495	1			T14	21		T32	29		T211	20
auto[0]	values[2]	values[2]	532	1			T96	10		T43	20		T42	22
auto[0]	values[2]	values[3]	538	1			T32	35		T263	2		T194	50
auto[0]	values[2]	values[4]	495	1			T44	20		T193	21		T199	93
auto[0]	values[2]	values[5]	524	1			T21	24		T31	59		T251	8
auto[0]	values[2]	values[6]	399	1			T45	20		T32	26		T223	48
auto[0]	values[2]	values[7]	456	1			T120	22		T23	20		T193	23
auto[0]	values[3]	values[0]	504	1			T37	16		T91	2		T23	20
auto[0]	values[3]	values[1]	486	1			T44	22		T195	20		T268	47
auto[0]	values[3]	values[2]	375	1			T8	22		T226	18		T193	21
auto[0]	values[3]	values[3]	261	1			T201	23		T260	35		T189	20
auto[0]	values[3]	values[4]	755	1			T8	35		T245	2		T42	26
auto[0]	values[3]	values[5]	310	1			T32	20		T23	20		T220	57
auto[0]	values[3]	values[6]	471	1			T89	8		T199	20		T218	19
auto[0]	values[3]	values[7]	412	1			T37	19		T224	19		T166	39
auto[0]	values[4]	values[0]	655	1			T21	20		T223	24		T213	20
auto[0]	values[4]	values[1]	661	1			T8	20		T42	20		T45	20
auto[0]	values[4]	values[2]	506	1			T41	4		T167	12		T61	20
auto[0]	values[4]	values[3]	385	1			T8	29		T257	2		T233	18
auto[0]	values[4]	values[4]	325	1			T23	57		T160	19		T272	18
auto[0]	values[4]	values[5]	644	1			T3	4		T40	12		T42	22
auto[0]	values[4]	values[6]	432	1			T5	2		T23	20		T197	48
auto[0]	values[4]	values[7]	562	1			T14	21		T43	21		T259	2
auto[0]	values[5]	values[0]	658	1			T43	27		T42	146		T32	34
auto[0]	values[5]	values[1]	387	1			T106	24		T212	36		T273	43
auto[0]	values[5]	values[2]	511	1			T51	46		T45	27		T32	49
auto[0]	values[5]	values[3]	342	1			T21	20		T44	18		T45	19
auto[0]	values[5]	values[4]	407	1			T43	38		T197	20		T213	25
auto[0]	values[5]	values[5]	302	1			T4	16		T8	20		T48	4
auto[0]	values[5]	values[6]	482	1			T37	19		T227	4		T193	20
auto[0]	values[5]	values[7]	571	1			T209	26		T23	21		T274	6
auto[0]	values[6]	values[0]	654	1			T45	33		T32	17		T23	20
auto[0]	values[6]	values[1]	552	1			T8	20		T42	59		T221	18
auto[0]	values[6]	values[2]	629	1			T160	24		T195	20		T240	20
auto[0]	values[6]	values[3]	535	1			T206	10		T213	58		T212	42
auto[0]	values[6]	values[4]	393	1			T8	25		T42	19		T44	23
auto[0]	values[6]	values[5]	385	1			T223	51		T197	26		T270	6
auto[0]	values[6]	values[6]	391	1			T8	20		T14	28		T170	8
auto[0]	values[6]	values[7]	640	1			T248	6		T197	79		T160	43
auto[0]	values[7]	values[0]	553	1			T43	33		T32	29		T23	24
auto[0]	values[7]	values[1]	386	1			T45	20		T32	30		T275	2
auto[0]	values[7]	values[2]	562	1			T44	45		T201	20		T189	40
auto[0]	values[7]	values[3]	463	1			T15	8		T45	32		T160	40
auto[0]	values[7]	values[4]	538	1			T45	22		T160	20		T276	8
auto[0]	values[7]	values[5]	352	1			T43	21		T224	23		T277	20
auto[0]	values[7]	values[6]	458	1			T8	22		T42	20		T44	20
auto[0]	values[7]	values[7]	516	1			T21	58		T42	117		T193	19
auto[1]	values[0]	values[0]	18	1			T228	3		T273	2		T266	3
auto[1]	values[0]	values[1]	4	1			T203	1		T278	1		T279	1
auto[1]	values[0]	values[2]	4	1			T45	2		T192	1		T280	1
auto[1]	values[0]	values[3]	15	1			T8	4		T160	1		T237	1
auto[1]	values[0]	values[4]	8	1			T220	1		T260	3		T266	1
auto[1]	values[0]	values[5]	9	1			T199	1		T281	1		T282	4
auto[1]	values[0]	values[6]	8	1			T194	1		T161	2		T210	1
auto[1]	values[0]	values[7]	18	1			T222	1		T214	1		T203	1
auto[1]	values[1]	values[0]	8	1			T8	1		T213	2		T203	1
auto[1]	values[1]	values[1]	9	1			T132	1		T283	2		T284	4
auto[1]	values[1]	values[2]	13	1			T45	2		T31	1		T213	1
auto[1]	values[1]	values[3]	19	1			T199	2		T202	3		T285	1
auto[1]	values[1]	values[4]	3	1			T202	1		T286	1		T287	1
auto[1]	values[1]	values[5]	13	1			T203	5		T268	1		T281	4
auto[1]	values[1]	values[6]	4	1			T189	1		T210	1		T237	1
auto[1]	values[1]	values[7]	10	1			T21	2		T44	1		T218	2
auto[1]	values[2]	values[0]	14	1			T32	1		T161	1		T253	1
auto[1]	values[2]	values[1]	15	1			T14	1		T32	1		T223	2
auto[1]	values[2]	values[2]	14	1			T42	2		T44	3		T190	4
auto[1]	values[2]	values[3]	14	1			T32	2		T288	2		T52	1
auto[1]	values[2]	values[4]	10	1			T199	1		T289	6		T290	2
auto[1]	values[2]	values[5]	18	1			T31	5		T160	3		T201	2
auto[1]	values[2]	values[6]	7	1			T32	3		T290	1		T291	3
auto[1]	values[2]	values[7]	6	1			T193	1		T268	1		T52	1
auto[1]	values[3]	values[0]	22	1			T37	4		T237	4		T132	2
auto[1]	values[3]	values[1]	10	1			T205	1		T292	3		T293	1
auto[1]	values[3]	values[2]	11	1			T8	1		T199	4		T195	2
auto[1]	values[3]	values[3]	7	1			T237	1		T165	4		T294	1
auto[1]	values[3]	values[4]	35	1			T42	1		T45	3		T32	2
auto[1]	values[3]	values[5]	7	1			T220	5		T217	1		T219	1
auto[1]	values[3]	values[6]	18	1			T218	1		T295	1		T273	3
auto[1]	values[3]	values[7]	10	1			T37	1		T224	2		T166	2
auto[1]	values[4]	values[0]	25	1			T223	1		T204	1		T296	2
auto[1]	values[4]	values[1]	11	1			T31	2		T201	1		T189	1
auto[1]	values[4]	values[2]	21	1			T194	4		T202	2		T212	1
auto[1]	values[4]	values[3]	8	1			T8	1		T202	2		T265	2
auto[1]	values[4]	values[4]	10	1			T23	2		T160	1		T205	2
auto[1]	values[4]	values[5]	18	1			T42	1		T193	1		T160	3
auto[1]	values[4]	values[6]	16	1			T202	2		T295	1		T297	4
auto[1]	values[4]	values[7]	20	1			T189	4		T132	1		T295	3
auto[1]	values[5]	values[0]	14	1			T43	1		T42	2		T32	2
auto[1]	values[5]	values[1]	10	1			T212	1		T273	1		T52	2
auto[1]	values[5]	values[2]	11	1			T32	2		T217	2		T273	3
auto[1]	values[5]	values[3]	14	1			T44	2		T45	1		T194	1
auto[1]	values[5]	values[4]	10	1			T43	2		T213	4		T217	1
auto[1]	values[5]	values[5]	18	1			T21	4		T194	2		T298	2
auto[1]	values[5]	values[6]	11	1			T37	1		T234	6		T299	1
auto[1]	values[5]	values[7]	20	1			T189	1		T269	6		T217	2
auto[1]	values[6]	values[0]	13	1			T45	1		T32	3		T268	2
auto[1]	values[6]	values[1]	17	1			T42	1		T213	4		T265	2
auto[1]	values[6]	values[2]	21	1			T160	1		T212	1		T268	1
auto[1]	values[6]	values[3]	13	1			T213	1		T192	2		T300	1
auto[1]	values[6]	values[4]	7	1			T42	1		T45	1		T218	4
auto[1]	values[6]	values[5]	11	1			T260	2		T165	2		T273	1
auto[1]	values[6]	values[6]	27	1			T43	2		T191	12		T301	2
auto[1]	values[6]	values[7]	18	1			T160	2		T194	2		T161	2
auto[1]	values[7]	values[0]	7	1			T46	2		T201	2		T266	1
auto[1]	values[7]	values[1]	6	1			T32	1		T203	1		T292	1
auto[1]	values[7]	values[2]	14	1			T44	3		T300	4		T299	1
auto[1]	values[7]	values[3]	10	1			T194	1		T201	1		T240	1
auto[1]	values[7]	values[4]	19	1			T45	2		T276	2		T302	2
auto[1]	values[7]	values[5]	17	1			T43	1		T303	4		T304	1
auto[1]	values[7]	values[6]	10	1			T8	2		T197	1		T189	2
auto[1]	values[7]	values[7]	7	1			T193	2		T260	2		T166	1