Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	790	1			T6	17		T8	17		T14	4
all_values[1]	790	1			T6	17		T8	17		T14	4
all_values[2]	790	1			T6	17		T8	17		T14	4
all_values[3]	790	1			T6	17		T8	17		T14	4
all_values[4]	790	1			T6	17		T8	17		T14	4
all_values[5]	790	1			T6	17		T8	17		T14	4
all_values[6]	790	1			T6	17		T8	17		T14	4
all_values[7]	790	1			T6	17		T8	17		T14	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3391

1

T6

61

T8

66

T14

19

auto[1]

2929

1

T6

75

T8

70

T14

13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2595

1

T6

52

T8

44

T14

16

auto[1]

3725

1

T6

84

T8

92

T14

16

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3674

1

T6

76

T8

76

T14

21

auto[1]

2646

1

T6

60

T8

60

T14

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	167	1			T6	5		T8	2		T14	1
all_values[0]	auto[0]	auto[0]	auto[1]	76	1			T6	1		T8	2		T14	1
all_values[0]	auto[0]	auto[1]	auto[0]	126	1			T6	4		T8	1		T14	1
all_values[0]	auto[0]	auto[1]	auto[1]	88	1			T6	1		T8	4		T18	2
all_values[0]	auto[1]	auto[0]	auto[1]	175	1			T6	2		T8	4		T18	2
all_values[0]	auto[1]	auto[1]	auto[1]	158	1			T6	4		T8	4		T14	1
all_values[1]	auto[0]	auto[0]	auto[0]	165	1			T6	3		T8	2		T17	1
all_values[1]	auto[0]	auto[0]	auto[1]	85	1			T6	3		T8	1		T14	1
all_values[1]	auto[0]	auto[1]	auto[0]	122	1			T6	6		T8	2		T14	1
all_values[1]	auto[0]	auto[1]	auto[1]	81	1			T6	2		T8	2		T18	1
all_values[1]	auto[1]	auto[0]	auto[1]	183	1			T6	1		T8	3		T14	2
all_values[1]	auto[1]	auto[1]	auto[1]	154	1			T6	2		T8	7		T17	1
all_values[2]	auto[0]	auto[0]	auto[0]	182	1			T6	6		T14	2		T17	2
all_values[2]	auto[0]	auto[0]	auto[1]	64	1			T6	1		T8	1		T19	1
all_values[2]	auto[0]	auto[1]	auto[0]	144	1			T6	2		T8	4		T17	1
all_values[2]	auto[0]	auto[1]	auto[1]	78	1			T6	2		T8	4		T18	2
all_values[2]	auto[1]	auto[0]	auto[1]	165	1			T6	3		T8	4		T14	2
all_values[2]	auto[1]	auto[1]	auto[1]	157	1			T6	3		T8	4		T18	1
all_values[3]	auto[0]	auto[0]	auto[0]	188	1			T6	2		T8	2		T18	6
all_values[3]	auto[0]	auto[0]	auto[1]	88	1			T6	3		T8	7		T17	1
all_values[3]	auto[0]	auto[1]	auto[0]	105	1			T6	1		T18	2		T20	1
all_values[3]	auto[0]	auto[1]	auto[1]	79	1			T6	1		T8	2		T14	2
all_values[3]	auto[1]	auto[0]	auto[1]	164	1			T6	6		T8	4		T14	1
all_values[3]	auto[1]	auto[1]	auto[1]	166	1			T6	4		T8	2		T14	1
all_values[4]	auto[0]	auto[0]	auto[0]	168	1			T6	3		T8	2		T14	4
all_values[4]	auto[0]	auto[0]	auto[1]	76	1			T8	2		T18	1		T172	2
all_values[4]	auto[0]	auto[1]	auto[0]	127	1			T6	5		T8	3		T18	3
all_values[4]	auto[0]	auto[1]	auto[1]	92	1			T6	2		T8	1		T17	1
all_values[4]	auto[1]	auto[0]	auto[1]	170	1			T6	2		T8	3		T17	2
all_values[4]	auto[1]	auto[1]	auto[1]	157	1			T6	5		T8	6		T18	2
all_values[5]	auto[0]	auto[0]	auto[0]	232	1			T6	3		T8	2		T14	1
all_values[5]	auto[0]	auto[1]	auto[0]	206	1			T6	6		T8	7		T14	2
all_values[5]	auto[1]	auto[0]	auto[1]	190	1			T6	2		T8	4		T18	1
all_values[5]	auto[1]	auto[1]	auto[1]	162	1			T6	6		T8	4		T14	1
all_values[6]	auto[0]	auto[0]	auto[0]	176	1			T6	1		T8	2		T17	3
all_values[6]	auto[0]	auto[0]	auto[1]	65	1			T6	1		T8	2		T18	4
all_values[6]	auto[0]	auto[1]	auto[0]	130	1			T6	1		T8	2		T14	2
all_values[6]	auto[0]	auto[1]	auto[1]	79	1			T6	4		T8	3		T14	1
all_values[6]	auto[1]	auto[0]	auto[1]	184	1			T6	5		T8	4		T14	1
all_values[6]	auto[1]	auto[1]	auto[1]	156	1			T6	5		T8	4		T18	2
all_values[7]	auto[0]	auto[0]	auto[0]	203	1			T6	1		T8	10		T14	1
all_values[7]	auto[0]	auto[0]	auto[1]	63	1			T6	2		T8	1		T17	1
all_values[7]	auto[0]	auto[1]	auto[0]	154	1			T6	3		T8	3		T14	1
all_values[7]	auto[0]	auto[1]	auto[1]	65	1			T6	1		T18	2		T22	1
all_values[7]	auto[1]	auto[0]	auto[1]	162	1			T6	5		T8	2		T14	2
all_values[7]	auto[1]	auto[1]	auto[1]	143	1			T6	5		T8	1		T19	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal