Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1751

1

T2

24

T6

6

T8

12

auto[1]

1683

1

T2

20

T6

3

T8

8

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1782

1

T6

3

T8

16

T13

2

auto[1]

1652

1

T2

44

T6

6

T8

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2742

1

T2

44

T6

7

T8

12

auto[1]

692

1

T6

2

T8

8

T13

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	701	1			T2	8		T6	3		T8	7
valid[1]	693	1			T2	8		T8	4		T14	6
valid[2]	666	1			T2	11		T6	3		T8	1
valid[3]	677	1			T2	8		T6	2		T8	3
valid[4]	697	1			T2	9		T6	1		T8	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	105	1			T8	2		T14	1		T30	1
auto[0]	auto[0]	valid[0]	auto[1]	171	1			T2	5		T6	3		T8	1
auto[0]	auto[0]	valid[1]	auto[0]	104	1			T14	2		T30	1		T21	1
auto[0]	auto[0]	valid[1]	auto[1]	159	1			T2	5		T27	6		T17	1
auto[0]	auto[0]	valid[2]	auto[0]	111	1			T49	1		T21	1		T45	2
auto[0]	auto[0]	valid[2]	auto[1]	175	1			T2	5		T14	1		T27	5
auto[0]	auto[0]	valid[3]	auto[0]	102	1			T8	2		T17	1		T30	1
auto[0]	auto[0]	valid[3]	auto[1]	180	1			T2	7		T6	1		T14	1
auto[0]	auto[0]	valid[4]	auto[0]	117	1			T8	1		T28	2		T30	1
auto[0]	auto[0]	valid[4]	auto[1]	163	1			T2	2		T6	1		T8	2
auto[0]	auto[1]	valid[0]	auto[0]	123	1			T14	2		T30	2		T49	1
auto[0]	auto[1]	valid[0]	auto[1]	161	1			T2	3		T8	1		T26	1
auto[0]	auto[1]	valid[1]	auto[0]	109	1			T8	1		T17	1		T28	1
auto[0]	auto[1]	valid[1]	auto[1]	161	1			T2	3		T27	3		T87	2
auto[0]	auto[1]	valid[2]	auto[0]	95	1			T8	1		T17	1		T49	1
auto[0]	auto[1]	valid[2]	auto[1]	153	1			T2	6		T6	1		T27	3
auto[0]	auto[1]	valid[3]	auto[0]	111	1			T6	1		T30	1		T49	1
auto[0]	auto[1]	valid[3]	auto[1]	158	1			T2	1		T27	5		T29	2
auto[0]	auto[1]	valid[4]	auto[0]	113	1			T8	1		T13	1		T14	2
auto[0]	auto[1]	valid[4]	auto[1]	171	1			T2	7		T27	7		T29	1
auto[1]	auto[0]	valid[0]	auto[0]	72	1			T8	1		T28	1		T31	1
auto[1]	auto[0]	valid[1]	auto[0]	85	1			T8	2		T14	3		T17	1
auto[1]	auto[0]	valid[2]	auto[0]	67	1			T6	1		T13	1		T14	1
auto[1]	auto[0]	valid[3]	auto[0]	72	1			T8	1		T28	2		T21	3
auto[1]	auto[0]	valid[4]	auto[0]	68	1			T43	1		T319	1		T174	1
auto[1]	auto[1]	valid[0]	auto[0]	69	1			T8	2		T14	1		T28	1
auto[1]	auto[1]	valid[1]	auto[0]	75	1			T8	1		T14	1		T17	1
auto[1]	auto[1]	valid[2]	auto[0]	65	1			T6	1		T14	1		T17	1
auto[1]	auto[1]	valid[3]	auto[0]	54	1			T14	1		T17	1		T45	1
auto[1]	auto[1]	valid[4]	auto[0]	65	1			T8	1		T49	1		T21	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal