Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45932

1

T6

133

T8

384

T13

54

auto[1]

16557

1

T2

533

T6

49

T8

108

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45411

1

T2

533

T6

128

T8

335

auto[1]

17078

1

T6

54

T8

157

T13

16

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32339	1			T2	263		T6	90		T8	255
others[1]	5254	1			T2	62		T6	17		T8	36
others[2]	5323	1			T2	44		T6	13		T8	39
others[3]	5845	1			T2	57		T6	26		T8	47
interest[1]	3464	1			T2	28		T6	7		T8	34
interest[4]	21099	1			T2	171		T6	65		T8	174
interest[64]	10264	1			T2	79		T6	29		T8	81

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14832	1			T6	35		T8	115		T13	20
auto[0]	auto[0]	others[1]	2456	1			T6	7		T8	13		T13	4
auto[0]	auto[0]	others[2]	2481	1			T6	4		T8	14		T13	3
auto[0]	auto[0]	others[3]	2748	1			T6	17		T8	22		T13	5
auto[0]	auto[0]	interest[1]	1579	1			T6	4		T8	20		T13	3
auto[0]	auto[0]	interest[4]	9617	1			T6	29		T8	84		T13	10
auto[0]	auto[0]	interest[64]	4758	1			T6	12		T8	43		T13	3
auto[0]	auto[1]	others[0]	8666	1			T2	263		T6	28		T8	60
auto[0]	auto[1]	others[1]	1370	1			T2	62		T6	5		T8	6
auto[0]	auto[1]	others[2]	1377	1			T2	44		T6	3		T8	13
auto[0]	auto[1]	others[3]	1500	1			T2	57		T6	4		T8	10
auto[0]	auto[1]	interest[1]	947	1			T2	28		T6	3		T8	3
auto[0]	auto[1]	interest[4]	5850	1			T2	171		T6	17		T8	40
auto[0]	auto[1]	interest[64]	2697	1			T2	79		T6	6		T8	16
auto[1]	auto[0]	others[0]	8841	1			T6	27		T8	80		T13	3
auto[1]	auto[0]	others[1]	1428	1			T6	5		T8	17		T13	3
auto[1]	auto[0]	others[2]	1465	1			T6	6		T8	12		T13	1
auto[1]	auto[0]	others[3]	1597	1			T6	5		T8	15		T14	11
auto[1]	auto[0]	interest[1]	938	1			T8	11		T13	4		T14	6
auto[1]	auto[0]	interest[4]	5632	1			T6	19		T8	50		T13	3
auto[1]	auto[0]	interest[64]	2809	1			T6	11		T8	22		T13	5

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal