Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.29 95.43 99.26


Total test records in report: 1151
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T158 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2956428218 Jul 15 06:23:01 PM PDT 24 Jul 15 06:23:05 PM PDT 24 287493016 ps
T1036 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1410601304 Jul 15 06:23:09 PM PDT 24 Jul 15 06:23:10 PM PDT 24 23513457 ps
T1037 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3788932534 Jul 15 06:23:09 PM PDT 24 Jul 15 06:23:10 PM PDT 24 40659674 ps
T159 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3198020782 Jul 15 06:22:33 PM PDT 24 Jul 15 06:22:37 PM PDT 24 441626739 ps
T118 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3235288374 Jul 15 06:23:10 PM PDT 24 Jul 15 06:23:32 PM PDT 24 3340935186 ps
T1038 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1195415731 Jul 15 06:23:07 PM PDT 24 Jul 15 06:23:09 PM PDT 24 32819311 ps
T104 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1129206554 Jul 15 06:22:47 PM PDT 24 Jul 15 06:22:49 PM PDT 24 314231812 ps
T122 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4127841064 Jul 15 06:22:41 PM PDT 24 Jul 15 06:22:44 PM PDT 24 107583159 ps
T1039 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2758199073 Jul 15 06:23:09 PM PDT 24 Jul 15 06:23:10 PM PDT 24 17953379 ps
T123 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1962573572 Jul 15 06:23:02 PM PDT 24 Jul 15 06:23:05 PM PDT 24 184498644 ps
T1040 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.426146657 Jul 15 06:23:15 PM PDT 24 Jul 15 06:23:18 PM PDT 24 24643924 ps
T1041 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1056653706 Jul 15 06:22:32 PM PDT 24 Jul 15 06:22:35 PM PDT 24 80794559 ps
T180 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2264172645 Jul 15 06:23:03 PM PDT 24 Jul 15 06:23:27 PM PDT 24 2432466802 ps
T1042 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1813342181 Jul 15 06:23:07 PM PDT 24 Jul 15 06:23:08 PM PDT 24 15344692 ps
T1043 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4260923531 Jul 15 06:23:07 PM PDT 24 Jul 15 06:23:09 PM PDT 24 41799747 ps
T103 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2778554046 Jul 15 06:23:10 PM PDT 24 Jul 15 06:23:13 PM PDT 24 251341147 ps
T108 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3238306978 Jul 15 06:22:51 PM PDT 24 Jul 15 06:22:56 PM PDT 24 1974924277 ps
T1044 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1678450412 Jul 15 06:23:14 PM PDT 24 Jul 15 06:23:16 PM PDT 24 29525142 ps
T1045 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3229655664 Jul 15 06:23:10 PM PDT 24 Jul 15 06:23:11 PM PDT 24 13844946 ps
T1046 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3223981857 Jul 15 06:22:52 PM PDT 24 Jul 15 06:22:56 PM PDT 24 58874492 ps
T112 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.857075177 Jul 15 06:22:49 PM PDT 24 Jul 15 06:22:54 PM PDT 24 1642323162 ps
T116 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.4055507100 Jul 15 06:22:50 PM PDT 24 Jul 15 06:23:03 PM PDT 24 1367777641 ps
T1047 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.414485102 Jul 15 06:22:44 PM PDT 24 Jul 15 06:22:48 PM PDT 24 93436369 ps
T1048 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.785506206 Jul 15 06:22:50 PM PDT 24 Jul 15 06:22:52 PM PDT 24 43729981 ps
T1049 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1384767774 Jul 15 06:22:55 PM PDT 24 Jul 15 06:22:57 PM PDT 24 52567410 ps
T124 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1757699494 Jul 15 06:22:40 PM PDT 24 Jul 15 06:22:43 PM PDT 24 96968273 ps
T1050 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2251415220 Jul 15 06:22:45 PM PDT 24 Jul 15 06:22:54 PM PDT 24 201649761 ps
T1051 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1387477275 Jul 15 06:23:15 PM PDT 24 Jul 15 06:23:18 PM PDT 24 22216072 ps
T83 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.676939980 Jul 15 06:22:33 PM PDT 24 Jul 15 06:22:34 PM PDT 24 199919454 ps
T1052 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.652423051 Jul 15 06:22:42 PM PDT 24 Jul 15 06:22:43 PM PDT 24 46352230 ps
T84 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2644262053 Jul 15 06:22:42 PM PDT 24 Jul 15 06:22:44 PM PDT 24 120124071 ps
T178 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3681925553 Jul 15 06:22:48 PM PDT 24 Jul 15 06:23:10 PM PDT 24 3432808950 ps
T1053 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.579388706 Jul 15 06:23:09 PM PDT 24 Jul 15 06:23:11 PM PDT 24 12225219 ps
T109 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4226797989 Jul 15 06:22:33 PM PDT 24 Jul 15 06:22:38 PM PDT 24 184587141 ps
T1054 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1583458905 Jul 15 06:22:58 PM PDT 24 Jul 15 06:22:59 PM PDT 24 15553357 ps
T1055 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.733376224 Jul 15 06:23:01 PM PDT 24 Jul 15 06:23:05 PM PDT 24 183969551 ps
T1056 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3011149103 Jul 15 06:23:09 PM PDT 24 Jul 15 06:23:11 PM PDT 24 14914043 ps
T183 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4115115361 Jul 15 06:22:49 PM PDT 24 Jul 15 06:22:57 PM PDT 24 100741324 ps
T125 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1842314908 Jul 15 06:23:00 PM PDT 24 Jul 15 06:23:02 PM PDT 24 471573545 ps
T126 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.477528759 Jul 15 06:22:42 PM PDT 24 Jul 15 06:23:04 PM PDT 24 495411295 ps
T1057 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1051540447 Jul 15 06:23:07 PM PDT 24 Jul 15 06:23:08 PM PDT 24 21125766 ps
T1058 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2594218184 Jul 15 06:23:02 PM PDT 24 Jul 15 06:23:07 PM PDT 24 1177588524 ps
T1059 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2673804320 Jul 15 06:22:56 PM PDT 24 Jul 15 06:23:00 PM PDT 24 189515564 ps
T1060 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3008870089 Jul 15 06:22:49 PM PDT 24 Jul 15 06:22:52 PM PDT 24 311410258 ps
T1061 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.935179616 Jul 15 06:23:08 PM PDT 24 Jul 15 06:23:09 PM PDT 24 13766934 ps
T181 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2583515554 Jul 15 06:22:56 PM PDT 24 Jul 15 06:23:16 PM PDT 24 1147590263 ps
T127 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1737247121 Jul 15 06:23:15 PM PDT 24 Jul 15 06:23:18 PM PDT 24 237597785 ps
T1062 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2129095917 Jul 15 06:22:57 PM PDT 24 Jul 15 06:23:00 PM PDT 24 82336278 ps
T128 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3537337152 Jul 15 06:22:47 PM PDT 24 Jul 15 06:22:50 PM PDT 24 40519656 ps
T1063 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2081699918 Jul 15 06:22:55 PM PDT 24 Jul 15 06:23:00 PM PDT 24 60444037 ps
T1064 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1193459867 Jul 15 06:23:09 PM PDT 24 Jul 15 06:23:10 PM PDT 24 18575061 ps
T1065 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1719912553 Jul 15 06:22:34 PM PDT 24 Jul 15 06:22:35 PM PDT 24 24742782 ps
T1066 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4008444444 Jul 15 06:22:32 PM PDT 24 Jul 15 06:22:36 PM PDT 24 91352614 ps
T110 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3709597608 Jul 15 06:22:47 PM PDT 24 Jul 15 06:22:50 PM PDT 24 79815990 ps
T1067 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.378190224 Jul 15 06:22:59 PM PDT 24 Jul 15 06:23:02 PM PDT 24 599322226 ps
T1068 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2028391803 Jul 15 06:22:43 PM PDT 24 Jul 15 06:22:46 PM PDT 24 46414114 ps
T1069 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.554696207 Jul 15 06:22:41 PM PDT 24 Jul 15 06:22:45 PM PDT 24 211826225 ps
T182 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.830866340 Jul 15 06:23:02 PM PDT 24 Jul 15 06:23:22 PM PDT 24 1191546908 ps
T85 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3102020060 Jul 15 06:22:36 PM PDT 24 Jul 15 06:22:38 PM PDT 24 159648779 ps
T129 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3853164776 Jul 15 06:22:45 PM PDT 24 Jul 15 06:23:03 PM PDT 24 8076654736 ps
T1070 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2885782369 Jul 15 06:23:15 PM PDT 24 Jul 15 06:23:17 PM PDT 24 37032541 ps
T1071 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2958102412 Jul 15 06:23:14 PM PDT 24 Jul 15 06:23:16 PM PDT 24 46319815 ps
T86 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1803186881 Jul 15 06:22:42 PM PDT 24 Jul 15 06:22:44 PM PDT 24 24564576 ps
T1072 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.852067920 Jul 15 06:22:44 PM PDT 24 Jul 15 06:22:46 PM PDT 24 29199443 ps
T1073 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.954910558 Jul 15 06:23:07 PM PDT 24 Jul 15 06:23:09 PM PDT 24 26322014 ps
T1074 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3210604971 Jul 15 06:23:07 PM PDT 24 Jul 15 06:23:08 PM PDT 24 15032876 ps
T1075 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2081299281 Jul 15 06:22:33 PM PDT 24 Jul 15 06:22:52 PM PDT 24 296435502 ps
T113 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1105833484 Jul 15 06:23:06 PM PDT 24 Jul 15 06:23:12 PM PDT 24 543120959 ps
T1076 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2889137515 Jul 15 06:22:52 PM PDT 24 Jul 15 06:22:54 PM PDT 24 93230032 ps
T1077 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2511662452 Jul 15 06:23:00 PM PDT 24 Jul 15 06:23:03 PM PDT 24 344270169 ps
T130 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2713586458 Jul 15 06:22:44 PM PDT 24 Jul 15 06:23:23 PM PDT 24 11238504091 ps
T1078 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3274762174 Jul 15 06:22:49 PM PDT 24 Jul 15 06:22:58 PM PDT 24 3231724777 ps
T1079 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3571506820 Jul 15 06:22:57 PM PDT 24 Jul 15 06:23:05 PM PDT 24 292270013 ps
T131 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2360917431 Jul 15 06:22:34 PM PDT 24 Jul 15 06:22:37 PM PDT 24 27770439 ps
T184 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.23068733 Jul 15 06:23:03 PM PDT 24 Jul 15 06:23:23 PM PDT 24 1213155472 ps
T1080 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2837925355 Jul 15 06:23:15 PM PDT 24 Jul 15 06:23:19 PM PDT 24 416992565 ps
T1081 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.151612735 Jul 15 06:22:55 PM PDT 24 Jul 15 06:22:56 PM PDT 24 63257198 ps
T179 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.538613135 Jul 15 06:22:44 PM PDT 24 Jul 15 06:22:52 PM PDT 24 549394112 ps
T111 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.206352569 Jul 15 06:22:41 PM PDT 24 Jul 15 06:22:45 PM PDT 24 590998739 ps
T1082 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2500374272 Jul 15 06:23:10 PM PDT 24 Jul 15 06:23:12 PM PDT 24 42273075 ps
T1083 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1017122048 Jul 15 06:23:04 PM PDT 24 Jul 15 06:23:07 PM PDT 24 148272326 ps
T1084 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.583672032 Jul 15 06:22:49 PM PDT 24 Jul 15 06:22:51 PM PDT 24 13303147 ps
T1085 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.568003246 Jul 15 06:22:57 PM PDT 24 Jul 15 06:23:11 PM PDT 24 657811786 ps
T1086 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2428322725 Jul 15 06:22:48 PM PDT 24 Jul 15 06:22:50 PM PDT 24 80338587 ps
T1087 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.613905558 Jul 15 06:23:07 PM PDT 24 Jul 15 06:23:09 PM PDT 24 13058381 ps
T1088 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1357093524 Jul 15 06:22:49 PM PDT 24 Jul 15 06:22:55 PM PDT 24 1044310989 ps
T1089 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2609232017 Jul 15 06:22:56 PM PDT 24 Jul 15 06:23:01 PM PDT 24 311335742 ps
T1090 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1433855726 Jul 15 06:23:10 PM PDT 24 Jul 15 06:23:11 PM PDT 24 29715707 ps
T1091 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.98089955 Jul 15 06:22:49 PM PDT 24 Jul 15 06:22:53 PM PDT 24 111846353 ps
T1092 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3985305464 Jul 15 06:23:02 PM PDT 24 Jul 15 06:23:06 PM PDT 24 98237463 ps
T1093 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.967264871 Jul 15 06:22:33 PM PDT 24 Jul 15 06:22:38 PM PDT 24 149303244 ps
T1094 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3346775488 Jul 15 06:22:35 PM PDT 24 Jul 15 06:22:37 PM PDT 24 56554870 ps
T1095 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1947411428 Jul 15 06:22:50 PM PDT 24 Jul 15 06:22:53 PM PDT 24 255035581 ps
T1096 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3255872789 Jul 15 06:22:42 PM PDT 24 Jul 15 06:22:43 PM PDT 24 44648117 ps
T1097 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.336815277 Jul 15 06:22:40 PM PDT 24 Jul 15 06:22:42 PM PDT 24 141417805 ps
T1098 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4060361022 Jul 15 06:22:49 PM PDT 24 Jul 15 06:22:53 PM PDT 24 301287075 ps
T1099 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2844020995 Jul 15 06:22:48 PM PDT 24 Jul 15 06:22:52 PM PDT 24 159659274 ps
T1100 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3027754030 Jul 15 06:22:55 PM PDT 24 Jul 15 06:22:57 PM PDT 24 90019623 ps
T1101 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2452389892 Jul 15 06:23:01 PM PDT 24 Jul 15 06:23:03 PM PDT 24 31014408 ps
T1102 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1186395644 Jul 15 06:22:32 PM PDT 24 Jul 15 06:22:41 PM PDT 24 410330631 ps
T1103 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3222487473 Jul 15 06:23:15 PM PDT 24 Jul 15 06:23:20 PM PDT 24 379056843 ps
T1104 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1232337243 Jul 15 06:23:11 PM PDT 24 Jul 15 06:23:12 PM PDT 24 11446527 ps
T1105 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3584372951 Jul 15 06:22:45 PM PDT 24 Jul 15 06:22:47 PM PDT 24 39559540 ps
T1106 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1903018474 Jul 15 06:22:49 PM PDT 24 Jul 15 06:22:54 PM PDT 24 54697079 ps
T1107 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2593926353 Jul 15 06:22:40 PM PDT 24 Jul 15 06:22:41 PM PDT 24 12942285 ps
T1108 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.477155568 Jul 15 06:22:49 PM PDT 24 Jul 15 06:22:52 PM PDT 24 26709199 ps
T1109 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1539517018 Jul 15 06:22:34 PM PDT 24 Jul 15 06:22:36 PM PDT 24 21646953 ps
T1110 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.90986294 Jul 15 06:23:09 PM PDT 24 Jul 15 06:23:10 PM PDT 24 119686605 ps
T1111 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3604380108 Jul 15 06:22:32 PM PDT 24 Jul 15 06:22:33 PM PDT 24 11359797 ps
T185 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2101040350 Jul 15 06:22:33 PM PDT 24 Jul 15 06:22:47 PM PDT 24 2267173412 ps
T1112 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1839190994 Jul 15 06:23:14 PM PDT 24 Jul 15 06:23:15 PM PDT 24 19801667 ps
T1113 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2105410365 Jul 15 06:22:33 PM PDT 24 Jul 15 06:22:34 PM PDT 24 83030106 ps
T1114 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1107144802 Jul 15 06:22:34 PM PDT 24 Jul 15 06:22:47 PM PDT 24 363302228 ps
T1115 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.71918876 Jul 15 06:22:56 PM PDT 24 Jul 15 06:22:58 PM PDT 24 29083101 ps
T1116 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1545419027 Jul 15 06:22:49 PM PDT 24 Jul 15 06:22:50 PM PDT 24 12878552 ps
T1117 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1515729157 Jul 15 06:23:00 PM PDT 24 Jul 15 06:23:04 PM PDT 24 179792004 ps
T1118 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3610301489 Jul 15 06:23:14 PM PDT 24 Jul 15 06:23:15 PM PDT 24 16059117 ps
T1119 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3708808190 Jul 15 06:22:45 PM PDT 24 Jul 15 06:23:03 PM PDT 24 2441032178 ps
T1120 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.475320023 Jul 15 06:22:42 PM PDT 24 Jul 15 06:22:46 PM PDT 24 253850073 ps
T1121 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.343821636 Jul 15 06:22:36 PM PDT 24 Jul 15 06:22:53 PM PDT 24 2203880928 ps
T1122 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.965583868 Jul 15 06:22:56 PM PDT 24 Jul 15 06:22:59 PM PDT 24 206361604 ps
T1123 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3618545442 Jul 15 06:22:32 PM PDT 24 Jul 15 06:22:33 PM PDT 24 18753509 ps
T1124 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.33704763 Jul 15 06:22:55 PM PDT 24 Jul 15 06:22:58 PM PDT 24 130037505 ps
T1125 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2261755542 Jul 15 06:23:14 PM PDT 24 Jul 15 06:23:19 PM PDT 24 62486936 ps
T1126 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.83826647 Jul 15 06:23:02 PM PDT 24 Jul 15 06:23:05 PM PDT 24 74877393 ps
T1127 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2101231233 Jul 15 06:23:15 PM PDT 24 Jul 15 06:23:17 PM PDT 24 26535543 ps
T1128 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.114166069 Jul 15 06:22:41 PM PDT 24 Jul 15 06:22:46 PM PDT 24 207510282 ps
T1129 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2925068121 Jul 15 06:23:08 PM PDT 24 Jul 15 06:23:09 PM PDT 24 66162665 ps
T1130 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2594698322 Jul 15 06:22:32 PM PDT 24 Jul 15 06:22:34 PM PDT 24 76298894 ps
T1131 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1744590298 Jul 15 06:22:42 PM PDT 24 Jul 15 06:22:47 PM PDT 24 153954233 ps
T1132 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.727810006 Jul 15 06:22:42 PM PDT 24 Jul 15 06:22:44 PM PDT 24 792410502 ps
T1133 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1175143458 Jul 15 06:22:51 PM PDT 24 Jul 15 06:23:03 PM PDT 24 385433489 ps
T1134 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.599513702 Jul 15 06:23:03 PM PDT 24 Jul 15 06:23:07 PM PDT 24 127350888 ps
T1135 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2191866044 Jul 15 06:22:44 PM PDT 24 Jul 15 06:22:47 PM PDT 24 67580536 ps
T1136 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1168902306 Jul 15 06:22:41 PM PDT 24 Jul 15 06:22:46 PM PDT 24 594026927 ps
T1137 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3042940718 Jul 15 06:22:57 PM PDT 24 Jul 15 06:23:01 PM PDT 24 202581998 ps
T1138 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2875061850 Jul 15 06:22:47 PM PDT 24 Jul 15 06:22:50 PM PDT 24 78513118 ps
T1139 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.772761924 Jul 15 06:22:51 PM PDT 24 Jul 15 06:22:55 PM PDT 24 56152454 ps
T1140 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.228243678 Jul 15 06:23:10 PM PDT 24 Jul 15 06:23:12 PM PDT 24 47256567 ps
T1141 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1987248972 Jul 15 06:22:56 PM PDT 24 Jul 15 06:22:57 PM PDT 24 39748004 ps
T1142 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.751903806 Jul 15 06:22:48 PM PDT 24 Jul 15 06:22:50 PM PDT 24 52765775 ps
T1143 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2267924752 Jul 15 06:22:54 PM PDT 24 Jul 15 06:22:57 PM PDT 24 1198627842 ps
T1144 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4224408480 Jul 15 06:22:58 PM PDT 24 Jul 15 06:22:59 PM PDT 24 40011279 ps
T1145 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3098955828 Jul 15 06:23:02 PM PDT 24 Jul 15 06:23:03 PM PDT 24 14710858 ps
T1146 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.328147135 Jul 15 06:22:34 PM PDT 24 Jul 15 06:23:16 PM PDT 24 11232883511 ps
T1147 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3233991817 Jul 15 06:22:33 PM PDT 24 Jul 15 06:22:37 PM PDT 24 74870945 ps
T1148 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2831252648 Jul 15 06:23:06 PM PDT 24 Jul 15 06:23:11 PM PDT 24 1965170939 ps
T1149 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1774348081 Jul 15 06:22:42 PM PDT 24 Jul 15 06:23:08 PM PDT 24 2517299292 ps
T1150 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3635395320 Jul 15 06:23:09 PM PDT 24 Jul 15 06:23:10 PM PDT 24 36985050 ps
T177 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3893271241 Jul 15 06:22:55 PM PDT 24 Jul 15 06:22:59 PM PDT 24 697794992 ps
T1151 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1571412946 Jul 15 06:23:03 PM PDT 24 Jul 15 06:23:06 PM PDT 24 37201668 ps

Test location /workspace/coverage/default/14.spi_device_stress_all.3661636557
Short name T8
Test name
Test status
Simulation time 18939249773 ps
CPU time 278.28 seconds
Started Jul 15 06:24:21 PM PDT 24
Finished Jul 15 06:29:00 PM PDT 24
Peak memory 271328 kb
Host smart-6eafc970-d73e-4da4-be3c-10dbcff53dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661636557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3661636557
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3851354998
Short name T13
Test name
Test status
Simulation time 47762962029 ps
CPU time 108.02 seconds
Started Jul 15 06:26:28 PM PDT 24
Finished Jul 15 06:28:17 PM PDT 24
Peak memory 255528 kb
Host smart-3100fb3d-9940-4d44-be35-a2e185db7fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851354998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3851354998
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.566695865
Short name T101
Test name
Test status
Simulation time 4649313781 ps
CPU time 20.43 seconds
Started Jul 15 06:23:06 PM PDT 24
Finished Jul 15 06:23:27 PM PDT 24
Peak memory 215560 kb
Host smart-2d3b928b-87d6-42ec-bdcc-90c231acdfa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566695865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.566695865
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.4067609323
Short name T45
Test name
Test status
Simulation time 106231964999 ps
CPU time 358.97 seconds
Started Jul 15 06:26:10 PM PDT 24
Finished Jul 15 06:32:11 PM PDT 24
Peak memory 266724 kb
Host smart-7f9ecc9a-574c-4308-b25a-493e1d8981b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067609323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.4067609323
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1844820758
Short name T220
Test name
Test status
Simulation time 18670749704 ps
CPU time 109.59 seconds
Started Jul 15 06:24:16 PM PDT 24
Finished Jul 15 06:26:06 PM PDT 24
Peak memory 254280 kb
Host smart-71bb59d8-6b51-49ca-a7fc-b2065b7ebcaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844820758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1844820758
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2267044078
Short name T65
Test name
Test status
Simulation time 54936107 ps
CPU time 0.74 seconds
Started Jul 15 06:23:16 PM PDT 24
Finished Jul 15 06:23:18 PM PDT 24
Peak memory 217028 kb
Host smart-9a865c08-6ef2-4fe0-bdfa-26cb3690f6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267044078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2267044078
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.431715704
Short name T23
Test name
Test status
Simulation time 28832775582 ps
CPU time 276.3 seconds
Started Jul 15 06:26:18 PM PDT 24
Finished Jul 15 06:30:55 PM PDT 24
Peak memory 266588 kb
Host smart-bef1ab59-080e-40b3-b35d-759af9080184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431715704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.431715704
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2171048902
Short name T21
Test name
Test status
Simulation time 276227597234 ps
CPU time 431.79 seconds
Started Jul 15 06:24:51 PM PDT 24
Finished Jul 15 06:32:04 PM PDT 24
Peak memory 258540 kb
Host smart-e08229a0-e256-4f40-81fc-0b5b726ea685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171048902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2171048902
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.712299871
Short name T32
Test name
Test status
Simulation time 171265893475 ps
CPU time 323.91 seconds
Started Jul 15 06:25:31 PM PDT 24
Finished Jul 15 06:30:56 PM PDT 24
Peak memory 274980 kb
Host smart-ab7c9e00-ca2c-4bf1-80af-cfa2c9881bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712299871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.712299871
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1646274501
Short name T166
Test name
Test status
Simulation time 62140552828 ps
CPU time 682.69 seconds
Started Jul 15 06:25:52 PM PDT 24
Finished Jul 15 06:37:16 PM PDT 24
Peak memory 282688 kb
Host smart-117bb964-b874-4a06-b751-a5430da3a4b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646274501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1646274501
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2587961598
Short name T98
Test name
Test status
Simulation time 219715957 ps
CPU time 4.43 seconds
Started Jul 15 06:23:01 PM PDT 24
Finished Jul 15 06:23:06 PM PDT 24
Peak memory 215728 kb
Host smart-d184cfa8-3b61-4675-a4f7-62288c8a6f1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587961598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2587961598
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.4042872568
Short name T168
Test name
Test status
Simulation time 42644976 ps
CPU time 0.79 seconds
Started Jul 15 06:23:15 PM PDT 24
Finished Jul 15 06:23:17 PM PDT 24
Peak memory 206396 kb
Host smart-71c02ba1-02a3-48ba-817a-1f721f9bed91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042872568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4
042872568
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3732952020
Short name T189
Test name
Test status
Simulation time 10831814686 ps
CPU time 140.65 seconds
Started Jul 15 06:23:37 PM PDT 24
Finished Jul 15 06:25:59 PM PDT 24
Peak memory 268156 kb
Host smart-f0d00744-14ca-4598-ae1b-a89b63b543e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732952020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3732952020
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.44746245
Short name T151
Test name
Test status
Simulation time 10062189784 ps
CPU time 24.41 seconds
Started Jul 15 06:25:35 PM PDT 24
Finished Jul 15 06:26:01 PM PDT 24
Peak memory 234412 kb
Host smart-61f29b6c-62e5-4b7e-9d16-24f3e76bc347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44746245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.44746245
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1609607247
Short name T199
Test name
Test status
Simulation time 55393606226 ps
CPU time 257.63 seconds
Started Jul 15 06:23:14 PM PDT 24
Finished Jul 15 06:27:32 PM PDT 24
Peak memory 256944 kb
Host smart-bbc6eda6-0fc5-4ebc-a4d1-3016a2ec6445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609607247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1609607247
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.676939980
Short name T83
Test name
Test status
Simulation time 199919454 ps
CPU time 1.22 seconds
Started Jul 15 06:22:33 PM PDT 24
Finished Jul 15 06:22:34 PM PDT 24
Peak memory 207300 kb
Host smart-889e9e89-3599-4351-a2fd-d33ec1fb9a0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676939980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.676939980
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.347208288
Short name T132
Test name
Test status
Simulation time 27602664257 ps
CPU time 353.87 seconds
Started Jul 15 06:25:36 PM PDT 24
Finished Jul 15 06:31:31 PM PDT 24
Peak memory 271468 kb
Host smart-cfbd8222-2d98-48ff-bec7-5ccfea3ca512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347208288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.347208288
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.236087372
Short name T202
Test name
Test status
Simulation time 78321604677 ps
CPU time 552.37 seconds
Started Jul 15 06:23:45 PM PDT 24
Finished Jul 15 06:32:58 PM PDT 24
Peak memory 273968 kb
Host smart-1ae58832-c653-4e51-ae26-517f2647e6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236087372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
236087372
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.40414180
Short name T42
Test name
Test status
Simulation time 16660910113 ps
CPU time 99.75 seconds
Started Jul 15 06:26:19 PM PDT 24
Finished Jul 15 06:28:00 PM PDT 24
Peak memory 274504 kb
Host smart-27baa548-2c9b-4384-a6a8-e44b2c4fe35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40414180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.40414180
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2897145664
Short name T36
Test name
Test status
Simulation time 51627096 ps
CPU time 1.06 seconds
Started Jul 15 06:23:16 PM PDT 24
Finished Jul 15 06:23:19 PM PDT 24
Peak memory 217688 kb
Host smart-72c17691-6434-47a7-b92f-6cd3c29be42c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897145664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2897145664
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1444054491
Short name T285
Test name
Test status
Simulation time 27361821508 ps
CPU time 353.05 seconds
Started Jul 15 06:26:01 PM PDT 24
Finished Jul 15 06:31:55 PM PDT 24
Peak memory 290756 kb
Host smart-982d6b9e-64f4-4e0c-9687-d4cc63d03c3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444054491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1444054491
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2322338803
Short name T68
Test name
Test status
Simulation time 193063644 ps
CPU time 1.17 seconds
Started Jul 15 06:23:16 PM PDT 24
Finished Jul 15 06:23:19 PM PDT 24
Peak memory 236376 kb
Host smart-01565b12-47ea-4df1-bffa-552f1a459f6f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322338803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2322338803
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3630899351
Short name T160
Test name
Test status
Simulation time 50165354727 ps
CPU time 195.62 seconds
Started Jul 15 06:25:02 PM PDT 24
Finished Jul 15 06:28:18 PM PDT 24
Peak memory 274404 kb
Host smart-b56c2e39-0336-4908-9c86-67c472dc74ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630899351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3630899351
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2223355354
Short name T203
Test name
Test status
Simulation time 32228756581 ps
CPU time 305.67 seconds
Started Jul 15 06:24:07 PM PDT 24
Finished Jul 15 06:29:14 PM PDT 24
Peak memory 256184 kb
Host smart-643b4aaf-32ec-458d-8042-d1763d02882a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223355354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2223355354
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3497304629
Short name T44
Test name
Test status
Simulation time 24664128119 ps
CPU time 316.04 seconds
Started Jul 15 06:24:14 PM PDT 24
Finished Jul 15 06:29:31 PM PDT 24
Peak memory 274728 kb
Host smart-424d3192-5aa7-4579-a807-ae5281d5bc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497304629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3497304629
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.4236658936
Short name T219
Test name
Test status
Simulation time 17178400358 ps
CPU time 178.53 seconds
Started Jul 15 06:26:17 PM PDT 24
Finished Jul 15 06:29:16 PM PDT 24
Peak memory 255000 kb
Host smart-50a8e7d1-5914-430c-ae7e-0a482e3e737b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236658936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.4236658936
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3681925553
Short name T178
Test name
Test status
Simulation time 3432808950 ps
CPU time 21.83 seconds
Started Jul 15 06:22:48 PM PDT 24
Finished Jul 15 06:23:10 PM PDT 24
Peak memory 215892 kb
Host smart-bd62dae5-8611-470d-b171-08e76c281723
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681925553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3681925553
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2265692491
Short name T43
Test name
Test status
Simulation time 13729617473 ps
CPU time 191.89 seconds
Started Jul 15 06:25:39 PM PDT 24
Finished Jul 15 06:28:51 PM PDT 24
Peak memory 274084 kb
Host smart-534a2170-8f53-4f6d-b3ef-30f8bdfbbab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265692491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2265692491
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2081525103
Short name T93
Test name
Test status
Simulation time 14347190764 ps
CPU time 63.45 seconds
Started Jul 15 06:26:00 PM PDT 24
Finished Jul 15 06:27:04 PM PDT 24
Peak memory 255000 kb
Host smart-7fa6181c-128b-4d3b-a82d-5a045cb56f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081525103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2081525103
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.967264871
Short name T1093
Test name
Test status
Simulation time 149303244 ps
CPU time 4.18 seconds
Started Jul 15 06:22:33 PM PDT 24
Finished Jul 15 06:22:38 PM PDT 24
Peak memory 215684 kb
Host smart-ab7e1656-1bde-4c97-b9b4-7bbb8ddb8c2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967264871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.967264871
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1446607290
Short name T267
Test name
Test status
Simulation time 10172165798 ps
CPU time 98.1 seconds
Started Jul 15 06:25:56 PM PDT 24
Finished Jul 15 06:27:35 PM PDT 24
Peak memory 251216 kb
Host smart-9e5bac9d-b2a0-42ea-a6b2-847775a86d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446607290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1446607290
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2894259464
Short name T306
Test name
Test status
Simulation time 960478733 ps
CPU time 13.05 seconds
Started Jul 15 06:23:48 PM PDT 24
Finished Jul 15 06:24:01 PM PDT 24
Peak memory 241872 kb
Host smart-416a52a5-4b6b-45a8-92e8-c57366a19c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894259464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2894259464
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.457534226
Short name T201
Test name
Test status
Simulation time 3862579580 ps
CPU time 103.18 seconds
Started Jul 15 06:23:24 PM PDT 24
Finished Jul 15 06:25:08 PM PDT 24
Peak memory 258568 kb
Host smart-84660835-0243-40a8-86c2-40e5379aa366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457534226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
457534226
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3899942156
Short name T161
Test name
Test status
Simulation time 45292931850 ps
CPU time 435.97 seconds
Started Jul 15 06:24:06 PM PDT 24
Finished Jul 15 06:31:23 PM PDT 24
Peak memory 252664 kb
Host smart-cdad8dc9-2d76-4c44-992b-73c2892e9bed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899942156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3899942156
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3340389415
Short name T17
Test name
Test status
Simulation time 63834825733 ps
CPU time 109.84 seconds
Started Jul 15 06:25:51 PM PDT 24
Finished Jul 15 06:27:42 PM PDT 24
Peak memory 256684 kb
Host smart-9f7ebf6e-6450-4495-b06d-bf85cda5d416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340389415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3340389415
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2489917819
Short name T48
Test name
Test status
Simulation time 10101178095 ps
CPU time 62.24 seconds
Started Jul 15 06:25:33 PM PDT 24
Finished Jul 15 06:26:36 PM PDT 24
Peak memory 233896 kb
Host smart-ce3db563-6359-4108-aa96-5fd40799890d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489917819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2489917819
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3919278263
Short name T273
Test name
Test status
Simulation time 114118905069 ps
CPU time 177.15 seconds
Started Jul 15 06:23:32 PM PDT 24
Finished Jul 15 06:26:30 PM PDT 24
Peak memory 266816 kb
Host smart-da7d94d4-1e33-4feb-8082-060ab1e4e39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919278263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3919278263
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1405364008
Short name T99
Test name
Test status
Simulation time 2429283260 ps
CPU time 3.64 seconds
Started Jul 15 06:23:08 PM PDT 24
Finished Jul 15 06:23:12 PM PDT 24
Peak memory 215860 kb
Host smart-c980b181-ebe7-4be8-ba70-60ffe54da607
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405364008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1405364008
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2101040350
Short name T185
Test name
Test status
Simulation time 2267173412 ps
CPU time 14.19 seconds
Started Jul 15 06:22:33 PM PDT 24
Finished Jul 15 06:22:47 PM PDT 24
Peak memory 215980 kb
Host smart-69291392-cd1e-4eda-8e82-895a7a096116
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101040350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2101040350
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.20266805
Short name T97
Test name
Test status
Simulation time 2822564345 ps
CPU time 14.89 seconds
Started Jul 15 06:22:35 PM PDT 24
Finished Jul 15 06:22:51 PM PDT 24
Peak memory 216732 kb
Host smart-aa441f29-c435-4ed4-90bf-88e08aec3e07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20266805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_t
l_intg_err.20266805
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1853297929
Short name T308
Test name
Test status
Simulation time 314676689 ps
CPU time 10.9 seconds
Started Jul 15 06:23:17 PM PDT 24
Finished Jul 15 06:23:29 PM PDT 24
Peak memory 233764 kb
Host smart-c7d3e5bd-f228-4673-aca7-3195b7855819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853297929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1853297929
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1258664258
Short name T292
Test name
Test status
Simulation time 41855862168 ps
CPU time 70.74 seconds
Started Jul 15 06:24:09 PM PDT 24
Finished Jul 15 06:25:20 PM PDT 24
Peak memory 251704 kb
Host smart-70090a32-ddc8-4f52-8be7-316f9a8e4364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258664258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1258664258
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2679390636
Short name T193
Test name
Test status
Simulation time 175693437439 ps
CPU time 378.74 seconds
Started Jul 15 06:24:14 PM PDT 24
Finished Jul 15 06:30:33 PM PDT 24
Peak memory 250384 kb
Host smart-e1f15e75-6082-4c7f-8881-4fd49d764f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679390636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2679390636
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1564479750
Short name T229
Test name
Test status
Simulation time 53999297725 ps
CPU time 147 seconds
Started Jul 15 06:24:14 PM PDT 24
Finished Jul 15 06:26:42 PM PDT 24
Peak memory 251136 kb
Host smart-9e2dc978-fe1a-43b8-a812-667acd53415d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564479750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1564479750
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.498174253
Short name T192
Test name
Test status
Simulation time 55697418061 ps
CPU time 564.17 seconds
Started Jul 15 06:24:16 PM PDT 24
Finished Jul 15 06:33:41 PM PDT 24
Peak memory 254884 kb
Host smart-233120f2-f965-45b4-a6b1-f3b934532f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498174253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.498174253
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1484581641
Short name T315
Test name
Test status
Simulation time 329196729 ps
CPU time 6.65 seconds
Started Jul 15 06:24:22 PM PDT 24
Finished Jul 15 06:24:29 PM PDT 24
Peak memory 233728 kb
Host smart-36a5ab9b-d6ae-4091-a7cf-456fee76db08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484581641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1484581641
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2043188539
Short name T165
Test name
Test status
Simulation time 42357131322 ps
CPU time 174.11 seconds
Started Jul 15 06:26:14 PM PDT 24
Finished Jul 15 06:29:09 PM PDT 24
Peak memory 266768 kb
Host smart-4bcdb03e-0370-4848-83d5-4d9327415fe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043188539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2043188539
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3155989160
Short name T150
Test name
Test status
Simulation time 635735028 ps
CPU time 9.03 seconds
Started Jul 15 06:24:40 PM PDT 24
Finished Jul 15 06:24:50 PM PDT 24
Peak memory 220956 kb
Host smart-86c4e4e8-d3d2-42ac-9cc3-07df04d9d9d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3155989160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3155989160
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.505303857
Short name T95
Test name
Test status
Simulation time 6544389851 ps
CPU time 50.66 seconds
Started Jul 15 06:25:18 PM PDT 24
Finished Jul 15 06:26:09 PM PDT 24
Peak memory 223800 kb
Host smart-d4ce948d-7048-4157-8b36-25ca57cf6284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505303857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.505303857
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3102020060
Short name T85
Test name
Test status
Simulation time 159648779 ps
CPU time 1.46 seconds
Started Jul 15 06:22:36 PM PDT 24
Finished Jul 15 06:22:38 PM PDT 24
Peak memory 207264 kb
Host smart-3ff2ae22-7b14-498a-9ac8-e295851ee03a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102020060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3102020060
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.343821636
Short name T1121
Test name
Test status
Simulation time 2203880928 ps
CPU time 16.63 seconds
Started Jul 15 06:22:36 PM PDT 24
Finished Jul 15 06:22:53 PM PDT 24
Peak memory 215544 kb
Host smart-a947f7ec-d2cd-4dcc-be6d-ab4dc7d37222
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343821636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.343821636
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1107144802
Short name T1114
Test name
Test status
Simulation time 363302228 ps
CPU time 12.58 seconds
Started Jul 15 06:22:34 PM PDT 24
Finished Jul 15 06:22:47 PM PDT 24
Peak memory 207376 kb
Host smart-6a9870e4-79c6-4519-be85-006cb4adbf0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107144802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1107144802
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3190323330
Short name T115
Test name
Test status
Simulation time 58517913 ps
CPU time 3.86 seconds
Started Jul 15 06:22:33 PM PDT 24
Finished Jul 15 06:22:38 PM PDT 24
Peak memory 218164 kb
Host smart-d4f1f85c-4f99-48c1-82dc-8e7539c33fa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190323330 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3190323330
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2594698322
Short name T1130
Test name
Test status
Simulation time 76298894 ps
CPU time 2.64 seconds
Started Jul 15 06:22:32 PM PDT 24
Finished Jul 15 06:22:34 PM PDT 24
Peak memory 215440 kb
Host smart-ab81ee6b-b768-49ea-867c-dfddf26556e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594698322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
594698322
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2105410365
Short name T1113
Test name
Test status
Simulation time 83030106 ps
CPU time 0.71 seconds
Started Jul 15 06:22:33 PM PDT 24
Finished Jul 15 06:22:34 PM PDT 24
Peak memory 204316 kb
Host smart-b83fcb91-258b-42a4-b372-f95b90d7b511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105410365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
105410365
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3233991817
Short name T1147
Test name
Test status
Simulation time 74870945 ps
CPU time 2.32 seconds
Started Jul 15 06:22:33 PM PDT 24
Finished Jul 15 06:22:37 PM PDT 24
Peak memory 215480 kb
Host smart-46a7b765-0a69-45f1-8b7d-b15a993f002c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233991817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3233991817
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1539517018
Short name T1109
Test name
Test status
Simulation time 21646953 ps
CPU time 0.65 seconds
Started Jul 15 06:22:34 PM PDT 24
Finished Jul 15 06:22:36 PM PDT 24
Peak memory 203868 kb
Host smart-ab2760b7-fb7e-42f3-8cf5-44df3de0bca0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539517018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1539517018
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1056653706
Short name T1041
Test name
Test status
Simulation time 80794559 ps
CPU time 2.73 seconds
Started Jul 15 06:22:32 PM PDT 24
Finished Jul 15 06:22:35 PM PDT 24
Peak memory 215536 kb
Host smart-9d02b4bf-ba0b-4e35-81df-09f9577743f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056653706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1056653706
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3346775488
Short name T1094
Test name
Test status
Simulation time 56554870 ps
CPU time 1.66 seconds
Started Jul 15 06:22:35 PM PDT 24
Finished Jul 15 06:22:37 PM PDT 24
Peak memory 215748 kb
Host smart-680b7224-69ca-4dcb-a1be-e8eddebe0b8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346775488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
346775488
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1186395644
Short name T1102
Test name
Test status
Simulation time 410330631 ps
CPU time 8.61 seconds
Started Jul 15 06:22:32 PM PDT 24
Finished Jul 15 06:22:41 PM PDT 24
Peak memory 207160 kb
Host smart-c40dee84-c87a-416a-8ff2-d60632f3e6a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186395644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1186395644
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.328147135
Short name T1146
Test name
Test status
Simulation time 11232883511 ps
CPU time 40.94 seconds
Started Jul 15 06:22:34 PM PDT 24
Finished Jul 15 06:23:16 PM PDT 24
Peak memory 215476 kb
Host smart-ccb39cbe-65ea-4ec8-823f-99456bf99772
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328147135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.328147135
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4008444444
Short name T1066
Test name
Test status
Simulation time 91352614 ps
CPU time 2.76 seconds
Started Jul 15 06:22:32 PM PDT 24
Finished Jul 15 06:22:36 PM PDT 24
Peak memory 218092 kb
Host smart-cbb4a359-9f7e-45a7-aeed-c306be37c52d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008444444 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4008444444
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3198020782
Short name T159
Test name
Test status
Simulation time 441626739 ps
CPU time 2.61 seconds
Started Jul 15 06:22:33 PM PDT 24
Finished Jul 15 06:22:37 PM PDT 24
Peak memory 207356 kb
Host smart-167e006e-ea77-4332-b6be-7be981eaaea7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198020782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
198020782
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3618545442
Short name T1123
Test name
Test status
Simulation time 18753509 ps
CPU time 0.73 seconds
Started Jul 15 06:22:32 PM PDT 24
Finished Jul 15 06:22:33 PM PDT 24
Peak memory 203908 kb
Host smart-62f046a4-ded7-4d1e-8c32-f200be0275cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618545442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
618545442
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2360917431
Short name T131
Test name
Test status
Simulation time 27770439 ps
CPU time 2.08 seconds
Started Jul 15 06:22:34 PM PDT 24
Finished Jul 15 06:22:37 PM PDT 24
Peak memory 215488 kb
Host smart-c61858d7-048f-4e48-bb2f-de147b799866
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360917431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2360917431
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1719912553
Short name T1065
Test name
Test status
Simulation time 24742782 ps
CPU time 0.62 seconds
Started Jul 15 06:22:34 PM PDT 24
Finished Jul 15 06:22:35 PM PDT 24
Peak memory 203792 kb
Host smart-38472d31-7d2a-43bb-9715-cef7374d452b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719912553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1719912553
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2719446779
Short name T157
Test name
Test status
Simulation time 275581018 ps
CPU time 1.81 seconds
Started Jul 15 06:22:33 PM PDT 24
Finished Jul 15 06:22:36 PM PDT 24
Peak memory 215528 kb
Host smart-e443df4f-0202-4c3e-824b-a5afa4cb26bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719446779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2719446779
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.582538440
Short name T100
Test name
Test status
Simulation time 116940689 ps
CPU time 1.74 seconds
Started Jul 15 06:22:57 PM PDT 24
Finished Jul 15 06:22:59 PM PDT 24
Peak memory 215632 kb
Host smart-bfce56f5-dda3-415b-9864-1162d3770fd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582538440 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.582538440
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1384767774
Short name T1049
Test name
Test status
Simulation time 52567410 ps
CPU time 1.8 seconds
Started Jul 15 06:22:55 PM PDT 24
Finished Jul 15 06:22:57 PM PDT 24
Peak memory 215504 kb
Host smart-c04d1966-b42d-4600-b57b-36c3cf221777
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384767774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1384767774
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.151612735
Short name T1081
Test name
Test status
Simulation time 63257198 ps
CPU time 0.74 seconds
Started Jul 15 06:22:55 PM PDT 24
Finished Jul 15 06:22:56 PM PDT 24
Peak memory 204032 kb
Host smart-8fa0a3c1-a3a6-4801-8056-2289eb8d363e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151612735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.151612735
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.33704763
Short name T1124
Test name
Test status
Simulation time 130037505 ps
CPU time 2.74 seconds
Started Jul 15 06:22:55 PM PDT 24
Finished Jul 15 06:22:58 PM PDT 24
Peak memory 215544 kb
Host smart-2fce8c2a-762e-4f09-9840-5eacd67943e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33704763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sp
i_device_same_csr_outstanding.33704763
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2267924752
Short name T1143
Test name
Test status
Simulation time 1198627842 ps
CPU time 3.19 seconds
Started Jul 15 06:22:54 PM PDT 24
Finished Jul 15 06:22:57 PM PDT 24
Peak memory 219648 kb
Host smart-577265e4-e98c-4ab8-b0d0-0fa1d753bf68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267924752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2267924752
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2583515554
Short name T181
Test name
Test status
Simulation time 1147590263 ps
CPU time 19.82 seconds
Started Jul 15 06:22:56 PM PDT 24
Finished Jul 15 06:23:16 PM PDT 24
Peak memory 217192 kb
Host smart-41be2a06-59ca-43b2-a511-cb6cf7de545e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583515554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2583515554
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2081699918
Short name T1063
Test name
Test status
Simulation time 60444037 ps
CPU time 4.07 seconds
Started Jul 15 06:22:55 PM PDT 24
Finished Jul 15 06:23:00 PM PDT 24
Peak memory 217184 kb
Host smart-e0ad876f-9eca-49d3-9e3d-30e9e8840dfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081699918 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2081699918
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.965583868
Short name T1122
Test name
Test status
Simulation time 206361604 ps
CPU time 2.95 seconds
Started Jul 15 06:22:56 PM PDT 24
Finished Jul 15 06:22:59 PM PDT 24
Peak memory 215448 kb
Host smart-4737d2dc-bee1-4534-958b-e5411eacbebc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965583868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.965583868
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4224408480
Short name T1144
Test name
Test status
Simulation time 40011279 ps
CPU time 0.7 seconds
Started Jul 15 06:22:58 PM PDT 24
Finished Jul 15 06:22:59 PM PDT 24
Peak memory 203916 kb
Host smart-1c1380ab-6163-4d4e-905b-5b2b37c6f37f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224408480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4224408480
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.71918876
Short name T1115
Test name
Test status
Simulation time 29083101 ps
CPU time 1.74 seconds
Started Jul 15 06:22:56 PM PDT 24
Finished Jul 15 06:22:58 PM PDT 24
Peak memory 215496 kb
Host smart-cfa707e9-b343-4da1-a556-0588f594982d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71918876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sp
i_device_same_csr_outstanding.71918876
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3893271241
Short name T177
Test name
Test status
Simulation time 697794992 ps
CPU time 4.11 seconds
Started Jul 15 06:22:55 PM PDT 24
Finished Jul 15 06:22:59 PM PDT 24
Peak memory 215656 kb
Host smart-37247624-5483-429e-814c-89b9e808cf54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893271241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3893271241
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.568003246
Short name T1085
Test name
Test status
Simulation time 657811786 ps
CPU time 13.45 seconds
Started Jul 15 06:22:57 PM PDT 24
Finished Jul 15 06:23:11 PM PDT 24
Peak memory 215536 kb
Host smart-f0e3553f-2056-41e5-b4cd-9f99ef5bae4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568003246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.568003246
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.378190224
Short name T1067
Test name
Test status
Simulation time 599322226 ps
CPU time 2.81 seconds
Started Jul 15 06:22:59 PM PDT 24
Finished Jul 15 06:23:02 PM PDT 24
Peak memory 217108 kb
Host smart-a13916fc-d3f8-4c58-a4d3-8f697b6436d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378190224 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.378190224
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3027754030
Short name T1100
Test name
Test status
Simulation time 90019623 ps
CPU time 1.34 seconds
Started Jul 15 06:22:55 PM PDT 24
Finished Jul 15 06:22:57 PM PDT 24
Peak memory 215500 kb
Host smart-eaa5c32c-f2f0-4eab-b32c-a3ce1a5dbff5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027754030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3027754030
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1583458905
Short name T1054
Test name
Test status
Simulation time 15553357 ps
CPU time 0.79 seconds
Started Jul 15 06:22:58 PM PDT 24
Finished Jul 15 06:22:59 PM PDT 24
Peak memory 204336 kb
Host smart-40b13000-5f5b-4af3-b675-2f03073b9339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583458905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1583458905
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3042940718
Short name T1137
Test name
Test status
Simulation time 202581998 ps
CPU time 3.84 seconds
Started Jul 15 06:22:57 PM PDT 24
Finished Jul 15 06:23:01 PM PDT 24
Peak memory 215584 kb
Host smart-5ec7cb74-3451-4dae-bdc5-7331cad37893
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042940718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3042940718
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2673804320
Short name T1059
Test name
Test status
Simulation time 189515564 ps
CPU time 2.47 seconds
Started Jul 15 06:22:56 PM PDT 24
Finished Jul 15 06:23:00 PM PDT 24
Peak memory 215700 kb
Host smart-096dbc88-f6aa-4c7b-beeb-60761acacc0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673804320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2673804320
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4047905415
Short name T102
Test name
Test status
Simulation time 2602050946 ps
CPU time 14.7 seconds
Started Jul 15 06:22:54 PM PDT 24
Finished Jul 15 06:23:09 PM PDT 24
Peak memory 215556 kb
Host smart-f68369a7-32b9-40af-b073-e94844c22f15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047905415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.4047905415
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2101231233
Short name T1127
Test name
Test status
Simulation time 26535543 ps
CPU time 1.81 seconds
Started Jul 15 06:23:15 PM PDT 24
Finished Jul 15 06:23:17 PM PDT 24
Peak memory 216568 kb
Host smart-9895f9ff-3759-4d04-acc2-0fdd1f3a23fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101231233 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2101231233
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2245076575
Short name T146
Test name
Test status
Simulation time 26527206 ps
CPU time 1.28 seconds
Started Jul 15 06:22:59 PM PDT 24
Finished Jul 15 06:23:00 PM PDT 24
Peak memory 207340 kb
Host smart-98505421-080a-4d75-a52f-b0285067525d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245076575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2245076575
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1987248972
Short name T1141
Test name
Test status
Simulation time 39748004 ps
CPU time 0.75 seconds
Started Jul 15 06:22:56 PM PDT 24
Finished Jul 15 06:22:57 PM PDT 24
Peak memory 204012 kb
Host smart-c892265c-040e-4907-a76b-8820296102e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987248972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1987248972
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2129095917
Short name T1062
Test name
Test status
Simulation time 82336278 ps
CPU time 2.73 seconds
Started Jul 15 06:22:57 PM PDT 24
Finished Jul 15 06:23:00 PM PDT 24
Peak memory 215520 kb
Host smart-07381a9c-2f1f-4d62-84d5-a5cdb204ed2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129095917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2129095917
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2609232017
Short name T1089
Test name
Test status
Simulation time 311335742 ps
CPU time 4.05 seconds
Started Jul 15 06:22:56 PM PDT 24
Finished Jul 15 06:23:01 PM PDT 24
Peak memory 215708 kb
Host smart-5bbbf5c4-89df-4873-acaa-eb351bfb7456
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609232017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2609232017
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3571506820
Short name T1079
Test name
Test status
Simulation time 292270013 ps
CPU time 6.58 seconds
Started Jul 15 06:22:57 PM PDT 24
Finished Jul 15 06:23:05 PM PDT 24
Peak memory 215880 kb
Host smart-0d897d14-56f4-4950-896d-1aecbdf85cb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571506820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3571506820
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3222487473
Short name T1103
Test name
Test status
Simulation time 379056843 ps
CPU time 3.05 seconds
Started Jul 15 06:23:15 PM PDT 24
Finished Jul 15 06:23:20 PM PDT 24
Peak memory 217060 kb
Host smart-83f863e2-342e-4dfe-89a4-17e4aa625ee1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222487473 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3222487473
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1842314908
Short name T125
Test name
Test status
Simulation time 471573545 ps
CPU time 1.87 seconds
Started Jul 15 06:23:00 PM PDT 24
Finished Jul 15 06:23:02 PM PDT 24
Peak memory 215528 kb
Host smart-c7957c4e-c983-48d4-bb13-54751334de6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842314908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1842314908
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1083997836
Short name T1028
Test name
Test status
Simulation time 36800692 ps
CPU time 0.73 seconds
Started Jul 15 06:23:02 PM PDT 24
Finished Jul 15 06:23:04 PM PDT 24
Peak memory 204044 kb
Host smart-c7838f1a-ab90-4773-bbbc-3f6168070e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083997836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1083997836
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2831252648
Short name T1148
Test name
Test status
Simulation time 1965170939 ps
CPU time 4.2 seconds
Started Jul 15 06:23:06 PM PDT 24
Finished Jul 15 06:23:11 PM PDT 24
Peak memory 215248 kb
Host smart-b20d0140-db78-41be-ae9b-8773fc18e9f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831252648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2831252648
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3985305464
Short name T1092
Test name
Test status
Simulation time 98237463 ps
CPU time 3.04 seconds
Started Jul 15 06:23:02 PM PDT 24
Finished Jul 15 06:23:06 PM PDT 24
Peak memory 215736 kb
Host smart-9c61ae2d-aad9-4c9d-87f8-56b7faa90c50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985305464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3985305464
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2511662452
Short name T1077
Test name
Test status
Simulation time 344270169 ps
CPU time 3 seconds
Started Jul 15 06:23:00 PM PDT 24
Finished Jul 15 06:23:03 PM PDT 24
Peak memory 216972 kb
Host smart-66d06817-7195-4556-a43e-53bf04e1784c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511662452 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2511662452
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1962573572
Short name T123
Test name
Test status
Simulation time 184498644 ps
CPU time 2.42 seconds
Started Jul 15 06:23:02 PM PDT 24
Finished Jul 15 06:23:05 PM PDT 24
Peak memory 207232 kb
Host smart-b7ea326b-0860-4e61-99db-a79acc26e7d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962573572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1962573572
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2452389892
Short name T1101
Test name
Test status
Simulation time 31014408 ps
CPU time 0.74 seconds
Started Jul 15 06:23:01 PM PDT 24
Finished Jul 15 06:23:03 PM PDT 24
Peak memory 204040 kb
Host smart-683a854a-e6d4-40dc-9f98-08a47474e7b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452389892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2452389892
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2261755542
Short name T1125
Test name
Test status
Simulation time 62486936 ps
CPU time 3.99 seconds
Started Jul 15 06:23:14 PM PDT 24
Finished Jul 15 06:23:19 PM PDT 24
Peak memory 215416 kb
Host smart-4587df15-cb87-447a-98fa-a0f1199b8969
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261755542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2261755542
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1515729157
Short name T1117
Test name
Test status
Simulation time 179792004 ps
CPU time 3.12 seconds
Started Jul 15 06:23:00 PM PDT 24
Finished Jul 15 06:23:04 PM PDT 24
Peak memory 216668 kb
Host smart-72790ff5-8015-43b4-93c5-37e859a52a3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515729157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1515729157
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.830866340
Short name T182
Test name
Test status
Simulation time 1191546908 ps
CPU time 18.53 seconds
Started Jul 15 06:23:02 PM PDT 24
Finished Jul 15 06:23:22 PM PDT 24
Peak memory 223572 kb
Host smart-2d9fca9e-b2b5-40e8-b598-318b7a709c09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830866340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.830866340
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2837925355
Short name T1080
Test name
Test status
Simulation time 416992565 ps
CPU time 3.01 seconds
Started Jul 15 06:23:15 PM PDT 24
Finished Jul 15 06:23:19 PM PDT 24
Peak memory 216628 kb
Host smart-5f37942b-6d2d-4854-a3ba-dbf78e0a777b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837925355 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2837925355
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1737247121
Short name T127
Test name
Test status
Simulation time 237597785 ps
CPU time 1.9 seconds
Started Jul 15 06:23:15 PM PDT 24
Finished Jul 15 06:23:18 PM PDT 24
Peak memory 215552 kb
Host smart-0a67fa97-d0f9-4eb3-9b39-b91f1d456982
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737247121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1737247121
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3098955828
Short name T1145
Test name
Test status
Simulation time 14710858 ps
CPU time 0.81 seconds
Started Jul 15 06:23:02 PM PDT 24
Finished Jul 15 06:23:03 PM PDT 24
Peak memory 203928 kb
Host smart-d0f8f932-723f-4c1b-b90a-83147015a240
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098955828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3098955828
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.733376224
Short name T1055
Test name
Test status
Simulation time 183969551 ps
CPU time 3.28 seconds
Started Jul 15 06:23:01 PM PDT 24
Finished Jul 15 06:23:05 PM PDT 24
Peak memory 215532 kb
Host smart-40a3e83d-c716-4fcf-988a-398341ca15aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733376224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.733376224
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.83826647
Short name T1126
Test name
Test status
Simulation time 74877393 ps
CPU time 2.31 seconds
Started Jul 15 06:23:02 PM PDT 24
Finished Jul 15 06:23:05 PM PDT 24
Peak memory 215704 kb
Host smart-5d9850da-d155-4d22-9566-56627ed8e4f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83826647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.83826647
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.23068733
Short name T184
Test name
Test status
Simulation time 1213155472 ps
CPU time 20 seconds
Started Jul 15 06:23:03 PM PDT 24
Finished Jul 15 06:23:23 PM PDT 24
Peak memory 215684 kb
Host smart-2c38c7eb-32ea-4c07-8648-10313c033dc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23068733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_
tl_intg_err.23068733
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1017122048
Short name T1083
Test name
Test status
Simulation time 148272326 ps
CPU time 2.96 seconds
Started Jul 15 06:23:04 PM PDT 24
Finished Jul 15 06:23:07 PM PDT 24
Peak memory 217288 kb
Host smart-90ae3305-97f8-4931-a964-8bcb579cda35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017122048 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1017122048
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1571412946
Short name T1151
Test name
Test status
Simulation time 37201668 ps
CPU time 2.46 seconds
Started Jul 15 06:23:03 PM PDT 24
Finished Jul 15 06:23:06 PM PDT 24
Peak memory 215508 kb
Host smart-240e4a0b-4ab9-49a0-a54b-b30c33451164
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571412946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1571412946
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2885782369
Short name T1070
Test name
Test status
Simulation time 37032541 ps
CPU time 0.73 seconds
Started Jul 15 06:23:15 PM PDT 24
Finished Jul 15 06:23:17 PM PDT 24
Peak memory 203984 kb
Host smart-6a93414c-8b32-4cd1-b86d-fd7d800fad15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885782369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2885782369
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2956428218
Short name T158
Test name
Test status
Simulation time 287493016 ps
CPU time 3.32 seconds
Started Jul 15 06:23:01 PM PDT 24
Finished Jul 15 06:23:05 PM PDT 24
Peak memory 215448 kb
Host smart-ec8598a3-05d8-4d88-b8e9-10e618b32fad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956428218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2956428218
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2492707611
Short name T117
Test name
Test status
Simulation time 5465656882 ps
CPU time 7.82 seconds
Started Jul 15 06:23:02 PM PDT 24
Finished Jul 15 06:23:11 PM PDT 24
Peak memory 215616 kb
Host smart-91d5e136-418e-41fe-8575-2f70fdc73443
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492707611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2492707611
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.599513702
Short name T1134
Test name
Test status
Simulation time 127350888 ps
CPU time 3.78 seconds
Started Jul 15 06:23:03 PM PDT 24
Finished Jul 15 06:23:07 PM PDT 24
Peak memory 217228 kb
Host smart-02a74c47-7e92-48ef-ad89-b316eef36823
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599513702 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.599513702
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1603217789
Short name T149
Test name
Test status
Simulation time 78237326 ps
CPU time 1.38 seconds
Started Jul 15 06:23:02 PM PDT 24
Finished Jul 15 06:23:05 PM PDT 24
Peak memory 207328 kb
Host smart-328d109d-ce4b-4285-bcd5-4ec7d1fa221b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603217789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1603217789
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1678450412
Short name T1044
Test name
Test status
Simulation time 29525142 ps
CPU time 0.76 seconds
Started Jul 15 06:23:14 PM PDT 24
Finished Jul 15 06:23:16 PM PDT 24
Peak memory 203836 kb
Host smart-83af20a1-7b31-4e36-82ff-919b37bb6bc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678450412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1678450412
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2594218184
Short name T1058
Test name
Test status
Simulation time 1177588524 ps
CPU time 3.97 seconds
Started Jul 15 06:23:02 PM PDT 24
Finished Jul 15 06:23:07 PM PDT 24
Peak memory 215548 kb
Host smart-b92bd382-1075-40ff-a216-faf28844b25d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594218184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2594218184
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1105833484
Short name T113
Test name
Test status
Simulation time 543120959 ps
CPU time 5.16 seconds
Started Jul 15 06:23:06 PM PDT 24
Finished Jul 15 06:23:12 PM PDT 24
Peak memory 215452 kb
Host smart-06de56ac-9f2b-4e91-ba06-84a8da28d48f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105833484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1105833484
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2264172645
Short name T180
Test name
Test status
Simulation time 2432466802 ps
CPU time 23.11 seconds
Started Jul 15 06:23:03 PM PDT 24
Finished Jul 15 06:23:27 PM PDT 24
Peak memory 216304 kb
Host smart-01194c9a-ff74-45d4-9aa3-81d897db40f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264172645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2264172645
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2778554046
Short name T103
Test name
Test status
Simulation time 251341147 ps
CPU time 1.7 seconds
Started Jul 15 06:23:10 PM PDT 24
Finished Jul 15 06:23:13 PM PDT 24
Peak memory 215548 kb
Host smart-c8cb3cf2-1fe7-4aa0-832d-2cb5320a6c49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778554046 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2778554046
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2138419381
Short name T148
Test name
Test status
Simulation time 150016768 ps
CPU time 1.41 seconds
Started Jul 15 06:23:10 PM PDT 24
Finished Jul 15 06:23:12 PM PDT 24
Peak memory 215484 kb
Host smart-826e41a6-7180-4213-a4f8-696e344aaa3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138419381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2138419381
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.954910558
Short name T1073
Test name
Test status
Simulation time 26322014 ps
CPU time 0.75 seconds
Started Jul 15 06:23:07 PM PDT 24
Finished Jul 15 06:23:09 PM PDT 24
Peak memory 204316 kb
Host smart-c3ac1905-aad0-4f1b-84fe-fda16baf3e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954910558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.954910558
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2345067483
Short name T145
Test name
Test status
Simulation time 72931713 ps
CPU time 4.22 seconds
Started Jul 15 06:23:11 PM PDT 24
Finished Jul 15 06:23:16 PM PDT 24
Peak memory 215548 kb
Host smart-d4aece55-3c54-42af-bbb5-8b1cab958a44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345067483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2345067483
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3235288374
Short name T118
Test name
Test status
Simulation time 3340935186 ps
CPU time 20.96 seconds
Started Jul 15 06:23:10 PM PDT 24
Finished Jul 15 06:23:32 PM PDT 24
Peak memory 216044 kb
Host smart-79f0ed2d-3b3a-4c3f-b749-0db28e713ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235288374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3235288374
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1774348081
Short name T1149
Test name
Test status
Simulation time 2517299292 ps
CPU time 24.7 seconds
Started Jul 15 06:22:42 PM PDT 24
Finished Jul 15 06:23:08 PM PDT 24
Peak memory 207576 kb
Host smart-d627d27c-7c77-4655-b255-a38d1c6229d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774348081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1774348081
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2713586458
Short name T130
Test name
Test status
Simulation time 11238504091 ps
CPU time 38.77 seconds
Started Jul 15 06:22:44 PM PDT 24
Finished Jul 15 06:23:23 PM PDT 24
Peak memory 207308 kb
Host smart-84f787eb-f9ec-43d4-b767-6c4071efdd97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713586458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2713586458
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3255872789
Short name T1096
Test name
Test status
Simulation time 44648117 ps
CPU time 0.94 seconds
Started Jul 15 06:22:42 PM PDT 24
Finished Jul 15 06:22:43 PM PDT 24
Peak memory 207084 kb
Host smart-4ced30a5-47d6-4c18-98c2-5b9d5eb3aa9e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255872789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3255872789
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.414485102
Short name T1047
Test name
Test status
Simulation time 93436369 ps
CPU time 2.67 seconds
Started Jul 15 06:22:44 PM PDT 24
Finished Jul 15 06:22:48 PM PDT 24
Peak memory 216548 kb
Host smart-a17a41c7-6819-40e8-8cb5-b7576f47cff2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414485102 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.414485102
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2028391803
Short name T1068
Test name
Test status
Simulation time 46414114 ps
CPU time 1.75 seconds
Started Jul 15 06:22:43 PM PDT 24
Finished Jul 15 06:22:46 PM PDT 24
Peak memory 215528 kb
Host smart-fe88bda6-f9aa-4f68-9f0c-41f1f58f0f42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028391803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
028391803
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3604380108
Short name T1111
Test name
Test status
Simulation time 11359797 ps
CPU time 0.7 seconds
Started Jul 15 06:22:32 PM PDT 24
Finished Jul 15 06:22:33 PM PDT 24
Peak memory 204036 kb
Host smart-83834373-41ac-45a3-b1bf-ddf6e5e6333f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604380108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
604380108
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.336815277
Short name T1097
Test name
Test status
Simulation time 141417805 ps
CPU time 1.31 seconds
Started Jul 15 06:22:40 PM PDT 24
Finished Jul 15 06:22:42 PM PDT 24
Peak memory 215420 kb
Host smart-25182521-467c-4b00-b34a-6c6d485e763a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336815277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.336815277
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2593926353
Short name T1107
Test name
Test status
Simulation time 12942285 ps
CPU time 0.7 seconds
Started Jul 15 06:22:40 PM PDT 24
Finished Jul 15 06:22:41 PM PDT 24
Peak memory 204220 kb
Host smart-6d1def5f-9f26-42e9-a5cc-db7835778bfc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593926353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2593926353
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.554696207
Short name T1069
Test name
Test status
Simulation time 211826225 ps
CPU time 3.53 seconds
Started Jul 15 06:22:41 PM PDT 24
Finished Jul 15 06:22:45 PM PDT 24
Peak memory 215420 kb
Host smart-8ee70eb5-5850-4de9-a4de-f269f491bb9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554696207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.554696207
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4226797989
Short name T109
Test name
Test status
Simulation time 184587141 ps
CPU time 4.6 seconds
Started Jul 15 06:22:33 PM PDT 24
Finished Jul 15 06:22:38 PM PDT 24
Peak memory 215720 kb
Host smart-f2c29f0d-3fb7-4033-945e-e5c8d5a8fdc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226797989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4
226797989
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2081299281
Short name T1075
Test name
Test status
Simulation time 296435502 ps
CPU time 18.85 seconds
Started Jul 15 06:22:33 PM PDT 24
Finished Jul 15 06:22:52 PM PDT 24
Peak memory 223740 kb
Host smart-302c03bc-5d84-4369-90d1-a37996b4edcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081299281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2081299281
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3688054517
Short name T1033
Test name
Test status
Simulation time 18551919 ps
CPU time 0.76 seconds
Started Jul 15 06:23:09 PM PDT 24
Finished Jul 15 06:23:10 PM PDT 24
Peak memory 204320 kb
Host smart-5f88f9ea-99a9-46a1-a169-840447355437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688054517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3688054517
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3788932534
Short name T1037
Test name
Test status
Simulation time 40659674 ps
CPU time 0.72 seconds
Started Jul 15 06:23:09 PM PDT 24
Finished Jul 15 06:23:10 PM PDT 24
Peak memory 204276 kb
Host smart-22f40446-d2ce-442f-af0d-7cd7fa296262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788932534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3788932534
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3011149103
Short name T1056
Test name
Test status
Simulation time 14914043 ps
CPU time 0.76 seconds
Started Jul 15 06:23:09 PM PDT 24
Finished Jul 15 06:23:11 PM PDT 24
Peak memory 204024 kb
Host smart-3c41c53d-0b3a-429a-ad7f-1fee7255d542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011149103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3011149103
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2925068121
Short name T1129
Test name
Test status
Simulation time 66162665 ps
CPU time 0.72 seconds
Started Jul 15 06:23:08 PM PDT 24
Finished Jul 15 06:23:09 PM PDT 24
Peak memory 203876 kb
Host smart-1554c2fd-f541-4cd6-b5e2-b65b978d22a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925068121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2925068121
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1433855726
Short name T1090
Test name
Test status
Simulation time 29715707 ps
CPU time 0.74 seconds
Started Jul 15 06:23:10 PM PDT 24
Finished Jul 15 06:23:11 PM PDT 24
Peak memory 204048 kb
Host smart-d118ad5c-af70-4eb9-9283-04043db2ec43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433855726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1433855726
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3210604971
Short name T1074
Test name
Test status
Simulation time 15032876 ps
CPU time 0.74 seconds
Started Jul 15 06:23:07 PM PDT 24
Finished Jul 15 06:23:08 PM PDT 24
Peak memory 204060 kb
Host smart-a3d78784-3782-4f96-8202-bc1e10740de7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210604971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3210604971
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3577903274
Short name T1029
Test name
Test status
Simulation time 16641572 ps
CPU time 0.75 seconds
Started Jul 15 06:23:09 PM PDT 24
Finished Jul 15 06:23:11 PM PDT 24
Peak memory 204320 kb
Host smart-808edc32-3a91-46bb-a53b-fd9ddd3d3501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577903274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3577903274
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4260923531
Short name T1043
Test name
Test status
Simulation time 41799747 ps
CPU time 0.73 seconds
Started Jul 15 06:23:07 PM PDT 24
Finished Jul 15 06:23:09 PM PDT 24
Peak memory 203984 kb
Host smart-8e3de388-0591-4125-b3b2-4df93a0fd8d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260923531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4260923531
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2758199073
Short name T1039
Test name
Test status
Simulation time 17953379 ps
CPU time 0.74 seconds
Started Jul 15 06:23:09 PM PDT 24
Finished Jul 15 06:23:10 PM PDT 24
Peak memory 204064 kb
Host smart-0c34b4c1-b006-4bd4-9b63-3891d794cc82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758199073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2758199073
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1387477275
Short name T1051
Test name
Test status
Simulation time 22216072 ps
CPU time 0.73 seconds
Started Jul 15 06:23:15 PM PDT 24
Finished Jul 15 06:23:18 PM PDT 24
Peak memory 203876 kb
Host smart-02cd5eba-de18-4586-932a-f3745bf893c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387477275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1387477275
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3708808190
Short name T1119
Test name
Test status
Simulation time 2441032178 ps
CPU time 16.77 seconds
Started Jul 15 06:22:45 PM PDT 24
Finished Jul 15 06:23:03 PM PDT 24
Peak memory 215612 kb
Host smart-31433a89-c4b6-4674-a7bf-6c1d001ef32e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708808190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3708808190
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1153503537
Short name T1034
Test name
Test status
Simulation time 1285187692 ps
CPU time 23.88 seconds
Started Jul 15 06:22:43 PM PDT 24
Finished Jul 15 06:23:07 PM PDT 24
Peak memory 207480 kb
Host smart-4bd357a8-72ad-4474-95a1-c970f1482d02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153503537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1153503537
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2644262053
Short name T84
Test name
Test status
Simulation time 120124071 ps
CPU time 1.2 seconds
Started Jul 15 06:22:42 PM PDT 24
Finished Jul 15 06:22:44 PM PDT 24
Peak memory 207312 kb
Host smart-d558de14-d76a-4f0b-94db-a3c0e03afac6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644262053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2644262053
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1168902306
Short name T1136
Test name
Test status
Simulation time 594026927 ps
CPU time 3.98 seconds
Started Jul 15 06:22:41 PM PDT 24
Finished Jul 15 06:22:46 PM PDT 24
Peak memory 217160 kb
Host smart-7ed4f2e5-afbe-4e3c-b580-2ee965fac91a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168902306 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1168902306
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.727810006
Short name T1132
Test name
Test status
Simulation time 792410502 ps
CPU time 1.88 seconds
Started Jul 15 06:22:42 PM PDT 24
Finished Jul 15 06:22:44 PM PDT 24
Peak memory 207272 kb
Host smart-23130978-ac26-4628-8825-980e2919e4ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727810006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.727810006
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.652423051
Short name T1052
Test name
Test status
Simulation time 46352230 ps
CPU time 0.75 seconds
Started Jul 15 06:22:42 PM PDT 24
Finished Jul 15 06:22:43 PM PDT 24
Peak memory 204248 kb
Host smart-200b0b34-ca1b-4cd8-ba72-912ada1153eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652423051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.652423051
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2191866044
Short name T1135
Test name
Test status
Simulation time 67580536 ps
CPU time 1.71 seconds
Started Jul 15 06:22:44 PM PDT 24
Finished Jul 15 06:22:47 PM PDT 24
Peak memory 215480 kb
Host smart-8144ab0e-70b0-4e3c-8fa6-866366446554
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191866044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2191866044
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3584372951
Short name T1105
Test name
Test status
Simulation time 39559540 ps
CPU time 0.65 seconds
Started Jul 15 06:22:45 PM PDT 24
Finished Jul 15 06:22:47 PM PDT 24
Peak memory 203924 kb
Host smart-af4c69f0-1695-45e4-981e-be5be89a9b18
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584372951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3584372951
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.114166069
Short name T1128
Test name
Test status
Simulation time 207510282 ps
CPU time 4.32 seconds
Started Jul 15 06:22:41 PM PDT 24
Finished Jul 15 06:22:46 PM PDT 24
Peak memory 215508 kb
Host smart-a435d183-cc79-417c-8139-a5281e9678ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114166069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.114166069
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.475320023
Short name T1120
Test name
Test status
Simulation time 253850073 ps
CPU time 3.13 seconds
Started Jul 15 06:22:42 PM PDT 24
Finished Jul 15 06:22:46 PM PDT 24
Peak memory 215680 kb
Host smart-9385e965-5e74-4f8f-b424-fade3c539f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475320023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.475320023
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.538613135
Short name T179
Test name
Test status
Simulation time 549394112 ps
CPU time 7.23 seconds
Started Jul 15 06:22:44 PM PDT 24
Finished Jul 15 06:22:52 PM PDT 24
Peak memory 215396 kb
Host smart-380022f5-2e2d-41bf-82bd-73633d86dc0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538613135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.538613135
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.935179616
Short name T1061
Test name
Test status
Simulation time 13766934 ps
CPU time 0.72 seconds
Started Jul 15 06:23:08 PM PDT 24
Finished Jul 15 06:23:09 PM PDT 24
Peak memory 203924 kb
Host smart-d904a572-954d-4107-bc77-78593e4d2aaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935179616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.935179616
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1051540447
Short name T1057
Test name
Test status
Simulation time 21125766 ps
CPU time 0.69 seconds
Started Jul 15 06:23:07 PM PDT 24
Finished Jul 15 06:23:08 PM PDT 24
Peak memory 203956 kb
Host smart-1069c0c4-a168-41a2-bdd4-6d51cd5154f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051540447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1051540447
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.579388706
Short name T1053
Test name
Test status
Simulation time 12225219 ps
CPU time 0.7 seconds
Started Jul 15 06:23:09 PM PDT 24
Finished Jul 15 06:23:11 PM PDT 24
Peak memory 204032 kb
Host smart-2fd1ba8b-d8f8-4189-a6c1-50652026495b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579388706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.579388706
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1813342181
Short name T1042
Test name
Test status
Simulation time 15344692 ps
CPU time 0.76 seconds
Started Jul 15 06:23:07 PM PDT 24
Finished Jul 15 06:23:08 PM PDT 24
Peak memory 203976 kb
Host smart-3c1bc511-8567-4e91-b888-47f0a9b59109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813342181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1813342181
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.228243678
Short name T1140
Test name
Test status
Simulation time 47256567 ps
CPU time 0.71 seconds
Started Jul 15 06:23:10 PM PDT 24
Finished Jul 15 06:23:12 PM PDT 24
Peak memory 203936 kb
Host smart-61225826-9dac-4db9-8270-d8c75ae63228
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228243678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.228243678
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.90986294
Short name T1110
Test name
Test status
Simulation time 119686605 ps
CPU time 0.68 seconds
Started Jul 15 06:23:09 PM PDT 24
Finished Jul 15 06:23:10 PM PDT 24
Peak memory 204256 kb
Host smart-44f40971-2a07-400c-b853-c8f5fe85eadf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90986294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.90986294
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3635395320
Short name T1150
Test name
Test status
Simulation time 36985050 ps
CPU time 0.77 seconds
Started Jul 15 06:23:09 PM PDT 24
Finished Jul 15 06:23:10 PM PDT 24
Peak memory 204036 kb
Host smart-08d1f6cd-cae0-40c8-ae9e-594701c8d34e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635395320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3635395320
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.426146657
Short name T1040
Test name
Test status
Simulation time 24643924 ps
CPU time 0.8 seconds
Started Jul 15 06:23:15 PM PDT 24
Finished Jul 15 06:23:18 PM PDT 24
Peak memory 203944 kb
Host smart-dc94cecd-66a4-4a7b-865e-a817a6c091de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426146657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.426146657
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.613905558
Short name T1087
Test name
Test status
Simulation time 13058381 ps
CPU time 0.71 seconds
Started Jul 15 06:23:07 PM PDT 24
Finished Jul 15 06:23:09 PM PDT 24
Peak memory 204280 kb
Host smart-0de7a60b-1422-45d3-a3b7-69ef7d3113bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613905558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.613905558
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1410601304
Short name T1036
Test name
Test status
Simulation time 23513457 ps
CPU time 0.74 seconds
Started Jul 15 06:23:09 PM PDT 24
Finished Jul 15 06:23:10 PM PDT 24
Peak memory 204168 kb
Host smart-249c309a-8fb5-4c8a-9820-27f63c7fb473
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410601304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1410601304
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3853164776
Short name T129
Test name
Test status
Simulation time 8076654736 ps
CPU time 16.9 seconds
Started Jul 15 06:22:45 PM PDT 24
Finished Jul 15 06:23:03 PM PDT 24
Peak memory 215612 kb
Host smart-ba8cd559-b05b-4aea-a9bd-f9998590dca0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853164776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3853164776
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.477528759
Short name T126
Test name
Test status
Simulation time 495411295 ps
CPU time 21.74 seconds
Started Jul 15 06:22:42 PM PDT 24
Finished Jul 15 06:23:04 PM PDT 24
Peak memory 215544 kb
Host smart-812fb5e4-08b4-4a63-b4d1-21d10f908d20
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477528759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.477528759
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1803186881
Short name T86
Test name
Test status
Simulation time 24564576 ps
CPU time 1.05 seconds
Started Jul 15 06:22:42 PM PDT 24
Finished Jul 15 06:22:44 PM PDT 24
Peak memory 207044 kb
Host smart-647d2305-ce18-408c-8371-046ba603a1e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803186881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1803186881
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3566840824
Short name T114
Test name
Test status
Simulation time 142352361 ps
CPU time 2.68 seconds
Started Jul 15 06:22:43 PM PDT 24
Finished Jul 15 06:22:46 PM PDT 24
Peak memory 216980 kb
Host smart-46ca8935-6205-47ec-92a8-64f433475b6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566840824 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3566840824
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1757699494
Short name T124
Test name
Test status
Simulation time 96968273 ps
CPU time 2.41 seconds
Started Jul 15 06:22:40 PM PDT 24
Finished Jul 15 06:22:43 PM PDT 24
Peak memory 207384 kb
Host smart-5cea7ddd-0c05-482e-a67c-dd09a4466919
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757699494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
757699494
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.852067920
Short name T1072
Test name
Test status
Simulation time 29199443 ps
CPU time 0.74 seconds
Started Jul 15 06:22:44 PM PDT 24
Finished Jul 15 06:22:46 PM PDT 24
Peak memory 204044 kb
Host smart-6b80942e-0274-4893-affb-186e7366f5d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852067920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.852067920
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4127841064
Short name T122
Test name
Test status
Simulation time 107583159 ps
CPU time 1.94 seconds
Started Jul 15 06:22:41 PM PDT 24
Finished Jul 15 06:22:44 PM PDT 24
Peak memory 215508 kb
Host smart-de6e1e1e-19d6-4ed5-93ac-de2ae60805b9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127841064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4127841064
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1370993416
Short name T1035
Test name
Test status
Simulation time 35617943 ps
CPU time 0.68 seconds
Started Jul 15 06:22:42 PM PDT 24
Finished Jul 15 06:22:43 PM PDT 24
Peak memory 203916 kb
Host smart-33908e8f-ff11-4648-aa75-c42ec35a80c3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370993416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1370993416
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1744590298
Short name T1131
Test name
Test status
Simulation time 153954233 ps
CPU time 4.24 seconds
Started Jul 15 06:22:42 PM PDT 24
Finished Jul 15 06:22:47 PM PDT 24
Peak memory 215460 kb
Host smart-2c1f9f1a-b948-4492-a9a8-4fbb2d6f8e7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744590298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1744590298
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.206352569
Short name T111
Test name
Test status
Simulation time 590998739 ps
CPU time 3.83 seconds
Started Jul 15 06:22:41 PM PDT 24
Finished Jul 15 06:22:45 PM PDT 24
Peak memory 215700 kb
Host smart-162084ea-5d00-499b-9404-317fd66e09af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206352569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.206352569
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2251415220
Short name T1050
Test name
Test status
Simulation time 201649761 ps
CPU time 7.82 seconds
Started Jul 15 06:22:45 PM PDT 24
Finished Jul 15 06:22:54 PM PDT 24
Peak memory 222400 kb
Host smart-01979040-c1ca-4c6c-9124-e687c32e063b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251415220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2251415220
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2500374272
Short name T1082
Test name
Test status
Simulation time 42273075 ps
CPU time 0.72 seconds
Started Jul 15 06:23:10 PM PDT 24
Finished Jul 15 06:23:12 PM PDT 24
Peak memory 204284 kb
Host smart-975ada8a-a41c-4359-a1a1-fde6ea3a64ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500374272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2500374272
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2096364459
Short name T1032
Test name
Test status
Simulation time 30954306 ps
CPU time 0.74 seconds
Started Jul 15 06:23:08 PM PDT 24
Finished Jul 15 06:23:10 PM PDT 24
Peak memory 203976 kb
Host smart-90c6cb37-dc62-4342-aae7-f81997809833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096364459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2096364459
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1232337243
Short name T1104
Test name
Test status
Simulation time 11446527 ps
CPU time 0.73 seconds
Started Jul 15 06:23:11 PM PDT 24
Finished Jul 15 06:23:12 PM PDT 24
Peak memory 204016 kb
Host smart-38671954-3364-45eb-aeae-e8467193eeb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232337243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1232337243
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3229655664
Short name T1045
Test name
Test status
Simulation time 13844946 ps
CPU time 0.71 seconds
Started Jul 15 06:23:10 PM PDT 24
Finished Jul 15 06:23:11 PM PDT 24
Peak memory 203956 kb
Host smart-044e7f94-2be8-4db0-8bae-8da2e44e416f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229655664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3229655664
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1193459867
Short name T1064
Test name
Test status
Simulation time 18575061 ps
CPU time 0.77 seconds
Started Jul 15 06:23:09 PM PDT 24
Finished Jul 15 06:23:10 PM PDT 24
Peak memory 204264 kb
Host smart-9ab371c7-cfca-4460-a474-01766089a6a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193459867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1193459867
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1195415731
Short name T1038
Test name
Test status
Simulation time 32819311 ps
CPU time 0.69 seconds
Started Jul 15 06:23:07 PM PDT 24
Finished Jul 15 06:23:09 PM PDT 24
Peak memory 204308 kb
Host smart-1e0ac01c-ad58-476e-9f15-a0d87d4f4d40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195415731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1195415731
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1839190994
Short name T1112
Test name
Test status
Simulation time 19801667 ps
CPU time 0.71 seconds
Started Jul 15 06:23:14 PM PDT 24
Finished Jul 15 06:23:15 PM PDT 24
Peak memory 203920 kb
Host smart-ce0e83b9-bd26-4732-a616-5db00f6ca755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839190994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1839190994
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2068996354
Short name T1030
Test name
Test status
Simulation time 60023167 ps
CPU time 0.76 seconds
Started Jul 15 06:23:16 PM PDT 24
Finished Jul 15 06:23:18 PM PDT 24
Peak memory 204292 kb
Host smart-5ad75c2f-22eb-4edb-92d2-fd0d0427953e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068996354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2068996354
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2958102412
Short name T1071
Test name
Test status
Simulation time 46319815 ps
CPU time 0.77 seconds
Started Jul 15 06:23:14 PM PDT 24
Finished Jul 15 06:23:16 PM PDT 24
Peak memory 204276 kb
Host smart-ecf8b413-ebbd-4023-ac23-b610f1777342
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958102412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2958102412
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3610301489
Short name T1118
Test name
Test status
Simulation time 16059117 ps
CPU time 0.73 seconds
Started Jul 15 06:23:14 PM PDT 24
Finished Jul 15 06:23:15 PM PDT 24
Peak memory 203928 kb
Host smart-a2a95ba6-3a72-4f34-9bcd-29f1a5d98f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610301489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3610301489
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.98089955
Short name T1091
Test name
Test status
Simulation time 111846353 ps
CPU time 1.78 seconds
Started Jul 15 06:22:49 PM PDT 24
Finished Jul 15 06:22:53 PM PDT 24
Peak memory 216624 kb
Host smart-e3a3bee3-5b16-4bea-95ef-e8fcfde81fa8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98089955 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.98089955
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3537337152
Short name T128
Test name
Test status
Simulation time 40519656 ps
CPU time 2.64 seconds
Started Jul 15 06:22:47 PM PDT 24
Finished Jul 15 06:22:50 PM PDT 24
Peak memory 207276 kb
Host smart-6d289566-3671-43b3-a470-29b32789209f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537337152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
537337152
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.751903806
Short name T1142
Test name
Test status
Simulation time 52765775 ps
CPU time 0.81 seconds
Started Jul 15 06:22:48 PM PDT 24
Finished Jul 15 06:22:50 PM PDT 24
Peak memory 204276 kb
Host smart-08d780ad-2b1f-41bc-8ad9-64a3861240e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751903806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.751903806
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.865132406
Short name T147
Test name
Test status
Simulation time 705597484 ps
CPU time 4.11 seconds
Started Jul 15 06:22:49 PM PDT 24
Finished Jul 15 06:22:55 PM PDT 24
Peak memory 215472 kb
Host smart-3b3d59c9-a990-49b5-9ccd-5eabfc8e45af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865132406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.865132406
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.857075177
Short name T112
Test name
Test status
Simulation time 1642323162 ps
CPU time 3.93 seconds
Started Jul 15 06:22:49 PM PDT 24
Finished Jul 15 06:22:54 PM PDT 24
Peak memory 216724 kb
Host smart-1c5fddf4-8a2c-40d4-90d5-a9887b1bcc7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857075177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.857075177
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1175143458
Short name T1133
Test name
Test status
Simulation time 385433489 ps
CPU time 11.48 seconds
Started Jul 15 06:22:51 PM PDT 24
Finished Jul 15 06:23:03 PM PDT 24
Peak memory 215532 kb
Host smart-d395c054-7dc7-4b19-a0c0-0735eb769697
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175143458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1175143458
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.477155568
Short name T1108
Test name
Test status
Simulation time 26709199 ps
CPU time 1.61 seconds
Started Jul 15 06:22:49 PM PDT 24
Finished Jul 15 06:22:52 PM PDT 24
Peak memory 216596 kb
Host smart-7436d17c-fb1f-4670-885f-7c1b4ae6b724
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477155568 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.477155568
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4060361022
Short name T1098
Test name
Test status
Simulation time 301287075 ps
CPU time 2.13 seconds
Started Jul 15 06:22:49 PM PDT 24
Finished Jul 15 06:22:53 PM PDT 24
Peak memory 215500 kb
Host smart-fb240229-41ca-4d41-8664-acac435f5a99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060361022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.4
060361022
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1545419027
Short name T1116
Test name
Test status
Simulation time 12878552 ps
CPU time 0.75 seconds
Started Jul 15 06:22:49 PM PDT 24
Finished Jul 15 06:22:50 PM PDT 24
Peak memory 204252 kb
Host smart-dac5b27a-70c4-4626-bc41-b5b39d1c1ad9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545419027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
545419027
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2844020995
Short name T1099
Test name
Test status
Simulation time 159659274 ps
CPU time 3.93 seconds
Started Jul 15 06:22:48 PM PDT 24
Finished Jul 15 06:22:52 PM PDT 24
Peak memory 215544 kb
Host smart-7cd7cf3b-5cff-4370-95e0-7f437fa294d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844020995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2844020995
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1947411428
Short name T1095
Test name
Test status
Simulation time 255035581 ps
CPU time 1.93 seconds
Started Jul 15 06:22:50 PM PDT 24
Finished Jul 15 06:22:53 PM PDT 24
Peak memory 215688 kb
Host smart-eb731c87-8ae0-4cbc-9175-1a011c03c72d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947411428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
947411428
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4115115361
Short name T183
Test name
Test status
Simulation time 100741324 ps
CPU time 6.41 seconds
Started Jul 15 06:22:49 PM PDT 24
Finished Jul 15 06:22:57 PM PDT 24
Peak memory 215536 kb
Host smart-e83c5ada-8628-4b2f-afe5-ee4a9fb10f9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115115361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.4115115361
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3008870089
Short name T1060
Test name
Test status
Simulation time 311410258 ps
CPU time 2.41 seconds
Started Jul 15 06:22:49 PM PDT 24
Finished Jul 15 06:22:52 PM PDT 24
Peak memory 216792 kb
Host smart-97119a6e-998f-4ae6-9910-9bae5db02931
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008870089 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3008870089
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2875061850
Short name T1138
Test name
Test status
Simulation time 78513118 ps
CPU time 2.05 seconds
Started Jul 15 06:22:47 PM PDT 24
Finished Jul 15 06:22:50 PM PDT 24
Peak memory 207248 kb
Host smart-bd8cfeee-6290-45f6-b558-92e0a98dfe9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875061850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
875061850
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.583672032
Short name T1084
Test name
Test status
Simulation time 13303147 ps
CPU time 0.74 seconds
Started Jul 15 06:22:49 PM PDT 24
Finished Jul 15 06:22:51 PM PDT 24
Peak memory 204032 kb
Host smart-a6053942-0fa9-4eba-a42c-34bd4328f3b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583672032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.583672032
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1357093524
Short name T1088
Test name
Test status
Simulation time 1044310989 ps
CPU time 4.33 seconds
Started Jul 15 06:22:49 PM PDT 24
Finished Jul 15 06:22:55 PM PDT 24
Peak memory 215684 kb
Host smart-cc798913-f26e-4df6-9a31-de9de0bdcf74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357093524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1357093524
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3709597608
Short name T110
Test name
Test status
Simulation time 79815990 ps
CPU time 2.53 seconds
Started Jul 15 06:22:47 PM PDT 24
Finished Jul 15 06:22:50 PM PDT 24
Peak memory 216636 kb
Host smart-d7066fd8-4ce6-4177-a924-c1941373aad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709597608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
709597608
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3274762174
Short name T1078
Test name
Test status
Simulation time 3231724777 ps
CPU time 7.83 seconds
Started Jul 15 06:22:49 PM PDT 24
Finished Jul 15 06:22:58 PM PDT 24
Peak memory 216676 kb
Host smart-42291a44-4aba-46b0-8194-406257290ef5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274762174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3274762174
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2889137515
Short name T1076
Test name
Test status
Simulation time 93230032 ps
CPU time 1.7 seconds
Started Jul 15 06:22:52 PM PDT 24
Finished Jul 15 06:22:54 PM PDT 24
Peak memory 215620 kb
Host smart-58d35713-2cf1-47d3-930c-80446f0593ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889137515 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2889137515
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2428322725
Short name T1086
Test name
Test status
Simulation time 80338587 ps
CPU time 1.35 seconds
Started Jul 15 06:22:48 PM PDT 24
Finished Jul 15 06:22:50 PM PDT 24
Peak memory 215544 kb
Host smart-8291568d-626e-47c7-a8e7-c34fc62e95b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428322725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
428322725
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.785506206
Short name T1048
Test name
Test status
Simulation time 43729981 ps
CPU time 0.7 seconds
Started Jul 15 06:22:50 PM PDT 24
Finished Jul 15 06:22:52 PM PDT 24
Peak memory 203988 kb
Host smart-ff3bb5de-c08b-4ddb-acd5-af1bd212b5e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785506206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.785506206
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.772761924
Short name T1139
Test name
Test status
Simulation time 56152454 ps
CPU time 3.55 seconds
Started Jul 15 06:22:51 PM PDT 24
Finished Jul 15 06:22:55 PM PDT 24
Peak memory 215512 kb
Host smart-65be3903-b778-4efe-9ffd-0527297c21c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772761924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.772761924
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1129206554
Short name T104
Test name
Test status
Simulation time 314231812 ps
CPU time 2.29 seconds
Started Jul 15 06:22:47 PM PDT 24
Finished Jul 15 06:22:49 PM PDT 24
Peak memory 215772 kb
Host smart-e576f688-e3fc-4b61-a6d4-8eeff57074b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129206554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
129206554
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1903018474
Short name T1106
Test name
Test status
Simulation time 54697079 ps
CPU time 3.79 seconds
Started Jul 15 06:22:49 PM PDT 24
Finished Jul 15 06:22:54 PM PDT 24
Peak memory 217484 kb
Host smart-964d5410-ed60-44ea-9970-eaa1f11a047f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903018474 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1903018474
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1077077292
Short name T121
Test name
Test status
Simulation time 420277530 ps
CPU time 2.58 seconds
Started Jul 15 06:22:52 PM PDT 24
Finished Jul 15 06:22:55 PM PDT 24
Peak memory 215568 kb
Host smart-345081c5-fe32-4490-b15a-bbeba1879170
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077077292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
077077292
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2168040683
Short name T1031
Test name
Test status
Simulation time 14362849 ps
CPU time 0.73 seconds
Started Jul 15 06:22:50 PM PDT 24
Finished Jul 15 06:22:52 PM PDT 24
Peak memory 204292 kb
Host smart-f6910864-d094-4f51-9f97-c5913f7d60f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168040683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
168040683
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3223981857
Short name T1046
Test name
Test status
Simulation time 58874492 ps
CPU time 3.93 seconds
Started Jul 15 06:22:52 PM PDT 24
Finished Jul 15 06:22:56 PM PDT 24
Peak memory 215536 kb
Host smart-5aba1ccd-afe3-43d5-bae1-b6dfb8a039e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223981857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3223981857
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3238306978
Short name T108
Test name
Test status
Simulation time 1974924277 ps
CPU time 4.24 seconds
Started Jul 15 06:22:51 PM PDT 24
Finished Jul 15 06:22:56 PM PDT 24
Peak memory 216056 kb
Host smart-54bafc28-34f6-4ca9-acb9-43224c2d388c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238306978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
238306978
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.4055507100
Short name T116
Test name
Test status
Simulation time 1367777641 ps
CPU time 11.93 seconds
Started Jul 15 06:22:50 PM PDT 24
Finished Jul 15 06:23:03 PM PDT 24
Peak memory 215428 kb
Host smart-5bf592f1-a84a-4a0a-ab0e-600a6147039d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055507100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.4055507100
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1030990213
Short name T350
Test name
Test status
Simulation time 134460608 ps
CPU time 3.56 seconds
Started Jul 15 06:23:16 PM PDT 24
Finished Jul 15 06:23:21 PM PDT 24
Peak memory 233704 kb
Host smart-6f0320eb-1cd7-4f1a-924a-cc9f544ccff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030990213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1030990213
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1525161214
Short name T863
Test name
Test status
Simulation time 138909145 ps
CPU time 0.79 seconds
Started Jul 15 06:23:16 PM PDT 24
Finished Jul 15 06:23:19 PM PDT 24
Peak memory 207460 kb
Host smart-879a9138-967f-4935-be99-cbe63c106db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525161214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1525161214
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1004806769
Short name T656
Test name
Test status
Simulation time 19827063160 ps
CPU time 141.71 seconds
Started Jul 15 06:23:16 PM PDT 24
Finished Jul 15 06:25:39 PM PDT 24
Peak memory 256160 kb
Host smart-ec76a7bb-a666-49fa-b525-c3d64f8c7506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004806769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1004806769
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3964448217
Short name T744
Test name
Test status
Simulation time 16538255774 ps
CPU time 124.67 seconds
Started Jul 15 06:23:14 PM PDT 24
Finished Jul 15 06:25:19 PM PDT 24
Peak memory 252816 kb
Host smart-097cf5af-701c-41f2-8dd6-65494a6fa312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964448217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3964448217
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.903851704
Short name T915
Test name
Test status
Simulation time 7248187722 ps
CPU time 51.62 seconds
Started Jul 15 06:23:16 PM PDT 24
Finished Jul 15 06:24:09 PM PDT 24
Peak memory 250320 kb
Host smart-86bc29a3-ed6e-4e3d-8320-ee0997520814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903851704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
903851704
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1872242405
Short name T39
Test name
Test status
Simulation time 388629451 ps
CPU time 4.91 seconds
Started Jul 15 06:23:18 PM PDT 24
Finished Jul 15 06:23:23 PM PDT 24
Peak memory 225524 kb
Host smart-7ed34a31-879f-4253-b877-cce149e469b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872242405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1872242405
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.146600388
Short name T73
Test name
Test status
Simulation time 14905628589 ps
CPU time 38.16 seconds
Started Jul 15 06:23:14 PM PDT 24
Finished Jul 15 06:23:53 PM PDT 24
Peak memory 233844 kb
Host smart-d5e828a0-2cfc-4bd9-9548-e78c2a1d1537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146600388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.146600388
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1590380641
Short name T831
Test name
Test status
Simulation time 943770489 ps
CPU time 4.74 seconds
Started Jul 15 06:23:14 PM PDT 24
Finished Jul 15 06:23:20 PM PDT 24
Peak memory 225628 kb
Host smart-86632cb2-6ecc-4d0c-8697-c00e986de776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590380641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1590380641
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2647320732
Short name T255
Test name
Test status
Simulation time 1147705905 ps
CPU time 7.96 seconds
Started Jul 15 06:23:17 PM PDT 24
Finished Jul 15 06:23:26 PM PDT 24
Peak memory 225576 kb
Host smart-564d8b3a-928c-4a10-9c2d-442e5e9ee79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647320732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2647320732
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.899989434
Short name T374
Test name
Test status
Simulation time 273993339 ps
CPU time 3.56 seconds
Started Jul 15 06:23:16 PM PDT 24
Finished Jul 15 06:23:21 PM PDT 24
Peak memory 221880 kb
Host smart-530820d7-3c0f-47b9-ac0e-02100977793f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=899989434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.899989434
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2733399121
Short name T280
Test name
Test status
Simulation time 310474904905 ps
CPU time 765.28 seconds
Started Jul 15 06:23:17 PM PDT 24
Finished Jul 15 06:36:04 PM PDT 24
Peak memory 265212 kb
Host smart-ffaa2634-8681-4fb2-b9c4-b8e2ea132ad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733399121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2733399121
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.561276936
Short name T28
Test name
Test status
Simulation time 6807143021 ps
CPU time 35.74 seconds
Started Jul 15 06:23:15 PM PDT 24
Finished Jul 15 06:23:52 PM PDT 24
Peak memory 217516 kb
Host smart-a381d3c7-2bf9-4287-8963-244980745b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561276936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.561276936
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.616787890
Short name T644
Test name
Test status
Simulation time 885672935 ps
CPU time 2.54 seconds
Started Jul 15 06:23:17 PM PDT 24
Finished Jul 15 06:23:20 PM PDT 24
Peak memory 217284 kb
Host smart-a2af3812-1aa7-4fed-85e2-3b95fa1c6473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616787890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.616787890
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4233279713
Short name T824
Test name
Test status
Simulation time 21325860 ps
CPU time 0.77 seconds
Started Jul 15 06:23:16 PM PDT 24
Finished Jul 15 06:23:18 PM PDT 24
Peak memory 206956 kb
Host smart-56d5cf88-0875-4e56-94bd-0ecefbe65ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233279713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4233279713
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2776728255
Short name T611
Test name
Test status
Simulation time 50972249 ps
CPU time 0.96 seconds
Started Jul 15 06:23:16 PM PDT 24
Finished Jul 15 06:23:18 PM PDT 24
Peak memory 207980 kb
Host smart-83ce7be1-f22d-4624-a0a5-b52dd9233c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776728255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2776728255
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3443181996
Short name T613
Test name
Test status
Simulation time 89434878 ps
CPU time 2.28 seconds
Started Jul 15 06:23:18 PM PDT 24
Finished Jul 15 06:23:21 PM PDT 24
Peak memory 225240 kb
Host smart-180e97bf-7351-4991-ab4f-b5b76b98c36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443181996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3443181996
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1577794019
Short name T645
Test name
Test status
Simulation time 12468307 ps
CPU time 0.73 seconds
Started Jul 15 06:23:23 PM PDT 24
Finished Jul 15 06:23:25 PM PDT 24
Peak memory 206312 kb
Host smart-677069f9-7457-47f1-ac72-2c74162245c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577794019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
577794019
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2655100405
Short name T91
Test name
Test status
Simulation time 1123088836 ps
CPU time 8.1 seconds
Started Jul 15 06:23:23 PM PDT 24
Finished Jul 15 06:23:33 PM PDT 24
Peak memory 225492 kb
Host smart-c8111232-8106-43b2-908e-161ec702311b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655100405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2655100405
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1364314154
Short name T771
Test name
Test status
Simulation time 16519916 ps
CPU time 0.79 seconds
Started Jul 15 06:23:15 PM PDT 24
Finished Jul 15 06:23:17 PM PDT 24
Peak memory 207440 kb
Host smart-f2bf3ad6-1ca5-4fff-a66a-df0502648fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364314154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1364314154
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1168624553
Short name T58
Test name
Test status
Simulation time 13812851198 ps
CPU time 123.86 seconds
Started Jul 15 06:23:22 PM PDT 24
Finished Jul 15 06:25:26 PM PDT 24
Peak memory 255464 kb
Host smart-02a9a307-9e14-4e3c-b912-9e41c62591bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168624553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1168624553
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2940048744
Short name T294
Test name
Test status
Simulation time 36728063487 ps
CPU time 123.23 seconds
Started Jul 15 06:23:26 PM PDT 24
Finished Jul 15 06:25:29 PM PDT 24
Peak memory 266744 kb
Host smart-58c3c500-355d-4a85-a6aa-952c6cf03c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940048744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2940048744
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2853294809
Short name T813
Test name
Test status
Simulation time 314977231 ps
CPU time 5.94 seconds
Started Jul 15 06:23:24 PM PDT 24
Finished Jul 15 06:23:31 PM PDT 24
Peak memory 233772 kb
Host smart-a0ffe7ab-0bd3-4a86-bc81-993bfc92c78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853294809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2853294809
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2665530702
Short name T955
Test name
Test status
Simulation time 109347319751 ps
CPU time 277.78 seconds
Started Jul 15 06:23:23 PM PDT 24
Finished Jul 15 06:28:03 PM PDT 24
Peak memory 258468 kb
Host smart-ef735fac-b677-43ab-bc38-41df6baf5f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665530702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2665530702
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1023344395
Short name T735
Test name
Test status
Simulation time 1448259637 ps
CPU time 14.83 seconds
Started Jul 15 06:23:23 PM PDT 24
Finished Jul 15 06:23:39 PM PDT 24
Peak memory 233796 kb
Host smart-0bdc8f48-59f5-4a09-842a-a6fb7a189b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023344395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1023344395
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.286299864
Short name T679
Test name
Test status
Simulation time 30876736 ps
CPU time 2.59 seconds
Started Jul 15 06:23:23 PM PDT 24
Finished Jul 15 06:23:27 PM PDT 24
Peak memory 233508 kb
Host smart-8a5a2200-e834-453f-9009-7cab55a8050e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286299864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.286299864
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2128420356
Short name T724
Test name
Test status
Simulation time 17597105 ps
CPU time 1.13 seconds
Started Jul 15 06:23:15 PM PDT 24
Finished Jul 15 06:23:18 PM PDT 24
Peak memory 218908 kb
Host smart-eb9a6eda-f96f-44f4-98e9-3cb343b388ff
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128420356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2128420356
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1814310347
Short name T191
Test name
Test status
Simulation time 45410245495 ps
CPU time 30.58 seconds
Started Jul 15 06:23:23 PM PDT 24
Finished Jul 15 06:23:55 PM PDT 24
Peak memory 241828 kb
Host smart-237e7fae-6cd6-426d-9340-8d96225e10e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814310347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1814310347
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4062748677
Short name T41
Test name
Test status
Simulation time 80601182 ps
CPU time 2.67 seconds
Started Jul 15 06:23:17 PM PDT 24
Finished Jul 15 06:23:21 PM PDT 24
Peak memory 233716 kb
Host smart-1af0a69a-2055-419f-b4d2-637b9000f8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062748677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4062748677
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3397888040
Short name T436
Test name
Test status
Simulation time 5822773544 ps
CPU time 5.97 seconds
Started Jul 15 06:23:20 PM PDT 24
Finished Jul 15 06:23:26 PM PDT 24
Peak memory 221440 kb
Host smart-faa35b60-994d-4e2b-b892-b5cab824e5d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3397888040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3397888040
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1691530055
Short name T69
Test name
Test status
Simulation time 182620264 ps
CPU time 1.22 seconds
Started Jul 15 06:23:21 PM PDT 24
Finished Jul 15 06:23:23 PM PDT 24
Peak memory 236352 kb
Host smart-b7258acb-26d8-4a31-a536-f94cf787cb89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691530055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1691530055
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.799966409
Short name T14
Test name
Test status
Simulation time 6633249722 ps
CPU time 114.03 seconds
Started Jul 15 06:23:26 PM PDT 24
Finished Jul 15 06:25:20 PM PDT 24
Peak memory 250364 kb
Host smart-14ed53df-f1e1-4408-a255-0a7143211b14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799966409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.799966409
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1987427579
Short name T590
Test name
Test status
Simulation time 15775069884 ps
CPU time 18.55 seconds
Started Jul 15 06:23:14 PM PDT 24
Finished Jul 15 06:23:33 PM PDT 24
Peak memory 217360 kb
Host smart-571f0a03-de9a-42bf-ab2b-b82b3d744d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987427579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1987427579
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.4156189437
Short name T900
Test name
Test status
Simulation time 135849604 ps
CPU time 1.17 seconds
Started Jul 15 06:23:18 PM PDT 24
Finished Jul 15 06:23:20 PM PDT 24
Peak memory 207992 kb
Host smart-af19a487-e72b-46d7-8d58-080ea32d6166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156189437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.4156189437
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1875071758
Short name T383
Test name
Test status
Simulation time 48499492 ps
CPU time 0.86 seconds
Started Jul 15 06:23:14 PM PDT 24
Finished Jul 15 06:23:16 PM PDT 24
Peak memory 207576 kb
Host smart-1079e459-5edf-487a-beea-83ada87b62fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875071758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1875071758
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1003467578
Short name T663
Test name
Test status
Simulation time 182100339 ps
CPU time 0.87 seconds
Started Jul 15 06:23:15 PM PDT 24
Finished Jul 15 06:23:17 PM PDT 24
Peak memory 206848 kb
Host smart-9089b132-f097-476e-944b-4afb3ca23ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003467578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1003467578
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.401673609
Short name T730
Test name
Test status
Simulation time 2712789848 ps
CPU time 12.3 seconds
Started Jul 15 06:23:22 PM PDT 24
Finished Jul 15 06:23:36 PM PDT 24
Peak memory 249216 kb
Host smart-0507fc89-4d28-47e9-8bbd-4ad632b994ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401673609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.401673609
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1351024543
Short name T818
Test name
Test status
Simulation time 39765482 ps
CPU time 0.76 seconds
Started Jul 15 06:24:04 PM PDT 24
Finished Jul 15 06:24:05 PM PDT 24
Peak memory 206724 kb
Host smart-c8a5cb68-a776-4fd0-9bde-2486c5e47ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351024543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1351024543
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2602642932
Short name T498
Test name
Test status
Simulation time 310507553 ps
CPU time 4.9 seconds
Started Jul 15 06:24:07 PM PDT 24
Finished Jul 15 06:24:13 PM PDT 24
Peak memory 233820 kb
Host smart-98a22c98-49e9-46b5-b224-1b9f8dffb557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602642932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2602642932
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1446552626
Short name T362
Test name
Test status
Simulation time 35979178 ps
CPU time 0.79 seconds
Started Jul 15 06:23:55 PM PDT 24
Finished Jul 15 06:23:57 PM PDT 24
Peak memory 207852 kb
Host smart-99f15b07-9cf6-4402-a55e-a123f21540ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446552626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1446552626
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.37398066
Short name T752
Test name
Test status
Simulation time 108127258787 ps
CPU time 167.26 seconds
Started Jul 15 06:24:02 PM PDT 24
Finished Jul 15 06:26:50 PM PDT 24
Peak memory 250264 kb
Host smart-8d40778a-dd75-4e1d-8440-733697ea3fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37398066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.37398066
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1086732849
Short name T212
Test name
Test status
Simulation time 19692658171 ps
CPU time 133.88 seconds
Started Jul 15 06:24:02 PM PDT 24
Finished Jul 15 06:26:16 PM PDT 24
Peak memory 264620 kb
Host smart-df955893-777f-4fd8-9c83-8cc1fd64ce96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086732849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1086732849
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.702397415
Short name T749
Test name
Test status
Simulation time 3277571881 ps
CPU time 88.81 seconds
Started Jul 15 06:24:07 PM PDT 24
Finished Jul 15 06:25:37 PM PDT 24
Peak memory 259896 kb
Host smart-a0e12486-863e-4bb2-adcd-1a26c1c3ad2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702397415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.702397415
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2220113094
Short name T769
Test name
Test status
Simulation time 3675100780 ps
CPU time 13.09 seconds
Started Jul 15 06:24:09 PM PDT 24
Finished Jul 15 06:24:23 PM PDT 24
Peak memory 225720 kb
Host smart-cda5a90a-8d25-491d-bc6f-ba60f3e33e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220113094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2220113094
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2597444649
Short name T222
Test name
Test status
Simulation time 2386275495 ps
CPU time 15 seconds
Started Jul 15 06:24:07 PM PDT 24
Finished Jul 15 06:24:23 PM PDT 24
Peak memory 238024 kb
Host smart-d7076f51-7644-42f2-9b63-2ff3d95eea23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597444649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2597444649
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1501843396
Short name T888
Test name
Test status
Simulation time 20572573954 ps
CPU time 20.12 seconds
Started Jul 15 06:24:03 PM PDT 24
Finished Jul 15 06:24:24 PM PDT 24
Peak memory 233944 kb
Host smart-1792bb50-74fa-4f69-814e-6f18fcc05a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501843396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1501843396
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2873106425
Short name T768
Test name
Test status
Simulation time 414168832 ps
CPU time 6.7 seconds
Started Jul 15 06:24:02 PM PDT 24
Finished Jul 15 06:24:10 PM PDT 24
Peak memory 233724 kb
Host smart-9e0e4482-e2d8-4a44-a6a9-b8a30f4361d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873106425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2873106425
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.317467521
Short name T34
Test name
Test status
Simulation time 60201818 ps
CPU time 1.13 seconds
Started Jul 15 06:23:59 PM PDT 24
Finished Jul 15 06:24:01 PM PDT 24
Peak memory 217616 kb
Host smart-94ce4bd6-e3d4-427d-944a-264b933138f3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317467521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.317467521
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2685315224
Short name T140
Test name
Test status
Simulation time 951288455 ps
CPU time 3.27 seconds
Started Jul 15 06:24:02 PM PDT 24
Finished Jul 15 06:24:06 PM PDT 24
Peak memory 233744 kb
Host smart-0dc11577-94b2-4a88-896b-8f3f0c93ac62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685315224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2685315224
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.369748580
Short name T595
Test name
Test status
Simulation time 3813131184 ps
CPU time 6.14 seconds
Started Jul 15 06:24:02 PM PDT 24
Finished Jul 15 06:24:09 PM PDT 24
Peak memory 225564 kb
Host smart-d5d967fe-885c-416c-86d2-8c5445fca03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369748580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.369748580
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2159961152
Short name T667
Test name
Test status
Simulation time 4088161811 ps
CPU time 12.14 seconds
Started Jul 15 06:24:06 PM PDT 24
Finished Jul 15 06:24:19 PM PDT 24
Peak memory 220424 kb
Host smart-37a8ab5a-30a2-402b-b4e5-927b979d664b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2159961152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2159961152
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2879316767
Short name T162
Test name
Test status
Simulation time 76001662 ps
CPU time 1.26 seconds
Started Jul 15 06:24:03 PM PDT 24
Finished Jul 15 06:24:05 PM PDT 24
Peak memory 208648 kb
Host smart-75051642-a261-4286-80c6-561a0f779631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879316767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2879316767
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1816077691
Short name T947
Test name
Test status
Simulation time 3815760747 ps
CPU time 23.96 seconds
Started Jul 15 06:24:07 PM PDT 24
Finished Jul 15 06:24:32 PM PDT 24
Peak memory 217488 kb
Host smart-e7565ed2-912d-4176-89bc-da5657df589c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816077691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1816077691
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2123347922
Short name T418
Test name
Test status
Simulation time 29018929 ps
CPU time 0.72 seconds
Started Jul 15 06:24:07 PM PDT 24
Finished Jul 15 06:24:09 PM PDT 24
Peak memory 206600 kb
Host smart-ac904d8b-c9fd-4c26-8338-632710ef1174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123347922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2123347922
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2597073017
Short name T352
Test name
Test status
Simulation time 210242234 ps
CPU time 1.22 seconds
Started Jul 15 06:24:09 PM PDT 24
Finished Jul 15 06:24:11 PM PDT 24
Peak memory 217324 kb
Host smart-75035339-7b67-464b-9ddd-fe6ee0c24717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597073017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2597073017
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.407865986
Short name T402
Test name
Test status
Simulation time 32666654 ps
CPU time 0.74 seconds
Started Jul 15 06:24:03 PM PDT 24
Finished Jul 15 06:24:04 PM PDT 24
Peak memory 206980 kb
Host smart-87140764-7fe0-40ee-8c4b-258625647fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407865986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.407865986
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1866322542
Short name T274
Test name
Test status
Simulation time 673619029 ps
CPU time 4.82 seconds
Started Jul 15 06:24:08 PM PDT 24
Finished Jul 15 06:24:14 PM PDT 24
Peak memory 233776 kb
Host smart-bf7ebd2e-6f57-4134-8abf-48a002159bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866322542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1866322542
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1828130805
Short name T788
Test name
Test status
Simulation time 28584243 ps
CPU time 0.75 seconds
Started Jul 15 06:24:04 PM PDT 24
Finished Jul 15 06:24:06 PM PDT 24
Peak memory 206668 kb
Host smart-e05beebc-51c8-45aa-aaa5-a03b3d0ef139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828130805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1828130805
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.478845355
Short name T261
Test name
Test status
Simulation time 285379819 ps
CPU time 2.28 seconds
Started Jul 15 06:24:02 PM PDT 24
Finished Jul 15 06:24:05 PM PDT 24
Peak memory 225516 kb
Host smart-f169f9f0-58b9-4270-9ddb-3858edae5bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478845355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.478845355
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3157032209
Short name T467
Test name
Test status
Simulation time 16381233 ps
CPU time 0.76 seconds
Started Jul 15 06:24:03 PM PDT 24
Finished Jul 15 06:24:04 PM PDT 24
Peak memory 206476 kb
Host smart-ed4298a8-db18-4edd-a023-10f06a77eeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157032209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3157032209
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3030847701
Short name T194
Test name
Test status
Simulation time 147756410754 ps
CPU time 293.71 seconds
Started Jul 15 06:24:07 PM PDT 24
Finished Jul 15 06:29:02 PM PDT 24
Peak memory 257424 kb
Host smart-0d3cb9da-e03b-4b42-b36c-77135b80d8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030847701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3030847701
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1937641200
Short name T310
Test name
Test status
Simulation time 813343188 ps
CPU time 5.82 seconds
Started Jul 15 06:24:04 PM PDT 24
Finished Jul 15 06:24:11 PM PDT 24
Peak memory 225612 kb
Host smart-6695cc36-fa1d-4c40-8924-4f9db0abeb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937641200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1937641200
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.843526892
Short name T293
Test name
Test status
Simulation time 36371137446 ps
CPU time 131.49 seconds
Started Jul 15 06:24:02 PM PDT 24
Finished Jul 15 06:26:14 PM PDT 24
Peak memory 250276 kb
Host smart-3fb7218e-8094-4ddb-9dd6-c6f49fc6e340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843526892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.843526892
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3205630605
Short name T957
Test name
Test status
Simulation time 11829662502 ps
CPU time 26.44 seconds
Started Jul 15 06:24:01 PM PDT 24
Finished Jul 15 06:24:29 PM PDT 24
Peak memory 233848 kb
Host smart-f5b2cc83-e943-44b2-b044-b13a70219eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205630605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3205630605
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3242195202
Short name T248
Test name
Test status
Simulation time 6599090406 ps
CPU time 51.92 seconds
Started Jul 15 06:24:04 PM PDT 24
Finished Jul 15 06:24:57 PM PDT 24
Peak memory 240504 kb
Host smart-1896b003-466f-4154-8994-9f44aca85f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242195202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3242195202
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3397889623
Short name T35
Test name
Test status
Simulation time 106494106 ps
CPU time 1.07 seconds
Started Jul 15 06:24:03 PM PDT 24
Finished Jul 15 06:24:04 PM PDT 24
Peak memory 217684 kb
Host smart-331cc7f5-6004-45e9-a611-2b75ce92ec6c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397889623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3397889623
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.311944160
Short name T302
Test name
Test status
Simulation time 232228446 ps
CPU time 4.33 seconds
Started Jul 15 06:24:03 PM PDT 24
Finished Jul 15 06:24:08 PM PDT 24
Peak memory 225656 kb
Host smart-c3026d40-6221-4f15-a984-7211a098e6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311944160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.311944160
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2706867425
Short name T597
Test name
Test status
Simulation time 1477274666 ps
CPU time 8.86 seconds
Started Jul 15 06:24:04 PM PDT 24
Finished Jul 15 06:24:13 PM PDT 24
Peak memory 233712 kb
Host smart-54e0ef39-13fc-4298-a270-8fc4569fa518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706867425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2706867425
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3235958056
Short name T421
Test name
Test status
Simulation time 178359949 ps
CPU time 4.7 seconds
Started Jul 15 06:24:07 PM PDT 24
Finished Jul 15 06:24:13 PM PDT 24
Peak memory 222816 kb
Host smart-4f3b0596-055f-414f-a678-7741b3096f21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3235958056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3235958056
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1120036372
Short name T848
Test name
Test status
Simulation time 108641329022 ps
CPU time 333.53 seconds
Started Jul 15 06:24:04 PM PDT 24
Finished Jul 15 06:29:38 PM PDT 24
Peak memory 282152 kb
Host smart-3560ec04-1a9e-4354-b21b-e82d66a98e3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120036372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1120036372
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2812080103
Short name T800
Test name
Test status
Simulation time 3901979219 ps
CPU time 27.96 seconds
Started Jul 15 06:24:09 PM PDT 24
Finished Jul 15 06:24:37 PM PDT 24
Peak memory 217512 kb
Host smart-40784a25-5a2a-453c-91fe-21b9e096ee25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812080103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2812080103
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.400046032
Short name T334
Test name
Test status
Simulation time 917578503 ps
CPU time 3.97 seconds
Started Jul 15 06:24:07 PM PDT 24
Finished Jul 15 06:24:12 PM PDT 24
Peak memory 216804 kb
Host smart-e060e80a-bc36-44b9-af9a-9eb9e1de4905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400046032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.400046032
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.230325895
Short name T997
Test name
Test status
Simulation time 159761684 ps
CPU time 8.05 seconds
Started Jul 15 06:24:01 PM PDT 24
Finished Jul 15 06:24:09 PM PDT 24
Peak memory 217312 kb
Host smart-72834719-1718-49da-ae31-edb118b3fb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230325895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.230325895
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.179201732
Short name T88
Test name
Test status
Simulation time 70346693 ps
CPU time 0.94 seconds
Started Jul 15 06:24:05 PM PDT 24
Finished Jul 15 06:24:06 PM PDT 24
Peak memory 207148 kb
Host smart-234132e5-a50f-4870-ba68-b5777e235752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179201732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.179201732
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2812291479
Short name T363
Test name
Test status
Simulation time 170887202 ps
CPU time 2.61 seconds
Started Jul 15 06:24:01 PM PDT 24
Finished Jul 15 06:24:04 PM PDT 24
Peak memory 233480 kb
Host smart-83ddaf3b-a550-4476-a197-6647f304ee59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812291479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2812291479
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2489803747
Short name T658
Test name
Test status
Simulation time 21552658 ps
CPU time 0.72 seconds
Started Jul 15 06:24:08 PM PDT 24
Finished Jul 15 06:24:09 PM PDT 24
Peak memory 206364 kb
Host smart-d39c7313-95b1-4d07-8b84-c3b4aa1930b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489803747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2489803747
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.556340511
Short name T511
Test name
Test status
Simulation time 643300004 ps
CPU time 9.19 seconds
Started Jul 15 06:24:07 PM PDT 24
Finished Jul 15 06:24:17 PM PDT 24
Peak memory 233756 kb
Host smart-b3278e9a-c8a2-4b87-a7c0-06ec8afa166f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556340511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.556340511
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1071051025
Short name T801
Test name
Test status
Simulation time 28258665 ps
CPU time 0.75 seconds
Started Jul 15 06:24:04 PM PDT 24
Finished Jul 15 06:24:05 PM PDT 24
Peak memory 206452 kb
Host smart-54a9f254-468c-4f92-b021-7e6719b3f135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071051025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1071051025
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.693673414
Short name T548
Test name
Test status
Simulation time 6556677427 ps
CPU time 15.79 seconds
Started Jul 15 06:24:14 PM PDT 24
Finished Jul 15 06:24:31 PM PDT 24
Peak memory 239132 kb
Host smart-32717460-6f67-47e8-b6ea-0611eba9098d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693673414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.693673414
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.609639370
Short name T211
Test name
Test status
Simulation time 2133199744 ps
CPU time 25.13 seconds
Started Jul 15 06:24:20 PM PDT 24
Finished Jul 15 06:24:46 PM PDT 24
Peak memory 225652 kb
Host smart-d069bc4b-5af7-48e0-b15a-3e71919caa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609639370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.609639370
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1175295210
Short name T479
Test name
Test status
Simulation time 1142579365 ps
CPU time 17.67 seconds
Started Jul 15 06:24:20 PM PDT 24
Finished Jul 15 06:24:38 PM PDT 24
Peak memory 225508 kb
Host smart-1ce931e1-dac6-4480-a32c-c7a5076fbd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175295210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1175295210
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.4019566111
Short name T188
Test name
Test status
Simulation time 6694437604 ps
CPU time 16.85 seconds
Started Jul 15 06:24:11 PM PDT 24
Finished Jul 15 06:24:29 PM PDT 24
Peak memory 249856 kb
Host smart-c269926e-d9c2-414d-b350-ab46382b34cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019566111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.4019566111
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.874573279
Short name T259
Test name
Test status
Simulation time 488690465 ps
CPU time 2.65 seconds
Started Jul 15 06:24:20 PM PDT 24
Finished Jul 15 06:24:23 PM PDT 24
Peak memory 225564 kb
Host smart-03d457a3-0805-4487-8099-d4710926a119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874573279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.874573279
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.4044081051
Short name T502
Test name
Test status
Simulation time 1013085771 ps
CPU time 9.57 seconds
Started Jul 15 06:24:11 PM PDT 24
Finished Jul 15 06:24:22 PM PDT 24
Peak memory 225596 kb
Host smart-f13846d5-e71c-41bb-bf02-45f6ea5b6430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044081051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4044081051
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3667761218
Short name T774
Test name
Test status
Simulation time 16278553 ps
CPU time 1.04 seconds
Started Jul 15 06:24:07 PM PDT 24
Finished Jul 15 06:24:09 PM PDT 24
Peak memory 218928 kb
Host smart-7b81a179-7c0c-4233-9ec6-e3e2fef477d8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667761218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3667761218
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1418631142
Short name T806
Test name
Test status
Simulation time 201861237 ps
CPU time 2.43 seconds
Started Jul 15 06:24:07 PM PDT 24
Finished Jul 15 06:24:10 PM PDT 24
Peak memory 233460 kb
Host smart-c1ca8770-5edd-4107-bfc1-d6e659043b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418631142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1418631142
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3229449177
Short name T911
Test name
Test status
Simulation time 5026271991 ps
CPU time 7.59 seconds
Started Jul 15 06:24:06 PM PDT 24
Finished Jul 15 06:24:14 PM PDT 24
Peak memory 233852 kb
Host smart-9a426631-a9f6-4ab2-a239-cf5411d8149e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229449177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3229449177
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3735142364
Short name T707
Test name
Test status
Simulation time 18955027567 ps
CPU time 8.82 seconds
Started Jul 15 06:24:07 PM PDT 24
Finished Jul 15 06:24:17 PM PDT 24
Peak memory 222748 kb
Host smart-50772716-6aeb-45db-8dfc-f06210840e34
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3735142364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3735142364
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.591827073
Short name T327
Test name
Test status
Simulation time 187557003 ps
CPU time 3.66 seconds
Started Jul 15 06:24:08 PM PDT 24
Finished Jul 15 06:24:13 PM PDT 24
Peak memory 217704 kb
Host smart-2cdf52ef-a45f-483b-89c2-e6473ff682e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591827073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.591827073
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1089345143
Short name T345
Test name
Test status
Simulation time 17316192069 ps
CPU time 21.36 seconds
Started Jul 15 06:24:03 PM PDT 24
Finished Jul 15 06:24:25 PM PDT 24
Peak memory 217436 kb
Host smart-84fd4ada-b530-4b33-a6c3-d39de5f5d894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089345143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1089345143
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3553266105
Short name T703
Test name
Test status
Simulation time 40711724 ps
CPU time 1.39 seconds
Started Jul 15 06:24:06 PM PDT 24
Finished Jul 15 06:24:07 PM PDT 24
Peak memory 217356 kb
Host smart-d2a06176-ef5f-486b-b81b-ffe9e4854a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553266105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3553266105
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3994488831
Short name T577
Test name
Test status
Simulation time 340142537 ps
CPU time 0.9 seconds
Started Jul 15 06:24:01 PM PDT 24
Finished Jul 15 06:24:03 PM PDT 24
Peak memory 206944 kb
Host smart-c092d51b-8b9f-4371-b001-5565493b0364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994488831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3994488831
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1588843255
Short name T408
Test name
Test status
Simulation time 4312555639 ps
CPU time 8.89 seconds
Started Jul 15 06:24:07 PM PDT 24
Finished Jul 15 06:24:16 PM PDT 24
Peak memory 236716 kb
Host smart-c21f1898-bac5-4d81-a160-dfb1b81a8ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588843255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1588843255
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1020764233
Short name T494
Test name
Test status
Simulation time 108777488 ps
CPU time 0.73 seconds
Started Jul 15 06:24:16 PM PDT 24
Finished Jul 15 06:24:17 PM PDT 24
Peak memory 206644 kb
Host smart-d4e9fb66-43b6-4c89-8d4f-0acc473cc8b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020764233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1020764233
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2020338507
Short name T347
Test name
Test status
Simulation time 32700461 ps
CPU time 2.37 seconds
Started Jul 15 06:24:15 PM PDT 24
Finished Jul 15 06:24:18 PM PDT 24
Peak memory 233552 kb
Host smart-dba6cd01-f4ad-47be-8a15-ae16f141b48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020338507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2020338507
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3663543551
Short name T561
Test name
Test status
Simulation time 46267353 ps
CPU time 0.77 seconds
Started Jul 15 06:24:21 PM PDT 24
Finished Jul 15 06:24:23 PM PDT 24
Peak memory 207500 kb
Host smart-881dff79-959c-46d5-9dde-30b6ae417919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663543551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3663543551
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.4077348396
Short name T414
Test name
Test status
Simulation time 16414527 ps
CPU time 0.77 seconds
Started Jul 15 06:24:17 PM PDT 24
Finished Jul 15 06:24:18 PM PDT 24
Peak memory 216896 kb
Host smart-3ef1ca00-6b6c-4338-a731-b75a0e033f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077348396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4077348396
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.991862826
Short name T49
Test name
Test status
Simulation time 2866802315 ps
CPU time 17.42 seconds
Started Jul 15 06:24:15 PM PDT 24
Finished Jul 15 06:24:33 PM PDT 24
Peak memory 218708 kb
Host smart-87c40416-0135-4758-abfb-62b979ef1c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991862826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.991862826
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3186856440
Short name T541
Test name
Test status
Simulation time 1071438049 ps
CPU time 11.64 seconds
Started Jul 15 06:24:17 PM PDT 24
Finished Jul 15 06:24:29 PM PDT 24
Peak memory 233776 kb
Host smart-131e21d0-3214-4d99-839a-d91f944efb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186856440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3186856440
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3075861655
Short name T930
Test name
Test status
Simulation time 125730670 ps
CPU time 3.4 seconds
Started Jul 15 06:24:19 PM PDT 24
Finished Jul 15 06:24:23 PM PDT 24
Peak memory 233728 kb
Host smart-f60556cb-761c-4558-8f0f-514d87a2dbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075861655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3075861655
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.292889195
Short name T960
Test name
Test status
Simulation time 5988368210 ps
CPU time 41.72 seconds
Started Jul 15 06:24:19 PM PDT 24
Finished Jul 15 06:25:01 PM PDT 24
Peak memory 225632 kb
Host smart-72ea467d-46ad-43b0-9eaa-4377d4f642d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292889195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.292889195
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3996674291
Short name T507
Test name
Test status
Simulation time 31245499 ps
CPU time 1.12 seconds
Started Jul 15 06:24:11 PM PDT 24
Finished Jul 15 06:24:13 PM PDT 24
Peak memory 217228 kb
Host smart-d7162a4d-90f0-475e-8c6b-cbd2ccb9f6f2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996674291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3996674291
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3409926780
Short name T614
Test name
Test status
Simulation time 1548184633 ps
CPU time 12.15 seconds
Started Jul 15 06:24:08 PM PDT 24
Finished Jul 15 06:24:21 PM PDT 24
Peak memory 233700 kb
Host smart-633876e8-9115-4c91-8f33-f4ac5d4e231c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409926780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3409926780
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3301270175
Short name T686
Test name
Test status
Simulation time 1207799242 ps
CPU time 3.06 seconds
Started Jul 15 06:24:13 PM PDT 24
Finished Jul 15 06:24:17 PM PDT 24
Peak memory 225460 kb
Host smart-037cfcae-698c-4a1d-96dc-c82b7906e2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301270175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3301270175
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.530510846
Short name T633
Test name
Test status
Simulation time 127253982 ps
CPU time 3.95 seconds
Started Jul 15 06:24:16 PM PDT 24
Finished Jul 15 06:24:20 PM PDT 24
Peak memory 224076 kb
Host smart-244e0f95-5d4a-497c-b72a-8bbeca365a56
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=530510846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.530510846
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2259004721
Short name T399
Test name
Test status
Simulation time 535592016 ps
CPU time 3.61 seconds
Started Jul 15 06:24:06 PM PDT 24
Finished Jul 15 06:24:10 PM PDT 24
Peak memory 217440 kb
Host smart-c2aa22b4-5812-4bbd-a1a5-4d4a590763c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259004721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2259004721
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.501587840
Short name T469
Test name
Test status
Simulation time 1454877133 ps
CPU time 9 seconds
Started Jul 15 06:24:20 PM PDT 24
Finished Jul 15 06:24:30 PM PDT 24
Peak memory 217340 kb
Host smart-98d1e9e9-b618-441a-b55e-66698caba066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501587840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.501587840
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1187084407
Short name T754
Test name
Test status
Simulation time 73729637 ps
CPU time 1.38 seconds
Started Jul 15 06:24:20 PM PDT 24
Finished Jul 15 06:24:21 PM PDT 24
Peak memory 209064 kb
Host smart-eb9457cd-ef3b-482e-9721-04e675792055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187084407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1187084407
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.206629550
Short name T427
Test name
Test status
Simulation time 1030145877 ps
CPU time 0.98 seconds
Started Jul 15 06:24:12 PM PDT 24
Finished Jul 15 06:24:14 PM PDT 24
Peak memory 207484 kb
Host smart-6b59f4d0-612b-4050-83b9-6630c0ca58c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206629550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.206629550
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1470317826
Short name T982
Test name
Test status
Simulation time 15424477465 ps
CPU time 15.89 seconds
Started Jul 15 06:24:13 PM PDT 24
Finished Jul 15 06:24:30 PM PDT 24
Peak memory 225624 kb
Host smart-bd24a973-382e-4dff-b9e9-1f2343c0c3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470317826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1470317826
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2074395627
Short name T501
Test name
Test status
Simulation time 13841658 ps
CPU time 0.68 seconds
Started Jul 15 06:24:23 PM PDT 24
Finished Jul 15 06:24:24 PM PDT 24
Peak memory 206760 kb
Host smart-303f288b-f67b-4541-89b9-8e8735da5bd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074395627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2074395627
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.411209378
Short name T503
Test name
Test status
Simulation time 1849703769 ps
CPU time 7.12 seconds
Started Jul 15 06:24:17 PM PDT 24
Finished Jul 15 06:24:24 PM PDT 24
Peak memory 225544 kb
Host smart-911dd413-fd56-4d5f-b8d6-dbb533de76dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411209378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.411209378
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3664075703
Short name T9
Test name
Test status
Simulation time 56988889 ps
CPU time 0.74 seconds
Started Jul 15 06:24:14 PM PDT 24
Finished Jul 15 06:24:15 PM PDT 24
Peak memory 206468 kb
Host smart-f339da10-d13f-4830-89d3-a3232db8eda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664075703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3664075703
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.877208637
Short name T240
Test name
Test status
Simulation time 2388910623 ps
CPU time 33.73 seconds
Started Jul 15 06:24:14 PM PDT 24
Finished Jul 15 06:24:49 PM PDT 24
Peak memory 257844 kb
Host smart-79e3be82-42cb-4719-a532-a79e88220159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877208637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.877208637
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.333876645
Short name T556
Test name
Test status
Simulation time 82754689794 ps
CPU time 326.35 seconds
Started Jul 15 06:24:24 PM PDT 24
Finished Jul 15 06:29:50 PM PDT 24
Peak memory 253656 kb
Host smart-475f3083-4623-49b4-9f86-89429b05f1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333876645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.333876645
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.189999649
Short name T516
Test name
Test status
Simulation time 478968234 ps
CPU time 4.38 seconds
Started Jul 15 06:24:17 PM PDT 24
Finished Jul 15 06:24:22 PM PDT 24
Peak memory 241964 kb
Host smart-f8f6e6cc-0c72-4d7a-86db-9521f7ebe1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189999649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.189999649
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.804893448
Short name T286
Test name
Test status
Simulation time 5270567012 ps
CPU time 43.02 seconds
Started Jul 15 06:24:15 PM PDT 24
Finished Jul 15 06:24:59 PM PDT 24
Peak memory 238132 kb
Host smart-8906d5ff-a73d-44ce-a39e-ff5e440163c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804893448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.804893448
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3598830942
Short name T932
Test name
Test status
Simulation time 718157538 ps
CPU time 5.12 seconds
Started Jul 15 06:24:15 PM PDT 24
Finished Jul 15 06:24:21 PM PDT 24
Peak memory 233652 kb
Host smart-d70adb56-11db-4552-bed7-d14ce6c04e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598830942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3598830942
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1607159379
Short name T60
Test name
Test status
Simulation time 3200773498 ps
CPU time 35.16 seconds
Started Jul 15 06:24:21 PM PDT 24
Finished Jul 15 06:24:57 PM PDT 24
Peak memory 233888 kb
Host smart-62432f86-6250-4579-a7c8-8c5d3ef77619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607159379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1607159379
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1058680173
Short name T722
Test name
Test status
Simulation time 15921445 ps
CPU time 1.03 seconds
Started Jul 15 06:24:14 PM PDT 24
Finished Jul 15 06:24:16 PM PDT 24
Peak memory 217652 kb
Host smart-a254a139-d617-40cd-be57-e715b6189986
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058680173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1058680173
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1159597821
Short name T694
Test name
Test status
Simulation time 4751673038 ps
CPU time 16.68 seconds
Started Jul 15 06:24:15 PM PDT 24
Finished Jul 15 06:24:32 PM PDT 24
Peak memory 250552 kb
Host smart-9634e109-5d86-42df-be36-7cae746d6074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159597821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1159597821
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1585071304
Short name T718
Test name
Test status
Simulation time 8907360781 ps
CPU time 8.29 seconds
Started Jul 15 06:24:16 PM PDT 24
Finished Jul 15 06:24:24 PM PDT 24
Peak memory 225720 kb
Host smart-ad07dbae-be11-4305-b6fc-bca1c493c6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585071304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1585071304
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.576768878
Short name T74
Test name
Test status
Simulation time 1707269913 ps
CPU time 4.27 seconds
Started Jul 15 06:24:14 PM PDT 24
Finished Jul 15 06:24:19 PM PDT 24
Peak memory 219840 kb
Host smart-0e0a842a-f439-4c4d-8c79-48c67c08a3a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=576768878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.576768878
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.472767632
Short name T966
Test name
Test status
Simulation time 4544633294 ps
CPU time 30.75 seconds
Started Jul 15 06:24:13 PM PDT 24
Finished Jul 15 06:24:45 PM PDT 24
Peak memory 217392 kb
Host smart-588608c6-f8a2-4dd9-b84f-ef24f521069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472767632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.472767632
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2244457609
Short name T868
Test name
Test status
Simulation time 1216382042 ps
CPU time 1.99 seconds
Started Jul 15 06:24:14 PM PDT 24
Finished Jul 15 06:24:17 PM PDT 24
Peak memory 217188 kb
Host smart-dbcff5a0-92d6-45cc-b1bb-16efcec38ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244457609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2244457609
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2389947647
Short name T592
Test name
Test status
Simulation time 176232338 ps
CPU time 7.62 seconds
Started Jul 15 06:24:21 PM PDT 24
Finished Jul 15 06:24:30 PM PDT 24
Peak memory 217308 kb
Host smart-9fe091e2-d30c-4430-a537-3df29acba26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389947647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2389947647
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1308020657
Short name T375
Test name
Test status
Simulation time 206562659 ps
CPU time 0.75 seconds
Started Jul 15 06:24:14 PM PDT 24
Finished Jul 15 06:24:16 PM PDT 24
Peak memory 206940 kb
Host smart-f5cb4632-c9b6-4dd0-800b-fcfac8553a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308020657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1308020657
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2926844651
Short name T635
Test name
Test status
Simulation time 22223204530 ps
CPU time 19.98 seconds
Started Jul 15 06:24:14 PM PDT 24
Finished Jul 15 06:24:35 PM PDT 24
Peak memory 241292 kb
Host smart-32b821e4-87f5-4607-b48e-8612bb58988e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926844651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2926844651
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3417648852
Short name T929
Test name
Test status
Simulation time 41103742 ps
CPU time 0.71 seconds
Started Jul 15 06:24:23 PM PDT 24
Finished Jul 15 06:24:24 PM PDT 24
Peak memory 205808 kb
Host smart-2c9ca51d-4973-445e-8985-a1eefc346d48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417648852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3417648852
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.910214327
Short name T566
Test name
Test status
Simulation time 712430432 ps
CPU time 5.33 seconds
Started Jul 15 06:24:26 PM PDT 24
Finished Jul 15 06:24:32 PM PDT 24
Peak memory 225432 kb
Host smart-185b0740-e39f-4a30-a7fd-dc4fd7084cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910214327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.910214327
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3549178074
Short name T1011
Test name
Test status
Simulation time 22153150 ps
CPU time 0.79 seconds
Started Jul 15 06:24:21 PM PDT 24
Finished Jul 15 06:24:22 PM PDT 24
Peak memory 207480 kb
Host smart-16b1d93b-5af4-414f-935e-a07c4763aa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549178074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3549178074
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1138343324
Short name T455
Test name
Test status
Simulation time 16005881835 ps
CPU time 111.24 seconds
Started Jul 15 06:24:26 PM PDT 24
Finished Jul 15 06:26:17 PM PDT 24
Peak memory 241380 kb
Host smart-2a907ef2-2866-45ef-bda5-8889eed90055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138343324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1138343324
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2862402009
Short name T723
Test name
Test status
Simulation time 5275882599 ps
CPU time 32.18 seconds
Started Jul 15 06:24:23 PM PDT 24
Finished Jul 15 06:24:57 PM PDT 24
Peak memory 238740 kb
Host smart-6f8ba42d-442a-40c7-82ae-8f3548c76daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862402009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2862402009
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.4166856590
Short name T751
Test name
Test status
Simulation time 5993431539 ps
CPU time 75.79 seconds
Started Jul 15 06:24:20 PM PDT 24
Finished Jul 15 06:25:36 PM PDT 24
Peak memory 255020 kb
Host smart-b1592a36-4815-4e61-bd02-9829a9d2ac4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166856590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.4166856590
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1013581472
Short name T1010
Test name
Test status
Simulation time 40491775506 ps
CPU time 279.48 seconds
Started Jul 15 06:24:22 PM PDT 24
Finished Jul 15 06:29:03 PM PDT 24
Peak memory 256556 kb
Host smart-c597e57e-286d-46c5-9acc-b8fdad279cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013581472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1013581472
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.890941707
Short name T478
Test name
Test status
Simulation time 4099389071 ps
CPU time 10.44 seconds
Started Jul 15 06:24:21 PM PDT 24
Finished Jul 15 06:24:32 PM PDT 24
Peak memory 225660 kb
Host smart-2e2b61e4-d8ce-437c-b038-016199043add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890941707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.890941707
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3526332844
Short name T721
Test name
Test status
Simulation time 20299009504 ps
CPU time 51.09 seconds
Started Jul 15 06:24:21 PM PDT 24
Finished Jul 15 06:25:12 PM PDT 24
Peak memory 233892 kb
Host smart-84f8e177-8377-4fa9-a1c9-de973a8c470f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526332844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3526332844
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2143768458
Short name T451
Test name
Test status
Simulation time 107180810 ps
CPU time 1.04 seconds
Started Jul 15 06:24:24 PM PDT 24
Finished Jul 15 06:24:26 PM PDT 24
Peak memory 217656 kb
Host smart-fb997f84-7f91-4704-9e07-e0baced9e6ca
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143768458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2143768458
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.330612445
Short name T526
Test name
Test status
Simulation time 1600207918 ps
CPU time 6.94 seconds
Started Jul 15 06:24:25 PM PDT 24
Finished Jul 15 06:24:33 PM PDT 24
Peak memory 233680 kb
Host smart-4b373597-3339-451f-9db2-e6174a7da8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330612445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.330612445
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1883168280
Short name T226
Test name
Test status
Simulation time 5011084301 ps
CPU time 8.32 seconds
Started Jul 15 06:24:23 PM PDT 24
Finished Jul 15 06:24:32 PM PDT 24
Peak memory 233836 kb
Host smart-7f57266a-ce5d-48ad-942c-bd58d0cdfc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883168280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1883168280
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.315014157
Short name T424
Test name
Test status
Simulation time 13372563442 ps
CPU time 18.73 seconds
Started Jul 15 06:24:21 PM PDT 24
Finished Jul 15 06:24:41 PM PDT 24
Peak memory 220692 kb
Host smart-043c4096-be40-4a8a-96ce-18dc2781c5d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=315014157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.315014157
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3677992915
Short name T491
Test name
Test status
Simulation time 135027212 ps
CPU time 0.89 seconds
Started Jul 15 06:24:22 PM PDT 24
Finished Jul 15 06:24:23 PM PDT 24
Peak memory 206524 kb
Host smart-b3b4db3b-ca11-4b76-b767-9c42603191ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677992915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3677992915
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.398388719
Short name T1022
Test name
Test status
Simulation time 23715135283 ps
CPU time 30.94 seconds
Started Jul 15 06:24:20 PM PDT 24
Finished Jul 15 06:24:52 PM PDT 24
Peak memory 217456 kb
Host smart-0913535a-758f-46c8-99ce-f86ae56a2230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398388719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.398388719
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.976893572
Short name T422
Test name
Test status
Simulation time 669376769 ps
CPU time 1.62 seconds
Started Jul 15 06:24:21 PM PDT 24
Finished Jul 15 06:24:23 PM PDT 24
Peak memory 208932 kb
Host smart-b41fad13-9436-4ca4-9272-76fddcb88367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976893572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.976893572
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.847585354
Short name T401
Test name
Test status
Simulation time 253626695 ps
CPU time 1.47 seconds
Started Jul 15 06:24:23 PM PDT 24
Finished Jul 15 06:24:25 PM PDT 24
Peak memory 217408 kb
Host smart-0c5536f1-55d6-4944-9e75-a22dbc9d4208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847585354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.847585354
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2480968765
Short name T1017
Test name
Test status
Simulation time 43670492 ps
CPU time 0.73 seconds
Started Jul 15 06:24:21 PM PDT 24
Finished Jul 15 06:24:23 PM PDT 24
Peak memory 206992 kb
Host smart-0754a968-bcb2-453e-bb37-d96bf366ce72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480968765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2480968765
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.4103866025
Short name T778
Test name
Test status
Simulation time 3026647000 ps
CPU time 6.09 seconds
Started Jul 15 06:24:22 PM PDT 24
Finished Jul 15 06:24:29 PM PDT 24
Peak memory 225584 kb
Host smart-95861618-1e74-411b-a22d-de5c19b29cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103866025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4103866025
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2686161520
Short name T1013
Test name
Test status
Simulation time 35358655 ps
CPU time 0.71 seconds
Started Jul 15 06:24:26 PM PDT 24
Finished Jul 15 06:24:28 PM PDT 24
Peak memory 205808 kb
Host smart-3e478dc1-84cf-4a7e-a1b2-7837f9970910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686161520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2686161520
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1889743950
Short name T254
Test name
Test status
Simulation time 6616381950 ps
CPU time 12.34 seconds
Started Jul 15 06:24:26 PM PDT 24
Finished Jul 15 06:24:39 PM PDT 24
Peak memory 233900 kb
Host smart-d91c4273-b043-4b7c-bf98-4130b6a355f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889743950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1889743950
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3421118835
Short name T938
Test name
Test status
Simulation time 46167254 ps
CPU time 0.76 seconds
Started Jul 15 06:24:22 PM PDT 24
Finished Jul 15 06:24:24 PM PDT 24
Peak memory 207800 kb
Host smart-916f34ff-87eb-4d05-91e4-bd1ad9283381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421118835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3421118835
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.915906135
Short name T815
Test name
Test status
Simulation time 875738627 ps
CPU time 8.78 seconds
Started Jul 15 06:24:30 PM PDT 24
Finished Jul 15 06:24:39 PM PDT 24
Peak memory 225560 kb
Host smart-38d4e56e-c098-4f17-b60e-dcdbb20716c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915906135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.915906135
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1827546155
Short name T187
Test name
Test status
Simulation time 8090804771 ps
CPU time 90.3 seconds
Started Jul 15 06:24:26 PM PDT 24
Finished Jul 15 06:25:57 PM PDT 24
Peak memory 254752 kb
Host smart-303a0518-6383-4707-948f-24afcd891460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827546155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1827546155
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2443217993
Short name T450
Test name
Test status
Simulation time 6730892939 ps
CPU time 26.97 seconds
Started Jul 15 06:24:28 PM PDT 24
Finished Jul 15 06:24:55 PM PDT 24
Peak memory 234032 kb
Host smart-2ffd932e-f349-424a-885a-d25a7ac447e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443217993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2443217993
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.773771728
Short name T970
Test name
Test status
Simulation time 2425445996 ps
CPU time 17.51 seconds
Started Jul 15 06:24:28 PM PDT 24
Finished Jul 15 06:24:46 PM PDT 24
Peak memory 233896 kb
Host smart-7fe0ac21-651e-4369-9a61-d7dfa4a2fe79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773771728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.773771728
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3483833237
Short name T688
Test name
Test status
Simulation time 9970037439 ps
CPU time 72.96 seconds
Started Jul 15 06:24:27 PM PDT 24
Finished Jul 15 06:25:41 PM PDT 24
Peak memory 251160 kb
Host smart-a9a4d17a-c9d0-4b84-bd2f-930fe99e29a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483833237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3483833237
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3456059712
Short name T64
Test name
Test status
Simulation time 2347841829 ps
CPU time 8.09 seconds
Started Jul 15 06:24:27 PM PDT 24
Finished Jul 15 06:24:36 PM PDT 24
Peak memory 225676 kb
Host smart-883c1384-4f85-42c9-a03f-802dcff0db00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456059712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3456059712
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2642555641
Short name T895
Test name
Test status
Simulation time 2632054415 ps
CPU time 14.26 seconds
Started Jul 15 06:24:28 PM PDT 24
Finished Jul 15 06:24:43 PM PDT 24
Peak memory 233924 kb
Host smart-1d4b6869-1706-407f-b7ac-9b55b91af0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642555641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2642555641
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1898898775
Short name T1027
Test name
Test status
Simulation time 64758928 ps
CPU time 1.05 seconds
Started Jul 15 06:24:24 PM PDT 24
Finished Jul 15 06:24:25 PM PDT 24
Peak memory 217768 kb
Host smart-3572f8c2-672a-4f7c-aa33-04e342949dc1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898898775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1898898775
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1536738144
Short name T264
Test name
Test status
Simulation time 367767921 ps
CPU time 3.05 seconds
Started Jul 15 06:24:28 PM PDT 24
Finished Jul 15 06:24:31 PM PDT 24
Peak memory 225388 kb
Host smart-cccec0f5-8fa0-45d0-a6d8-d35b50456044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536738144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1536738144
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2486772935
Short name T1009
Test name
Test status
Simulation time 4029709152 ps
CPU time 14.04 seconds
Started Jul 15 06:24:25 PM PDT 24
Finished Jul 15 06:24:39 PM PDT 24
Peak memory 233912 kb
Host smart-d75fff3b-ffca-4afa-bde6-7151cf081307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486772935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2486772935
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3562345456
Short name T775
Test name
Test status
Simulation time 153806621 ps
CPU time 4.45 seconds
Started Jul 15 06:24:26 PM PDT 24
Finished Jul 15 06:24:30 PM PDT 24
Peak memory 224068 kb
Host smart-f0f61180-90da-4f66-8a9c-7a3c6362e924
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3562345456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3562345456
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2403832272
Short name T299
Test name
Test status
Simulation time 3846631026 ps
CPU time 80.1 seconds
Started Jul 15 06:24:28 PM PDT 24
Finished Jul 15 06:25:48 PM PDT 24
Peak memory 256024 kb
Host smart-5d72bc7b-befa-4956-a515-f328037b4aec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403832272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2403832272
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2303630974
Short name T487
Test name
Test status
Simulation time 2857668003 ps
CPU time 8 seconds
Started Jul 15 06:24:27 PM PDT 24
Finished Jul 15 06:24:36 PM PDT 24
Peak memory 217420 kb
Host smart-9ca18792-fae9-430d-ba81-3cc342a48265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303630974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2303630974
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1641303898
Short name T484
Test name
Test status
Simulation time 643496823 ps
CPU time 1.85 seconds
Started Jul 15 06:24:27 PM PDT 24
Finished Jul 15 06:24:30 PM PDT 24
Peak memory 208872 kb
Host smart-b512bea9-97b3-4ec3-a28c-349e0a5858bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641303898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1641303898
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1852662626
Short name T107
Test name
Test status
Simulation time 781554396 ps
CPU time 1.65 seconds
Started Jul 15 06:24:27 PM PDT 24
Finished Jul 15 06:24:29 PM PDT 24
Peak memory 209184 kb
Host smart-c8aaeb4b-7a7f-4623-abf5-0b290c5aba34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852662626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1852662626
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3932815823
Short name T378
Test name
Test status
Simulation time 36302640 ps
CPU time 0.85 seconds
Started Jul 15 06:24:25 PM PDT 24
Finished Jul 15 06:24:26 PM PDT 24
Peak memory 208004 kb
Host smart-54af1771-8cfc-44c6-9779-6f2809734c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932815823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3932815823
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3100960143
Short name T72
Test name
Test status
Simulation time 1239032386 ps
CPU time 4.11 seconds
Started Jul 15 06:24:26 PM PDT 24
Finished Jul 15 06:24:31 PM PDT 24
Peak memory 225508 kb
Host smart-e634da02-8487-49f2-8167-6446b515bb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100960143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3100960143
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1844754918
Short name T80
Test name
Test status
Simulation time 44560424 ps
CPU time 0.69 seconds
Started Jul 15 06:24:39 PM PDT 24
Finished Jul 15 06:24:40 PM PDT 24
Peak memory 206356 kb
Host smart-b278b40a-43c4-406a-912a-60968bc600ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844754918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1844754918
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.615122612
Short name T802
Test name
Test status
Simulation time 1495203525 ps
CPU time 8.15 seconds
Started Jul 15 06:24:26 PM PDT 24
Finished Jul 15 06:24:35 PM PDT 24
Peak memory 233740 kb
Host smart-9b737303-d510-4120-9166-8bed7dbe0565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615122612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.615122612
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3481072533
Short name T770
Test name
Test status
Simulation time 81252719 ps
CPU time 0.8 seconds
Started Jul 15 06:24:30 PM PDT 24
Finished Jul 15 06:24:31 PM PDT 24
Peak memory 207496 kb
Host smart-f55418df-a817-4824-aadf-4dd1a7d601da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481072533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3481072533
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1889793297
Short name T301
Test name
Test status
Simulation time 16559458900 ps
CPU time 113.4 seconds
Started Jul 15 06:24:39 PM PDT 24
Finished Jul 15 06:26:33 PM PDT 24
Peak memory 242060 kb
Host smart-bd831dc7-edbb-43af-8e81-0f63ea83e402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889793297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1889793297
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3674950221
Short name T529
Test name
Test status
Simulation time 64586102752 ps
CPU time 95.19 seconds
Started Jul 15 06:24:44 PM PDT 24
Finished Jul 15 06:26:21 PM PDT 24
Peak memory 258536 kb
Host smart-d0d3fbcf-aba3-48a5-b8f1-c4d6af7a1a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674950221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3674950221
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.358492939
Short name T804
Test name
Test status
Simulation time 2745734641 ps
CPU time 19.62 seconds
Started Jul 15 06:24:42 PM PDT 24
Finished Jul 15 06:25:02 PM PDT 24
Peak memory 234004 kb
Host smart-d3da42a9-d560-4663-b630-7616a03d5d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358492939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.358492939
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1862642035
Short name T702
Test name
Test status
Simulation time 4502825324 ps
CPU time 14.31 seconds
Started Jul 15 06:24:39 PM PDT 24
Finished Jul 15 06:24:53 PM PDT 24
Peak memory 242100 kb
Host smart-50e05216-2891-4b03-b8d7-0702c38978ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862642035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1862642035
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2156205487
Short name T76
Test name
Test status
Simulation time 12517379452 ps
CPU time 90.28 seconds
Started Jul 15 06:24:40 PM PDT 24
Finished Jul 15 06:26:11 PM PDT 24
Peak memory 253040 kb
Host smart-57b2c389-3e39-4890-bff7-1b5acd28b650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156205487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2156205487
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3379761903
Short name T532
Test name
Test status
Simulation time 5928712744 ps
CPU time 13.14 seconds
Started Jul 15 06:24:27 PM PDT 24
Finished Jul 15 06:24:40 PM PDT 24
Peak memory 233808 kb
Host smart-f4b5f12a-e4e1-4299-a8fe-c7c16c6eb1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379761903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3379761903
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2463646197
Short name T580
Test name
Test status
Simulation time 70679662 ps
CPU time 2.11 seconds
Started Jul 15 06:24:28 PM PDT 24
Finished Jul 15 06:24:31 PM PDT 24
Peak memory 224960 kb
Host smart-6c8628c0-7543-47cf-b229-a422af92845a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463646197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2463646197
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.253027867
Short name T538
Test name
Test status
Simulation time 43090452 ps
CPU time 1.04 seconds
Started Jul 15 06:24:27 PM PDT 24
Finished Jul 15 06:24:29 PM PDT 24
Peak memory 217544 kb
Host smart-0d14b376-2821-454f-8e13-a16488a0b33f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253027867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.253027867
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.702959986
Short name T448
Test name
Test status
Simulation time 30100805 ps
CPU time 2.52 seconds
Started Jul 15 06:24:26 PM PDT 24
Finished Jul 15 06:24:29 PM PDT 24
Peak memory 233492 kb
Host smart-c25c0105-e0b8-40f0-869f-a774b03c0294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702959986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.702959986
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1356303308
Short name T976
Test name
Test status
Simulation time 162144688 ps
CPU time 4.14 seconds
Started Jul 15 06:24:27 PM PDT 24
Finished Jul 15 06:24:32 PM PDT 24
Peak memory 225548 kb
Host smart-129c2de5-2eb2-44cc-a0dc-c6112a546cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356303308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1356303308
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1930450652
Short name T163
Test name
Test status
Simulation time 5646931016 ps
CPU time 73.94 seconds
Started Jul 15 06:24:37 PM PDT 24
Finished Jul 15 06:25:52 PM PDT 24
Peak memory 250428 kb
Host smart-0a7fb893-b51a-4bd9-bfd7-fae782e93b71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930450652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1930450652
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.617115416
Short name T671
Test name
Test status
Simulation time 1711533592 ps
CPU time 22.91 seconds
Started Jul 15 06:24:27 PM PDT 24
Finished Jul 15 06:24:50 PM PDT 24
Peak memory 217312 kb
Host smart-0af9142b-cca2-4ab6-82e4-306a97ce84b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617115416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.617115416
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2666861731
Short name T390
Test name
Test status
Simulation time 19324490493 ps
CPU time 7.27 seconds
Started Jul 15 06:24:28 PM PDT 24
Finished Jul 15 06:24:36 PM PDT 24
Peak memory 217492 kb
Host smart-e5c82eb3-91d9-4966-b550-b09de7717eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666861731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2666861731
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3746160306
Short name T905
Test name
Test status
Simulation time 39225646 ps
CPU time 0.69 seconds
Started Jul 15 06:24:27 PM PDT 24
Finished Jul 15 06:24:29 PM PDT 24
Peak memory 206516 kb
Host smart-c2a86be5-1b96-4ff0-b2c4-8a9002ff7168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746160306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3746160306
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1889608481
Short name T535
Test name
Test status
Simulation time 46565833 ps
CPU time 0.84 seconds
Started Jul 15 06:24:29 PM PDT 24
Finished Jul 15 06:24:30 PM PDT 24
Peak memory 206956 kb
Host smart-29fca105-eb4e-456e-b7b7-b99fffe77874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889608481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1889608481
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3758690982
Short name T737
Test name
Test status
Simulation time 11102542795 ps
CPU time 14.6 seconds
Started Jul 15 06:24:26 PM PDT 24
Finished Jul 15 06:24:42 PM PDT 24
Peak memory 241880 kb
Host smart-69e32b4c-a9aa-4206-88f4-470564d54dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758690982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3758690982
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.144684813
Short name T632
Test name
Test status
Simulation time 80461346 ps
CPU time 0.74 seconds
Started Jul 15 06:24:40 PM PDT 24
Finished Jul 15 06:24:41 PM PDT 24
Peak memory 206712 kb
Host smart-d2f859c0-4a2b-49b0-8cd4-4257940aae41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144684813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.144684813
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3021344312
Short name T696
Test name
Test status
Simulation time 2754057660 ps
CPU time 9.84 seconds
Started Jul 15 06:24:44 PM PDT 24
Finished Jul 15 06:24:55 PM PDT 24
Peak memory 225624 kb
Host smart-439356be-de81-46a2-bed8-0fafcf80db48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021344312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3021344312
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1832934119
Short name T137
Test name
Test status
Simulation time 102911657 ps
CPU time 0.76 seconds
Started Jul 15 06:24:44 PM PDT 24
Finished Jul 15 06:24:46 PM PDT 24
Peak memory 206452 kb
Host smart-117738ab-ade6-4e9a-8d01-cfc743d6c250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832934119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1832934119
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.656211574
Short name T213
Test name
Test status
Simulation time 21336577523 ps
CPU time 144.88 seconds
Started Jul 15 06:24:45 PM PDT 24
Finished Jul 15 06:27:12 PM PDT 24
Peak memory 268168 kb
Host smart-ec880f94-d649-4b25-85d1-b796e2c72850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656211574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.656211574
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.4112375936
Short name T923
Test name
Test status
Simulation time 39189652493 ps
CPU time 166.79 seconds
Started Jul 15 06:24:49 PM PDT 24
Finished Jul 15 06:27:37 PM PDT 24
Peak memory 251412 kb
Host smart-f2897cfb-ec36-4f53-badd-d874228cc8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112375936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.4112375936
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2818779268
Short name T835
Test name
Test status
Simulation time 17713235958 ps
CPU time 84.54 seconds
Started Jul 15 06:24:37 PM PDT 24
Finished Jul 15 06:26:02 PM PDT 24
Peak memory 266508 kb
Host smart-2cf12f51-5bc7-418e-9197-d00f36d81bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818779268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2818779268
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3691408166
Short name T333
Test name
Test status
Simulation time 225267965 ps
CPU time 4.94 seconds
Started Jul 15 06:24:43 PM PDT 24
Finished Jul 15 06:24:49 PM PDT 24
Peak memory 235772 kb
Host smart-1f961331-182f-47e6-808a-4c4d8d4e5c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691408166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3691408166
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.4222011289
Short name T792
Test name
Test status
Simulation time 4510205250 ps
CPU time 15.22 seconds
Started Jul 15 06:24:49 PM PDT 24
Finished Jul 15 06:25:05 PM PDT 24
Peak memory 225656 kb
Host smart-7ee307db-66e9-41cd-82d6-cb8e35d19fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222011289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.4222011289
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1750117375
Short name T781
Test name
Test status
Simulation time 156970868 ps
CPU time 4.45 seconds
Started Jul 15 06:24:42 PM PDT 24
Finished Jul 15 06:24:46 PM PDT 24
Peak memory 233784 kb
Host smart-d85b8e3e-f217-44e3-ac02-e189be0ad787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750117375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1750117375
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2266616699
Short name T861
Test name
Test status
Simulation time 2299364753 ps
CPU time 10.1 seconds
Started Jul 15 06:24:42 PM PDT 24
Finished Jul 15 06:24:53 PM PDT 24
Peak memory 225648 kb
Host smart-c8a67b05-8b05-4cf2-808e-7734df9f41d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266616699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2266616699
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2504141635
Short name T449
Test name
Test status
Simulation time 17802165 ps
CPU time 1.07 seconds
Started Jul 15 06:24:40 PM PDT 24
Finished Jul 15 06:24:41 PM PDT 24
Peak memory 217620 kb
Host smart-f82058a0-6d20-4127-adbb-a08a6c263320
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504141635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2504141635
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.640940063
Short name T647
Test name
Test status
Simulation time 51025252 ps
CPU time 2.45 seconds
Started Jul 15 06:24:43 PM PDT 24
Finished Jul 15 06:24:46 PM PDT 24
Peak memory 233584 kb
Host smart-cc43c479-91f8-48bf-b827-e09b03d94ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640940063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.640940063
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.262173656
Short name T549
Test name
Test status
Simulation time 8831911883 ps
CPU time 25.57 seconds
Started Jul 15 06:24:42 PM PDT 24
Finished Jul 15 06:25:09 PM PDT 24
Peak memory 242068 kb
Host smart-2b9b134c-342e-4006-aefe-79a7305ae56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262173656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.262173656
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.346419101
Short name T904
Test name
Test status
Simulation time 528065453 ps
CPU time 5.63 seconds
Started Jul 15 06:24:42 PM PDT 24
Finished Jul 15 06:24:48 PM PDT 24
Peak memory 219708 kb
Host smart-7b8b1f02-bef1-427f-ad9f-68187c0120e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=346419101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.346419101
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2486928638
Short name T57
Test name
Test status
Simulation time 8216665030 ps
CPU time 54.3 seconds
Started Jul 15 06:24:42 PM PDT 24
Finished Jul 15 06:25:37 PM PDT 24
Peak memory 225808 kb
Host smart-20e4f640-c657-420f-891d-5e0231bbf787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486928638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2486928638
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2216667124
Short name T687
Test name
Test status
Simulation time 975062384 ps
CPU time 12.12 seconds
Started Jul 15 06:24:49 PM PDT 24
Finished Jul 15 06:25:02 PM PDT 24
Peak memory 217380 kb
Host smart-c39065ee-2338-48a1-814b-9bdd2d40a8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216667124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2216667124
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3530541714
Short name T720
Test name
Test status
Simulation time 11943852 ps
CPU time 0.72 seconds
Started Jul 15 06:24:41 PM PDT 24
Finished Jul 15 06:24:42 PM PDT 24
Peak memory 206624 kb
Host smart-c442e8d0-7ef7-45c4-abc5-7e6e259c4f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530541714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3530541714
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2097800722
Short name T476
Test name
Test status
Simulation time 98375127 ps
CPU time 1.15 seconds
Started Jul 15 06:24:38 PM PDT 24
Finished Jul 15 06:24:39 PM PDT 24
Peak memory 208940 kb
Host smart-c8ecf605-24d0-42f1-aa41-f3e4201e0e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097800722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2097800722
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1372973743
Short name T979
Test name
Test status
Simulation time 56732559 ps
CPU time 0.8 seconds
Started Jul 15 06:24:42 PM PDT 24
Finished Jul 15 06:24:43 PM PDT 24
Peak memory 207916 kb
Host smart-4b5681cb-9330-4518-a7e8-8a8f72074f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372973743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1372973743
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1707306427
Short name T761
Test name
Test status
Simulation time 4699654001 ps
CPU time 12.94 seconds
Started Jul 15 06:24:46 PM PDT 24
Finished Jul 15 06:25:01 PM PDT 24
Peak memory 233900 kb
Host smart-29b4172f-2d88-489b-b985-4d270dd771b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707306427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1707306427
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2975137448
Short name T846
Test name
Test status
Simulation time 12541122 ps
CPU time 0.71 seconds
Started Jul 15 06:24:48 PM PDT 24
Finished Jul 15 06:24:49 PM PDT 24
Peak memory 206336 kb
Host smart-f0261596-3566-434b-bcd7-a44a38d57fe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975137448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2975137448
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1798423220
Short name T628
Test name
Test status
Simulation time 78162785 ps
CPU time 3.1 seconds
Started Jul 15 06:24:46 PM PDT 24
Finished Jul 15 06:24:50 PM PDT 24
Peak memory 233736 kb
Host smart-83f8b04b-d8cd-4717-87b0-ceefc2f1572d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798423220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1798423220
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3461032452
Short name T1004
Test name
Test status
Simulation time 19481929 ps
CPU time 0.8 seconds
Started Jul 15 06:24:42 PM PDT 24
Finished Jul 15 06:24:44 PM PDT 24
Peak memory 207536 kb
Host smart-7eefd324-70d8-40a6-a481-e14ebec55a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461032452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3461032452
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3143897066
Short name T244
Test name
Test status
Simulation time 2890118125 ps
CPU time 21.28 seconds
Started Jul 15 06:24:45 PM PDT 24
Finished Jul 15 06:25:07 PM PDT 24
Peak memory 234360 kb
Host smart-dc8d5948-540a-4642-9afd-4be93756ddbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143897066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3143897066
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.808797163
Short name T290
Test name
Test status
Simulation time 18092457127 ps
CPU time 227.22 seconds
Started Jul 15 06:24:46 PM PDT 24
Finished Jul 15 06:28:35 PM PDT 24
Peak memory 274948 kb
Host smart-21948654-d975-4b98-93ea-4cfaa338728f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808797163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.808797163
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.649092414
Short name T82
Test name
Test status
Simulation time 9973704995 ps
CPU time 104.33 seconds
Started Jul 15 06:24:47 PM PDT 24
Finished Jul 15 06:26:32 PM PDT 24
Peak memory 266860 kb
Host smart-95eb612e-28e1-48c2-9b74-b2270663a34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649092414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.649092414
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2272882400
Short name T746
Test name
Test status
Simulation time 2377414120 ps
CPU time 35.89 seconds
Started Jul 15 06:24:45 PM PDT 24
Finished Jul 15 06:25:22 PM PDT 24
Peak memory 233880 kb
Host smart-c4fe7935-c2b2-4e73-a22d-e060cb9866c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272882400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2272882400
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2280811946
Short name T265
Test name
Test status
Simulation time 3941500042 ps
CPU time 48.59 seconds
Started Jul 15 06:24:45 PM PDT 24
Finished Jul 15 06:25:35 PM PDT 24
Peak memory 251716 kb
Host smart-120d1ff3-ffcc-4919-874f-92b8b04c3005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280811946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2280811946
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1795188933
Short name T139
Test name
Test status
Simulation time 8975256359 ps
CPU time 24.69 seconds
Started Jul 15 06:24:47 PM PDT 24
Finished Jul 15 06:25:13 PM PDT 24
Peak memory 225708 kb
Host smart-1fd92017-5f33-4a00-8e0a-866eac4fa4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795188933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1795188933
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.4259704162
Short name T480
Test name
Test status
Simulation time 768658466 ps
CPU time 16.93 seconds
Started Jul 15 06:24:46 PM PDT 24
Finished Jul 15 06:25:04 PM PDT 24
Peak memory 233736 kb
Host smart-c18269e7-7970-4cae-a0ac-a28b0e625cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259704162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.4259704162
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.4178654389
Short name T926
Test name
Test status
Simulation time 15021792 ps
CPU time 1.01 seconds
Started Jul 15 06:24:44 PM PDT 24
Finished Jul 15 06:24:46 PM PDT 24
Peak memory 217604 kb
Host smart-73e3d477-f099-4cc3-9c1d-eaf6d81585b8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178654389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.4178654389
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2508570311
Short name T660
Test name
Test status
Simulation time 495703156 ps
CPU time 4.29 seconds
Started Jul 15 06:24:48 PM PDT 24
Finished Jul 15 06:24:53 PM PDT 24
Peak memory 225392 kb
Host smart-599ddd4f-4f64-4283-adee-3c4f0a67185d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508570311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2508570311
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2628625760
Short name T485
Test name
Test status
Simulation time 573602568 ps
CPU time 6.12 seconds
Started Jul 15 06:24:46 PM PDT 24
Finished Jul 15 06:24:54 PM PDT 24
Peak memory 225596 kb
Host smart-d9261fa4-32bd-42be-94f0-632b2a0c8003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628625760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2628625760
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4095584984
Short name T1015
Test name
Test status
Simulation time 1001677792 ps
CPU time 7.97 seconds
Started Jul 15 06:24:43 PM PDT 24
Finished Jul 15 06:24:52 PM PDT 24
Peak memory 222596 kb
Host smart-c60cb050-819c-45ae-a098-dcbe92810d84
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4095584984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4095584984
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3646569648
Short name T53
Test name
Test status
Simulation time 9632541854 ps
CPU time 64.18 seconds
Started Jul 15 06:24:48 PM PDT 24
Finished Jul 15 06:25:53 PM PDT 24
Peak memory 250356 kb
Host smart-57fe1e34-9939-4b33-bdb8-15dc98e3c494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646569648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3646569648
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3528572968
Short name T321
Test name
Test status
Simulation time 29060708634 ps
CPU time 29.91 seconds
Started Jul 15 06:24:43 PM PDT 24
Finished Jul 15 06:25:13 PM PDT 24
Peak memory 221216 kb
Host smart-749741d7-0340-4a72-9028-d616a67508aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528572968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3528572968
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2870209424
Short name T537
Test name
Test status
Simulation time 8605238926 ps
CPU time 7.79 seconds
Started Jul 15 06:24:44 PM PDT 24
Finished Jul 15 06:24:52 PM PDT 24
Peak memory 217428 kb
Host smart-ea01bbcf-b9bc-450d-aa27-ee8395b39656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870209424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2870209424
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3491856960
Short name T1018
Test name
Test status
Simulation time 388513373 ps
CPU time 3.56 seconds
Started Jul 15 06:24:46 PM PDT 24
Finished Jul 15 06:24:51 PM PDT 24
Peak memory 217352 kb
Host smart-626b0b1e-5e67-4e02-9a5f-f433cd1a99b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491856960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3491856960
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.387639778
Short name T348
Test name
Test status
Simulation time 29932000 ps
CPU time 0.82 seconds
Started Jul 15 06:24:46 PM PDT 24
Finished Jul 15 06:24:49 PM PDT 24
Peak memory 207224 kb
Host smart-1abb3df4-9594-4182-9db7-c7c77ee23391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387639778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.387639778
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2331899634
Short name T1005
Test name
Test status
Simulation time 476824494 ps
CPU time 3.44 seconds
Started Jul 15 06:24:46 PM PDT 24
Finished Jul 15 06:24:51 PM PDT 24
Peak memory 225576 kb
Host smart-5c73af22-06c7-4c36-b25d-bf2446062017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331899634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2331899634
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.166025185
Short name T821
Test name
Test status
Simulation time 70622364 ps
CPU time 0.75 seconds
Started Jul 15 06:23:30 PM PDT 24
Finished Jul 15 06:23:32 PM PDT 24
Peak memory 206332 kb
Host smart-0a0a5ee2-8a2c-4ffa-b8ea-6a780658e06f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166025185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.166025185
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2028090164
Short name T620
Test name
Test status
Simulation time 991048607 ps
CPU time 3.7 seconds
Started Jul 15 06:23:23 PM PDT 24
Finished Jul 15 06:23:28 PM PDT 24
Peak memory 225516 kb
Host smart-0443fa67-6dea-4b88-8767-0feb62a9e326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028090164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2028090164
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1358772265
Short name T599
Test name
Test status
Simulation time 137297074 ps
CPU time 0.76 seconds
Started Jul 15 06:23:22 PM PDT 24
Finished Jul 15 06:23:23 PM PDT 24
Peak memory 207476 kb
Host smart-c341924f-3b56-462d-b7d8-65302b1d9de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358772265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1358772265
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3055610856
Short name T260
Test name
Test status
Simulation time 68605228636 ps
CPU time 259.89 seconds
Started Jul 15 06:23:29 PM PDT 24
Finished Jul 15 06:27:49 PM PDT 24
Peak memory 257844 kb
Host smart-5376f9fd-c649-4d1d-8c24-95ea8dcacdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055610856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3055610856
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.660608955
Short name T1007
Test name
Test status
Simulation time 67910378928 ps
CPU time 658.15 seconds
Started Jul 15 06:23:33 PM PDT 24
Finished Jul 15 06:34:31 PM PDT 24
Peak memory 272792 kb
Host smart-e4cbc066-1e94-4f6d-803f-e6d69a621d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660608955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.660608955
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.4250774234
Short name T906
Test name
Test status
Simulation time 22398927541 ps
CPU time 84.34 seconds
Started Jul 15 06:23:32 PM PDT 24
Finished Jul 15 06:24:57 PM PDT 24
Peak memory 255732 kb
Host smart-e71e811e-f786-4e70-aa55-01d33d24b68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250774234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.4250774234
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.307356984
Short name T314
Test name
Test status
Simulation time 5643993163 ps
CPU time 16.3 seconds
Started Jul 15 06:23:29 PM PDT 24
Finished Jul 15 06:23:46 PM PDT 24
Peak memory 235104 kb
Host smart-53fbdc94-194f-4a09-885b-56caecdf810d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307356984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.307356984
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1172927811
Short name T175
Test name
Test status
Simulation time 3009298870 ps
CPU time 33.03 seconds
Started Jul 15 06:23:31 PM PDT 24
Finished Jul 15 06:24:05 PM PDT 24
Peak memory 251232 kb
Host smart-2327f84f-047f-4fef-b923-ef7986ec10e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172927811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1172927811
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3321522750
Short name T134
Test name
Test status
Simulation time 1871328139 ps
CPU time 18.72 seconds
Started Jul 15 06:23:21 PM PDT 24
Finished Jul 15 06:23:41 PM PDT 24
Peak memory 219888 kb
Host smart-9a63d0a8-a374-4615-a011-01ff543d02cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321522750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3321522750
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2653461940
Short name T1001
Test name
Test status
Simulation time 102874542 ps
CPU time 2.09 seconds
Started Jul 15 06:23:22 PM PDT 24
Finished Jul 15 06:23:25 PM PDT 24
Peak memory 225012 kb
Host smart-343601a3-5eef-4435-b400-e83f131eac1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653461940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2653461940
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2027848568
Short name T839
Test name
Test status
Simulation time 50333409 ps
CPU time 1.11 seconds
Started Jul 15 06:23:26 PM PDT 24
Finished Jul 15 06:23:27 PM PDT 24
Peak memory 217612 kb
Host smart-c36ea637-e8ae-4831-911f-837a40567188
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027848568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2027848568
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.331216448
Short name T46
Test name
Test status
Simulation time 8478037850 ps
CPU time 13.85 seconds
Started Jul 15 06:23:22 PM PDT 24
Finished Jul 15 06:23:38 PM PDT 24
Peak memory 233800 kb
Host smart-0adf1058-75c5-4fcb-b7b1-5760ee729ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331216448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
331216448
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2702828840
Short name T239
Test name
Test status
Simulation time 2419391945 ps
CPU time 7.92 seconds
Started Jul 15 06:23:23 PM PDT 24
Finished Jul 15 06:23:32 PM PDT 24
Peak memory 233832 kb
Host smart-eee477ff-3998-4329-9197-4ef324ccc8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702828840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2702828840
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.4078365396
Short name T725
Test name
Test status
Simulation time 860021657 ps
CPU time 4.71 seconds
Started Jul 15 06:23:30 PM PDT 24
Finished Jul 15 06:23:35 PM PDT 24
Peak memory 224220 kb
Host smart-629be97b-acdc-43a1-b94f-24ae864e4b27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4078365396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.4078365396
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3430404773
Short name T70
Test name
Test status
Simulation time 323876741 ps
CPU time 1.13 seconds
Started Jul 15 06:23:29 PM PDT 24
Finished Jul 15 06:23:31 PM PDT 24
Peak memory 236388 kb
Host smart-bbcf4d35-e722-4ea6-981a-426b9b350ce9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430404773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3430404773
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1247183550
Short name T965
Test name
Test status
Simulation time 256950673 ps
CPU time 1.02 seconds
Started Jul 15 06:23:31 PM PDT 24
Finished Jul 15 06:23:33 PM PDT 24
Peak memory 208448 kb
Host smart-c285bcc6-2e54-426c-b309-1bb4f5cbe0f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247183550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1247183550
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1306273264
Short name T486
Test name
Test status
Simulation time 1798387801 ps
CPU time 11.02 seconds
Started Jul 15 06:23:22 PM PDT 24
Finished Jul 15 06:23:35 PM PDT 24
Peak memory 217368 kb
Host smart-6ea0ebb9-b83b-4a9e-b5f5-27603be782c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306273264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1306273264
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.84671271
Short name T664
Test name
Test status
Simulation time 21690307003 ps
CPU time 10.74 seconds
Started Jul 15 06:23:24 PM PDT 24
Finished Jul 15 06:23:36 PM PDT 24
Peak memory 217480 kb
Host smart-d23ba926-34a6-48fa-9a9b-7e6fd160606b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84671271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.84671271
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3266720649
Short name T897
Test name
Test status
Simulation time 53869306 ps
CPU time 1.03 seconds
Started Jul 15 06:23:22 PM PDT 24
Finished Jul 15 06:23:25 PM PDT 24
Peak memory 208544 kb
Host smart-90008412-6ab8-4cff-acc2-443bfe4d0c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266720649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3266720649
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1264384674
Short name T649
Test name
Test status
Simulation time 209344959 ps
CPU time 0.76 seconds
Started Jul 15 06:23:22 PM PDT 24
Finished Jul 15 06:23:24 PM PDT 24
Peak memory 206992 kb
Host smart-3a933567-4516-437b-827e-5e126a244357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264384674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1264384674
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.828060393
Short name T678
Test name
Test status
Simulation time 3122209649 ps
CPU time 7.21 seconds
Started Jul 15 06:23:23 PM PDT 24
Finished Jul 15 06:23:32 PM PDT 24
Peak memory 225588 kb
Host smart-0e78d4e9-0cdd-4752-9414-31f73351773a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828060393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.828060393
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3368068491
Short name T330
Test name
Test status
Simulation time 34992985 ps
CPU time 0.76 seconds
Started Jul 15 06:24:55 PM PDT 24
Finished Jul 15 06:24:56 PM PDT 24
Peak memory 206352 kb
Host smart-eafd71d6-33cb-4d15-a395-cb06e4b181b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368068491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3368068491
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1982314670
Short name T776
Test name
Test status
Simulation time 94726242 ps
CPU time 3.1 seconds
Started Jul 15 06:24:44 PM PDT 24
Finished Jul 15 06:24:48 PM PDT 24
Peak memory 233732 kb
Host smart-d2486981-5550-4444-9bde-9973005c4bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982314670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1982314670
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3067216289
Short name T552
Test name
Test status
Simulation time 14158015 ps
CPU time 0.75 seconds
Started Jul 15 06:24:43 PM PDT 24
Finished Jul 15 06:24:44 PM PDT 24
Peak memory 207756 kb
Host smart-2fbbff94-07a0-4513-ad14-b03aabfe5a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067216289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3067216289
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.268904767
Short name T472
Test name
Test status
Simulation time 7450093690 ps
CPU time 27.76 seconds
Started Jul 15 06:24:46 PM PDT 24
Finished Jul 15 06:25:15 PM PDT 24
Peak memory 241120 kb
Host smart-e1e5ef2c-b9ba-4623-bcf6-d03bdb2752b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268904767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.268904767
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2819850036
Short name T876
Test name
Test status
Simulation time 2586462777 ps
CPU time 13.21 seconds
Started Jul 15 06:24:47 PM PDT 24
Finished Jul 15 06:25:02 PM PDT 24
Peak memory 218848 kb
Host smart-f5bfb0e3-8354-4650-8fd1-9838df477302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819850036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2819850036
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2636122393
Short name T734
Test name
Test status
Simulation time 49726517711 ps
CPU time 476.31 seconds
Started Jul 15 06:24:45 PM PDT 24
Finished Jul 15 06:32:43 PM PDT 24
Peak memory 260368 kb
Host smart-0d7917a9-3361-4e4d-8101-c2d5dabffc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636122393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2636122393
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1163614667
Short name T834
Test name
Test status
Simulation time 2768493097 ps
CPU time 42.8 seconds
Started Jul 15 06:24:46 PM PDT 24
Finished Jul 15 06:25:30 PM PDT 24
Peak memory 251716 kb
Host smart-4b933012-d820-466a-bac7-4d1b0c165b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163614667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1163614667
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.927988018
Short name T393
Test name
Test status
Simulation time 283109430 ps
CPU time 8.24 seconds
Started Jul 15 06:24:48 PM PDT 24
Finished Jul 15 06:24:57 PM PDT 24
Peak memory 241980 kb
Host smart-c4e0d83c-2250-49b9-84cf-96936e1146c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927988018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.927988018
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2948080082
Short name T59
Test name
Test status
Simulation time 144173861 ps
CPU time 2.25 seconds
Started Jul 15 06:24:45 PM PDT 24
Finished Jul 15 06:24:49 PM PDT 24
Peak memory 224824 kb
Host smart-bd741c4f-d690-4313-9cc6-b8a765967d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948080082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2948080082
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.478703966
Short name T550
Test name
Test status
Simulation time 2458294333 ps
CPU time 22.66 seconds
Started Jul 15 06:24:46 PM PDT 24
Finished Jul 15 06:25:10 PM PDT 24
Peak memory 233832 kb
Host smart-fe769200-f42a-44d7-ba5a-45b8f916a1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478703966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.478703966
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.127392036
Short name T209
Test name
Test status
Simulation time 4070786556 ps
CPU time 3.88 seconds
Started Jul 15 06:24:46 PM PDT 24
Finished Jul 15 06:24:51 PM PDT 24
Peak memory 225680 kb
Host smart-39665e4d-842f-4ce4-aaca-4e029ee75e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127392036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.127392036
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.4208086161
Short name T913
Test name
Test status
Simulation time 3749026114 ps
CPU time 7.77 seconds
Started Jul 15 06:24:47 PM PDT 24
Finished Jul 15 06:24:56 PM PDT 24
Peak memory 233880 kb
Host smart-bc49a979-56c4-4813-9f37-6b800868fcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208086161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.4208086161
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3165968626
Short name T810
Test name
Test status
Simulation time 2241136187 ps
CPU time 9.16 seconds
Started Jul 15 06:24:49 PM PDT 24
Finished Jul 15 06:24:59 PM PDT 24
Peak memory 223176 kb
Host smart-f136468d-1e50-4ad0-b916-66bedf507968
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3165968626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3165968626
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.927641848
Short name T164
Test name
Test status
Simulation time 34344057370 ps
CPU time 221.01 seconds
Started Jul 15 06:24:49 PM PDT 24
Finished Jul 15 06:28:31 PM PDT 24
Peak memory 258580 kb
Host smart-c5ef8355-0c59-49ec-af6b-16152ee562ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927641848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.927641848
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3843033847
Short name T141
Test name
Test status
Simulation time 2758842232 ps
CPU time 24.64 seconds
Started Jul 15 06:24:45 PM PDT 24
Finished Jul 15 06:25:10 PM PDT 24
Peak memory 217488 kb
Host smart-31eddc17-61a5-4daf-a8fb-791569526f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843033847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3843033847
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1405053405
Short name T415
Test name
Test status
Simulation time 699099590 ps
CPU time 4.16 seconds
Started Jul 15 06:24:45 PM PDT 24
Finished Jul 15 06:24:50 PM PDT 24
Peak memory 217192 kb
Host smart-e703c991-4b78-4cb8-b97d-0ce176c74847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405053405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1405053405
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1574347998
Short name T522
Test name
Test status
Simulation time 74784992 ps
CPU time 2.86 seconds
Started Jul 15 06:24:44 PM PDT 24
Finished Jul 15 06:24:47 PM PDT 24
Peak memory 217348 kb
Host smart-7217717e-2425-4664-84e9-1d12f8359f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574347998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1574347998
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2962019836
Short name T951
Test name
Test status
Simulation time 93205540 ps
CPU time 0.82 seconds
Started Jul 15 06:24:45 PM PDT 24
Finished Jul 15 06:24:47 PM PDT 24
Peak memory 206860 kb
Host smart-d1d0bfe3-23ba-4417-836e-bd4dd475ed47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962019836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2962019836
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3435103561
Short name T593
Test name
Test status
Simulation time 3184120380 ps
CPU time 15.28 seconds
Started Jul 15 06:24:44 PM PDT 24
Finished Jul 15 06:25:01 PM PDT 24
Peak memory 225688 kb
Host smart-9d0b52ff-da02-44ac-bbf0-ce5ed77a8240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435103561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3435103561
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2881502894
Short name T496
Test name
Test status
Simulation time 29812759 ps
CPU time 0.73 seconds
Started Jul 15 06:24:54 PM PDT 24
Finished Jul 15 06:24:55 PM PDT 24
Peak memory 206292 kb
Host smart-ea30595a-be9b-4942-ae3f-898054b7bcdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881502894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2881502894
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3367980034
Short name T447
Test name
Test status
Simulation time 178067281 ps
CPU time 2.12 seconds
Started Jul 15 06:24:57 PM PDT 24
Finished Jul 15 06:25:00 PM PDT 24
Peak memory 225456 kb
Host smart-2bd1a600-538c-4cf2-a60f-a8932dbc36e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367980034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3367980034
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.715029288
Short name T766
Test name
Test status
Simulation time 24161209 ps
CPU time 0.81 seconds
Started Jul 15 06:24:50 PM PDT 24
Finished Jul 15 06:24:52 PM PDT 24
Peak memory 207816 kb
Host smart-37011600-352c-4dc9-ac01-44460e017719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715029288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.715029288
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3084054019
Short name T738
Test name
Test status
Simulation time 2511818796 ps
CPU time 58.7 seconds
Started Jul 15 06:24:51 PM PDT 24
Finished Jul 15 06:25:50 PM PDT 24
Peak memory 256320 kb
Host smart-84636d1e-8f4c-48b6-88ad-19672791a495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084054019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3084054019
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3313855508
Short name T685
Test name
Test status
Simulation time 1400972407 ps
CPU time 14.51 seconds
Started Jul 15 06:24:53 PM PDT 24
Finished Jul 15 06:25:08 PM PDT 24
Peak memory 238656 kb
Host smart-fa846a34-c14c-4a2c-bcc3-002b1d0c8453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313855508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3313855508
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.869554788
Short name T935
Test name
Test status
Simulation time 26280462161 ps
CPU time 52.2 seconds
Started Jul 15 06:24:49 PM PDT 24
Finished Jul 15 06:25:43 PM PDT 24
Peak memory 240768 kb
Host smart-fa0f4b21-41cc-42e5-ae59-b234fe0d2648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869554788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.869554788
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3054725153
Short name T918
Test name
Test status
Simulation time 234113457 ps
CPU time 9.43 seconds
Started Jul 15 06:24:53 PM PDT 24
Finished Jul 15 06:25:04 PM PDT 24
Peak memory 241788 kb
Host smart-5188f02a-6014-4009-9b86-6533e408dbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054725153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3054725153
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3195167920
Short name T741
Test name
Test status
Simulation time 11534062192 ps
CPU time 20.82 seconds
Started Jul 15 06:24:51 PM PDT 24
Finished Jul 15 06:25:13 PM PDT 24
Peak memory 235764 kb
Host smart-3efe186e-6490-45eb-8f0e-6626d0e827a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195167920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3195167920
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2604348252
Short name T206
Test name
Test status
Simulation time 1701313912 ps
CPU time 4.61 seconds
Started Jul 15 06:24:52 PM PDT 24
Finished Jul 15 06:24:57 PM PDT 24
Peak memory 225480 kb
Host smart-10bb203e-fdcb-4718-981c-f26f7a3a4d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604348252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2604348252
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2282657225
Short name T227
Test name
Test status
Simulation time 6336353229 ps
CPU time 39.99 seconds
Started Jul 15 06:24:50 PM PDT 24
Finished Jul 15 06:25:31 PM PDT 24
Peak memory 225684 kb
Host smart-c5c27be1-6cf7-4043-b91e-b53900c22b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282657225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2282657225
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1414674923
Short name T975
Test name
Test status
Simulation time 37509520391 ps
CPU time 25.1 seconds
Started Jul 15 06:24:48 PM PDT 24
Finished Jul 15 06:25:14 PM PDT 24
Peak memory 225644 kb
Host smart-aca0430d-538a-4afc-b5a3-36a5d3528bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414674923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1414674923
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.403650277
Short name T466
Test name
Test status
Simulation time 9687798045 ps
CPU time 13.47 seconds
Started Jul 15 06:24:52 PM PDT 24
Finished Jul 15 06:25:06 PM PDT 24
Peak memory 225688 kb
Host smart-45f54d73-79b2-46a6-a434-bef5971937bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403650277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.403650277
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.55737008
Short name T454
Test name
Test status
Simulation time 1009651089 ps
CPU time 13.22 seconds
Started Jul 15 06:24:50 PM PDT 24
Finished Jul 15 06:25:04 PM PDT 24
Peak memory 221536 kb
Host smart-4a92a643-0c2a-4f6f-9987-1dfabb88ef8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=55737008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direc
t.55737008
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.489718410
Short name T842
Test name
Test status
Simulation time 5728001465 ps
CPU time 27.19 seconds
Started Jul 15 06:24:49 PM PDT 24
Finished Jul 15 06:25:17 PM PDT 24
Peak memory 217476 kb
Host smart-decce0b0-2bdb-4dc7-b3dc-d3eaafe6c0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489718410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.489718410
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2302188409
Short name T570
Test name
Test status
Simulation time 479578501 ps
CPU time 2.58 seconds
Started Jul 15 06:24:49 PM PDT 24
Finished Jul 15 06:24:53 PM PDT 24
Peak memory 217368 kb
Host smart-530fc05d-419c-4991-b494-d3847d165310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302188409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2302188409
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3712729932
Short name T604
Test name
Test status
Simulation time 740897948 ps
CPU time 1.72 seconds
Started Jul 15 06:24:51 PM PDT 24
Finished Jul 15 06:24:53 PM PDT 24
Peak memory 217176 kb
Host smart-e17561af-3f50-4d96-a2dd-f09ff93d0a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712729932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3712729932
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3188102158
Short name T972
Test name
Test status
Simulation time 150773376 ps
CPU time 1.01 seconds
Started Jul 15 06:24:53 PM PDT 24
Finished Jul 15 06:24:54 PM PDT 24
Peak memory 206972 kb
Host smart-13aaf1de-d3cd-4ce9-9e1a-87e2dc0c5cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188102158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3188102158
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3316916991
Short name T77
Test name
Test status
Simulation time 1914736759 ps
CPU time 15.36 seconds
Started Jul 15 06:24:50 PM PDT 24
Finished Jul 15 06:25:06 PM PDT 24
Peak memory 241872 kb
Host smart-b0f908e9-aeb2-4e9b-8276-e24083203bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316916991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3316916991
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3687837924
Short name T760
Test name
Test status
Simulation time 22134032 ps
CPU time 0.74 seconds
Started Jul 15 06:24:56 PM PDT 24
Finished Jul 15 06:24:57 PM PDT 24
Peak memory 206348 kb
Host smart-c12d1dcc-6075-4f39-ae7b-61f5aae303f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687837924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3687837924
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2625863086
Short name T767
Test name
Test status
Simulation time 2240393046 ps
CPU time 7.28 seconds
Started Jul 15 06:24:55 PM PDT 24
Finished Jul 15 06:25:03 PM PDT 24
Peak memory 233808 kb
Host smart-d16ce3ce-712f-41c8-9ae1-4f1926011a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625863086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2625863086
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.169906947
Short name T670
Test name
Test status
Simulation time 49000206 ps
CPU time 0.81 seconds
Started Jul 15 06:24:52 PM PDT 24
Finished Jul 15 06:24:54 PM PDT 24
Peak memory 207512 kb
Host smart-13e6086d-9054-454d-8101-c80f9d1f9075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169906947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.169906947
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2943932225
Short name T210
Test name
Test status
Simulation time 228161252823 ps
CPU time 361.15 seconds
Started Jul 15 06:24:54 PM PDT 24
Finished Jul 15 06:30:56 PM PDT 24
Peak memory 262376 kb
Host smart-a025959d-7f82-4478-9114-ffff8d7d278f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943932225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2943932225
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4203732151
Short name T426
Test name
Test status
Simulation time 9472862984 ps
CPU time 88.16 seconds
Started Jul 15 06:25:01 PM PDT 24
Finished Jul 15 06:26:31 PM PDT 24
Peak memory 240404 kb
Host smart-fab6e182-737b-4483-9423-3ebd5fabfd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203732151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4203732151
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2397802502
Short name T143
Test name
Test status
Simulation time 5159329794 ps
CPU time 60.09 seconds
Started Jul 15 06:25:01 PM PDT 24
Finished Jul 15 06:26:02 PM PDT 24
Peak memory 250448 kb
Host smart-5b752fd0-3eea-4199-82e6-929dec7f7073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397802502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2397802502
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.599541994
Short name T759
Test name
Test status
Simulation time 3167235670 ps
CPU time 15.16 seconds
Started Jul 15 06:24:58 PM PDT 24
Finished Jul 15 06:25:14 PM PDT 24
Peak memory 225640 kb
Host smart-0fa53a4d-b340-4fa8-a138-2f4e6c6a47b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599541994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.599541994
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2557850495
Short name T410
Test name
Test status
Simulation time 22274991680 ps
CPU time 203.29 seconds
Started Jul 15 06:24:54 PM PDT 24
Finished Jul 15 06:28:18 PM PDT 24
Peak memory 252680 kb
Host smart-c447eb32-b241-478e-841f-44350d0240ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557850495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2557850495
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.4072890274
Short name T377
Test name
Test status
Simulation time 60976985 ps
CPU time 2.33 seconds
Started Jul 15 06:24:59 PM PDT 24
Finished Jul 15 06:25:02 PM PDT 24
Peak memory 233532 kb
Host smart-eaa3addf-8559-4c15-8a7e-a29f3e6aa2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072890274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.4072890274
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3971984110
Short name T270
Test name
Test status
Simulation time 3658601963 ps
CPU time 23.23 seconds
Started Jul 15 06:24:56 PM PDT 24
Finished Jul 15 06:25:19 PM PDT 24
Peak memory 233824 kb
Host smart-e6cfc3cc-387e-4658-988c-8dffd8abbb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971984110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3971984110
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2243636839
Short name T836
Test name
Test status
Simulation time 203409272 ps
CPU time 2.97 seconds
Started Jul 15 06:24:57 PM PDT 24
Finished Jul 15 06:25:00 PM PDT 24
Peak memory 233804 kb
Host smart-6d1d0c49-729f-411a-ab86-62a906c93d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243636839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2243636839
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2424646647
Short name T553
Test name
Test status
Simulation time 3825463649 ps
CPU time 6.3 seconds
Started Jul 15 06:24:59 PM PDT 24
Finished Jul 15 06:25:07 PM PDT 24
Peak memory 225636 kb
Host smart-e5a7fa82-3a4d-44ed-9fee-02bfc3d35b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424646647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2424646647
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3658942814
Short name T621
Test name
Test status
Simulation time 115527872 ps
CPU time 3.44 seconds
Started Jul 15 06:24:52 PM PDT 24
Finished Jul 15 06:24:56 PM PDT 24
Peak memory 220392 kb
Host smart-4ed14ecb-11a6-4b8c-922b-5316c15e176b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3658942814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3658942814
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.287053620
Short name T20
Test name
Test status
Simulation time 126125105 ps
CPU time 1.09 seconds
Started Jul 15 06:24:59 PM PDT 24
Finished Jul 15 06:25:01 PM PDT 24
Peak memory 207796 kb
Host smart-39607cf1-47db-406d-a596-bed5def4d86d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287053620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.287053620
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1925451444
Short name T652
Test name
Test status
Simulation time 39842153481 ps
CPU time 50.02 seconds
Started Jul 15 06:24:54 PM PDT 24
Finished Jul 15 06:25:45 PM PDT 24
Peak memory 217380 kb
Host smart-5fc30e4b-72f8-4541-a8f7-b4c8fdb8600c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925451444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1925451444
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2119335560
Short name T617
Test name
Test status
Simulation time 8915725170 ps
CPU time 18.33 seconds
Started Jul 15 06:24:50 PM PDT 24
Finished Jul 15 06:25:09 PM PDT 24
Peak memory 217520 kb
Host smart-f9cb0154-a317-42d9-8fab-e4af00322a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119335560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2119335560
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.4230140680
Short name T328
Test name
Test status
Simulation time 222559003 ps
CPU time 2.19 seconds
Started Jul 15 06:24:59 PM PDT 24
Finished Jul 15 06:25:03 PM PDT 24
Peak memory 217288 kb
Host smart-38734706-92dc-4458-8cf4-6a6e504eeafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230140680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.4230140680
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2821269994
Short name T341
Test name
Test status
Simulation time 87434418 ps
CPU time 0.78 seconds
Started Jul 15 06:24:56 PM PDT 24
Finished Jul 15 06:24:58 PM PDT 24
Peak memory 206936 kb
Host smart-89fbfe6e-a377-4aaf-bcb4-729c9bba8c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821269994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2821269994
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.443778870
Short name T403
Test name
Test status
Simulation time 12200218285 ps
CPU time 17.26 seconds
Started Jul 15 06:24:55 PM PDT 24
Finished Jul 15 06:25:13 PM PDT 24
Peak memory 225600 kb
Host smart-b0ff17cc-19ae-4f46-928e-1ebc6b90e584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443778870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.443778870
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.4106654683
Short name T586
Test name
Test status
Simulation time 98213232 ps
CPU time 0.69 seconds
Started Jul 15 06:24:59 PM PDT 24
Finished Jul 15 06:25:00 PM PDT 24
Peak memory 206364 kb
Host smart-23a397b9-8686-4379-94ef-63c27ec1d666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106654683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
4106654683
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2120642414
Short name T732
Test name
Test status
Simulation time 686863817 ps
CPU time 2.49 seconds
Started Jul 15 06:25:01 PM PDT 24
Finished Jul 15 06:25:04 PM PDT 24
Peak memory 225556 kb
Host smart-932e5e30-a258-49ea-a011-c873f956fe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120642414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2120642414
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.478241808
Short name T575
Test name
Test status
Simulation time 15185258 ps
CPU time 0.76 seconds
Started Jul 15 06:25:03 PM PDT 24
Finished Jul 15 06:25:04 PM PDT 24
Peak memory 206504 kb
Host smart-081801cb-0c52-4364-9987-3342df409a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478241808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.478241808
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3183657109
Short name T370
Test name
Test status
Simulation time 1624981064 ps
CPU time 14.41 seconds
Started Jul 15 06:25:01 PM PDT 24
Finished Jul 15 06:25:17 PM PDT 24
Peak memory 225584 kb
Host smart-2f88eb11-65bf-4ef7-a91e-53aea1e84ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183657109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3183657109
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3481085180
Short name T1019
Test name
Test status
Simulation time 2328433570 ps
CPU time 19.37 seconds
Started Jul 15 06:24:59 PM PDT 24
Finished Jul 15 06:25:19 PM PDT 24
Peak memory 250256 kb
Host smart-87e87458-8960-4ab4-ba63-b543f296b68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481085180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3481085180
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2780374214
Short name T287
Test name
Test status
Simulation time 17141942061 ps
CPU time 67.23 seconds
Started Jul 15 06:24:58 PM PDT 24
Finished Jul 15 06:26:06 PM PDT 24
Peak memory 254268 kb
Host smart-a513378f-f822-42e6-8d24-ce82868a0db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780374214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2780374214
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2342561970
Short name T814
Test name
Test status
Simulation time 296343747 ps
CPU time 3.25 seconds
Started Jul 15 06:24:59 PM PDT 24
Finished Jul 15 06:25:03 PM PDT 24
Peak memory 225528 kb
Host smart-1113a5b2-eed1-4af4-b332-962edb872ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342561970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2342561970
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2614846186
Short name T364
Test name
Test status
Simulation time 31151109542 ps
CPU time 142.99 seconds
Started Jul 15 06:24:59 PM PDT 24
Finished Jul 15 06:27:23 PM PDT 24
Peak memory 258496 kb
Host smart-56125a81-54dd-4046-930f-6e8584e0e30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614846186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2614846186
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.882271815
Short name T574
Test name
Test status
Simulation time 290509713 ps
CPU time 2.3 seconds
Started Jul 15 06:24:59 PM PDT 24
Finished Jul 15 06:25:02 PM PDT 24
Peak memory 225004 kb
Host smart-27f217bc-683f-4251-b974-c9d740960bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882271815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.882271815
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3865344755
Short name T954
Test name
Test status
Simulation time 3084993582 ps
CPU time 14.78 seconds
Started Jul 15 06:25:02 PM PDT 24
Finished Jul 15 06:25:18 PM PDT 24
Peak memory 237036 kb
Host smart-11527c5f-8567-4f0c-8eaa-cd82360d8a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865344755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3865344755
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1798954261
Short name T269
Test name
Test status
Simulation time 1635476812 ps
CPU time 7.7 seconds
Started Jul 15 06:24:58 PM PDT 24
Finished Jul 15 06:25:07 PM PDT 24
Peak memory 241508 kb
Host smart-3e7e8a1f-158a-4e25-b07f-fcf11e96c98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798954261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1798954261
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3768886291
Short name T61
Test name
Test status
Simulation time 20228867482 ps
CPU time 14.42 seconds
Started Jul 15 06:24:53 PM PDT 24
Finished Jul 15 06:25:08 PM PDT 24
Peak memory 225672 kb
Host smart-f844e45c-a8db-450b-beb0-2f65d6a03130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768886291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3768886291
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2691570386
Short name T482
Test name
Test status
Simulation time 3746815948 ps
CPU time 8.95 seconds
Started Jul 15 06:24:58 PM PDT 24
Finished Jul 15 06:25:08 PM PDT 24
Peak memory 220592 kb
Host smart-04ec1ac7-8bce-451f-8201-414e1ef80b29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2691570386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2691570386
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2270149813
Short name T19
Test name
Test status
Simulation time 171050159 ps
CPU time 1.01 seconds
Started Jul 15 06:24:58 PM PDT 24
Finished Jul 15 06:25:00 PM PDT 24
Peak memory 208652 kb
Host smart-20737293-bdf0-4b5d-9969-af433a13a38b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270149813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2270149813
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2910047922
Short name T30
Test name
Test status
Simulation time 13519953846 ps
CPU time 18.64 seconds
Started Jul 15 06:24:53 PM PDT 24
Finished Jul 15 06:25:13 PM PDT 24
Peak memory 217488 kb
Host smart-8c6f205a-7452-4d96-bbf1-936af1c0c4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910047922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2910047922
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3301100220
Short name T758
Test name
Test status
Simulation time 33441032550 ps
CPU time 21.93 seconds
Started Jul 15 06:24:56 PM PDT 24
Finished Jul 15 06:25:19 PM PDT 24
Peak memory 217484 kb
Host smart-1917fab6-1d29-42e3-99ac-8751ef9d8a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301100220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3301100220
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3748044025
Short name T50
Test name
Test status
Simulation time 86846230 ps
CPU time 1.49 seconds
Started Jul 15 06:25:00 PM PDT 24
Finished Jul 15 06:25:02 PM PDT 24
Peak memory 217316 kb
Host smart-0306bd7e-169c-460f-aefe-94ac654a0820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748044025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3748044025
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1160290012
Short name T684
Test name
Test status
Simulation time 51533256 ps
CPU time 0.86 seconds
Started Jul 15 06:24:55 PM PDT 24
Finished Jul 15 06:24:57 PM PDT 24
Peak memory 207056 kb
Host smart-d111521d-ae14-44ea-8537-d3b773bbe890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160290012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1160290012
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2707863965
Short name T51
Test name
Test status
Simulation time 17729682015 ps
CPU time 12.84 seconds
Started Jul 15 06:25:04 PM PDT 24
Finished Jul 15 06:25:17 PM PDT 24
Peak memory 233920 kb
Host smart-a01efbb3-5517-44f5-a718-20fe13a1db90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707863965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2707863965
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2060590428
Short name T990
Test name
Test status
Simulation time 22098015 ps
CPU time 0.68 seconds
Started Jul 15 06:25:05 PM PDT 24
Finished Jul 15 06:25:07 PM PDT 24
Peak memory 206708 kb
Host smart-49ed155f-30c5-451d-bfe9-99f03d413c3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060590428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2060590428
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2586969515
Short name T94
Test name
Test status
Simulation time 184503628 ps
CPU time 3.67 seconds
Started Jul 15 06:25:04 PM PDT 24
Finished Jul 15 06:25:08 PM PDT 24
Peak memory 233788 kb
Host smart-ff86eba2-12b7-40fa-b976-3567f57fbe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586969515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2586969515
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.770861766
Short name T857
Test name
Test status
Simulation time 50214177 ps
CPU time 0.76 seconds
Started Jul 15 06:25:00 PM PDT 24
Finished Jul 15 06:25:02 PM PDT 24
Peak memory 207368 kb
Host smart-f3de58c7-64f7-4a2e-9345-b7c851c192b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770861766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.770861766
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3295785736
Short name T985
Test name
Test status
Simulation time 8513700923 ps
CPU time 64.32 seconds
Started Jul 15 06:25:06 PM PDT 24
Finished Jul 15 06:26:12 PM PDT 24
Peak memory 250260 kb
Host smart-31365459-06f6-44f0-a168-eca075615904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295785736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3295785736
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3078934096
Short name T417
Test name
Test status
Simulation time 7856485340 ps
CPU time 62.15 seconds
Started Jul 15 06:25:04 PM PDT 24
Finished Jul 15 06:26:07 PM PDT 24
Peak memory 250448 kb
Host smart-86512690-25d1-422c-88f2-a911b3d96217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078934096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3078934096
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3736942204
Short name T903
Test name
Test status
Simulation time 52927889339 ps
CPU time 134.55 seconds
Started Jul 15 06:25:00 PM PDT 24
Finished Jul 15 06:27:15 PM PDT 24
Peak memory 267120 kb
Host smart-4d097241-47d6-4bc8-912a-a00fb032d528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736942204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3736942204
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2712597522
Short name T764
Test name
Test status
Simulation time 757058749 ps
CPU time 4.15 seconds
Started Jul 15 06:25:00 PM PDT 24
Finished Jul 15 06:25:05 PM PDT 24
Peak memory 225568 kb
Host smart-8ebe63c9-ee7c-43c7-ba12-5ce33884a6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712597522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2712597522
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3523809724
Short name T1002
Test name
Test status
Simulation time 8407403482 ps
CPU time 60.86 seconds
Started Jul 15 06:25:03 PM PDT 24
Finished Jul 15 06:26:05 PM PDT 24
Peak memory 252588 kb
Host smart-21a8080e-164d-47fb-ba0f-b3b7428d7e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523809724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3523809724
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3516587095
Short name T207
Test name
Test status
Simulation time 825330503 ps
CPU time 4.25 seconds
Started Jul 15 06:25:01 PM PDT 24
Finished Jul 15 06:25:06 PM PDT 24
Peak memory 225524 kb
Host smart-381cfd74-63ff-40a3-ab35-0283d6db7938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516587095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3516587095
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1603680399
Short name T993
Test name
Test status
Simulation time 3523687220 ps
CPU time 41.62 seconds
Started Jul 15 06:25:03 PM PDT 24
Finished Jul 15 06:25:45 PM PDT 24
Peak memory 250052 kb
Host smart-2252c850-eca3-42fb-8c0a-ce4426dff5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603680399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1603680399
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1232701081
Short name T276
Test name
Test status
Simulation time 162219640 ps
CPU time 2.98 seconds
Started Jul 15 06:25:04 PM PDT 24
Finished Jul 15 06:25:07 PM PDT 24
Peak memory 233732 kb
Host smart-a1803c5d-3d82-43c4-ab18-4821fcfe73dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232701081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1232701081
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.461179490
Short name T544
Test name
Test status
Simulation time 649077593 ps
CPU time 4.01 seconds
Started Jul 15 06:24:58 PM PDT 24
Finished Jul 15 06:25:02 PM PDT 24
Peak memory 225588 kb
Host smart-743febe6-574d-4694-b45d-da861d9c7d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461179490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.461179490
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.4048327244
Short name T1023
Test name
Test status
Simulation time 1286608573 ps
CPU time 8.13 seconds
Started Jul 15 06:25:10 PM PDT 24
Finished Jul 15 06:25:19 PM PDT 24
Peak memory 224028 kb
Host smart-c2fbf433-ff67-4541-8860-b4ddec3ed84c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4048327244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.4048327244
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1725072362
Short name T584
Test name
Test status
Simulation time 8058335370 ps
CPU time 22.63 seconds
Started Jul 15 06:25:02 PM PDT 24
Finished Jul 15 06:25:26 PM PDT 24
Peak memory 217488 kb
Host smart-310b02cd-b482-4ae7-9340-7524ecc9bdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725072362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1725072362
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1280296991
Short name T936
Test name
Test status
Simulation time 2243754029 ps
CPU time 5.03 seconds
Started Jul 15 06:25:01 PM PDT 24
Finished Jul 15 06:25:07 PM PDT 24
Peak memory 217404 kb
Host smart-1721ded8-274c-4ad9-8a42-a57cd991657b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280296991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1280296991
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2578979214
Short name T880
Test name
Test status
Simulation time 42363247 ps
CPU time 1.05 seconds
Started Jul 15 06:25:00 PM PDT 24
Finished Jul 15 06:25:02 PM PDT 24
Peak memory 208304 kb
Host smart-4f2fc76f-3d50-429e-b0d7-13c3132494be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578979214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2578979214
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2466033820
Short name T811
Test name
Test status
Simulation time 187173925 ps
CPU time 1.1 seconds
Started Jul 15 06:24:59 PM PDT 24
Finished Jul 15 06:25:01 PM PDT 24
Peak memory 207996 kb
Host smart-ee837f91-af86-4337-a280-710a78b869b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466033820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2466033820
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3532618106
Short name T763
Test name
Test status
Simulation time 10704476283 ps
CPU time 7.9 seconds
Started Jul 15 06:25:02 PM PDT 24
Finished Jul 15 06:25:10 PM PDT 24
Peak memory 225608 kb
Host smart-44c36e4b-e636-4907-950f-f6eaf7c41084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532618106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3532618106
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3752810439
Short name T369
Test name
Test status
Simulation time 121831228 ps
CPU time 0.77 seconds
Started Jul 15 06:25:07 PM PDT 24
Finished Jul 15 06:25:09 PM PDT 24
Peak memory 205772 kb
Host smart-fe493281-e22a-4b2c-8aca-935f7a5dbd4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752810439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3752810439
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2666848646
Short name T858
Test name
Test status
Simulation time 684307176 ps
CPU time 4.91 seconds
Started Jul 15 06:25:10 PM PDT 24
Finished Jul 15 06:25:16 PM PDT 24
Peak memory 233772 kb
Host smart-6c7d37c8-d36f-4654-9242-8c622f32ebb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666848646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2666848646
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2887232618
Short name T878
Test name
Test status
Simulation time 16094257 ps
CPU time 0.8 seconds
Started Jul 15 06:25:06 PM PDT 24
Finished Jul 15 06:25:08 PM PDT 24
Peak memory 207868 kb
Host smart-0a056361-673f-4379-a304-e31619526b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887232618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2887232618
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3351669018
Short name T539
Test name
Test status
Simulation time 209662985413 ps
CPU time 127.88 seconds
Started Jul 15 06:25:09 PM PDT 24
Finished Jul 15 06:27:18 PM PDT 24
Peak memory 254492 kb
Host smart-ee0153a1-523b-441d-9d27-04840c131fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351669018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3351669018
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3034000105
Short name T594
Test name
Test status
Simulation time 15682071378 ps
CPU time 138.29 seconds
Started Jul 15 06:25:07 PM PDT 24
Finished Jul 15 06:27:26 PM PDT 24
Peak memory 253484 kb
Host smart-1908ef31-c55a-4eb6-af1e-99ddb32c1c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034000105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3034000105
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1623607084
Short name T513
Test name
Test status
Simulation time 9725724612 ps
CPU time 93.82 seconds
Started Jul 15 06:25:06 PM PDT 24
Finished Jul 15 06:26:41 PM PDT 24
Peak memory 257988 kb
Host smart-86c4aebd-78c2-44eb-a7c5-127097acacd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623607084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1623607084
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.4085828249
Short name T316
Test name
Test status
Simulation time 15633137107 ps
CPU time 14.39 seconds
Started Jul 15 06:25:06 PM PDT 24
Finished Jul 15 06:25:21 PM PDT 24
Peak memory 234948 kb
Host smart-9fd02919-4237-4040-8e7e-2b96a6ab9a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085828249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4085828249
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1762549293
Short name T816
Test name
Test status
Simulation time 18154875536 ps
CPU time 125.24 seconds
Started Jul 15 06:25:10 PM PDT 24
Finished Jul 15 06:27:16 PM PDT 24
Peak memory 251600 kb
Host smart-1b4fc19b-27dc-4812-9dd4-1a87e1018b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762549293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1762549293
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.4039886571
Short name T669
Test name
Test status
Simulation time 487370365 ps
CPU time 6.5 seconds
Started Jul 15 06:24:59 PM PDT 24
Finished Jul 15 06:25:06 PM PDT 24
Peak memory 233756 kb
Host smart-6becffb5-93b5-467e-b07d-35015a82a988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039886571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.4039886571
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2069530529
Short name T875
Test name
Test status
Simulation time 8836148572 ps
CPU time 28.51 seconds
Started Jul 15 06:25:06 PM PDT 24
Finished Jul 15 06:25:36 PM PDT 24
Peak memory 233956 kb
Host smart-de7feb11-abe1-4fce-96c1-c9484738f7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069530529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2069530529
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1443595303
Short name T567
Test name
Test status
Simulation time 720670579 ps
CPU time 5.2 seconds
Started Jul 15 06:25:02 PM PDT 24
Finished Jul 15 06:25:08 PM PDT 24
Peak memory 225524 kb
Host smart-508cec32-ff2a-4ceb-8ac5-6dde8d283610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443595303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1443595303
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3274237537
Short name T381
Test name
Test status
Simulation time 9006198500 ps
CPU time 13.83 seconds
Started Jul 15 06:25:02 PM PDT 24
Finished Jul 15 06:25:17 PM PDT 24
Peak memory 225852 kb
Host smart-b7643ab9-56b9-4c48-afd6-bad6fc70d2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274237537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3274237537
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3799207949
Short name T488
Test name
Test status
Simulation time 7051240104 ps
CPU time 18.7 seconds
Started Jul 15 06:25:02 PM PDT 24
Finished Jul 15 06:25:21 PM PDT 24
Peak memory 220652 kb
Host smart-61bb5179-8b93-40ce-98dc-f546568f5d3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3799207949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3799207949
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.452124941
Short name T665
Test name
Test status
Simulation time 123988926 ps
CPU time 0.92 seconds
Started Jul 15 06:25:05 PM PDT 24
Finished Jul 15 06:25:06 PM PDT 24
Peak memory 207704 kb
Host smart-a9f35aac-9dc1-476c-a080-cb8a473b5717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452124941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.452124941
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2381541530
Short name T912
Test name
Test status
Simulation time 4813620523 ps
CPU time 14.4 seconds
Started Jul 15 06:25:10 PM PDT 24
Finished Jul 15 06:25:25 PM PDT 24
Peak memory 217356 kb
Host smart-f09d0075-ca2c-4d81-969e-d1a90d1efefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381541530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2381541530
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1546010988
Short name T105
Test name
Test status
Simulation time 42057170 ps
CPU time 0.72 seconds
Started Jul 15 06:25:06 PM PDT 24
Finished Jul 15 06:25:08 PM PDT 24
Peak memory 206616 kb
Host smart-a59206d3-7c65-47f6-b9f2-748128977502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546010988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1546010988
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2136441631
Short name T359
Test name
Test status
Simulation time 1566109655 ps
CPU time 10.06 seconds
Started Jul 15 06:25:03 PM PDT 24
Finished Jul 15 06:25:14 PM PDT 24
Peak memory 217360 kb
Host smart-1b3162ca-1553-4560-adca-123f8da93439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136441631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2136441631
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2634757807
Short name T568
Test name
Test status
Simulation time 94020855 ps
CPU time 0.76 seconds
Started Jul 15 06:25:02 PM PDT 24
Finished Jul 15 06:25:04 PM PDT 24
Peak memory 206960 kb
Host smart-6c1d6ee6-1d73-4c9a-96a5-0eb3f9243b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634757807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2634757807
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3967775120
Short name T525
Test name
Test status
Simulation time 1043197425 ps
CPU time 8.65 seconds
Started Jul 15 06:25:10 PM PDT 24
Finished Jul 15 06:25:20 PM PDT 24
Peak memory 241916 kb
Host smart-86bfeef2-35a9-49bf-97b0-991cc1f879d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967775120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3967775120
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3721036607
Short name T25
Test name
Test status
Simulation time 11944210 ps
CPU time 0.73 seconds
Started Jul 15 06:25:11 PM PDT 24
Finished Jul 15 06:25:12 PM PDT 24
Peak memory 206472 kb
Host smart-b8a71639-326f-4195-8a8e-51b82279572c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721036607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3721036607
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2079188489
Short name T429
Test name
Test status
Simulation time 1594783529 ps
CPU time 8.41 seconds
Started Jul 15 06:25:11 PM PDT 24
Finished Jul 15 06:25:20 PM PDT 24
Peak memory 225636 kb
Host smart-f74f03d0-6591-4850-a063-8b1e3b89451f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079188489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2079188489
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.688202958
Short name T509
Test name
Test status
Simulation time 16238963 ps
CPU time 0.8 seconds
Started Jul 15 06:25:08 PM PDT 24
Finished Jul 15 06:25:09 PM PDT 24
Peak memory 207512 kb
Host smart-b390918e-f133-4222-b4b8-3b5081f32b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688202958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.688202958
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2222468194
Short name T740
Test name
Test status
Simulation time 35495272823 ps
CPU time 245.61 seconds
Started Jul 15 06:25:06 PM PDT 24
Finished Jul 15 06:29:13 PM PDT 24
Peak memory 266404 kb
Host smart-df8c56f5-baa6-4077-ba5d-bc8e5b5ac4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222468194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2222468194
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.106879915
Short name T283
Test name
Test status
Simulation time 65873272055 ps
CPU time 624.7 seconds
Started Jul 15 06:25:08 PM PDT 24
Finished Jul 15 06:35:33 PM PDT 24
Peak memory 268168 kb
Host smart-b5c2bd4c-8b68-4c12-8a4e-0d4d5933dd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106879915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.106879915
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2465727458
Short name T284
Test name
Test status
Simulation time 8098412439 ps
CPU time 113.89 seconds
Started Jul 15 06:25:08 PM PDT 24
Finished Jul 15 06:27:03 PM PDT 24
Peak memory 273296 kb
Host smart-0d2c9d00-244f-49bb-810a-72fc4dbba0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465727458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2465727458
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.822535466
Short name T313
Test name
Test status
Simulation time 248920666 ps
CPU time 8.67 seconds
Started Jul 15 06:25:07 PM PDT 24
Finished Jul 15 06:25:17 PM PDT 24
Peak memory 234792 kb
Host smart-186e0584-47a4-4e08-941d-f42dfcfce46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822535466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.822535466
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2117972686
Short name T391
Test name
Test status
Simulation time 18838162 ps
CPU time 0.75 seconds
Started Jul 15 06:25:11 PM PDT 24
Finished Jul 15 06:25:12 PM PDT 24
Peak memory 216888 kb
Host smart-949c0c8f-d135-4343-a5fd-1f0fa8d3bd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117972686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2117972686
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3241323233
Short name T853
Test name
Test status
Simulation time 3117970357 ps
CPU time 20.75 seconds
Started Jul 15 06:25:08 PM PDT 24
Finished Jul 15 06:25:30 PM PDT 24
Peak memory 233960 kb
Host smart-17d437ff-f2ca-44d3-86b0-c3bbd37505a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241323233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3241323233
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.888289790
Short name T701
Test name
Test status
Simulation time 40852103403 ps
CPU time 90.06 seconds
Started Jul 15 06:25:05 PM PDT 24
Finished Jul 15 06:26:36 PM PDT 24
Peak memory 233752 kb
Host smart-18c11a4b-6ef3-4782-a5d6-47310ff7f42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888289790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.888289790
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2131596274
Short name T138
Test name
Test status
Simulation time 364587776 ps
CPU time 2.25 seconds
Started Jul 15 06:25:11 PM PDT 24
Finished Jul 15 06:25:14 PM PDT 24
Peak memory 224852 kb
Host smart-19db74ae-1613-40f9-ad30-2ea782bda2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131596274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2131596274
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2221031585
Short name T495
Test name
Test status
Simulation time 1883831466 ps
CPU time 3.74 seconds
Started Jul 15 06:25:06 PM PDT 24
Finished Jul 15 06:25:11 PM PDT 24
Peak memory 233668 kb
Host smart-70e272d9-4424-45b4-87ea-164bd67887d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221031585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2221031585
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3005355171
Short name T1
Test name
Test status
Simulation time 12232177388 ps
CPU time 9.19 seconds
Started Jul 15 06:25:06 PM PDT 24
Finished Jul 15 06:25:17 PM PDT 24
Peak memory 224440 kb
Host smart-3e5a8180-8dff-4d13-9cd9-dbb358f36091
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3005355171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3005355171
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.170489385
Short name T205
Test name
Test status
Simulation time 181164669614 ps
CPU time 430.62 seconds
Started Jul 15 06:25:06 PM PDT 24
Finished Jul 15 06:32:18 PM PDT 24
Peak memory 256980 kb
Host smart-74af6067-e6d0-4d62-8c7e-bc469ad4bc19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170489385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.170489385
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1962930344
Short name T992
Test name
Test status
Simulation time 12261286267 ps
CPU time 22.71 seconds
Started Jul 15 06:25:10 PM PDT 24
Finished Jul 15 06:25:34 PM PDT 24
Peak memory 217616 kb
Host smart-058e4689-e85f-43b7-9f2e-120abf4f1d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962930344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1962930344
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.192288546
Short name T588
Test name
Test status
Simulation time 686152522 ps
CPU time 4.72 seconds
Started Jul 15 06:25:05 PM PDT 24
Finished Jul 15 06:25:11 PM PDT 24
Peak memory 217308 kb
Host smart-124bca5e-b209-43e2-8be2-750d42120168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192288546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.192288546
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1767185903
Short name T841
Test name
Test status
Simulation time 209500045 ps
CPU time 1.99 seconds
Started Jul 15 06:25:11 PM PDT 24
Finished Jul 15 06:25:14 PM PDT 24
Peak memory 217396 kb
Host smart-5edf7f90-fb31-4106-8b85-f837fa664f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767185903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1767185903
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1187578120
Short name T833
Test name
Test status
Simulation time 57180937 ps
CPU time 0.86 seconds
Started Jul 15 06:25:06 PM PDT 24
Finished Jul 15 06:25:08 PM PDT 24
Peak memory 207308 kb
Host smart-8081a363-612d-43da-9c1e-229a5ae708ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187578120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1187578120
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1560566856
Short name T642
Test name
Test status
Simulation time 354629267 ps
CPU time 3.02 seconds
Started Jul 15 06:25:07 PM PDT 24
Finished Jul 15 06:25:12 PM PDT 24
Peak memory 233760 kb
Host smart-ac10c1cc-6a9d-44b5-a2fe-9bb05b2f59a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560566856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1560566856
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2259513327
Short name T681
Test name
Test status
Simulation time 13739724 ps
CPU time 0.74 seconds
Started Jul 15 06:25:11 PM PDT 24
Finished Jul 15 06:25:13 PM PDT 24
Peak memory 206376 kb
Host smart-5ef75b19-17ea-42c4-bcdb-23a9c8d7a0f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259513327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2259513327
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1767787550
Short name T820
Test name
Test status
Simulation time 994183119 ps
CPU time 3.92 seconds
Started Jul 15 06:25:09 PM PDT 24
Finished Jul 15 06:25:14 PM PDT 24
Peak memory 233780 kb
Host smart-1c5b4c9d-3a4b-40ed-afc4-80187d6280bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767787550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1767787550
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1847592394
Short name T638
Test name
Test status
Simulation time 70650437 ps
CPU time 0.8 seconds
Started Jul 15 06:25:08 PM PDT 24
Finished Jul 15 06:25:10 PM PDT 24
Peak memory 207492 kb
Host smart-01490835-d358-4d91-aae9-23bfe7caf1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847592394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1847592394
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1974648931
Short name T646
Test name
Test status
Simulation time 3296089851 ps
CPU time 55.16 seconds
Started Jul 15 06:25:12 PM PDT 24
Finished Jul 15 06:26:08 PM PDT 24
Peak memory 257160 kb
Host smart-f380b524-b301-4872-9c10-ea1d19461aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974648931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1974648931
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1437064106
Short name T933
Test name
Test status
Simulation time 9282171683 ps
CPU time 72.1 seconds
Started Jul 15 06:25:11 PM PDT 24
Finished Jul 15 06:26:24 PM PDT 24
Peak memory 257196 kb
Host smart-e85948f2-0e17-4269-ba8a-1d77dbcbc7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437064106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1437064106
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1234797338
Short name T675
Test name
Test status
Simulation time 50217008748 ps
CPU time 226.55 seconds
Started Jul 15 06:25:16 PM PDT 24
Finished Jul 15 06:29:03 PM PDT 24
Peak memory 242352 kb
Host smart-fb5161ea-70df-4827-8d32-1cdc7978d9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234797338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1234797338
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.949755625
Short name T974
Test name
Test status
Simulation time 426750305 ps
CPU time 9.13 seconds
Started Jul 15 06:25:12 PM PDT 24
Finished Jul 15 06:25:21 PM PDT 24
Peak memory 225600 kb
Host smart-e025f15d-d592-4a11-8e10-943d09524b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949755625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.949755625
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1094046489
Short name T651
Test name
Test status
Simulation time 940053644 ps
CPU time 9.48 seconds
Started Jul 15 06:25:14 PM PDT 24
Finished Jul 15 06:25:24 PM PDT 24
Peak memory 233800 kb
Host smart-8e79df7c-5f1b-4bc7-b19a-e68e9a4302ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094046489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1094046489
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.955434551
Short name T582
Test name
Test status
Simulation time 2171766669 ps
CPU time 4.96 seconds
Started Jul 15 06:25:06 PM PDT 24
Finished Jul 15 06:25:12 PM PDT 24
Peak memory 233808 kb
Host smart-0bbeee14-ce2e-4ec0-a117-b5b39801cb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955434551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.955434551
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2992211100
Short name T872
Test name
Test status
Simulation time 4530945673 ps
CPU time 44.33 seconds
Started Jul 15 06:25:09 PM PDT 24
Finished Jul 15 06:25:54 PM PDT 24
Peak memory 240808 kb
Host smart-912fb85a-8c18-4d66-9cd0-54aab16ba5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992211100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2992211100
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.310904288
Short name T944
Test name
Test status
Simulation time 53761116989 ps
CPU time 27.6 seconds
Started Jul 15 06:25:09 PM PDT 24
Finished Jul 15 06:25:37 PM PDT 24
Peak memory 250016 kb
Host smart-d24986ae-845f-4c25-ad74-62a1843fa039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310904288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.310904288
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2343679939
Short name T637
Test name
Test status
Simulation time 110033093 ps
CPU time 2.41 seconds
Started Jul 15 06:25:09 PM PDT 24
Finished Jul 15 06:25:12 PM PDT 24
Peak memory 233700 kb
Host smart-e9620a67-995c-469d-8d82-080cd26be701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343679939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2343679939
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3729547498
Short name T618
Test name
Test status
Simulation time 6864994232 ps
CPU time 13.79 seconds
Started Jul 15 06:25:13 PM PDT 24
Finished Jul 15 06:25:27 PM PDT 24
Peak memory 219908 kb
Host smart-61be8dbb-a3e1-4633-a989-4e0df349ddea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3729547498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3729547498
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1648809859
Short name T172
Test name
Test status
Simulation time 52514991 ps
CPU time 1.03 seconds
Started Jul 15 06:25:13 PM PDT 24
Finished Jul 15 06:25:15 PM PDT 24
Peak memory 207736 kb
Host smart-f4b2f140-1a52-4058-a6b7-17358e5a570a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648809859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1648809859
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.4070966030
Short name T716
Test name
Test status
Simulation time 2788313776 ps
CPU time 23.04 seconds
Started Jul 15 06:25:08 PM PDT 24
Finished Jul 15 06:25:32 PM PDT 24
Peak memory 217784 kb
Host smart-f9bf7c63-2efe-4e97-8962-09e0a4139b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070966030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4070966030
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2383025242
Short name T493
Test name
Test status
Simulation time 4375618228 ps
CPU time 5.59 seconds
Started Jul 15 06:25:07 PM PDT 24
Finished Jul 15 06:25:14 PM PDT 24
Peak memory 217536 kb
Host smart-593736f8-34c7-455b-a0bf-467494db288b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383025242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2383025242
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3413651043
Short name T1024
Test name
Test status
Simulation time 70643017 ps
CPU time 1.33 seconds
Started Jul 15 06:25:09 PM PDT 24
Finished Jul 15 06:25:11 PM PDT 24
Peak memory 217128 kb
Host smart-9fe3920b-0da2-4771-ba2f-3da48e3d3fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413651043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3413651043
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2633478952
Short name T346
Test name
Test status
Simulation time 298711154 ps
CPU time 0.88 seconds
Started Jul 15 06:25:04 PM PDT 24
Finished Jul 15 06:25:06 PM PDT 24
Peak memory 207432 kb
Host smart-7a14a53f-638c-4656-a064-5c3c2afd1ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633478952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2633478952
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.730022227
Short name T398
Test name
Test status
Simulation time 599933453 ps
CPU time 7.6 seconds
Started Jul 15 06:25:10 PM PDT 24
Finished Jul 15 06:25:18 PM PDT 24
Peak memory 225588 kb
Host smart-bb69ecff-1b27-48dd-b12a-b8117b5fca67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730022227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.730022227
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.825619931
Short name T994
Test name
Test status
Simulation time 19022303 ps
CPU time 0.76 seconds
Started Jul 15 06:25:18 PM PDT 24
Finished Jul 15 06:25:20 PM PDT 24
Peak memory 206696 kb
Host smart-b15a1591-224f-4a17-a22e-ad6a6051188e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825619931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.825619931
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.909130543
Short name T927
Test name
Test status
Simulation time 745515597 ps
CPU time 8.03 seconds
Started Jul 15 06:25:18 PM PDT 24
Finished Jul 15 06:25:27 PM PDT 24
Peak memory 233756 kb
Host smart-f7538c11-1836-47f1-95a1-4af3089484b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909130543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.909130543
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2991595146
Short name T790
Test name
Test status
Simulation time 48677545 ps
CPU time 0.81 seconds
Started Jul 15 06:25:15 PM PDT 24
Finished Jul 15 06:25:16 PM PDT 24
Peak memory 207512 kb
Host smart-11f37eb1-1d92-4a9f-8de6-1a1e0d6b8cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991595146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2991595146
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2764288868
Short name T432
Test name
Test status
Simulation time 5293543441 ps
CPU time 21.59 seconds
Started Jul 15 06:25:18 PM PDT 24
Finished Jul 15 06:25:41 PM PDT 24
Peak memory 236984 kb
Host smart-379d8e2a-ee4d-4049-9901-1d6c6e7955c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764288868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2764288868
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2261586117
Short name T217
Test name
Test status
Simulation time 5384355847 ps
CPU time 60.46 seconds
Started Jul 15 06:25:18 PM PDT 24
Finished Jul 15 06:26:19 PM PDT 24
Peak memory 252488 kb
Host smart-4e4f10d6-c5d2-459e-850d-b9f56854724e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261586117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2261586117
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4081277044
Short name T419
Test name
Test status
Simulation time 14004703054 ps
CPU time 117.89 seconds
Started Jul 15 06:25:20 PM PDT 24
Finished Jul 15 06:27:18 PM PDT 24
Peak memory 257344 kb
Host smart-27f25802-2dd5-476d-8ed4-78a017eb4556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081277044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.4081277044
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1713152256
Short name T945
Test name
Test status
Simulation time 451994524 ps
CPU time 3.78 seconds
Started Jul 15 06:25:17 PM PDT 24
Finished Jul 15 06:25:21 PM PDT 24
Peak memory 225548 kb
Host smart-517284ce-1f45-4a0b-9a10-058d3315a459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713152256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1713152256
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3906814455
Short name T869
Test name
Test status
Simulation time 703318753 ps
CPU time 5.99 seconds
Started Jul 15 06:25:16 PM PDT 24
Finished Jul 15 06:25:23 PM PDT 24
Peak memory 233860 kb
Host smart-70925f8d-5fb3-4f45-96fc-b260fe288ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906814455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3906814455
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3295543376
Short name T909
Test name
Test status
Simulation time 212392316 ps
CPU time 5.4 seconds
Started Jul 15 06:25:18 PM PDT 24
Finished Jul 15 06:25:24 PM PDT 24
Peak memory 233784 kb
Host smart-50081a20-46dc-48b5-88a1-28708165e51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295543376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3295543376
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1328587595
Short name T784
Test name
Test status
Simulation time 582175478 ps
CPU time 11.15 seconds
Started Jul 15 06:25:18 PM PDT 24
Finished Jul 15 06:25:30 PM PDT 24
Peak memory 241412 kb
Host smart-daa39fa2-5a28-459a-840b-8a6282ff4a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328587595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1328587595
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.851411827
Short name T772
Test name
Test status
Simulation time 4636488618 ps
CPU time 4.95 seconds
Started Jul 15 06:25:17 PM PDT 24
Finished Jul 15 06:25:22 PM PDT 24
Peak memory 225748 kb
Host smart-14daa2f5-4d5a-4e90-85e2-b99613600dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851411827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.851411827
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1621770970
Short name T995
Test name
Test status
Simulation time 2222835961 ps
CPU time 6.33 seconds
Started Jul 15 06:25:18 PM PDT 24
Finished Jul 15 06:25:25 PM PDT 24
Peak memory 225604 kb
Host smart-048e145e-af2e-4b4e-92ba-86d627127af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621770970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1621770970
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2059905896
Short name T981
Test name
Test status
Simulation time 712305888 ps
CPU time 5.14 seconds
Started Jul 15 06:25:17 PM PDT 24
Finished Jul 15 06:25:23 PM PDT 24
Peak memory 220828 kb
Host smart-c66e86d4-b64b-4cef-83e9-c755fb32ee3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2059905896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2059905896
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1695293016
Short name T405
Test name
Test status
Simulation time 19530664458 ps
CPU time 21.54 seconds
Started Jul 15 06:25:12 PM PDT 24
Finished Jul 15 06:25:34 PM PDT 24
Peak memory 217580 kb
Host smart-26824e31-b7e8-44ca-a28a-d1a1b670acc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695293016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1695293016
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1782816591
Short name T531
Test name
Test status
Simulation time 5094403584 ps
CPU time 3.97 seconds
Started Jul 15 06:25:14 PM PDT 24
Finished Jul 15 06:25:18 PM PDT 24
Peak memory 217460 kb
Host smart-8590bb57-0b9c-4237-8495-7c0de0973242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782816591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1782816591
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3748379793
Short name T325
Test name
Test status
Simulation time 576206156 ps
CPU time 1.38 seconds
Started Jul 15 06:25:17 PM PDT 24
Finished Jul 15 06:25:19 PM PDT 24
Peak memory 217380 kb
Host smart-bdc44e41-7bbf-4126-af98-58bc663dbff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748379793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3748379793
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2137465626
Short name T29
Test name
Test status
Simulation time 30784784 ps
CPU time 0.83 seconds
Started Jul 15 06:25:19 PM PDT 24
Finished Jul 15 06:25:20 PM PDT 24
Peak memory 206972 kb
Host smart-8aea81bc-5269-4524-9e5a-79be193e5f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137465626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2137465626
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1662182486
Short name T940
Test name
Test status
Simulation time 330902055 ps
CPU time 4.37 seconds
Started Jul 15 06:25:17 PM PDT 24
Finished Jul 15 06:25:22 PM PDT 24
Peak memory 233628 kb
Host smart-c7e7c89d-422e-4d97-9120-32ddf824a0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662182486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1662182486
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3071574064
Short name T657
Test name
Test status
Simulation time 20915470 ps
CPU time 0.74 seconds
Started Jul 15 06:25:23 PM PDT 24
Finished Jul 15 06:25:24 PM PDT 24
Peak memory 206708 kb
Host smart-7ffe24c2-65d1-433f-b646-c554a9a3d997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071574064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3071574064
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3672489537
Short name T711
Test name
Test status
Simulation time 542051709 ps
CPU time 7.79 seconds
Started Jul 15 06:25:31 PM PDT 24
Finished Jul 15 06:25:39 PM PDT 24
Peak memory 233664 kb
Host smart-91fa94d1-5dca-4f83-b12f-32da5f271003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672489537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3672489537
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.687324301
Short name T622
Test name
Test status
Simulation time 71260733 ps
CPU time 0.83 seconds
Started Jul 15 06:25:17 PM PDT 24
Finished Jul 15 06:25:18 PM PDT 24
Peak memory 207776 kb
Host smart-e59a3c26-52a0-41c8-b680-433629d245ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687324301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.687324301
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1037529826
Short name T946
Test name
Test status
Simulation time 126195759311 ps
CPU time 109.13 seconds
Started Jul 15 06:25:24 PM PDT 24
Finished Jul 15 06:27:14 PM PDT 24
Peak memory 254744 kb
Host smart-f6de787e-d042-411c-9fe1-04435b8bd293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037529826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1037529826
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.147769681
Short name T560
Test name
Test status
Simulation time 169268744524 ps
CPU time 76.28 seconds
Started Jul 15 06:25:24 PM PDT 24
Finished Jul 15 06:26:41 PM PDT 24
Peak memory 242184 kb
Host smart-28ed2faf-0970-4c3c-9ff9-1e49e45304e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147769681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.147769681
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.621969165
Short name T668
Test name
Test status
Simulation time 14497113094 ps
CPU time 72.67 seconds
Started Jul 15 06:25:31 PM PDT 24
Finished Jul 15 06:26:44 PM PDT 24
Peak memory 233924 kb
Host smart-f6fa64d3-1cbd-451f-b722-e59ed8dd0827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621969165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.621969165
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3256576224
Short name T921
Test name
Test status
Simulation time 3700401213 ps
CPU time 12.06 seconds
Started Jul 15 06:25:22 PM PDT 24
Finished Jul 15 06:25:35 PM PDT 24
Peak memory 238508 kb
Host smart-4b85ecd5-fc59-41dd-8900-b4dffddfc2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256576224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3256576224
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2001890093
Short name T1020
Test name
Test status
Simulation time 28972600118 ps
CPU time 101.77 seconds
Started Jul 15 06:25:22 PM PDT 24
Finished Jul 15 06:27:05 PM PDT 24
Peak memory 251524 kb
Host smart-82840d46-7151-4791-8818-47bc022a7205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001890093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2001890093
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.412395634
Short name T626
Test name
Test status
Simulation time 226161547 ps
CPU time 3.72 seconds
Started Jul 15 06:25:24 PM PDT 24
Finished Jul 15 06:25:29 PM PDT 24
Peak memory 233760 kb
Host smart-7fdee646-0551-403b-9156-aa4e4ab805bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412395634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.412395634
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1505345996
Short name T601
Test name
Test status
Simulation time 709975416 ps
CPU time 13.01 seconds
Started Jul 15 06:25:23 PM PDT 24
Finished Jul 15 06:25:36 PM PDT 24
Peak memory 249264 kb
Host smart-2ad84314-2b49-4a35-b1fc-a991d406a1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505345996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1505345996
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2542596291
Short name T354
Test name
Test status
Simulation time 3216915584 ps
CPU time 11.25 seconds
Started Jul 15 06:25:22 PM PDT 24
Finished Jul 15 06:25:34 PM PDT 24
Peak memory 225544 kb
Host smart-f4cede14-6dc0-4606-ba60-fc7a7dc41f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542596291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2542596291
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2028327661
Short name T1008
Test name
Test status
Simulation time 165120803 ps
CPU time 3.45 seconds
Started Jul 15 06:25:22 PM PDT 24
Finished Jul 15 06:25:26 PM PDT 24
Peak memory 225608 kb
Host smart-86d19fb4-d077-4409-9205-af4447f1b2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028327661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2028327661
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3553957245
Short name T12
Test name
Test status
Simulation time 876941863 ps
CPU time 5.86 seconds
Started Jul 15 06:25:31 PM PDT 24
Finished Jul 15 06:25:37 PM PDT 24
Peak memory 222900 kb
Host smart-d49545f3-6f69-420c-b5da-effbcddc2aa6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3553957245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3553957245
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2826022757
Short name T22
Test name
Test status
Simulation time 2865736231 ps
CPU time 61.82 seconds
Started Jul 15 06:25:31 PM PDT 24
Finished Jul 15 06:26:33 PM PDT 24
Peak memory 250388 kb
Host smart-15f3816c-faad-40d4-8416-65bde56439d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826022757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2826022757
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3605343421
Short name T881
Test name
Test status
Simulation time 415244630 ps
CPU time 1.87 seconds
Started Jul 15 06:25:22 PM PDT 24
Finished Jul 15 06:25:24 PM PDT 24
Peak memory 217244 kb
Host smart-5b2cd0c3-b0c0-4fae-b991-b686a777e50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605343421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3605343421
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3317894498
Short name T332
Test name
Test status
Simulation time 21323047 ps
CPU time 0.71 seconds
Started Jul 15 06:25:17 PM PDT 24
Finished Jul 15 06:25:19 PM PDT 24
Peak memory 206584 kb
Host smart-77885c2e-7e44-4d98-a71f-a4d64cfc909b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317894498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3317894498
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.897822037
Short name T787
Test name
Test status
Simulation time 197679636 ps
CPU time 2.3 seconds
Started Jul 15 06:25:23 PM PDT 24
Finished Jul 15 06:25:26 PM PDT 24
Peak memory 217396 kb
Host smart-1db328b5-c248-4063-a905-8600cd25b595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897822037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.897822037
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2111940014
Short name T607
Test name
Test status
Simulation time 34893167 ps
CPU time 0.75 seconds
Started Jul 15 06:25:24 PM PDT 24
Finished Jul 15 06:25:26 PM PDT 24
Peak memory 206912 kb
Host smart-8f8d94ac-5cd7-4b0b-adbe-66e8d85fc3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111940014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2111940014
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3453182176
Short name T706
Test name
Test status
Simulation time 1210358840 ps
CPU time 6.37 seconds
Started Jul 15 06:25:24 PM PDT 24
Finished Jul 15 06:25:31 PM PDT 24
Peak memory 233788 kb
Host smart-72f7b3bb-50fd-4805-9412-484a0c1a6c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453182176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3453182176
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.945365444
Short name T748
Test name
Test status
Simulation time 17664352 ps
CPU time 0.73 seconds
Started Jul 15 06:23:29 PM PDT 24
Finished Jul 15 06:23:31 PM PDT 24
Peak memory 205772 kb
Host smart-0e964bd4-947c-47d5-8bcf-edaf9f68f349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945365444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.945365444
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1824427899
Short name T464
Test name
Test status
Simulation time 177586285 ps
CPU time 3.97 seconds
Started Jul 15 06:23:30 PM PDT 24
Finished Jul 15 06:23:34 PM PDT 24
Peak memory 233764 kb
Host smart-da8aa913-0762-45fb-86e4-a48138713227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824427899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1824427899
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3570321440
Short name T634
Test name
Test status
Simulation time 15886557 ps
CPU time 0.77 seconds
Started Jul 15 06:23:29 PM PDT 24
Finished Jul 15 06:23:31 PM PDT 24
Peak memory 207828 kb
Host smart-0f640b8b-347f-4998-a2b6-50e62160f897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570321440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3570321440
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.4069785295
Short name T713
Test name
Test status
Simulation time 22483570766 ps
CPU time 74.83 seconds
Started Jul 15 06:23:30 PM PDT 24
Finished Jul 15 06:24:45 PM PDT 24
Peak memory 253148 kb
Host smart-35ef70d0-5baa-4635-97f6-820270bdfe55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069785295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.4069785295
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2090634044
Short name T253
Test name
Test status
Simulation time 59672384367 ps
CPU time 145.62 seconds
Started Jul 15 06:23:32 PM PDT 24
Finished Jul 15 06:25:59 PM PDT 24
Peak memory 234008 kb
Host smart-1a5dd7f9-549d-4061-83e1-b2e7e8672efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090634044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2090634044
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2676667906
Short name T366
Test name
Test status
Simulation time 5129027959 ps
CPU time 9.39 seconds
Started Jul 15 06:23:28 PM PDT 24
Finished Jul 15 06:23:38 PM PDT 24
Peak memory 233948 kb
Host smart-c43e0a4f-e657-4a05-8fa7-4267e9c4cbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676667906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2676667906
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.163366845
Short name T281
Test name
Test status
Simulation time 133923833624 ps
CPU time 247.11 seconds
Started Jul 15 06:23:31 PM PDT 24
Finished Jul 15 06:27:39 PM PDT 24
Peak memory 266656 kb
Host smart-95931bee-fa5c-4600-93dd-01c397bd26ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163366845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
163366845
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3057695606
Short name T120
Test name
Test status
Simulation time 823306856 ps
CPU time 8.36 seconds
Started Jul 15 06:23:32 PM PDT 24
Finished Jul 15 06:23:41 PM PDT 24
Peak memory 225560 kb
Host smart-ebf5810a-7d3e-42d9-ae75-5f1d5dcc81b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057695606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3057695606
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.294872996
Short name T884
Test name
Test status
Simulation time 153119241 ps
CPU time 2.34 seconds
Started Jul 15 06:23:30 PM PDT 24
Finished Jul 15 06:23:34 PM PDT 24
Peak memory 225552 kb
Host smart-94b2273c-a7d8-44fd-959e-6f3d173211cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294872996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.294872996
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.19269889
Short name T843
Test name
Test status
Simulation time 16393945 ps
CPU time 1.03 seconds
Started Jul 15 06:23:29 PM PDT 24
Finished Jul 15 06:23:31 PM PDT 24
Peak memory 218952 kb
Host smart-fa48b50b-6c23-4073-be2d-3fa5886fe777
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19269889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.19269889
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.908533538
Short name T631
Test name
Test status
Simulation time 101621265 ps
CPU time 2.5 seconds
Started Jul 15 06:23:32 PM PDT 24
Finished Jul 15 06:23:35 PM PDT 24
Peak memory 233548 kb
Host smart-bd7ded39-f760-4f76-9bd8-f074abecf655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908533538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
908533538
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1365857245
Short name T572
Test name
Test status
Simulation time 77657132 ps
CPU time 2.32 seconds
Started Jul 15 06:23:30 PM PDT 24
Finished Jul 15 06:23:33 PM PDT 24
Peak memory 224860 kb
Host smart-55ee0fe1-b0e7-4c2f-93eb-464f4e28f72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365857245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1365857245
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.601656876
Short name T38
Test name
Test status
Simulation time 616799135 ps
CPU time 9.98 seconds
Started Jul 15 06:23:31 PM PDT 24
Finished Jul 15 06:23:42 PM PDT 24
Peak memory 221420 kb
Host smart-a635664d-ecb1-453c-bf14-28e582bae9bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=601656876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.601656876
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1093245304
Short name T67
Test name
Test status
Simulation time 255176745 ps
CPU time 1.02 seconds
Started Jul 15 06:23:30 PM PDT 24
Finished Jul 15 06:23:32 PM PDT 24
Peak memory 236508 kb
Host smart-8ffb765c-dc88-493c-870b-574538139132
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093245304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1093245304
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.4086767269
Short name T18
Test name
Test status
Simulation time 8822860118 ps
CPU time 47.32 seconds
Started Jul 15 06:23:29 PM PDT 24
Finished Jul 15 06:24:18 PM PDT 24
Peak memory 256716 kb
Host smart-eef5a620-786b-4cd7-80d8-2671e6f98870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086767269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.4086767269
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2579491631
Short name T528
Test name
Test status
Simulation time 6930222934 ps
CPU time 38.41 seconds
Started Jul 15 06:23:33 PM PDT 24
Finished Jul 15 06:24:12 PM PDT 24
Peak memory 217396 kb
Host smart-b8ae53ab-0606-4f1f-8782-43b2860c0817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579491631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2579491631
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4187856316
Short name T75
Test name
Test status
Simulation time 1534741749 ps
CPU time 7.49 seconds
Started Jul 15 06:23:31 PM PDT 24
Finished Jul 15 06:23:39 PM PDT 24
Peak memory 217340 kb
Host smart-a68ebbbc-03a6-45f4-af5b-bdedd5d7e7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187856316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4187856316
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3528608795
Short name T596
Test name
Test status
Simulation time 88338184 ps
CPU time 2.02 seconds
Started Jul 15 06:23:31 PM PDT 24
Finished Jul 15 06:23:34 PM PDT 24
Peak memory 217368 kb
Host smart-214099e4-cb2f-48c7-a813-99b015bf5045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528608795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3528608795
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3165317371
Short name T420
Test name
Test status
Simulation time 73272519 ps
CPU time 0.82 seconds
Started Jul 15 06:23:31 PM PDT 24
Finished Jul 15 06:23:32 PM PDT 24
Peak memory 206908 kb
Host smart-95acf60c-b14b-4b7d-ade6-e48a15bc5226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165317371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3165317371
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2211695274
Short name T777
Test name
Test status
Simulation time 853616672 ps
CPU time 5.06 seconds
Started Jul 15 06:23:30 PM PDT 24
Finished Jul 15 06:23:36 PM PDT 24
Peak memory 233692 kb
Host smart-c191f767-2687-45a4-8405-b17d42617547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211695274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2211695274
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2321713802
Short name T430
Test name
Test status
Simulation time 12482556 ps
CPU time 0.71 seconds
Started Jul 15 06:25:28 PM PDT 24
Finished Jul 15 06:25:29 PM PDT 24
Peak memory 205792 kb
Host smart-97ba405b-e6b3-4519-8373-bf3728c2746f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321713802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2321713802
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.478245251
Short name T745
Test name
Test status
Simulation time 3032768392 ps
CPU time 11.03 seconds
Started Jul 15 06:25:29 PM PDT 24
Finished Jul 15 06:25:40 PM PDT 24
Peak memory 233796 kb
Host smart-0832e55b-7093-4b44-bd8b-021cb3981f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478245251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.478245251
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1777262505
Short name T357
Test name
Test status
Simulation time 22839415 ps
CPU time 0.83 seconds
Started Jul 15 06:25:22 PM PDT 24
Finished Jul 15 06:25:24 PM PDT 24
Peak memory 207520 kb
Host smart-d3b17aef-3e0c-465a-b9dc-25334329d5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777262505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1777262505
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.99243868
Short name T697
Test name
Test status
Simulation time 9008233997 ps
CPU time 64.31 seconds
Started Jul 15 06:25:32 PM PDT 24
Finished Jul 15 06:26:37 PM PDT 24
Peak memory 250336 kb
Host smart-d1351b74-824a-4d54-bd08-185e50172304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99243868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.99243868
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2502987281
Short name T186
Test name
Test status
Simulation time 28622934717 ps
CPU time 36.06 seconds
Started Jul 15 06:25:29 PM PDT 24
Finished Jul 15 06:26:05 PM PDT 24
Peak memory 238936 kb
Host smart-6f21ee0f-de99-4c05-a095-66a3a75bd637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502987281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2502987281
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3221288974
Short name T309
Test name
Test status
Simulation time 390122329 ps
CPU time 7.57 seconds
Started Jul 15 06:25:30 PM PDT 24
Finished Jul 15 06:25:38 PM PDT 24
Peak memory 235564 kb
Host smart-338c070e-ea4c-4201-822c-f8113d41fd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221288974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3221288974
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.255139257
Short name T90
Test name
Test status
Simulation time 11856830070 ps
CPU time 83.67 seconds
Started Jul 15 06:25:32 PM PDT 24
Finished Jul 15 06:26:56 PM PDT 24
Peak memory 253224 kb
Host smart-f05f711a-052a-4995-82c8-3285b4ef4553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255139257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.255139257
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3768522017
Short name T823
Test name
Test status
Simulation time 1956810022 ps
CPU time 16.08 seconds
Started Jul 15 06:25:30 PM PDT 24
Finished Jul 15 06:25:47 PM PDT 24
Peak memory 225568 kb
Host smart-f0427e8e-5043-489e-8233-e6d3efb8a420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768522017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3768522017
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3757974505
Short name T245
Test name
Test status
Simulation time 2001049611 ps
CPU time 7.75 seconds
Started Jul 15 06:25:30 PM PDT 24
Finished Jul 15 06:25:38 PM PDT 24
Peak memory 225560 kb
Host smart-f764c47e-a1bf-4d0d-b6c4-096ac7a18aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757974505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3757974505
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3443433509
Short name T591
Test name
Test status
Simulation time 11108479141 ps
CPU time 23.79 seconds
Started Jul 15 06:25:29 PM PDT 24
Finished Jul 15 06:25:53 PM PDT 24
Peak memory 233876 kb
Host smart-0251278c-2269-425a-912d-09d1ece7d9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443433509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3443433509
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.245057985
Short name T579
Test name
Test status
Simulation time 454977995 ps
CPU time 3.22 seconds
Started Jul 15 06:25:30 PM PDT 24
Finished Jul 15 06:25:34 PM PDT 24
Peak memory 225604 kb
Host smart-029eb34f-0f7b-4c09-be24-058c04f344dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245057985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.245057985
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1179030486
Short name T155
Test name
Test status
Simulation time 2825294694 ps
CPU time 5.81 seconds
Started Jul 15 06:25:29 PM PDT 24
Finished Jul 15 06:25:35 PM PDT 24
Peak memory 220472 kb
Host smart-2df5b60b-78aa-45c7-92c8-fe40735d211a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1179030486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1179030486
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1810610621
Short name T278
Test name
Test status
Simulation time 15152280021 ps
CPU time 145.04 seconds
Started Jul 15 06:25:31 PM PDT 24
Finished Jul 15 06:27:57 PM PDT 24
Peak memory 258580 kb
Host smart-b4b45063-5ed3-4dbc-ae7b-f57b682d3e42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810610621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1810610621
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3929932398
Short name T983
Test name
Test status
Simulation time 1245695697 ps
CPU time 2.31 seconds
Started Jul 15 06:25:21 PM PDT 24
Finished Jul 15 06:25:24 PM PDT 24
Peak memory 217676 kb
Host smart-c14db01e-5255-4c59-aca7-3ce6dc49c51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929932398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3929932398
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3788540891
Short name T886
Test name
Test status
Simulation time 20199998292 ps
CPU time 6.43 seconds
Started Jul 15 06:25:22 PM PDT 24
Finished Jul 15 06:25:29 PM PDT 24
Peak memory 217488 kb
Host smart-d67422d5-4640-4f18-ad80-76723332b018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788540891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3788540891
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.791254515
Short name T855
Test name
Test status
Simulation time 101522321 ps
CPU time 1.95 seconds
Started Jul 15 06:25:23 PM PDT 24
Finished Jul 15 06:25:25 PM PDT 24
Peak memory 216768 kb
Host smart-30c184e4-b46c-4652-9f92-5f090da14995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791254515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.791254515
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1633508399
Short name T371
Test name
Test status
Simulation time 335268881 ps
CPU time 0.97 seconds
Started Jul 15 06:25:22 PM PDT 24
Finished Jul 15 06:25:24 PM PDT 24
Peak memory 207960 kb
Host smart-14881d5a-e4b4-4630-9037-0810e3cfc0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633508399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1633508399
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.345967946
Short name T874
Test name
Test status
Simulation time 2810263243 ps
CPU time 11.37 seconds
Started Jul 15 06:25:34 PM PDT 24
Finished Jul 15 06:25:46 PM PDT 24
Peak memory 233880 kb
Host smart-9a0a1d75-cf30-4bac-840d-1dc4b815c6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345967946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.345967946
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1213487759
Short name T710
Test name
Test status
Simulation time 20782346 ps
CPU time 0.75 seconds
Started Jul 15 06:25:35 PM PDT 24
Finished Jul 15 06:25:36 PM PDT 24
Peak memory 206332 kb
Host smart-d07151e5-78d8-4af3-8fab-bc51bc102063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213487759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1213487759
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1293166356
Short name T167
Test name
Test status
Simulation time 276006272 ps
CPU time 5.85 seconds
Started Jul 15 06:25:30 PM PDT 24
Finished Jul 15 06:25:36 PM PDT 24
Peak memory 233764 kb
Host smart-2e1e20b8-dbba-4e75-888d-d8ad3e78a6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293166356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1293166356
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1110029802
Short name T615
Test name
Test status
Simulation time 48854826 ps
CPU time 0.81 seconds
Started Jul 15 06:25:27 PM PDT 24
Finished Jul 15 06:25:29 PM PDT 24
Peak memory 207532 kb
Host smart-232e423c-c774-4081-92ca-31b063e0fe32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110029802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1110029802
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.311683636
Short name T797
Test name
Test status
Simulation time 20614506673 ps
CPU time 157.84 seconds
Started Jul 15 06:25:34 PM PDT 24
Finished Jul 15 06:28:12 PM PDT 24
Peak memory 250380 kb
Host smart-a925c034-ea97-4484-8f71-fb569d0a30ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311683636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.311683636
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2155614067
Short name T917
Test name
Test status
Simulation time 369962321573 ps
CPU time 833.08 seconds
Started Jul 15 06:25:35 PM PDT 24
Finished Jul 15 06:39:29 PM PDT 24
Peak memory 269528 kb
Host smart-8f8bd971-20ca-4fbc-8ce7-2a9ac91e36db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155614067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2155614067
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2980441862
Short name T850
Test name
Test status
Simulation time 6117201899 ps
CPU time 34.89 seconds
Started Jul 15 06:25:28 PM PDT 24
Finished Jul 15 06:26:03 PM PDT 24
Peak memory 225704 kb
Host smart-b4c57786-f710-4df9-ae02-f36d6cfc7061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980441862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2980441862
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2081486769
Short name T1012
Test name
Test status
Simulation time 2189289233 ps
CPU time 44.3 seconds
Started Jul 15 06:25:33 PM PDT 24
Finished Jul 15 06:26:17 PM PDT 24
Peak memory 233892 kb
Host smart-88ddec24-ab19-4632-ba29-db823bbbc7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081486769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2081486769
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3061812127
Short name T931
Test name
Test status
Simulation time 2202702661 ps
CPU time 9.31 seconds
Started Jul 15 06:25:29 PM PDT 24
Finished Jul 15 06:25:38 PM PDT 24
Peak memory 233960 kb
Host smart-18b49901-4910-4c32-93e5-fe8afc94f17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061812127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3061812127
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1643713248
Short name T729
Test name
Test status
Simulation time 3502281197 ps
CPU time 9.86 seconds
Started Jul 15 06:25:27 PM PDT 24
Finished Jul 15 06:25:38 PM PDT 24
Peak memory 235372 kb
Host smart-c425db61-23af-4631-bbe4-2d9bc2438cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643713248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1643713248
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3221487514
Short name T11
Test name
Test status
Simulation time 647488205 ps
CPU time 4.05 seconds
Started Jul 15 06:25:30 PM PDT 24
Finished Jul 15 06:25:34 PM PDT 24
Peak memory 225492 kb
Host smart-65fa9c36-3c27-4dab-8248-310379e06d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221487514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3221487514
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4089579196
Short name T367
Test name
Test status
Simulation time 1429669574 ps
CPU time 19.09 seconds
Started Jul 15 06:25:28 PM PDT 24
Finished Jul 15 06:25:48 PM PDT 24
Peak memory 220000 kb
Host smart-26b8504c-9d64-4747-94c7-1089ebe42261
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4089579196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4089579196
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2360083402
Short name T322
Test name
Test status
Simulation time 41747367243 ps
CPU time 46.66 seconds
Started Jul 15 06:25:28 PM PDT 24
Finished Jul 15 06:26:16 PM PDT 24
Peak memory 221840 kb
Host smart-b4ca9d01-d662-40d5-9d86-040182e80374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360083402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2360083402
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.965345369
Short name T873
Test name
Test status
Simulation time 1558667856 ps
CPU time 4.84 seconds
Started Jul 15 06:25:27 PM PDT 24
Finished Jul 15 06:25:33 PM PDT 24
Peak memory 217336 kb
Host smart-e4a99a8f-632e-46f7-948e-6fd5751dae7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965345369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.965345369
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.820568663
Short name T978
Test name
Test status
Simulation time 265801224 ps
CPU time 1.04 seconds
Started Jul 15 06:25:32 PM PDT 24
Finished Jul 15 06:25:34 PM PDT 24
Peak memory 208132 kb
Host smart-f372ca27-50e9-4874-a384-3e5612119de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820568663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.820568663
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.921392954
Short name T712
Test name
Test status
Simulation time 10764043 ps
CPU time 0.7 seconds
Started Jul 15 06:25:27 PM PDT 24
Finished Jul 15 06:25:29 PM PDT 24
Peak memory 206528 kb
Host smart-93f90fd1-64ed-4b90-a62d-4494b83d9192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921392954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.921392954
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3612446147
Short name T135
Test name
Test status
Simulation time 494598160 ps
CPU time 4.45 seconds
Started Jul 15 06:25:27 PM PDT 24
Finished Jul 15 06:25:32 PM PDT 24
Peak memory 225464 kb
Host smart-961ed653-03fd-413b-9455-91dcae951642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612446147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3612446147
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.425049029
Short name T386
Test name
Test status
Simulation time 29147085 ps
CPU time 0.68 seconds
Started Jul 15 06:25:37 PM PDT 24
Finished Jul 15 06:25:38 PM PDT 24
Peak memory 206372 kb
Host smart-8b19d8ab-066d-4608-86f5-e159b7f91817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425049029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.425049029
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.4227279102
Short name T692
Test name
Test status
Simulation time 973098153 ps
CPU time 4.26 seconds
Started Jul 15 06:25:35 PM PDT 24
Finished Jul 15 06:25:40 PM PDT 24
Peak memory 225564 kb
Host smart-fcd962b7-b133-4275-b096-70091e66af2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227279102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.4227279102
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2088284804
Short name T789
Test name
Test status
Simulation time 18044197 ps
CPU time 0.81 seconds
Started Jul 15 06:25:35 PM PDT 24
Finished Jul 15 06:25:37 PM PDT 24
Peak memory 207508 kb
Host smart-638b18f6-abf4-4442-a4d5-6aaa699e0385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088284804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2088284804
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2715863787
Short name T829
Test name
Test status
Simulation time 89644957174 ps
CPU time 135.46 seconds
Started Jul 15 06:25:36 PM PDT 24
Finished Jul 15 06:27:52 PM PDT 24
Peak memory 255060 kb
Host smart-1725109f-2083-4230-8d3e-bcf2d3f22c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715863787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2715863787
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3695232263
Short name T55
Test name
Test status
Simulation time 10192967753 ps
CPU time 106.8 seconds
Started Jul 15 06:25:33 PM PDT 24
Finished Jul 15 06:27:20 PM PDT 24
Peak memory 264940 kb
Host smart-303baf42-a667-41b4-abac-a5245731f743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695232263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3695232263
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.492192706
Short name T413
Test name
Test status
Simulation time 450819339365 ps
CPU time 209.07 seconds
Started Jul 15 06:25:37 PM PDT 24
Finished Jul 15 06:29:07 PM PDT 24
Peak memory 250360 kb
Host smart-c11c6c5d-4e20-4e70-af33-bdc960f30203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492192706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.492192706
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2597415726
Short name T37
Test name
Test status
Simulation time 1748915183 ps
CPU time 24.55 seconds
Started Jul 15 06:25:33 PM PDT 24
Finished Jul 15 06:25:58 PM PDT 24
Peak memory 254280 kb
Host smart-19015200-a953-4d9b-8d3c-b84b3b8c4f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597415726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2597415726
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2848238403
Short name T1006
Test name
Test status
Simulation time 3638529775 ps
CPU time 8.64 seconds
Started Jul 15 06:25:36 PM PDT 24
Finished Jul 15 06:25:45 PM PDT 24
Peak memory 233912 kb
Host smart-dfd589d5-6ca5-4b11-b39e-aad85200dbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848238403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2848238403
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3552687426
Short name T431
Test name
Test status
Simulation time 94114498 ps
CPU time 2.93 seconds
Started Jul 15 06:25:35 PM PDT 24
Finished Jul 15 06:25:38 PM PDT 24
Peak memory 225476 kb
Host smart-34493d84-affa-404c-acb5-eeb23d8088fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552687426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3552687426
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1995446921
Short name T434
Test name
Test status
Simulation time 609322370 ps
CPU time 2.57 seconds
Started Jul 15 06:25:34 PM PDT 24
Finished Jul 15 06:25:37 PM PDT 24
Peak memory 225560 kb
Host smart-b140aaee-3900-4538-8ada-25520cd8a40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995446921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1995446921
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4226381298
Short name T233
Test name
Test status
Simulation time 4604723900 ps
CPU time 17.17 seconds
Started Jul 15 06:25:33 PM PDT 24
Finished Jul 15 06:25:51 PM PDT 24
Peak memory 250332 kb
Host smart-cdce792e-8183-4f21-aaaf-5c10e817265c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226381298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4226381298
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3861592443
Short name T564
Test name
Test status
Simulation time 177814047 ps
CPU time 4.68 seconds
Started Jul 15 06:25:36 PM PDT 24
Finished Jul 15 06:25:42 PM PDT 24
Peak memory 220324 kb
Host smart-68c4407f-a9b9-434a-b34d-945dd37b97bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3861592443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3861592443
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2537809119
Short name T808
Test name
Test status
Simulation time 38822620292 ps
CPU time 239.55 seconds
Started Jul 15 06:25:38 PM PDT 24
Finished Jul 15 06:29:39 PM PDT 24
Peak memory 266464 kb
Host smart-9581d90d-7080-4c25-935c-aa20a463d5c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537809119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2537809119
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.84907168
Short name T133
Test name
Test status
Simulation time 2558186056 ps
CPU time 7.48 seconds
Started Jul 15 06:25:37 PM PDT 24
Finished Jul 15 06:25:45 PM PDT 24
Peak memory 217420 kb
Host smart-9af115a3-c985-4732-af1a-421568d89713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84907168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.84907168
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1466200955
Short name T545
Test name
Test status
Simulation time 47526314517 ps
CPU time 21.1 seconds
Started Jul 15 06:25:36 PM PDT 24
Finished Jul 15 06:25:58 PM PDT 24
Peak memory 217464 kb
Host smart-fc81764a-0dd2-4f90-82a6-46fa1582b0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466200955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1466200955
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1371523744
Short name T971
Test name
Test status
Simulation time 226822235 ps
CPU time 7.27 seconds
Started Jul 15 06:25:35 PM PDT 24
Finished Jul 15 06:25:43 PM PDT 24
Peak memory 217340 kb
Host smart-2516d747-a79b-4d06-8120-c4518c8bba3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371523744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1371523744
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3970783767
Short name T1003
Test name
Test status
Simulation time 95462105 ps
CPU time 0.81 seconds
Started Jul 15 06:25:36 PM PDT 24
Finished Jul 15 06:25:38 PM PDT 24
Peak memory 206948 kb
Host smart-873c9e93-b0fc-4a4c-8ab1-1e3b3f00f311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970783767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3970783767
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.65140901
Short name T650
Test name
Test status
Simulation time 3982718012 ps
CPU time 6.43 seconds
Started Jul 15 06:25:33 PM PDT 24
Finished Jul 15 06:25:40 PM PDT 24
Peak memory 233776 kb
Host smart-462d4fe8-2cff-4667-8438-9a73f225ed6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65140901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.65140901
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.711717214
Short name T351
Test name
Test status
Simulation time 23041546 ps
CPU time 0.81 seconds
Started Jul 15 06:25:38 PM PDT 24
Finished Jul 15 06:25:40 PM PDT 24
Peak memory 205804 kb
Host smart-3f572c86-d011-4b00-b4e2-d755b09f073b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711717214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.711717214
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1151718946
Short name T543
Test name
Test status
Simulation time 199722535 ps
CPU time 2.77 seconds
Started Jul 15 06:25:40 PM PDT 24
Finished Jul 15 06:25:44 PM PDT 24
Peak memory 233712 kb
Host smart-9ca3bee6-cc58-4537-b31f-af6b899fd86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151718946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1151718946
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.72439968
Short name T379
Test name
Test status
Simulation time 18750192 ps
CPU time 0.8 seconds
Started Jul 15 06:25:36 PM PDT 24
Finished Jul 15 06:25:38 PM PDT 24
Peak memory 207492 kb
Host smart-9a0e4ef4-3bb0-4b4a-b546-af5ad82eb1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72439968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.72439968
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.152521633
Short name T443
Test name
Test status
Simulation time 19867475700 ps
CPU time 40.29 seconds
Started Jul 15 06:25:42 PM PDT 24
Finished Jul 15 06:26:22 PM PDT 24
Peak memory 225664 kb
Host smart-53720e1a-2999-4087-adc1-46eab680e2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152521633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.152521633
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2526509673
Short name T571
Test name
Test status
Simulation time 9936011164 ps
CPU time 48.53 seconds
Started Jul 15 06:25:39 PM PDT 24
Finished Jul 15 06:26:29 PM PDT 24
Peak memory 250540 kb
Host smart-986fbef3-8a9f-4cbd-b541-5293e48c5a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526509673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2526509673
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.165381530
Short name T174
Test name
Test status
Simulation time 208030929166 ps
CPU time 344.51 seconds
Started Jul 15 06:25:37 PM PDT 24
Finished Jul 15 06:31:23 PM PDT 24
Peak memory 257184 kb
Host smart-ac076579-e81d-44e6-84b4-f63d4fef0181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165381530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.165381530
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1960336001
Short name T709
Test name
Test status
Simulation time 289127368 ps
CPU time 6.7 seconds
Started Jul 15 06:25:39 PM PDT 24
Finished Jul 15 06:25:46 PM PDT 24
Peak memory 225568 kb
Host smart-02b0d10d-14e1-47aa-9708-6862003ed827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960336001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1960336001
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1597438307
Short name T916
Test name
Test status
Simulation time 18802350800 ps
CPU time 142.65 seconds
Started Jul 15 06:25:38 PM PDT 24
Finished Jul 15 06:28:02 PM PDT 24
Peak memory 250308 kb
Host smart-292b6f28-6327-4da7-8dcb-7160937edefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597438307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1597438307
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2481070399
Short name T581
Test name
Test status
Simulation time 8300114658 ps
CPU time 7.45 seconds
Started Jul 15 06:25:41 PM PDT 24
Finished Jul 15 06:25:49 PM PDT 24
Peak memory 233884 kb
Host smart-e0e4b652-7ed8-42b6-ba0a-923255445434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481070399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2481070399
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3992748090
Short name T119
Test name
Test status
Simulation time 15714282394 ps
CPU time 61.93 seconds
Started Jul 15 06:25:41 PM PDT 24
Finished Jul 15 06:26:44 PM PDT 24
Peak memory 242108 kb
Host smart-42056f1b-b9eb-47cc-a3af-190289f6ee1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992748090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3992748090
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3811044265
Short name T481
Test name
Test status
Simulation time 13178786255 ps
CPU time 12.42 seconds
Started Jul 15 06:25:38 PM PDT 24
Finished Jul 15 06:25:51 PM PDT 24
Peak memory 225688 kb
Host smart-80761c8f-8be2-480c-b7a6-9e0e7ea1fad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811044265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3811044265
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.559220689
Short name T337
Test name
Test status
Simulation time 484937503 ps
CPU time 2.12 seconds
Started Jul 15 06:25:41 PM PDT 24
Finished Jul 15 06:25:44 PM PDT 24
Peak memory 224672 kb
Host smart-8ea75514-f738-45dc-933f-486d2971766c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559220689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.559220689
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1997400438
Short name T380
Test name
Test status
Simulation time 713344771 ps
CPU time 9.44 seconds
Started Jul 15 06:25:41 PM PDT 24
Finished Jul 15 06:25:51 PM PDT 24
Peak memory 223272 kb
Host smart-9c4c187b-79a1-4ac5-ad38-d8a6a7c6dc54
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1997400438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1997400438
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.966617356
Short name T190
Test name
Test status
Simulation time 1568268994 ps
CPU time 36.44 seconds
Started Jul 15 06:25:43 PM PDT 24
Finished Jul 15 06:26:20 PM PDT 24
Peak memory 241516 kb
Host smart-d0f98918-d008-431e-ad91-5ad86dfa8c9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966617356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.966617356
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.36360989
Short name T765
Test name
Test status
Simulation time 35514253 ps
CPU time 0.7 seconds
Started Jul 15 06:25:39 PM PDT 24
Finished Jul 15 06:25:41 PM PDT 24
Peak memory 206664 kb
Host smart-738436d6-ca36-4b9a-a31c-f5d1d92f5ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36360989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.36360989
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.4096962953
Short name T462
Test name
Test status
Simulation time 13603941128 ps
CPU time 11.02 seconds
Started Jul 15 06:25:34 PM PDT 24
Finished Jul 15 06:25:45 PM PDT 24
Peak memory 217424 kb
Host smart-478e6b77-c570-4222-83cc-e20561e7cbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096962953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.4096962953
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3711079966
Short name T988
Test name
Test status
Simulation time 186364336 ps
CPU time 1.81 seconds
Started Jul 15 06:25:39 PM PDT 24
Finished Jul 15 06:25:41 PM PDT 24
Peak memory 217364 kb
Host smart-1ca9482c-f1a6-4d00-889d-003ffeb2918e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711079966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3711079966
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.540044663
Short name T623
Test name
Test status
Simulation time 16333943 ps
CPU time 0.7 seconds
Started Jul 15 06:25:39 PM PDT 24
Finished Jul 15 06:25:40 PM PDT 24
Peak memory 206512 kb
Host smart-9079a3d6-7034-4aef-bcea-49e308ec49b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540044663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.540044663
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1981250344
Short name T411
Test name
Test status
Simulation time 3922893070 ps
CPU time 5.05 seconds
Started Jul 15 06:25:40 PM PDT 24
Finished Jul 15 06:25:46 PM PDT 24
Peak memory 225624 kb
Host smart-c0d05ecb-716e-45dd-92d9-d2008277c702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981250344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1981250344
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2512866430
Short name T799
Test name
Test status
Simulation time 11116587 ps
CPU time 0.75 seconds
Started Jul 15 06:25:46 PM PDT 24
Finished Jul 15 06:25:48 PM PDT 24
Peak memory 206704 kb
Host smart-c44b3c2d-b955-40f6-9800-811e7c31332e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512866430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2512866430
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3669312975
Short name T89
Test name
Test status
Simulation time 5695193563 ps
CPU time 14.01 seconds
Started Jul 15 06:25:41 PM PDT 24
Finished Jul 15 06:25:55 PM PDT 24
Peak memory 233924 kb
Host smart-5f4a9ee2-4473-4675-a4fd-bdf83953b806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669312975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3669312975
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2115656622
Short name T812
Test name
Test status
Simulation time 46833191 ps
CPU time 0.8 seconds
Started Jul 15 06:25:40 PM PDT 24
Finished Jul 15 06:25:41 PM PDT 24
Peak memory 207800 kb
Host smart-264fff71-ff94-4ee8-9d28-732b228e4e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115656622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2115656622
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1122178962
Short name T689
Test name
Test status
Simulation time 109643309973 ps
CPU time 238.27 seconds
Started Jul 15 06:25:39 PM PDT 24
Finished Jul 15 06:29:38 PM PDT 24
Peak memory 258500 kb
Host smart-2ca5c601-6b13-4dda-9d3f-35bfa2402b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122178962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1122178962
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.274858279
Short name T698
Test name
Test status
Simulation time 6923530975 ps
CPU time 97.77 seconds
Started Jul 15 06:25:40 PM PDT 24
Finished Jul 15 06:27:18 PM PDT 24
Peak memory 250420 kb
Host smart-bca57969-8511-45aa-928f-b430621dd03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274858279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.274858279
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.10186274
Short name T608
Test name
Test status
Simulation time 13128301938 ps
CPU time 153.2 seconds
Started Jul 15 06:25:39 PM PDT 24
Finished Jul 15 06:28:14 PM PDT 24
Peak memory 270328 kb
Host smart-dbf4c49c-a68e-41fe-bb13-f69a951d987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10186274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.10186274
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.650894609
Short name T47
Test name
Test status
Simulation time 193404144 ps
CPU time 4.38 seconds
Started Jul 15 06:25:40 PM PDT 24
Finished Jul 15 06:25:45 PM PDT 24
Peak memory 225556 kb
Host smart-be21abd4-bac5-4cf1-8ee0-cec36ebe2ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650894609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.650894609
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2597775176
Short name T266
Test name
Test status
Simulation time 6102819017 ps
CPU time 65.25 seconds
Started Jul 15 06:25:42 PM PDT 24
Finished Jul 15 06:26:48 PM PDT 24
Peak memory 266668 kb
Host smart-8db9ef05-5e82-4f26-818e-68c1976e6b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597775176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2597775176
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4292257252
Short name T609
Test name
Test status
Simulation time 32541659 ps
CPU time 2.51 seconds
Started Jul 15 06:25:43 PM PDT 24
Finished Jul 15 06:25:46 PM PDT 24
Peak memory 233464 kb
Host smart-978d8b69-3014-4542-95f3-836fc3133684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292257252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4292257252
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3554721545
Short name T106
Test name
Test status
Simulation time 6635653725 ps
CPU time 51.02 seconds
Started Jul 15 06:25:38 PM PDT 24
Finished Jul 15 06:26:30 PM PDT 24
Peak memory 233848 kb
Host smart-1639c7b2-8781-4944-b7f7-7fa5d35dc13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554721545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3554721545
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1462807177
Short name T446
Test name
Test status
Simulation time 278621692 ps
CPU time 2.8 seconds
Started Jul 15 06:25:41 PM PDT 24
Finished Jul 15 06:25:45 PM PDT 24
Peak memory 233744 kb
Host smart-ae4afb52-66f0-437d-b0f5-611d7ca03257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462807177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1462807177
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3017358551
Short name T600
Test name
Test status
Simulation time 132935044 ps
CPU time 2.7 seconds
Started Jul 15 06:25:37 PM PDT 24
Finished Jul 15 06:25:41 PM PDT 24
Peak memory 225532 kb
Host smart-bc80ee2e-9460-4220-99ae-80bb473fa9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017358551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3017358551
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3728733969
Short name T832
Test name
Test status
Simulation time 3238621823 ps
CPU time 10.63 seconds
Started Jul 15 06:25:43 PM PDT 24
Finished Jul 15 06:25:54 PM PDT 24
Peak memory 220296 kb
Host smart-fed5ba5c-912d-4fb0-9a3d-3124c9da231a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3728733969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3728733969
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.364558434
Short name T837
Test name
Test status
Simulation time 6994754701 ps
CPU time 19.5 seconds
Started Jul 15 06:25:45 PM PDT 24
Finished Jul 15 06:26:06 PM PDT 24
Peak memory 225848 kb
Host smart-35c1c00f-f3d6-4a1a-afeb-0eab95646d9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364558434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.364558434
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2707743544
Short name T461
Test name
Test status
Simulation time 2456340353 ps
CPU time 24.03 seconds
Started Jul 15 06:25:37 PM PDT 24
Finished Jul 15 06:26:03 PM PDT 24
Peak memory 217488 kb
Host smart-dfe545a3-367f-4f00-9361-ec24ff23ebf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707743544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2707743544
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.63661327
Short name T2
Test name
Test status
Simulation time 19274972943 ps
CPU time 18.82 seconds
Started Jul 15 06:25:38 PM PDT 24
Finished Jul 15 06:25:58 PM PDT 24
Peak memory 217460 kb
Host smart-54857d45-b0a1-4a0b-80f7-3b7746520210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63661327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.63661327
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.824357620
Short name T949
Test name
Test status
Simulation time 786686041 ps
CPU time 4.64 seconds
Started Jul 15 06:25:38 PM PDT 24
Finished Jul 15 06:25:44 PM PDT 24
Peak memory 217360 kb
Host smart-fb3b7d79-b46b-4ce9-8290-a606d10e5aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824357620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.824357620
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3720504096
Short name T807
Test name
Test status
Simulation time 155485735 ps
CPU time 0.87 seconds
Started Jul 15 06:25:39 PM PDT 24
Finished Jul 15 06:25:41 PM PDT 24
Peak memory 206916 kb
Host smart-6ee844ff-774c-4741-99cc-7e91a87c5537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720504096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3720504096
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.4104950193
Short name T396
Test name
Test status
Simulation time 871515377 ps
CPU time 2.41 seconds
Started Jul 15 06:25:43 PM PDT 24
Finished Jul 15 06:25:46 PM PDT 24
Peak memory 224316 kb
Host smart-ce1e6694-d85b-4e6b-a13f-87f4ad0f4184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104950193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4104950193
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.249307260
Short name T7
Test name
Test status
Simulation time 15970906 ps
CPU time 0.7 seconds
Started Jul 15 06:25:49 PM PDT 24
Finished Jul 15 06:25:51 PM PDT 24
Peak memory 206340 kb
Host smart-351c33dc-927d-4449-aa58-eac9e5a530ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249307260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.249307260
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2120642232
Short name T406
Test name
Test status
Simulation time 4349740031 ps
CPU time 6.08 seconds
Started Jul 15 06:25:45 PM PDT 24
Finished Jul 15 06:25:52 PM PDT 24
Peak memory 233824 kb
Host smart-cba0cbb5-d6b8-4b70-b92e-bd7224c1884d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120642232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2120642232
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1870038307
Short name T755
Test name
Test status
Simulation time 34519652 ps
CPU time 0.77 seconds
Started Jul 15 06:25:45 PM PDT 24
Finished Jul 15 06:25:47 PM PDT 24
Peak memory 207508 kb
Host smart-1767db3f-b90a-4d01-92d9-4cdac4782802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870038307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1870038307
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1445413503
Short name T197
Test name
Test status
Simulation time 8063400916 ps
CPU time 106.94 seconds
Started Jul 15 06:25:44 PM PDT 24
Finished Jul 15 06:27:32 PM PDT 24
Peak memory 251264 kb
Host smart-259d0160-8a9a-49d1-9b27-b520d5176e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445413503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1445413503
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3014427833
Short name T304
Test name
Test status
Simulation time 1105924738 ps
CPU time 20.87 seconds
Started Jul 15 06:25:46 PM PDT 24
Finished Jul 15 06:26:08 PM PDT 24
Peak memory 254008 kb
Host smart-93d0febf-6943-41a9-8f90-e6e180721772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014427833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3014427833
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.9930786
Short name T468
Test name
Test status
Simulation time 143903732399 ps
CPU time 310.98 seconds
Started Jul 15 06:25:48 PM PDT 24
Finished Jul 15 06:31:00 PM PDT 24
Peak memory 265928 kb
Host smart-4339f02f-78c6-452e-934b-58454fa53e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9930786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.9930786
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3767655650
Short name T845
Test name
Test status
Simulation time 274134234 ps
CPU time 5.9 seconds
Started Jul 15 06:25:45 PM PDT 24
Finished Jul 15 06:25:52 PM PDT 24
Peak memory 250168 kb
Host smart-d5750f62-6e5b-4f22-b07d-61f8afbafce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767655650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3767655650
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.42995501
Short name T619
Test name
Test status
Simulation time 8817937455 ps
CPU time 20.64 seconds
Started Jul 15 06:25:56 PM PDT 24
Finished Jul 15 06:26:17 PM PDT 24
Peak memory 222500 kb
Host smart-5566babc-e8ee-460d-b637-94d825ebd18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42995501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.42995501
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.409135012
Short name T691
Test name
Test status
Simulation time 1106456498 ps
CPU time 4.89 seconds
Started Jul 15 06:25:43 PM PDT 24
Finished Jul 15 06:25:49 PM PDT 24
Peak memory 233728 kb
Host smart-0caeeca3-f40d-4b35-a7a2-9b74d16bd325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409135012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.409135012
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1361440508
Short name T176
Test name
Test status
Simulation time 5221036809 ps
CPU time 44.01 seconds
Started Jul 15 06:25:45 PM PDT 24
Finished Jul 15 06:26:30 PM PDT 24
Peak memory 225700 kb
Host smart-a14cbb59-699a-4ecc-9c01-fa92b84fb909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361440508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1361440508
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2389384158
Short name T1021
Test name
Test status
Simulation time 52810838 ps
CPU time 2.66 seconds
Started Jul 15 06:25:44 PM PDT 24
Finished Jul 15 06:25:47 PM PDT 24
Peak memory 233776 kb
Host smart-af168ce4-e0d6-48de-a8f7-383e59b66bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389384158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2389384158
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1646679886
Short name T3
Test name
Test status
Simulation time 849586936 ps
CPU time 2.84 seconds
Started Jul 15 06:25:45 PM PDT 24
Finished Jul 15 06:25:49 PM PDT 24
Peak memory 225600 kb
Host smart-004ac495-7f9d-4814-abca-724c39a81c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646679886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1646679886
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.818563428
Short name T838
Test name
Test status
Simulation time 1196580212 ps
CPU time 5.98 seconds
Started Jul 15 06:25:45 PM PDT 24
Finished Jul 15 06:25:51 PM PDT 24
Peak memory 220292 kb
Host smart-ac60cd4c-df56-400a-a034-4fe17b4bf67b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=818563428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.818563428
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.883598014
Short name T928
Test name
Test status
Simulation time 36058951688 ps
CPU time 129.1 seconds
Started Jul 15 06:25:46 PM PDT 24
Finished Jul 15 06:27:56 PM PDT 24
Peak memory 268440 kb
Host smart-e7b1215b-ee40-4e00-a42d-a2163b55991d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883598014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.883598014
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3448621609
Short name T318
Test name
Test status
Simulation time 979766270 ps
CPU time 6.06 seconds
Started Jul 15 06:25:45 PM PDT 24
Finished Jul 15 06:25:52 PM PDT 24
Peak memory 217336 kb
Host smart-6d2601cd-b1da-4de4-955b-f351376c6b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448621609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3448621609
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.965862646
Short name T661
Test name
Test status
Simulation time 13832316598 ps
CPU time 6.1 seconds
Started Jul 15 06:25:48 PM PDT 24
Finished Jul 15 06:25:55 PM PDT 24
Peak memory 217320 kb
Host smart-dab5b4bc-8432-4fbe-86d3-1d93aa09ee60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965862646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.965862646
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.499621771
Short name T559
Test name
Test status
Simulation time 12280351 ps
CPU time 0.72 seconds
Started Jul 15 06:25:49 PM PDT 24
Finished Jul 15 06:25:50 PM PDT 24
Peak memory 206956 kb
Host smart-33f70b40-a8f4-470b-8990-fb1a645f71e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499621771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.499621771
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3478551839
Short name T736
Test name
Test status
Simulation time 50614938 ps
CPU time 0.81 seconds
Started Jul 15 06:25:46 PM PDT 24
Finished Jul 15 06:25:48 PM PDT 24
Peak memory 207004 kb
Host smart-f67c927e-1be2-4dc3-9853-016b344e5dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478551839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3478551839
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.168319302
Short name T565
Test name
Test status
Simulation time 178306390 ps
CPU time 3.32 seconds
Started Jul 15 06:25:44 PM PDT 24
Finished Jul 15 06:25:48 PM PDT 24
Peak memory 225528 kb
Host smart-28bd59f0-31ed-4686-b752-0c92c5202adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168319302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.168319302
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.143804323
Short name T394
Test name
Test status
Simulation time 111310410 ps
CPU time 0.69 seconds
Started Jul 15 06:25:50 PM PDT 24
Finished Jul 15 06:25:51 PM PDT 24
Peak memory 206724 kb
Host smart-cdab4768-41ba-493a-95ab-5f94b36633d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143804323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.143804323
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3681441228
Short name T512
Test name
Test status
Simulation time 1042733552 ps
CPU time 5.34 seconds
Started Jul 15 06:25:44 PM PDT 24
Finished Jul 15 06:25:50 PM PDT 24
Peak memory 233764 kb
Host smart-24426350-b93e-415d-8959-82152adc0c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681441228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3681441228
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1520653882
Short name T849
Test name
Test status
Simulation time 30885126 ps
CPU time 0.75 seconds
Started Jul 15 06:25:48 PM PDT 24
Finished Jul 15 06:25:50 PM PDT 24
Peak memory 207384 kb
Host smart-0344562e-e176-483b-8302-c82212f8a382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520653882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1520653882
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4252721460
Short name T368
Test name
Test status
Simulation time 24653552183 ps
CPU time 78.66 seconds
Started Jul 15 06:25:51 PM PDT 24
Finished Jul 15 06:27:11 PM PDT 24
Peak memory 242100 kb
Host smart-d4becf69-fd76-407c-847e-17cd2ff9397d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252721460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4252721460
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1243479002
Short name T238
Test name
Test status
Simulation time 6806819918 ps
CPU time 38.63 seconds
Started Jul 15 06:25:49 PM PDT 24
Finished Jul 15 06:26:29 PM PDT 24
Peak memory 250652 kb
Host smart-f8e1fa03-f818-46c5-919e-71be5e2716e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243479002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1243479002
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1318444109
Short name T54
Test name
Test status
Simulation time 8939160724 ps
CPU time 142.66 seconds
Started Jul 15 06:25:50 PM PDT 24
Finished Jul 15 06:28:15 PM PDT 24
Peak memory 266204 kb
Host smart-c8e7a1da-74d6-4320-99f4-2a9059584011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318444109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1318444109
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3219209162
Short name T311
Test name
Test status
Simulation time 516645882 ps
CPU time 11.48 seconds
Started Jul 15 06:25:44 PM PDT 24
Finished Jul 15 06:25:57 PM PDT 24
Peak memory 225548 kb
Host smart-1630ab28-9669-419b-ba41-9cb90730b841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219209162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3219209162
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2012836164
Short name T987
Test name
Test status
Simulation time 3614416097 ps
CPU time 78.38 seconds
Started Jul 15 06:26:01 PM PDT 24
Finished Jul 15 06:27:20 PM PDT 24
Peak memory 258220 kb
Host smart-5399d75d-feb0-41ad-8877-cc891d0c76e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012836164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2012836164
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2059145360
Short name T726
Test name
Test status
Simulation time 150497863 ps
CPU time 4.49 seconds
Started Jul 15 06:25:48 PM PDT 24
Finished Jul 15 06:25:54 PM PDT 24
Peak memory 233792 kb
Host smart-20eb630c-beba-4679-84e9-a6dee2a31f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059145360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2059145360
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.278731845
Short name T676
Test name
Test status
Simulation time 30257713 ps
CPU time 2.13 seconds
Started Jul 15 06:25:47 PM PDT 24
Finished Jul 15 06:25:50 PM PDT 24
Peak memory 233504 kb
Host smart-d92f946a-ce34-4ddf-a41f-409008cb8e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278731845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.278731845
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3491248545
Short name T208
Test name
Test status
Simulation time 719671470 ps
CPU time 3.69 seconds
Started Jul 15 06:25:44 PM PDT 24
Finished Jul 15 06:25:49 PM PDT 24
Peak memory 225544 kb
Host smart-75569d8b-ff56-46dc-8a43-ff1711f5dab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491248545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3491248545
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3244320833
Short name T902
Test name
Test status
Simulation time 5416865419 ps
CPU time 14.02 seconds
Started Jul 15 06:25:45 PM PDT 24
Finished Jul 15 06:26:00 PM PDT 24
Peak memory 225640 kb
Host smart-338212c7-1f68-48d6-8869-0873624b7249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244320833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3244320833
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.4175871034
Short name T63
Test name
Test status
Simulation time 491909845 ps
CPU time 4.61 seconds
Started Jul 15 06:25:48 PM PDT 24
Finished Jul 15 06:25:53 PM PDT 24
Peak memory 223976 kb
Host smart-e166a1cc-3082-4603-8196-4d499bf33485
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4175871034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.4175871034
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3187800665
Short name T1026
Test name
Test status
Simulation time 28899139822 ps
CPU time 41.01 seconds
Started Jul 15 06:25:45 PM PDT 24
Finished Jul 15 06:26:27 PM PDT 24
Peak memory 221224 kb
Host smart-d7c58183-7bcb-4e9e-837d-6dcefdb766fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187800665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3187800665
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1987727370
Short name T640
Test name
Test status
Simulation time 3725119964 ps
CPU time 10.06 seconds
Started Jul 15 06:25:48 PM PDT 24
Finished Jul 15 06:25:59 PM PDT 24
Peak memory 217440 kb
Host smart-cba0d4e0-ceb7-4ee9-8968-c59df7246ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987727370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1987727370
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2071663394
Short name T866
Test name
Test status
Simulation time 61887131 ps
CPU time 1.09 seconds
Started Jul 15 06:25:46 PM PDT 24
Finished Jul 15 06:25:48 PM PDT 24
Peak memory 217156 kb
Host smart-e6497444-6b12-4623-8e47-2b139adb7d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071663394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2071663394
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1757562574
Short name T477
Test name
Test status
Simulation time 112809629 ps
CPU time 0.86 seconds
Started Jul 15 06:25:45 PM PDT 24
Finished Jul 15 06:25:47 PM PDT 24
Peak memory 207948 kb
Host smart-ed71042f-a9e5-40a9-ae47-f261dee58fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757562574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1757562574
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1705980953
Short name T557
Test name
Test status
Simulation time 184650328 ps
CPU time 2.09 seconds
Started Jul 15 06:25:49 PM PDT 24
Finished Jul 15 06:25:52 PM PDT 24
Peak memory 225144 kb
Host smart-45927aba-47d3-477f-b37c-c95ad5f995f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705980953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1705980953
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.4115564639
Short name T344
Test name
Test status
Simulation time 18829221 ps
CPU time 0.69 seconds
Started Jul 15 06:25:50 PM PDT 24
Finished Jul 15 06:25:51 PM PDT 24
Peak memory 206364 kb
Host smart-79f0f4e0-3614-4e71-9a5d-5d0fea7affcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115564639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
4115564639
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2755449614
Short name T648
Test name
Test status
Simulation time 6254596471 ps
CPU time 4.39 seconds
Started Jul 15 06:25:50 PM PDT 24
Finished Jul 15 06:25:56 PM PDT 24
Peak memory 225616 kb
Host smart-b87c71b5-006a-4ca1-b3bf-72ce3082264e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755449614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2755449614
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3633349937
Short name T506
Test name
Test status
Simulation time 79264229 ps
CPU time 0.8 seconds
Started Jul 15 06:25:49 PM PDT 24
Finished Jul 15 06:25:51 PM PDT 24
Peak memory 207832 kb
Host smart-24cd6b9c-2271-47ab-b7fd-92b2f28f059d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633349937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3633349937
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1966224134
Short name T555
Test name
Test status
Simulation time 22461695342 ps
CPU time 61.12 seconds
Started Jul 15 06:25:50 PM PDT 24
Finished Jul 15 06:26:52 PM PDT 24
Peak memory 251324 kb
Host smart-926040f3-d9ce-4ea1-939c-ece78727ca6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966224134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1966224134
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.229510269
Short name T603
Test name
Test status
Simulation time 23050334717 ps
CPU time 247.06 seconds
Started Jul 15 06:25:50 PM PDT 24
Finished Jul 15 06:29:58 PM PDT 24
Peak memory 266360 kb
Host smart-2e3cd598-1987-4370-8726-c2ca70a1f3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229510269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.229510269
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.768627412
Short name T798
Test name
Test status
Simulation time 82624670116 ps
CPU time 449.01 seconds
Started Jul 15 06:25:51 PM PDT 24
Finished Jul 15 06:33:21 PM PDT 24
Peak memory 264452 kb
Host smart-b64f468a-a102-476f-b15f-93865abc5554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768627412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.768627412
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1208389033
Short name T715
Test name
Test status
Simulation time 1375415580 ps
CPU time 20.79 seconds
Started Jul 15 06:25:52 PM PDT 24
Finished Jul 15 06:26:13 PM PDT 24
Peak memory 233812 kb
Host smart-a900cb19-37dc-49e2-9c6e-a93f2d19a648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208389033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1208389033
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2362817314
Short name T719
Test name
Test status
Simulation time 1531235018 ps
CPU time 33.23 seconds
Started Jul 15 06:25:51 PM PDT 24
Finished Jul 15 06:26:26 PM PDT 24
Peak memory 242196 kb
Host smart-105d4c6f-431c-4106-b06f-050e9508e6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362817314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2362817314
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2438213389
Short name T952
Test name
Test status
Simulation time 1257631025 ps
CPU time 13.21 seconds
Started Jul 15 06:25:50 PM PDT 24
Finished Jul 15 06:26:05 PM PDT 24
Peak memory 233756 kb
Host smart-b629275c-f48b-42bf-aa72-99eabe6dbc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438213389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2438213389
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.4283479987
Short name T247
Test name
Test status
Simulation time 921813145 ps
CPU time 3.32 seconds
Started Jul 15 06:25:52 PM PDT 24
Finished Jul 15 06:25:56 PM PDT 24
Peak memory 225600 kb
Host smart-461b89d3-318b-439c-9892-c4042fbc18a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283479987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.4283479987
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2538170611
Short name T298
Test name
Test status
Simulation time 6857314401 ps
CPU time 16.89 seconds
Started Jul 15 06:26:01 PM PDT 24
Finished Jul 15 06:26:19 PM PDT 24
Peak memory 225668 kb
Host smart-269a6717-0d3e-4834-bab0-95fc44549d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538170611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2538170611
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1206117168
Short name T961
Test name
Test status
Simulation time 4508505501 ps
CPU time 13.38 seconds
Started Jul 15 06:25:50 PM PDT 24
Finished Jul 15 06:26:05 PM PDT 24
Peak memory 233812 kb
Host smart-85482adf-3674-4ba5-8ad7-953b0dd53c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206117168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1206117168
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3260339561
Short name T470
Test name
Test status
Simulation time 6380142004 ps
CPU time 16.72 seconds
Started Jul 15 06:25:51 PM PDT 24
Finished Jul 15 06:26:09 PM PDT 24
Peak memory 224272 kb
Host smart-e59857b8-8910-4831-914c-763770f74cde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3260339561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3260339561
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.288696345
Short name T326
Test name
Test status
Simulation time 2941913099 ps
CPU time 6.57 seconds
Started Jul 15 06:26:01 PM PDT 24
Finished Jul 15 06:26:09 PM PDT 24
Peak memory 217488 kb
Host smart-a38f72ee-d951-422b-ad63-5c3ba92e26aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288696345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.288696345
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2743589650
Short name T826
Test name
Test status
Simulation time 20893189316 ps
CPU time 7.77 seconds
Started Jul 15 06:25:50 PM PDT 24
Finished Jul 15 06:26:00 PM PDT 24
Peak memory 217540 kb
Host smart-5370b46a-d50a-443f-95f7-3491953357e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743589650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2743589650
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1110747656
Short name T62
Test name
Test status
Simulation time 1337708001 ps
CPU time 1.58 seconds
Started Jul 15 06:25:52 PM PDT 24
Finished Jul 15 06:25:55 PM PDT 24
Peak memory 217372 kb
Host smart-f68f18de-fa76-44e3-b264-9bd2cc5b0c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110747656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1110747656
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3000799434
Short name T844
Test name
Test status
Simulation time 95916029 ps
CPU time 0.97 seconds
Started Jul 15 06:25:51 PM PDT 24
Finished Jul 15 06:25:53 PM PDT 24
Peak memory 207952 kb
Host smart-3c6c2a97-44ad-4ff0-afee-62fc24b697d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000799434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3000799434
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1153270189
Short name T416
Test name
Test status
Simulation time 32355633 ps
CPU time 2.05 seconds
Started Jul 15 06:26:01 PM PDT 24
Finished Jul 15 06:26:04 PM PDT 24
Peak memory 225200 kb
Host smart-1a267b2a-24b1-47d1-932f-e7cf83bffff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153270189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1153270189
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2673686401
Short name T731
Test name
Test status
Simulation time 27161424 ps
CPU time 0.76 seconds
Started Jul 15 06:25:54 PM PDT 24
Finished Jul 15 06:25:55 PM PDT 24
Peak memory 205836 kb
Host smart-11549d1c-a8da-4940-8af1-d34146f7dd7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673686401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2673686401
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.4280882673
Short name T439
Test name
Test status
Simulation time 1531381810 ps
CPU time 5.57 seconds
Started Jul 15 06:25:57 PM PDT 24
Finished Jul 15 06:26:03 PM PDT 24
Peak memory 225444 kb
Host smart-61844537-6c4b-43c2-a6db-7d02c405754d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280882673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4280882673
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2229681226
Short name T16
Test name
Test status
Simulation time 18920355 ps
CPU time 0.78 seconds
Started Jul 15 06:25:50 PM PDT 24
Finished Jul 15 06:25:51 PM PDT 24
Peak memory 206492 kb
Host smart-abccde61-19da-4c59-87c9-c40917fb5be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229681226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2229681226
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3602323713
Short name T827
Test name
Test status
Simulation time 4027474739 ps
CPU time 44.26 seconds
Started Jul 15 06:25:58 PM PDT 24
Finished Jul 15 06:26:43 PM PDT 24
Peak memory 257420 kb
Host smart-59534ec3-dc58-4371-9541-16167a5a6b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602323713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3602323713
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.68185898
Short name T851
Test name
Test status
Simulation time 52439461587 ps
CPU time 514.37 seconds
Started Jul 15 06:25:55 PM PDT 24
Finished Jul 15 06:34:30 PM PDT 24
Peak memory 264604 kb
Host smart-3053212d-8072-4cf8-886b-fa274e7d546a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68185898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.68185898
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3532971351
Short name T204
Test name
Test status
Simulation time 13563185116 ps
CPU time 214.43 seconds
Started Jul 15 06:25:57 PM PDT 24
Finished Jul 15 06:29:32 PM PDT 24
Peak memory 272192 kb
Host smart-c25d5785-aca9-4aed-8aab-e3d97996fb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532971351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3532971351
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4115282805
Short name T610
Test name
Test status
Simulation time 410910051 ps
CPU time 6.12 seconds
Started Jul 15 06:25:55 PM PDT 24
Finished Jul 15 06:26:02 PM PDT 24
Peak memory 225468 kb
Host smart-cfd45d85-7976-427f-8e67-dcee956428fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115282805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4115282805
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2608118849
Short name T81
Test name
Test status
Simulation time 80874649280 ps
CPU time 125.44 seconds
Started Jul 15 06:25:56 PM PDT 24
Finished Jul 15 06:28:02 PM PDT 24
Peak memory 254064 kb
Host smart-5652aa74-2ad9-4f87-aeaf-90ffe8771d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608118849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2608118849
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.573477695
Short name T235
Test name
Test status
Simulation time 203782527 ps
CPU time 4.81 seconds
Started Jul 15 06:25:54 PM PDT 24
Finished Jul 15 06:26:00 PM PDT 24
Peak memory 233824 kb
Host smart-723ac00e-fff6-4ab2-acb0-1f4e123bfa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573477695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.573477695
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3534871265
Short name T937
Test name
Test status
Simulation time 496198371 ps
CPU time 4.01 seconds
Started Jul 15 06:25:55 PM PDT 24
Finished Jul 15 06:26:00 PM PDT 24
Peak memory 233792 kb
Host smart-67fe0da2-6249-4857-b34f-adbc63ed1c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534871265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3534871265
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1641655833
Short name T672
Test name
Test status
Simulation time 928959828 ps
CPU time 4.43 seconds
Started Jul 15 06:25:57 PM PDT 24
Finished Jul 15 06:26:03 PM PDT 24
Peak memory 225532 kb
Host smart-283de27b-bc38-444d-b4c4-15c7d9067dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641655833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1641655833
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2063397828
Short name T277
Test name
Test status
Simulation time 10997283518 ps
CPU time 27.63 seconds
Started Jul 15 06:25:53 PM PDT 24
Finished Jul 15 06:26:22 PM PDT 24
Peak memory 241672 kb
Host smart-7508a4ab-9da0-418e-80bd-6d47ca3e003b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063397828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2063397828
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3699197029
Short name T392
Test name
Test status
Simulation time 675896702 ps
CPU time 8.09 seconds
Started Jul 15 06:26:01 PM PDT 24
Finished Jul 15 06:26:11 PM PDT 24
Peak memory 223496 kb
Host smart-457ecff2-4c80-469f-b183-5b611ec03d15
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3699197029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3699197029
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1498787419
Short name T423
Test name
Test status
Simulation time 3756946797 ps
CPU time 16.92 seconds
Started Jul 15 06:25:50 PM PDT 24
Finished Jul 15 06:26:07 PM PDT 24
Peak memory 217456 kb
Host smart-5a0960dc-0976-4ffd-8080-df32a5ffec48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498787419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1498787419
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3785510794
Short name T641
Test name
Test status
Simulation time 516856058 ps
CPU time 3.23 seconds
Started Jul 15 06:25:57 PM PDT 24
Finished Jul 15 06:26:01 PM PDT 24
Peak memory 217472 kb
Host smart-211f491d-4bf7-4741-a8ad-93edeb3153a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785510794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3785510794
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.443319810
Short name T680
Test name
Test status
Simulation time 89632989 ps
CPU time 1.91 seconds
Started Jul 15 06:25:54 PM PDT 24
Finished Jul 15 06:25:57 PM PDT 24
Peak memory 217364 kb
Host smart-ae49a791-bc81-4e2a-bd2d-ae5d516f0110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443319810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.443319810
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2261432110
Short name T492
Test name
Test status
Simulation time 16087599 ps
CPU time 0.75 seconds
Started Jul 15 06:25:51 PM PDT 24
Finished Jul 15 06:25:53 PM PDT 24
Peak memory 206928 kb
Host smart-e27f70df-7695-477e-b18b-ec141b9c32fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261432110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2261432110
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.952640284
Short name T221
Test name
Test status
Simulation time 60509533607 ps
CPU time 31.9 seconds
Started Jul 15 06:25:53 PM PDT 24
Finished Jul 15 06:26:26 PM PDT 24
Peak memory 238908 kb
Host smart-cfb34af5-045d-4a6d-8271-df5b3e975a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952640284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.952640284
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2636744506
Short name T456
Test name
Test status
Simulation time 22706629 ps
CPU time 0.73 seconds
Started Jul 15 06:26:01 PM PDT 24
Finished Jul 15 06:26:03 PM PDT 24
Peak memory 206376 kb
Host smart-490db4d8-9c4c-44f4-8aa5-67bed40558ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636744506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2636744506
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2409481376
Short name T407
Test name
Test status
Simulation time 355813140 ps
CPU time 6.27 seconds
Started Jul 15 06:25:55 PM PDT 24
Finished Jul 15 06:26:02 PM PDT 24
Peak memory 233780 kb
Host smart-d828d655-034c-4537-bd2e-0b8b171a2196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409481376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2409481376
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1705822883
Short name T542
Test name
Test status
Simulation time 31735599 ps
CPU time 0.76 seconds
Started Jul 15 06:25:57 PM PDT 24
Finished Jul 15 06:25:58 PM PDT 24
Peak memory 206492 kb
Host smart-38a075c2-a758-4fce-9b8d-8faff867815b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705822883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1705822883
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3793437566
Short name T819
Test name
Test status
Simulation time 17262808946 ps
CPU time 146.21 seconds
Started Jul 15 06:25:55 PM PDT 24
Finished Jul 15 06:28:22 PM PDT 24
Peak memory 258364 kb
Host smart-c3c5a7dc-e72d-4f89-be9f-8342dd5b2959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793437566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3793437566
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.4100974205
Short name T602
Test name
Test status
Simulation time 40109785590 ps
CPU time 168.25 seconds
Started Jul 15 06:25:59 PM PDT 24
Finished Jul 15 06:28:47 PM PDT 24
Peak memory 250240 kb
Host smart-86ec07dd-feb1-48f1-b695-eb4238f15099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100974205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.4100974205
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2709497882
Short name T662
Test name
Test status
Simulation time 5143680182 ps
CPU time 26 seconds
Started Jul 15 06:26:01 PM PDT 24
Finished Jul 15 06:26:29 PM PDT 24
Peak memory 218760 kb
Host smart-6430b66f-aec8-4b45-9974-0d7b5a151988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709497882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2709497882
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.647243955
Short name T500
Test name
Test status
Simulation time 1017848480 ps
CPU time 11.93 seconds
Started Jul 15 06:25:55 PM PDT 24
Finished Jul 15 06:26:07 PM PDT 24
Peak memory 249704 kb
Host smart-f849a80a-9a80-4de5-895c-bf1e118372f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647243955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.647243955
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1111110413
Short name T230
Test name
Test status
Simulation time 113970042 ps
CPU time 2.73 seconds
Started Jul 15 06:25:53 PM PDT 24
Finished Jul 15 06:25:57 PM PDT 24
Peak memory 225528 kb
Host smart-12cfad0e-5bcc-4fb1-831f-98a60c449ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111110413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1111110413
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3219325302
Short name T257
Test name
Test status
Simulation time 737689826 ps
CPU time 4.09 seconds
Started Jul 15 06:25:54 PM PDT 24
Finished Jul 15 06:25:59 PM PDT 24
Peak memory 225528 kb
Host smart-35925ae4-af6e-4bfd-92f2-388b223d8512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219325302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3219325302
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1467155178
Short name T728
Test name
Test status
Simulation time 4702568416 ps
CPU time 5.56 seconds
Started Jul 15 06:25:54 PM PDT 24
Finished Jul 15 06:26:00 PM PDT 24
Peak memory 233880 kb
Host smart-fbe37dd1-6b67-42e3-915a-08d8b18cee42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467155178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1467155178
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2683774805
Short name T395
Test name
Test status
Simulation time 3293435401 ps
CPU time 11.37 seconds
Started Jul 15 06:25:55 PM PDT 24
Finished Jul 15 06:26:07 PM PDT 24
Peak memory 233860 kb
Host smart-e1ab6a5e-3e81-425f-9857-9250be9bc9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683774805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2683774805
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.4181810936
Short name T471
Test name
Test status
Simulation time 882042459 ps
CPU time 8.48 seconds
Started Jul 15 06:26:01 PM PDT 24
Finished Jul 15 06:26:11 PM PDT 24
Peak memory 219976 kb
Host smart-c11820f8-af9e-4855-bdf2-b35433ea43a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4181810936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.4181810936
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3933003051
Short name T856
Test name
Test status
Simulation time 70807439832 ps
CPU time 204.52 seconds
Started Jul 15 06:25:59 PM PDT 24
Finished Jul 15 06:29:24 PM PDT 24
Peak memory 266344 kb
Host smart-c097b434-ca5c-4075-90f9-4b48ad16f767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933003051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3933003051
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3223393366
Short name T353
Test name
Test status
Simulation time 165464556 ps
CPU time 3.48 seconds
Started Jul 15 06:25:57 PM PDT 24
Finished Jul 15 06:26:01 PM PDT 24
Peak memory 219880 kb
Host smart-4d5993db-0499-405b-9791-dea423e3fdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223393366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3223393366
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2922159597
Short name T639
Test name
Test status
Simulation time 235738289 ps
CPU time 1.78 seconds
Started Jul 15 06:25:55 PM PDT 24
Finished Jul 15 06:25:58 PM PDT 24
Peak memory 208936 kb
Host smart-be8167b7-f6ed-4806-99a9-38548f5f749d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922159597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2922159597
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.810188354
Short name T908
Test name
Test status
Simulation time 217239552 ps
CPU time 2.51 seconds
Started Jul 15 06:25:56 PM PDT 24
Finished Jul 15 06:26:00 PM PDT 24
Peak memory 217380 kb
Host smart-1327fcbb-d303-4d4a-84a7-e6b51237d62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810188354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.810188354
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.151269090
Short name T753
Test name
Test status
Simulation time 67434030 ps
CPU time 0.89 seconds
Started Jul 15 06:25:54 PM PDT 24
Finished Jul 15 06:25:55 PM PDT 24
Peak memory 206940 kb
Host smart-fb94f87d-3128-418b-9cc0-4f8f32e7a43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151269090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.151269090
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.599600920
Short name T714
Test name
Test status
Simulation time 2960299028 ps
CPU time 13.24 seconds
Started Jul 15 06:25:57 PM PDT 24
Finished Jul 15 06:26:11 PM PDT 24
Peak memory 249528 kb
Host smart-e7c40826-71f9-4452-8e9f-156c7bf14602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599600920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.599600920
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.4042544169
Short name T750
Test name
Test status
Simulation time 38538067 ps
CPU time 0.7 seconds
Started Jul 15 06:23:37 PM PDT 24
Finished Jul 15 06:23:39 PM PDT 24
Peak memory 205824 kb
Host smart-df740c31-91f8-4f68-aa15-ee9a8b840108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042544169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.4
042544169
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.392635873
Short name T896
Test name
Test status
Simulation time 116360955 ps
CPU time 2.56 seconds
Started Jul 15 06:23:40 PM PDT 24
Finished Jul 15 06:23:43 PM PDT 24
Peak memory 233752 kb
Host smart-e744b220-d324-48f8-91a1-592c579040be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392635873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.392635873
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3898263
Short name T998
Test name
Test status
Simulation time 15499349 ps
CPU time 0.8 seconds
Started Jul 15 06:23:29 PM PDT 24
Finished Jul 15 06:23:31 PM PDT 24
Peak memory 207480 kb
Host smart-d447065a-2907-4851-b3d8-5077a5f5d549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3898263
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1336323738
Short name T825
Test name
Test status
Simulation time 150618001 ps
CPU time 0.8 seconds
Started Jul 15 06:23:38 PM PDT 24
Finished Jul 15 06:23:40 PM PDT 24
Peak memory 216932 kb
Host smart-fe1a06ec-aa56-4343-a521-611b5c4a313d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336323738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1336323738
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2808871347
Short name T195
Test name
Test status
Simulation time 45918890633 ps
CPU time 132.05 seconds
Started Jul 15 06:23:39 PM PDT 24
Finished Jul 15 06:25:51 PM PDT 24
Peak memory 250384 kb
Host smart-7d0df6db-a0c3-4996-8b66-cb3322433b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808871347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2808871347
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.84706591
Short name T576
Test name
Test status
Simulation time 7073362800 ps
CPU time 19.52 seconds
Started Jul 15 06:23:36 PM PDT 24
Finished Jul 15 06:23:56 PM PDT 24
Peak memory 240684 kb
Host smart-26a56bf7-4ca9-44f4-a308-cfba46b66e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84706591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.84706591
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1246984503
Short name T305
Test name
Test status
Simulation time 1513749381 ps
CPU time 24.67 seconds
Started Jul 15 06:23:35 PM PDT 24
Finished Jul 15 06:24:00 PM PDT 24
Peak memory 225472 kb
Host smart-7a54a8dd-8248-47db-93eb-ef4128cc54fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246984503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1246984503
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.519693283
Short name T252
Test name
Test status
Simulation time 469122329 ps
CPU time 6.42 seconds
Started Jul 15 06:23:41 PM PDT 24
Finished Jul 15 06:23:47 PM PDT 24
Peak memory 233824 kb
Host smart-a0c92102-58ac-4b1d-888d-503196573bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519693283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.519693283
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1358867340
Short name T625
Test name
Test status
Simulation time 1012571294 ps
CPU time 11.46 seconds
Started Jul 15 06:23:40 PM PDT 24
Finished Jul 15 06:23:52 PM PDT 24
Peak memory 233724 kb
Host smart-4b845505-89bb-46d5-864c-9682889457e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358867340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1358867340
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.4293247437
Short name T445
Test name
Test status
Simulation time 45582353 ps
CPU time 1.02 seconds
Started Jul 15 06:23:38 PM PDT 24
Finished Jul 15 06:23:40 PM PDT 24
Peak memory 217604 kb
Host smart-3061f6ae-2557-42fc-8926-c0faa12eb584
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293247437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.4293247437
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2542345593
Short name T877
Test name
Test status
Simulation time 3726828779 ps
CPU time 8.44 seconds
Started Jul 15 06:23:36 PM PDT 24
Finished Jul 15 06:23:45 PM PDT 24
Peak memory 233728 kb
Host smart-9ac2566c-bd47-4f64-af24-975b3dced100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542345593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2542345593
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.987478118
Short name T505
Test name
Test status
Simulation time 185778412 ps
CPU time 3.42 seconds
Started Jul 15 06:23:42 PM PDT 24
Finished Jul 15 06:23:46 PM PDT 24
Peak memory 225564 kb
Host smart-0cfeb344-0a27-4756-b0d6-55262716e191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987478118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.987478118
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1651411215
Short name T920
Test name
Test status
Simulation time 650790469 ps
CPU time 3.68 seconds
Started Jul 15 06:23:38 PM PDT 24
Finished Jul 15 06:23:43 PM PDT 24
Peak memory 220392 kb
Host smart-4d4664b0-3088-4af7-a451-5a2645d4bbfc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1651411215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1651411215
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.758483151
Short name T66
Test name
Test status
Simulation time 71474467 ps
CPU time 1.05 seconds
Started Jul 15 06:23:38 PM PDT 24
Finished Jul 15 06:23:40 PM PDT 24
Peak memory 236392 kb
Host smart-198fafd8-0cd0-4299-90c8-38d20399c495
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758483151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.758483151
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3206230133
Short name T400
Test name
Test status
Simulation time 152789652 ps
CPU time 0.97 seconds
Started Jul 15 06:23:37 PM PDT 24
Finished Jul 15 06:23:39 PM PDT 24
Peak memory 208824 kb
Host smart-6f783430-a4e9-49a3-928b-144fcb8465c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206230133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3206230133
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3098375480
Short name T733
Test name
Test status
Simulation time 1597484874 ps
CPU time 21.67 seconds
Started Jul 15 06:23:35 PM PDT 24
Finished Jul 15 06:23:57 PM PDT 24
Peak memory 217572 kb
Host smart-4e045ae6-5e57-4cbb-ba74-a1507e9b3d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098375480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3098375480
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3977345370
Short name T440
Test name
Test status
Simulation time 15967621997 ps
CPU time 14.42 seconds
Started Jul 15 06:23:37 PM PDT 24
Finished Jul 15 06:23:53 PM PDT 24
Peak memory 217460 kb
Host smart-eeb7e6a8-c7be-4484-876b-bf52c846b092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977345370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3977345370
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3045306831
Short name T514
Test name
Test status
Simulation time 13495443 ps
CPU time 0.8 seconds
Started Jul 15 06:23:37 PM PDT 24
Finished Jul 15 06:23:39 PM PDT 24
Peak memory 207028 kb
Host smart-09611360-9552-405c-bbde-968c8eca66d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045306831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3045306831
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1616057529
Short name T655
Test name
Test status
Simulation time 408960396 ps
CPU time 1.04 seconds
Started Jul 15 06:23:36 PM PDT 24
Finished Jul 15 06:23:37 PM PDT 24
Peak memory 207944 kb
Host smart-aca0e057-09ce-40f5-a61c-3532541df4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616057529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1616057529
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.849753833
Short name T251
Test name
Test status
Simulation time 38813522723 ps
CPU time 13.87 seconds
Started Jul 15 06:23:38 PM PDT 24
Finished Jul 15 06:23:53 PM PDT 24
Peak memory 237648 kb
Host smart-55dfd944-20ff-4b3c-9925-61912e97a5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849753833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.849753833
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1025909734
Short name T10
Test name
Test status
Simulation time 14400436 ps
CPU time 0.71 seconds
Started Jul 15 06:26:07 PM PDT 24
Finished Jul 15 06:26:09 PM PDT 24
Peak memory 206356 kb
Host smart-35f74883-d459-422a-bad4-39f124c3c5f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025909734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1025909734
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3318577761
Short name T791
Test name
Test status
Simulation time 42307786 ps
CPU time 2.56 seconds
Started Jul 15 06:26:08 PM PDT 24
Finished Jul 15 06:26:12 PM PDT 24
Peak memory 233476 kb
Host smart-001fbb82-ca07-4c03-b760-61bb958150f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318577761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3318577761
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1694192999
Short name T727
Test name
Test status
Simulation time 27640841 ps
CPU time 0.82 seconds
Started Jul 15 06:26:00 PM PDT 24
Finished Jul 15 06:26:02 PM PDT 24
Peak memory 206836 kb
Host smart-45a90e4d-c229-4035-b1cb-d529de9c356c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694192999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1694192999
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2537757039
Short name T941
Test name
Test status
Simulation time 1123221825 ps
CPU time 27.2 seconds
Started Jul 15 06:26:10 PM PDT 24
Finished Jul 15 06:26:39 PM PDT 24
Peak memory 253856 kb
Host smart-288ad340-b01b-4470-a0a7-adffcda2102d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537757039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2537757039
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1327245080
Short name T968
Test name
Test status
Simulation time 150424410223 ps
CPU time 742.98 seconds
Started Jul 15 06:26:02 PM PDT 24
Finished Jul 15 06:38:27 PM PDT 24
Peak memory 266760 kb
Host smart-32428c32-cb06-4b82-ab4e-be701c3dc0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327245080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1327245080
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3275103641
Short name T558
Test name
Test status
Simulation time 6030343933 ps
CPU time 13.48 seconds
Started Jul 15 06:26:02 PM PDT 24
Finished Jul 15 06:26:17 PM PDT 24
Peak memory 225688 kb
Host smart-4e1a27dc-6e58-4892-8ebe-40c896bf7a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275103641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3275103641
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4132230156
Short name T5
Test name
Test status
Simulation time 503506527 ps
CPU time 6.8 seconds
Started Jul 15 06:26:03 PM PDT 24
Finished Jul 15 06:26:11 PM PDT 24
Peak memory 225576 kb
Host smart-020bb73e-6516-415e-a0c2-039257cd964b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132230156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4132230156
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1671544487
Short name T809
Test name
Test status
Simulation time 5220241509 ps
CPU time 22.97 seconds
Started Jul 15 06:26:01 PM PDT 24
Finished Jul 15 06:26:25 PM PDT 24
Peak memory 233920 kb
Host smart-e424856e-868d-4e39-bebf-4036c2324a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671544487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1671544487
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.953054388
Short name T782
Test name
Test status
Simulation time 183616872 ps
CPU time 3.65 seconds
Started Jul 15 06:26:02 PM PDT 24
Finished Jul 15 06:26:07 PM PDT 24
Peak memory 233732 kb
Host smart-46b9f1af-4e39-441e-9992-362ef684141c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953054388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.953054388
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1314717800
Short name T173
Test name
Test status
Simulation time 1991066298 ps
CPU time 3.7 seconds
Started Jul 15 06:26:03 PM PDT 24
Finished Jul 15 06:26:08 PM PDT 24
Peak memory 225580 kb
Host smart-f2cfccb2-0e77-492a-862c-b281c13415d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314717800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1314717800
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2233783536
Short name T154
Test name
Test status
Simulation time 218381317 ps
CPU time 5.12 seconds
Started Jul 15 06:26:03 PM PDT 24
Finished Jul 15 06:26:09 PM PDT 24
Peak memory 223732 kb
Host smart-0dc83590-0c04-4979-9163-0ad655a02c92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2233783536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2233783536
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2731095951
Short name T780
Test name
Test status
Simulation time 9160173929 ps
CPU time 38.16 seconds
Started Jul 15 06:26:07 PM PDT 24
Finished Jul 15 06:26:46 PM PDT 24
Peak memory 242124 kb
Host smart-d9d209da-c436-4dbe-bf98-73203b9031d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731095951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2731095951
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1997022752
Short name T996
Test name
Test status
Simulation time 7648045923 ps
CPU time 11.51 seconds
Started Jul 15 06:26:00 PM PDT 24
Finished Jul 15 06:26:13 PM PDT 24
Peak memory 217528 kb
Host smart-2ccd8c24-3f0d-4937-9611-3eda922c52c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997022752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1997022752
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.474419173
Short name T862
Test name
Test status
Simulation time 663546907 ps
CPU time 1.33 seconds
Started Jul 15 06:26:00 PM PDT 24
Finished Jul 15 06:26:02 PM PDT 24
Peak memory 208820 kb
Host smart-8ec96e43-33e0-4ec3-b416-ad334142c5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474419173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.474419173
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2541106655
Short name T794
Test name
Test status
Simulation time 442671306 ps
CPU time 2.27 seconds
Started Jul 15 06:26:00 PM PDT 24
Finished Jul 15 06:26:03 PM PDT 24
Peak memory 217344 kb
Host smart-5b811953-79ac-41b6-a1a8-5d51d970fad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541106655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2541106655
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2837643980
Short name T762
Test name
Test status
Simulation time 47085162 ps
CPU time 0.78 seconds
Started Jul 15 06:26:00 PM PDT 24
Finished Jul 15 06:26:02 PM PDT 24
Peak memory 206972 kb
Host smart-5c3262ef-05a9-4877-9ffd-3ac894ca1e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837643980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2837643980
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.848395665
Short name T1016
Test name
Test status
Simulation time 6890882448 ps
CPU time 6.41 seconds
Started Jul 15 06:26:02 PM PDT 24
Finished Jul 15 06:26:10 PM PDT 24
Peak memory 233880 kb
Host smart-a56e63f5-19e7-4da1-9fb1-8100894f6fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848395665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.848395665
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1343676977
Short name T786
Test name
Test status
Simulation time 34008905 ps
CPU time 0.77 seconds
Started Jul 15 06:26:18 PM PDT 24
Finished Jul 15 06:26:20 PM PDT 24
Peak memory 206384 kb
Host smart-6202b4d5-732f-4a63-abc9-5f1086a106e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343676977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1343676977
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3948042741
Short name T854
Test name
Test status
Simulation time 641347322 ps
CPU time 10.08 seconds
Started Jul 15 06:26:09 PM PDT 24
Finished Jul 15 06:26:21 PM PDT 24
Peak memory 225640 kb
Host smart-3d48cdda-539f-4d5a-8fe6-f4622979cee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948042741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3948042741
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.401410555
Short name T338
Test name
Test status
Simulation time 19673168 ps
CPU time 0.86 seconds
Started Jul 15 06:26:01 PM PDT 24
Finished Jul 15 06:26:03 PM PDT 24
Peak memory 207516 kb
Host smart-db1094f3-8144-4bee-b516-d7e715058397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401410555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.401410555
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2345008980
Short name T223
Test name
Test status
Simulation time 42868111526 ps
CPU time 166.63 seconds
Started Jul 15 06:26:08 PM PDT 24
Finished Jul 15 06:28:57 PM PDT 24
Peak memory 250256 kb
Host smart-d6c75005-34cf-44a9-85e9-76aa00e38f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345008980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2345008980
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.9391521
Short name T215
Test name
Test status
Simulation time 178330666241 ps
CPU time 415.77 seconds
Started Jul 15 06:26:09 PM PDT 24
Finished Jul 15 06:33:07 PM PDT 24
Peak memory 253908 kb
Host smart-359aa4e4-ed22-49a9-885b-d09bb9257ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9391521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.9391521
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2558219206
Short name T237
Test name
Test status
Simulation time 20366291092 ps
CPU time 203.35 seconds
Started Jul 15 06:26:12 PM PDT 24
Finished Jul 15 06:29:37 PM PDT 24
Peak memory 268452 kb
Host smart-40b126f2-ebe4-4209-b1cf-122152c9909a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558219206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2558219206
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.939962223
Short name T828
Test name
Test status
Simulation time 1863015915 ps
CPU time 29.5 seconds
Started Jul 15 06:26:09 PM PDT 24
Finished Jul 15 06:26:40 PM PDT 24
Peak memory 231936 kb
Host smart-b3be30ac-8068-4c80-b9a3-481b56308c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939962223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.939962223
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3415898538
Short name T520
Test name
Test status
Simulation time 11362782567 ps
CPU time 119.84 seconds
Started Jul 15 06:26:08 PM PDT 24
Finished Jul 15 06:28:10 PM PDT 24
Peak memory 253384 kb
Host smart-f74277f6-c0fa-4fd9-8e19-b47ff041de54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415898538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3415898538
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.303475513
Short name T249
Test name
Test status
Simulation time 121575900 ps
CPU time 2.87 seconds
Started Jul 15 06:26:07 PM PDT 24
Finished Jul 15 06:26:12 PM PDT 24
Peak memory 225552 kb
Host smart-1746acac-0bdb-4c52-910c-5c1568c39b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303475513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.303475513
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1775865878
Short name T242
Test name
Test status
Simulation time 7071763901 ps
CPU time 43.63 seconds
Started Jul 15 06:26:08 PM PDT 24
Finished Jul 15 06:26:53 PM PDT 24
Peak memory 225716 kb
Host smart-da6be733-e187-403a-a3af-67c3728eb674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775865878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1775865878
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.157289031
Short name T700
Test name
Test status
Simulation time 4138508904 ps
CPU time 6.74 seconds
Started Jul 15 06:26:08 PM PDT 24
Finished Jul 15 06:26:17 PM PDT 24
Peak memory 242080 kb
Host smart-db7e8df2-9ba5-42b2-9b03-070832749ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157289031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.157289031
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.838117381
Short name T397
Test name
Test status
Simulation time 11094182778 ps
CPU time 11.72 seconds
Started Jul 15 06:26:06 PM PDT 24
Finished Jul 15 06:26:20 PM PDT 24
Peak memory 233864 kb
Host smart-c6b3b895-dc1b-43e9-92d6-8f51cf6975f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838117381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.838117381
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1824116145
Short name T376
Test name
Test status
Simulation time 459338184 ps
CPU time 6.3 seconds
Started Jul 15 06:26:09 PM PDT 24
Finished Jul 15 06:26:17 PM PDT 24
Peak memory 220724 kb
Host smart-aae2d2b3-1be0-4335-9f44-42183b8eddd2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1824116145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1824116145
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3883521376
Short name T360
Test name
Test status
Simulation time 832851161 ps
CPU time 8.47 seconds
Started Jul 15 06:26:08 PM PDT 24
Finished Jul 15 06:26:19 PM PDT 24
Peak memory 217636 kb
Host smart-7b1961ef-4ce0-44b5-ad35-92cc5358407f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883521376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3883521376
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3903381826
Short name T629
Test name
Test status
Simulation time 1462387109 ps
CPU time 2.65 seconds
Started Jul 15 06:26:00 PM PDT 24
Finished Jul 15 06:26:03 PM PDT 24
Peak memory 217320 kb
Host smart-6b3857f7-baf4-486d-bb3e-9fa013a08fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903381826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3903381826
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1714926021
Short name T388
Test name
Test status
Simulation time 91434365 ps
CPU time 1.08 seconds
Started Jul 15 06:26:08 PM PDT 24
Finished Jul 15 06:26:10 PM PDT 24
Peak memory 208940 kb
Host smart-3e572ae7-22dc-40fe-9254-4e3b7ca32594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714926021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1714926021
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3547964676
Short name T563
Test name
Test status
Simulation time 832719173 ps
CPU time 0.87 seconds
Started Jul 15 06:26:06 PM PDT 24
Finished Jul 15 06:26:07 PM PDT 24
Peak memory 206936 kb
Host smart-68351574-64a3-4804-9c33-4d62bc535b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547964676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3547964676
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3486856629
Short name T4
Test name
Test status
Simulation time 9311481330 ps
CPU time 7.97 seconds
Started Jul 15 06:26:10 PM PDT 24
Finished Jul 15 06:26:19 PM PDT 24
Peak memory 233888 kb
Host smart-4718e2fb-4dc9-4c04-b983-cb6991d1bdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486856629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3486856629
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3131361686
Short name T943
Test name
Test status
Simulation time 26009934 ps
CPU time 0.72 seconds
Started Jul 15 06:26:14 PM PDT 24
Finished Jul 15 06:26:16 PM PDT 24
Peak memory 205816 kb
Host smart-ce8554c1-f937-4c11-b52a-c3f893b272be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131361686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3131361686
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1632160268
Short name T444
Test name
Test status
Simulation time 17418185413 ps
CPU time 15.61 seconds
Started Jul 15 06:26:18 PM PDT 24
Finished Jul 15 06:26:34 PM PDT 24
Peak memory 225604 kb
Host smart-7c82c4aa-09a8-44e2-b810-9d01ea18b215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632160268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1632160268
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2068512350
Short name T56
Test name
Test status
Simulation time 15798855 ps
CPU time 0.79 seconds
Started Jul 15 06:26:18 PM PDT 24
Finished Jul 15 06:26:20 PM PDT 24
Peak memory 207528 kb
Host smart-a7acd6c8-8ad2-4053-939b-9bf64be61642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068512350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2068512350
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3379426720
Short name T300
Test name
Test status
Simulation time 27838837572 ps
CPU time 89.38 seconds
Started Jul 15 06:26:15 PM PDT 24
Finished Jul 15 06:27:45 PM PDT 24
Peak memory 253440 kb
Host smart-c6d46858-1a67-41c1-9c86-33c6d1c7452f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379426720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3379426720
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1102750714
Short name T142
Test name
Test status
Simulation time 78084786282 ps
CPU time 309.87 seconds
Started Jul 15 06:26:15 PM PDT 24
Finished Jul 15 06:31:26 PM PDT 24
Peak memory 251596 kb
Host smart-628baba5-7dca-4e6b-ab44-c3889a4433d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102750714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1102750714
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1760745424
Short name T329
Test name
Test status
Simulation time 6657162775 ps
CPU time 107.3 seconds
Started Jul 15 06:26:15 PM PDT 24
Finished Jul 15 06:28:03 PM PDT 24
Peak memory 251428 kb
Host smart-4d84cbb7-a4e3-4f66-a309-553922ce8ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760745424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1760745424
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1774101035
Short name T225
Test name
Test status
Simulation time 31393619 ps
CPU time 2.9 seconds
Started Jul 15 06:26:18 PM PDT 24
Finished Jul 15 06:26:22 PM PDT 24
Peak memory 233716 kb
Host smart-2d85e9d5-0871-4858-8aa2-dac5197d388f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774101035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1774101035
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4148035013
Short name T92
Test name
Test status
Simulation time 612906373 ps
CPU time 10.14 seconds
Started Jul 15 06:26:14 PM PDT 24
Finished Jul 15 06:26:26 PM PDT 24
Peak memory 233764 kb
Host smart-865eeb40-6f10-49e2-81dc-aa1a454fe53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148035013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4148035013
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3667446196
Short name T910
Test name
Test status
Simulation time 21011338984 ps
CPU time 54.49 seconds
Started Jul 15 06:26:13 PM PDT 24
Finished Jul 15 06:27:08 PM PDT 24
Peak memory 240904 kb
Host smart-df94200d-fccf-43ba-b987-acf026010407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667446196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3667446196
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3336609656
Short name T523
Test name
Test status
Simulation time 5497695785 ps
CPU time 11.95 seconds
Started Jul 15 06:26:15 PM PDT 24
Finished Jul 15 06:26:28 PM PDT 24
Peak memory 242132 kb
Host smart-fb7f9836-5b71-47ec-903f-3721cff52ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336609656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3336609656
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1166404363
Short name T887
Test name
Test status
Simulation time 2173101196 ps
CPU time 10.81 seconds
Started Jul 15 06:26:11 PM PDT 24
Finished Jul 15 06:26:24 PM PDT 24
Peak memory 233836 kb
Host smart-5edb8c40-fa4e-44ea-971c-0e5ae0ec98f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166404363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1166404363
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2926808263
Short name T510
Test name
Test status
Simulation time 2453586877 ps
CPU time 13.03 seconds
Started Jul 15 06:26:15 PM PDT 24
Finished Jul 15 06:26:29 PM PDT 24
Peak memory 219984 kb
Host smart-0dec34d7-3611-48b9-aadd-19e614837e93
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2926808263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2926808263
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2496611801
Short name T747
Test name
Test status
Simulation time 15539611813 ps
CPU time 112.27 seconds
Started Jul 15 06:26:15 PM PDT 24
Finished Jul 15 06:28:08 PM PDT 24
Peak memory 258568 kb
Host smart-3ec8c013-3da2-4349-920b-920146b96dc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496611801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2496611801
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3511593246
Short name T323
Test name
Test status
Simulation time 21352051477 ps
CPU time 49.77 seconds
Started Jul 15 06:26:12 PM PDT 24
Finished Jul 15 06:27:03 PM PDT 24
Peak memory 217524 kb
Host smart-f56aac26-66cb-40d0-afeb-b5522f2dfa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511593246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3511593246
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3279564623
Short name T659
Test name
Test status
Simulation time 2408429819 ps
CPU time 2.78 seconds
Started Jul 15 06:26:15 PM PDT 24
Finished Jul 15 06:26:19 PM PDT 24
Peak memory 217308 kb
Host smart-bfc24eaa-b249-495a-aa5b-b902bcf2ff4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279564623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3279564623
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1140545641
Short name T654
Test name
Test status
Simulation time 213421006 ps
CPU time 1.38 seconds
Started Jul 15 06:26:15 PM PDT 24
Finished Jul 15 06:26:18 PM PDT 24
Peak memory 217468 kb
Host smart-62544fae-977d-486c-80de-ccb84cbec236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140545641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1140545641
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3394485485
Short name T519
Test name
Test status
Simulation time 82325996 ps
CPU time 0.98 seconds
Started Jul 15 06:26:14 PM PDT 24
Finished Jul 15 06:26:16 PM PDT 24
Peak memory 207324 kb
Host smart-4878e421-9a82-4132-9086-2fc34e152ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394485485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3394485485
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2415248251
Short name T15
Test name
Test status
Simulation time 5732353361 ps
CPU time 7.28 seconds
Started Jul 15 06:26:15 PM PDT 24
Finished Jul 15 06:26:23 PM PDT 24
Peak memory 233912 kb
Host smart-6b18f9a3-bec3-404a-a563-432b501141b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415248251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2415248251
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.4231204283
Short name T339
Test name
Test status
Simulation time 19228091 ps
CPU time 0.73 seconds
Started Jul 15 06:26:19 PM PDT 24
Finished Jul 15 06:26:21 PM PDT 24
Peak memory 206660 kb
Host smart-aed0a917-c95a-4708-a2fc-bd69ea2f468c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231204283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
4231204283
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2765781947
Short name T171
Test name
Test status
Simulation time 3785547009 ps
CPU time 10.43 seconds
Started Jul 15 06:26:13 PM PDT 24
Finished Jul 15 06:26:25 PM PDT 24
Peak memory 225772 kb
Host smart-531d0b2f-d245-406c-b68f-025d679f9f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765781947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2765781947
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.588776367
Short name T463
Test name
Test status
Simulation time 70274424 ps
CPU time 0.77 seconds
Started Jul 15 06:26:17 PM PDT 24
Finished Jul 15 06:26:18 PM PDT 24
Peak memory 207736 kb
Host smart-5b4cf12e-97d9-4287-8913-d812828f2047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588776367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.588776367
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3649683690
Short name T234
Test name
Test status
Simulation time 6309862790 ps
CPU time 81.46 seconds
Started Jul 15 06:26:19 PM PDT 24
Finished Jul 15 06:27:42 PM PDT 24
Peak memory 273292 kb
Host smart-a4b66ca3-3dce-4daa-b09e-647d57c472df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649683690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3649683690
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4175538454
Short name T144
Test name
Test status
Simulation time 1627888864 ps
CPU time 38.86 seconds
Started Jul 15 06:26:20 PM PDT 24
Finished Jul 15 06:27:00 PM PDT 24
Peak memory 253428 kb
Host smart-01c39fac-6039-4dd4-b025-a794dbb96f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175538454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4175538454
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3629328896
Short name T153
Test name
Test status
Simulation time 12048982688 ps
CPU time 25.57 seconds
Started Jul 15 06:26:13 PM PDT 24
Finished Jul 15 06:26:40 PM PDT 24
Peak memory 238988 kb
Host smart-7089752b-088f-4549-a2c6-f00cc1b54d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629328896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3629328896
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2382693339
Short name T533
Test name
Test status
Simulation time 40155071 ps
CPU time 0.76 seconds
Started Jul 15 06:26:20 PM PDT 24
Finished Jul 15 06:26:22 PM PDT 24
Peak memory 216936 kb
Host smart-24e43b12-750e-418c-8426-d8eedc88f906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382693339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2382693339
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3803577059
Short name T704
Test name
Test status
Simulation time 442400716 ps
CPU time 2.39 seconds
Started Jul 15 06:26:14 PM PDT 24
Finished Jul 15 06:26:18 PM PDT 24
Peak memory 233472 kb
Host smart-c0c2699f-8058-4812-96ec-9143bc87fada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803577059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3803577059
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.4227855130
Short name T71
Test name
Test status
Simulation time 3126531117 ps
CPU time 4.83 seconds
Started Jul 15 06:26:13 PM PDT 24
Finished Jul 15 06:26:19 PM PDT 24
Peak memory 225732 kb
Host smart-8172e874-518f-4089-9d50-fdb608a37f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227855130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4227855130
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2161289806
Short name T296
Test name
Test status
Simulation time 20910369436 ps
CPU time 21.18 seconds
Started Jul 15 06:26:15 PM PDT 24
Finished Jul 15 06:26:37 PM PDT 24
Peak memory 257636 kb
Host smart-02e86606-3b2e-432e-b5fa-a36274529208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161289806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2161289806
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3709760107
Short name T241
Test name
Test status
Simulation time 10990289871 ps
CPU time 30.8 seconds
Started Jul 15 06:26:12 PM PDT 24
Finished Jul 15 06:26:44 PM PDT 24
Peak memory 233948 kb
Host smart-3c10e02f-3683-4e0b-a225-a41c2582139d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709760107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3709760107
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1858000077
Short name T460
Test name
Test status
Simulation time 110981023 ps
CPU time 4.19 seconds
Started Jul 15 06:26:22 PM PDT 24
Finished Jul 15 06:26:27 PM PDT 24
Peak memory 224092 kb
Host smart-60576efb-139b-4918-943d-e74feb759dbc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1858000077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1858000077
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2003395785
Short name T320
Test name
Test status
Simulation time 4043956659 ps
CPU time 8.08 seconds
Started Jul 15 06:26:18 PM PDT 24
Finished Jul 15 06:26:27 PM PDT 24
Peak memory 217544 kb
Host smart-04580889-ea1d-4dda-b3ce-9cdc048febf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003395785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2003395785
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1468113773
Short name T489
Test name
Test status
Simulation time 7070453115 ps
CPU time 4.24 seconds
Started Jul 15 06:26:11 PM PDT 24
Finished Jul 15 06:26:17 PM PDT 24
Peak memory 217380 kb
Host smart-dba9407a-e48e-4a3f-a6fc-c5cefdf39ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468113773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1468113773
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1601605653
Short name T361
Test name
Test status
Simulation time 141320938 ps
CPU time 2.04 seconds
Started Jul 15 06:26:17 PM PDT 24
Finished Jul 15 06:26:20 PM PDT 24
Peak memory 217284 kb
Host smart-8c96c406-07b5-44f2-93cd-0ec4ff1ab426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601605653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1601605653
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1375602932
Short name T682
Test name
Test status
Simulation time 72808122 ps
CPU time 0.92 seconds
Started Jul 15 06:26:15 PM PDT 24
Finished Jul 15 06:26:17 PM PDT 24
Peak memory 206996 kb
Host smart-2a220661-1768-4427-ab73-8684f60f6a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375602932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1375602932
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2867199006
Short name T653
Test name
Test status
Simulation time 316695828 ps
CPU time 2.84 seconds
Started Jul 15 06:26:15 PM PDT 24
Finished Jul 15 06:26:19 PM PDT 24
Peak memory 225508 kb
Host smart-bf3c872c-3f2a-40d5-bb8e-75ccb81b24c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867199006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2867199006
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3685244454
Short name T340
Test name
Test status
Simulation time 22677168 ps
CPU time 0.71 seconds
Started Jul 15 06:26:26 PM PDT 24
Finished Jul 15 06:26:28 PM PDT 24
Peak memory 206320 kb
Host smart-ed481fe4-77a3-4564-8f83-88795c1fcf0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685244454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3685244454
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1335721871
Short name T458
Test name
Test status
Simulation time 40564574 ps
CPU time 2.56 seconds
Started Jul 15 06:26:20 PM PDT 24
Finished Jul 15 06:26:24 PM PDT 24
Peak memory 233700 kb
Host smart-373285b6-1488-4fe3-91de-32b358aa1963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335721871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1335721871
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3391512104
Short name T578
Test name
Test status
Simulation time 47546839 ps
CPU time 0.8 seconds
Started Jul 15 06:26:20 PM PDT 24
Finished Jul 15 06:26:22 PM PDT 24
Peak memory 207484 kb
Host smart-70dc10e2-5de8-4ed5-b059-83d015d50b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391512104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3391512104
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1396282849
Short name T885
Test name
Test status
Simulation time 47702983 ps
CPU time 0.79 seconds
Started Jul 15 06:26:20 PM PDT 24
Finished Jul 15 06:26:22 PM PDT 24
Peak memory 216904 kb
Host smart-04e5ec2d-dd05-4163-ad16-ed7b3d4d1b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396282849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1396282849
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2694633495
Short name T33
Test name
Test status
Simulation time 8878185202 ps
CPU time 78.23 seconds
Started Jul 15 06:26:21 PM PDT 24
Finished Jul 15 06:27:40 PM PDT 24
Peak memory 250576 kb
Host smart-1ecb06f8-5684-4efa-a908-ce7ed735607f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694633495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2694633495
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4197818139
Short name T288
Test name
Test status
Simulation time 3929853118 ps
CPU time 46.67 seconds
Started Jul 15 06:26:19 PM PDT 24
Finished Jul 15 06:27:06 PM PDT 24
Peak memory 233968 kb
Host smart-af9e4077-8f9a-426c-9e06-c8a0be3f5000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197818139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4197818139
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2137078649
Short name T624
Test name
Test status
Simulation time 634026975 ps
CPU time 5.78 seconds
Started Jul 15 06:26:20 PM PDT 24
Finished Jul 15 06:26:27 PM PDT 24
Peak memory 241968 kb
Host smart-34d3cd4d-6af3-44e6-8ac7-c6f9c68a2f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137078649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2137078649
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1413679708
Short name T442
Test name
Test status
Simulation time 50591321 ps
CPU time 0.79 seconds
Started Jul 15 06:26:19 PM PDT 24
Finished Jul 15 06:26:21 PM PDT 24
Peak memory 216908 kb
Host smart-b1a74453-f0ef-4bdb-94ad-663d7b0a170f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413679708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1413679708
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3199074750
Short name T980
Test name
Test status
Simulation time 4411543741 ps
CPU time 9.43 seconds
Started Jul 15 06:26:19 PM PDT 24
Finished Jul 15 06:26:29 PM PDT 24
Peak memory 225688 kb
Host smart-a4126135-f962-4ffd-b022-c7c04bd9e23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199074750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3199074750
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.730122708
Short name T852
Test name
Test status
Simulation time 24025740465 ps
CPU time 137.22 seconds
Started Jul 15 06:26:20 PM PDT 24
Finished Jul 15 06:28:38 PM PDT 24
Peak memory 234908 kb
Host smart-05a6bf0f-af17-439c-98b7-980e8e4fe34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730122708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.730122708
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2969526972
Short name T598
Test name
Test status
Simulation time 31471619 ps
CPU time 2 seconds
Started Jul 15 06:26:20 PM PDT 24
Finished Jul 15 06:26:23 PM PDT 24
Peak memory 225248 kb
Host smart-eb8dead7-a4b4-4a73-a89f-54d6ab68feae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969526972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2969526972
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.951782375
Short name T1025
Test name
Test status
Simulation time 1206858765 ps
CPU time 3.48 seconds
Started Jul 15 06:26:19 PM PDT 24
Finished Jul 15 06:26:24 PM PDT 24
Peak memory 233724 kb
Host smart-53a0005b-6ebf-4c5d-bce7-c2a8ee423951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951782375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.951782375
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2261194614
Short name T914
Test name
Test status
Simulation time 5665446089 ps
CPU time 7.92 seconds
Started Jul 15 06:26:20 PM PDT 24
Finished Jul 15 06:26:29 PM PDT 24
Peak memory 221808 kb
Host smart-56dc9dc3-ec74-45bd-aa55-ef5fe9275323
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2261194614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2261194614
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2124396841
Short name T773
Test name
Test status
Simulation time 1984922108 ps
CPU time 39.99 seconds
Started Jul 15 06:26:25 PM PDT 24
Finished Jul 15 06:27:05 PM PDT 24
Peak memory 238832 kb
Host smart-ab649376-7573-45ec-8945-ad4dc1f5a300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124396841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2124396841
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.601198874
Short name T967
Test name
Test status
Simulation time 7312863411 ps
CPU time 37.12 seconds
Started Jul 15 06:26:21 PM PDT 24
Finished Jul 15 06:26:59 PM PDT 24
Peak memory 217508 kb
Host smart-2905cd94-4226-4163-8be4-0f636521edbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601198874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.601198874
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2576780553
Short name T356
Test name
Test status
Simulation time 1256579348 ps
CPU time 5.83 seconds
Started Jul 15 06:26:20 PM PDT 24
Finished Jul 15 06:26:27 PM PDT 24
Peak memory 217348 kb
Host smart-93b20a2d-ae07-49a9-8f5b-3b02cdb49bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576780553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2576780553
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1019566267
Short name T499
Test name
Test status
Simulation time 127507131 ps
CPU time 1.7 seconds
Started Jul 15 06:26:21 PM PDT 24
Finished Jul 15 06:26:24 PM PDT 24
Peak memory 217312 kb
Host smart-68ca8ae1-dfa5-407e-9bd9-1ca675ae2cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019566267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1019566267
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1028762010
Short name T717
Test name
Test status
Simulation time 65241944 ps
CPU time 0.87 seconds
Started Jul 15 06:26:21 PM PDT 24
Finished Jul 15 06:26:23 PM PDT 24
Peak memory 206996 kb
Host smart-7466cb80-cd72-45c3-9cc3-0027c478abb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028762010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1028762010
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1653885507
Short name T389
Test name
Test status
Simulation time 9390885002 ps
CPU time 7.59 seconds
Started Jul 15 06:26:19 PM PDT 24
Finished Jul 15 06:26:28 PM PDT 24
Peak memory 233984 kb
Host smart-8684a475-9884-4093-a8eb-0e509b33ad5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653885507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1653885507
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2713868023
Short name T830
Test name
Test status
Simulation time 12457536 ps
CPU time 0.71 seconds
Started Jul 15 06:26:28 PM PDT 24
Finished Jul 15 06:26:30 PM PDT 24
Peak memory 205700 kb
Host smart-91b345a9-1887-419c-8efb-6a72c5d2f157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713868023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2713868023
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1083909143
Short name T907
Test name
Test status
Simulation time 396205079 ps
CPU time 2.74 seconds
Started Jul 15 06:26:28 PM PDT 24
Finished Jul 15 06:26:32 PM PDT 24
Peak memory 225640 kb
Host smart-fd654f8f-cfd4-4920-9a4a-018a778c9679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083909143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1083909143
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.843960792
Short name T919
Test name
Test status
Simulation time 29488790 ps
CPU time 0.82 seconds
Started Jul 15 06:26:28 PM PDT 24
Finished Jul 15 06:26:30 PM PDT 24
Peak memory 207936 kb
Host smart-a057b756-c2fe-4eaa-8275-6fe58f3553ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843960792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.843960792
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1830987022
Short name T457
Test name
Test status
Simulation time 4634476172 ps
CPU time 22.35 seconds
Started Jul 15 06:26:28 PM PDT 24
Finished Jul 15 06:26:51 PM PDT 24
Peak memory 236984 kb
Host smart-26fc6f08-f136-463b-8cb1-ddd72a16ab31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830987022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1830987022
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.147522378
Short name T889
Test name
Test status
Simulation time 52404529793 ps
CPU time 235 seconds
Started Jul 15 06:26:29 PM PDT 24
Finished Jul 15 06:30:25 PM PDT 24
Peak memory 256024 kb
Host smart-0a305985-8854-468a-9199-b1b73378008d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147522378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.147522378
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2893982231
Short name T939
Test name
Test status
Simulation time 5360124952 ps
CPU time 56.51 seconds
Started Jul 15 06:26:32 PM PDT 24
Finished Jul 15 06:27:29 PM PDT 24
Peak memory 250440 kb
Host smart-177832a1-4680-4a8f-be63-4788be4b2c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893982231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2893982231
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.4149033381
Short name T783
Test name
Test status
Simulation time 378230133 ps
CPU time 4.98 seconds
Started Jul 15 06:26:26 PM PDT 24
Finished Jul 15 06:26:32 PM PDT 24
Peak memory 233800 kb
Host smart-2f3ee9e8-4af9-4457-9f7a-8f92d37143a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149033381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4149033381
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1109311371
Short name T803
Test name
Test status
Simulation time 2074054478 ps
CPU time 27.62 seconds
Started Jul 15 06:26:28 PM PDT 24
Finished Jul 15 06:26:57 PM PDT 24
Peak memory 235996 kb
Host smart-63ef6630-022d-4f26-ba29-246b34f6eb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109311371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1109311371
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1981618362
Short name T40
Test name
Test status
Simulation time 2807887319 ps
CPU time 21.73 seconds
Started Jul 15 06:26:28 PM PDT 24
Finished Jul 15 06:26:51 PM PDT 24
Peak memory 233892 kb
Host smart-a0375dcd-334a-4eaf-a81c-cac60e50a592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981618362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1981618362
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.4153544441
Short name T256
Test name
Test status
Simulation time 3057764055 ps
CPU time 26.23 seconds
Started Jul 15 06:26:29 PM PDT 24
Finished Jul 15 06:26:56 PM PDT 24
Peak memory 225692 kb
Host smart-fe5798e5-044e-4d6f-b03a-45f156115238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153544441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4153544441
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.959543366
Short name T262
Test name
Test status
Simulation time 1503858738 ps
CPU time 10.81 seconds
Started Jul 15 06:26:26 PM PDT 24
Finished Jul 15 06:26:37 PM PDT 24
Peak memory 241744 kb
Host smart-9d69fa7b-d283-43a3-83fd-abffaa8641ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959543366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.959543366
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.4218946437
Short name T742
Test name
Test status
Simulation time 1176092593 ps
CPU time 4.67 seconds
Started Jul 15 06:26:26 PM PDT 24
Finished Jul 15 06:26:32 PM PDT 24
Peak memory 225572 kb
Host smart-11decce3-be2d-48f9-8cfe-2bc65b2d1442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218946437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.4218946437
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.193420961
Short name T585
Test name
Test status
Simulation time 1747256250 ps
CPU time 9.82 seconds
Started Jul 15 06:26:28 PM PDT 24
Finished Jul 15 06:26:39 PM PDT 24
Peak memory 221748 kb
Host smart-47ddc50e-7905-4d50-a7ce-7c0aa278804c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=193420961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.193420961
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2497419010
Short name T373
Test name
Test status
Simulation time 85529104 ps
CPU time 1 seconds
Started Jul 15 06:26:26 PM PDT 24
Finished Jul 15 06:26:27 PM PDT 24
Peak memory 208652 kb
Host smart-fc5f5c7e-8558-458b-9f1b-dc9dc44cce33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497419010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2497419010
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3684057060
Short name T589
Test name
Test status
Simulation time 116707292965 ps
CPU time 41.76 seconds
Started Jul 15 06:26:25 PM PDT 24
Finished Jul 15 06:27:07 PM PDT 24
Peak memory 217392 kb
Host smart-764e50da-9a79-4b62-93d5-2b360ec06a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684057060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3684057060
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1029678241
Short name T87
Test name
Test status
Simulation time 2036821411 ps
CPU time 4.01 seconds
Started Jul 15 06:26:27 PM PDT 24
Finished Jul 15 06:26:32 PM PDT 24
Peak memory 217400 kb
Host smart-131b27cc-fa9c-42d9-b68b-f74b95fcddc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029678241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1029678241
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.395935645
Short name T959
Test name
Test status
Simulation time 143194983 ps
CPU time 6.38 seconds
Started Jul 15 06:26:27 PM PDT 24
Finished Jul 15 06:26:34 PM PDT 24
Peak memory 217348 kb
Host smart-7c6082ee-dfc6-4705-8da7-932567c9af83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395935645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.395935645
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2764493292
Short name T518
Test name
Test status
Simulation time 386230420 ps
CPU time 0.95 seconds
Started Jul 15 06:26:25 PM PDT 24
Finished Jul 15 06:26:27 PM PDT 24
Peak memory 206988 kb
Host smart-16d6eaea-0545-4980-9e5b-4c0dafedf806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764493292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2764493292
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3690994447
Short name T934
Test name
Test status
Simulation time 5171450597 ps
CPU time 16.6 seconds
Started Jul 15 06:26:28 PM PDT 24
Finished Jul 15 06:26:46 PM PDT 24
Peak memory 233892 kb
Host smart-2890ffaa-645d-45bc-89df-573af4b91c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690994447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3690994447
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2814083425
Short name T521
Test name
Test status
Simulation time 15389239 ps
CPU time 0.72 seconds
Started Jul 15 06:26:32 PM PDT 24
Finished Jul 15 06:26:34 PM PDT 24
Peak memory 206364 kb
Host smart-7687a45f-0704-46d9-9191-e1affbaa2134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814083425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2814083425
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2456200191
Short name T942
Test name
Test status
Simulation time 113090212 ps
CPU time 2.64 seconds
Started Jul 15 06:26:26 PM PDT 24
Finished Jul 15 06:26:30 PM PDT 24
Peak memory 233684 kb
Host smart-627c1f5c-e96f-4eb9-9ddc-11cb9a530182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456200191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2456200191
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1683932451
Short name T859
Test name
Test status
Simulation time 66903697 ps
CPU time 0.76 seconds
Started Jul 15 06:26:27 PM PDT 24
Finished Jul 15 06:26:28 PM PDT 24
Peak memory 207472 kb
Host smart-245ff03d-c52c-4bc4-b6bc-a4b9cddaafd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683932451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1683932451
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3882215627
Short name T282
Test name
Test status
Simulation time 8184199528 ps
CPU time 111.78 seconds
Started Jul 15 06:26:26 PM PDT 24
Finished Jul 15 06:28:18 PM PDT 24
Peak memory 258424 kb
Host smart-66dd3c25-5b36-44a0-a9a0-f199964eab3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882215627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3882215627
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.794730418
Short name T214
Test name
Test status
Simulation time 7707973099 ps
CPU time 74.88 seconds
Started Jul 15 06:26:32 PM PDT 24
Finished Jul 15 06:27:48 PM PDT 24
Peak memory 233996 kb
Host smart-0fedbfdd-c896-44b7-a181-17d928fb7b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794730418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.794730418
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4118677784
Short name T991
Test name
Test status
Simulation time 312215675 ps
CPU time 6.63 seconds
Started Jul 15 06:26:26 PM PDT 24
Finished Jul 15 06:26:33 PM PDT 24
Peak memory 233948 kb
Host smart-66a8de91-c1de-461f-8f5b-6808be2e2b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118677784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4118677784
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1144860329
Short name T756
Test name
Test status
Simulation time 7297442940 ps
CPU time 57 seconds
Started Jul 15 06:26:27 PM PDT 24
Finished Jul 15 06:27:25 PM PDT 24
Peak memory 247916 kb
Host smart-f7f2b67a-1050-488c-bbb2-9c45ddc7579e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144860329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1144860329
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2659838423
Short name T236
Test name
Test status
Simulation time 2330381017 ps
CPU time 9.85 seconds
Started Jul 15 06:26:29 PM PDT 24
Finished Jul 15 06:26:40 PM PDT 24
Peak memory 225704 kb
Host smart-33887ace-9048-45c0-bda2-727c42439603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659838423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2659838423
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.4182382387
Short name T508
Test name
Test status
Simulation time 21411359444 ps
CPU time 24.83 seconds
Started Jul 15 06:26:27 PM PDT 24
Finished Jul 15 06:26:53 PM PDT 24
Peak memory 251156 kb
Host smart-b44d7271-f63a-4ca1-b3df-aa836c40240d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182382387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4182382387
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1278083679
Short name T289
Test name
Test status
Simulation time 13403234862 ps
CPU time 11.95 seconds
Started Jul 15 06:26:28 PM PDT 24
Finished Jul 15 06:26:41 PM PDT 24
Peak memory 240692 kb
Host smart-38a17333-f82f-46d5-b64c-13f4aafbd6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278083679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1278083679
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.4125808374
Short name T473
Test name
Test status
Simulation time 1593003784 ps
CPU time 7.48 seconds
Started Jul 15 06:26:27 PM PDT 24
Finished Jul 15 06:26:36 PM PDT 24
Peak memory 225500 kb
Host smart-726791b2-7bc1-4828-9a91-69f85dddb657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125808374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4125808374
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2335512732
Short name T536
Test name
Test status
Simulation time 359504803 ps
CPU time 5.19 seconds
Started Jul 15 06:26:28 PM PDT 24
Finished Jul 15 06:26:34 PM PDT 24
Peak memory 221680 kb
Host smart-f81b3e94-932b-4202-b73f-b5d41ed7a12b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2335512732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2335512732
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3935183122
Short name T879
Test name
Test status
Simulation time 31414922379 ps
CPU time 71.8 seconds
Started Jul 15 06:26:32 PM PDT 24
Finished Jul 15 06:27:45 PM PDT 24
Peak memory 242180 kb
Host smart-baab0d83-f11e-4c5f-bdd7-cd8b01bdde04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935183122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3935183122
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2308810844
Short name T871
Test name
Test status
Simulation time 11360387110 ps
CPU time 15.53 seconds
Started Jul 15 06:26:26 PM PDT 24
Finished Jul 15 06:26:43 PM PDT 24
Peak memory 217492 kb
Host smart-6f8741ce-20d9-43d0-b0ae-f84571faaece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308810844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2308810844
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2584775357
Short name T546
Test name
Test status
Simulation time 2669526689 ps
CPU time 7.46 seconds
Started Jul 15 06:26:27 PM PDT 24
Finished Jul 15 06:26:35 PM PDT 24
Peak memory 217480 kb
Host smart-26bdefb6-c781-4245-931d-295c928e6b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584775357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2584775357
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3458148550
Short name T708
Test name
Test status
Simulation time 213894015 ps
CPU time 1.09 seconds
Started Jul 15 06:26:27 PM PDT 24
Finished Jul 15 06:26:29 PM PDT 24
Peak memory 208940 kb
Host smart-e0f3f481-34f8-40ae-8b70-c931d790f928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458148550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3458148550
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1067836476
Short name T673
Test name
Test status
Simulation time 208157263 ps
CPU time 0.85 seconds
Started Jul 15 06:26:28 PM PDT 24
Finished Jul 15 06:26:31 PM PDT 24
Peak memory 207028 kb
Host smart-38126cf1-7905-49ff-bc31-1cd842dd58af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067836476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1067836476
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3307932541
Short name T677
Test name
Test status
Simulation time 88487928 ps
CPU time 2.88 seconds
Started Jul 15 06:26:27 PM PDT 24
Finished Jul 15 06:26:31 PM PDT 24
Peak memory 233736 kb
Host smart-5add574b-8aaf-4704-b0e8-3bc73deaabbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307932541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3307932541
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2489912943
Short name T540
Test name
Test status
Simulation time 13688308 ps
CPU time 0.72 seconds
Started Jul 15 06:26:32 PM PDT 24
Finished Jul 15 06:26:34 PM PDT 24
Peak memory 206360 kb
Host smart-da1303e7-0c80-45a3-912a-7fa737439dfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489912943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2489912943
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1971299291
Short name T705
Test name
Test status
Simulation time 5182553230 ps
CPU time 6.31 seconds
Started Jul 15 06:26:34 PM PDT 24
Finished Jul 15 06:26:42 PM PDT 24
Peak memory 225704 kb
Host smart-b99d7cdd-14cb-4ae5-b4a6-ddcf54775ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971299291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1971299291
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1916691725
Short name T1014
Test name
Test status
Simulation time 50122325 ps
CPU time 0.78 seconds
Started Jul 15 06:26:35 PM PDT 24
Finished Jul 15 06:26:36 PM PDT 24
Peak memory 206840 kb
Host smart-b717bf24-40e5-4ab7-832a-9bf40831f4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916691725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1916691725
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3090439833
Short name T243
Test name
Test status
Simulation time 24487336667 ps
CPU time 130.17 seconds
Started Jul 15 06:26:37 PM PDT 24
Finished Jul 15 06:28:48 PM PDT 24
Peak memory 262084 kb
Host smart-787cf556-fa2b-4126-92e2-ba30a870d1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090439833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3090439833
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.449689716
Short name T483
Test name
Test status
Simulation time 4329930281 ps
CPU time 79.94 seconds
Started Jul 15 06:26:32 PM PDT 24
Finished Jul 15 06:27:53 PM PDT 24
Peak memory 251140 kb
Host smart-956e351d-6bd8-4ed2-aac2-64c97b3b08a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449689716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.449689716
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.604582558
Short name T984
Test name
Test status
Simulation time 7753028941 ps
CPU time 33.38 seconds
Started Jul 15 06:26:32 PM PDT 24
Finished Jul 15 06:27:06 PM PDT 24
Peak memory 250408 kb
Host smart-0ba29ef8-e528-44bb-a2e9-4380c6dd870b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604582558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.604582558
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1469214171
Short name T79
Test name
Test status
Simulation time 157914154 ps
CPU time 2.4 seconds
Started Jul 15 06:26:34 PM PDT 24
Finished Jul 15 06:26:38 PM PDT 24
Peak memory 225532 kb
Host smart-0f1e4e51-cda0-4c11-a455-8a8ee135cd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469214171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1469214171
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3567528297
Short name T218
Test name
Test status
Simulation time 97858720846 ps
CPU time 152.65 seconds
Started Jul 15 06:26:34 PM PDT 24
Finished Jul 15 06:29:08 PM PDT 24
Peak memory 251448 kb
Host smart-b4859802-8e73-4c8f-8a73-18dcbb0fce98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567528297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3567528297
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3265700454
Short name T272
Test name
Test status
Simulation time 3610773509 ps
CPU time 7.28 seconds
Started Jul 15 06:26:34 PM PDT 24
Finished Jul 15 06:26:42 PM PDT 24
Peak memory 233896 kb
Host smart-defdbd23-ab40-4692-bc9a-b22c61256baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265700454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3265700454
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.581511380
Short name T958
Test name
Test status
Simulation time 56395122 ps
CPU time 3.03 seconds
Started Jul 15 06:26:37 PM PDT 24
Finished Jul 15 06:26:41 PM PDT 24
Peak memory 233776 kb
Host smart-faf8420b-480c-4c76-bc94-a3c6bd7768a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581511380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.581511380
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1527326883
Short name T757
Test name
Test status
Simulation time 536918949 ps
CPU time 5.15 seconds
Started Jul 15 06:26:32 PM PDT 24
Finished Jul 15 06:26:38 PM PDT 24
Peak memory 233816 kb
Host smart-c78ec680-8230-40bc-a46e-3dcd425525c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527326883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1527326883
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3921827036
Short name T438
Test name
Test status
Simulation time 334725720 ps
CPU time 5.26 seconds
Started Jul 15 06:26:37 PM PDT 24
Finished Jul 15 06:26:43 PM PDT 24
Peak memory 225568 kb
Host smart-f30fc54f-a441-4d8c-86c1-6779c7a7869f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921827036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3921827036
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3504304892
Short name T605
Test name
Test status
Simulation time 2569146989 ps
CPU time 7.7 seconds
Started Jul 15 06:26:36 PM PDT 24
Finished Jul 15 06:26:44 PM PDT 24
Peak memory 221260 kb
Host smart-3ca9a144-118f-43e2-9c8d-663255533527
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3504304892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3504304892
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2501997662
Short name T969
Test name
Test status
Simulation time 15881589684 ps
CPU time 37.3 seconds
Started Jul 15 06:26:34 PM PDT 24
Finished Jul 15 06:27:12 PM PDT 24
Peak memory 240548 kb
Host smart-6b23475a-3d04-427c-9bb7-bc1b22db22b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501997662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2501997662
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.382138096
Short name T883
Test name
Test status
Simulation time 1268633308 ps
CPU time 2.46 seconds
Started Jul 15 06:26:33 PM PDT 24
Finished Jul 15 06:26:37 PM PDT 24
Peak memory 217632 kb
Host smart-baee418d-68f8-42f4-b8ae-2f83d315f46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382138096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.382138096
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1907638946
Short name T336
Test name
Test status
Simulation time 514644072 ps
CPU time 2.54 seconds
Started Jul 15 06:26:41 PM PDT 24
Finished Jul 15 06:26:45 PM PDT 24
Peak memory 217296 kb
Host smart-f92f74b7-d17a-481d-920d-35cfc9e5a053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907638946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1907638946
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1214129232
Short name T785
Test name
Test status
Simulation time 32243192 ps
CPU time 0.67 seconds
Started Jul 15 06:26:32 PM PDT 24
Finished Jul 15 06:26:33 PM PDT 24
Peak memory 206544 kb
Host smart-efdace4a-3ab7-44e6-8c52-71708d08ef9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214129232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1214129232
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2890323364
Short name T524
Test name
Test status
Simulation time 85626303 ps
CPU time 0.82 seconds
Started Jul 15 06:26:35 PM PDT 24
Finished Jul 15 06:26:37 PM PDT 24
Peak memory 206948 kb
Host smart-3038c4f9-bf56-48b8-8145-a4c48a732759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890323364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2890323364
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.395827752
Short name T693
Test name
Test status
Simulation time 54340933 ps
CPU time 1.99 seconds
Started Jul 15 06:26:33 PM PDT 24
Finished Jul 15 06:26:36 PM PDT 24
Peak memory 225288 kb
Host smart-9b6519c8-f64d-4f86-b137-2c52571ac504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395827752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.395827752
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.820661379
Short name T606
Test name
Test status
Simulation time 33590761 ps
CPU time 0.74 seconds
Started Jul 15 06:26:34 PM PDT 24
Finished Jul 15 06:26:36 PM PDT 24
Peak memory 206752 kb
Host smart-b5e9c24a-ce13-42f2-9e01-5172fdc5b552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820661379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.820661379
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.4191123565
Short name T743
Test name
Test status
Simulation time 435561905 ps
CPU time 2.39 seconds
Started Jul 15 06:26:35 PM PDT 24
Finished Jul 15 06:26:38 PM PDT 24
Peak memory 233704 kb
Host smart-118ef3aa-1cc0-4985-a697-ae39665d3f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191123565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.4191123565
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.25624691
Short name T950
Test name
Test status
Simulation time 35589253 ps
CPU time 0.77 seconds
Started Jul 15 06:26:32 PM PDT 24
Finished Jul 15 06:26:34 PM PDT 24
Peak memory 207888 kb
Host smart-7715eaf7-e51b-4689-ab67-2b5ff2d15be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25624691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.25624691
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2336446387
Short name T643
Test name
Test status
Simulation time 15001965885 ps
CPU time 56.8 seconds
Started Jul 15 06:26:33 PM PDT 24
Finished Jul 15 06:27:31 PM PDT 24
Peak memory 225720 kb
Host smart-d903b816-60d9-4963-bde5-63731a8814d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336446387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2336446387
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2964539874
Short name T295
Test name
Test status
Simulation time 39386181699 ps
CPU time 267.13 seconds
Started Jul 15 06:26:33 PM PDT 24
Finished Jul 15 06:31:01 PM PDT 24
Peak memory 250308 kb
Host smart-a118500e-446e-47a9-8a22-0e938766515d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964539874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2964539874
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1496773232
Short name T412
Test name
Test status
Simulation time 108213187685 ps
CPU time 106.11 seconds
Started Jul 15 06:26:33 PM PDT 24
Finished Jul 15 06:28:20 PM PDT 24
Peak memory 255276 kb
Host smart-4189c8e8-9c98-4cc8-a870-7fecbed7c49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496773232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1496773232
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.769157744
Short name T963
Test name
Test status
Simulation time 1152267566 ps
CPU time 3.66 seconds
Started Jul 15 06:26:35 PM PDT 24
Finished Jul 15 06:26:39 PM PDT 24
Peak memory 233748 kb
Host smart-dea59a17-02b9-45d3-9a8d-ac57add3dfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769157744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.769157744
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.230542345
Short name T925
Test name
Test status
Simulation time 27956581861 ps
CPU time 142.95 seconds
Started Jul 15 06:26:34 PM PDT 24
Finished Jul 15 06:28:58 PM PDT 24
Peak memory 269848 kb
Host smart-b5fe3d98-82c5-42d7-889c-9e7902eaa451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230542345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.230542345
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1513728162
Short name T216
Test name
Test status
Simulation time 1053837173 ps
CPU time 9.64 seconds
Started Jul 15 06:26:44 PM PDT 24
Finished Jul 15 06:26:56 PM PDT 24
Peak memory 233728 kb
Host smart-44d76789-fea6-468c-823b-47f212fa99aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513728162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1513728162
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4222970790
Short name T96
Test name
Test status
Simulation time 13843290917 ps
CPU time 35.3 seconds
Started Jul 15 06:26:33 PM PDT 24
Finished Jul 15 06:27:10 PM PDT 24
Peak memory 225628 kb
Host smart-46b581bd-52eb-4bbb-bcad-fb924c19bdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222970790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4222970790
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3161459543
Short name T297
Test name
Test status
Simulation time 767482312 ps
CPU time 4.55 seconds
Started Jul 15 06:26:33 PM PDT 24
Finished Jul 15 06:26:39 PM PDT 24
Peak memory 225492 kb
Host smart-c184666a-54ec-48b9-85bc-baa8c3d981c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161459543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3161459543
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.671790125
Short name T779
Test name
Test status
Simulation time 6134990469 ps
CPU time 5.75 seconds
Started Jul 15 06:26:41 PM PDT 24
Finished Jul 15 06:26:48 PM PDT 24
Peak memory 225604 kb
Host smart-24066f42-56b8-4e7a-914b-46d5395a396e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671790125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.671790125
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1331063007
Short name T899
Test name
Test status
Simulation time 243186045 ps
CPU time 4.87 seconds
Started Jul 15 06:26:33 PM PDT 24
Finished Jul 15 06:26:39 PM PDT 24
Peak memory 224220 kb
Host smart-a824d2bc-c4dc-40bb-9443-5818c53145c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1331063007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1331063007
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1619471751
Short name T882
Test name
Test status
Simulation time 7582512528 ps
CPU time 67.31 seconds
Started Jul 15 06:26:34 PM PDT 24
Finished Jul 15 06:27:43 PM PDT 24
Peak memory 235364 kb
Host smart-60a3a80b-fffb-4838-aa9d-6ab4744eee2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619471751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1619471751
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1514027024
Short name T901
Test name
Test status
Simulation time 21598723410 ps
CPU time 12.45 seconds
Started Jul 15 06:26:31 PM PDT 24
Finished Jul 15 06:26:43 PM PDT 24
Peak memory 221640 kb
Host smart-9267bf16-ffd2-4e8e-b4f8-429647886914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514027024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1514027024
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1695835370
Short name T530
Test name
Test status
Simulation time 2385884295 ps
CPU time 2.53 seconds
Started Jul 15 06:26:34 PM PDT 24
Finished Jul 15 06:26:38 PM PDT 24
Peak memory 208396 kb
Host smart-632c189f-5871-48ba-9b29-0c3c9da9816c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695835370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1695835370
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1102503185
Short name T890
Test name
Test status
Simulation time 174664800 ps
CPU time 2.03 seconds
Started Jul 15 06:26:32 PM PDT 24
Finished Jul 15 06:26:35 PM PDT 24
Peak memory 217356 kb
Host smart-f21e520b-3776-4cfe-acd5-289617559cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102503185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1102503185
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3663902778
Short name T739
Test name
Test status
Simulation time 34511963 ps
CPU time 0.73 seconds
Started Jul 15 06:26:41 PM PDT 24
Finished Jul 15 06:26:43 PM PDT 24
Peak memory 206884 kb
Host smart-14c161de-347b-44c9-8946-ab67a1febfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663902778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3663902778
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2626335731
Short name T956
Test name
Test status
Simulation time 622993288 ps
CPU time 3.98 seconds
Started Jul 15 06:26:34 PM PDT 24
Finished Jul 15 06:26:39 PM PDT 24
Peak memory 225528 kb
Host smart-af21ece0-72bd-4a5d-a047-ed2f97bc9aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626335731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2626335731
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1174756150
Short name T924
Test name
Test status
Simulation time 42708715 ps
CPU time 0.72 seconds
Started Jul 15 06:26:37 PM PDT 24
Finished Jul 15 06:26:38 PM PDT 24
Peak memory 205688 kb
Host smart-789c45b0-7717-4ec5-8467-e24f074392d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174756150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1174756150
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.528159902
Short name T922
Test name
Test status
Simulation time 138841382 ps
CPU time 2.9 seconds
Started Jul 15 06:26:38 PM PDT 24
Finished Jul 15 06:26:42 PM PDT 24
Peak memory 225616 kb
Host smart-7ab59b40-3b28-4261-9342-dbc755903656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528159902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.528159902
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.303539218
Short name T382
Test name
Test status
Simulation time 23327780 ps
CPU time 0.75 seconds
Started Jul 15 06:26:44 PM PDT 24
Finished Jul 15 06:26:46 PM PDT 24
Peak memory 206732 kb
Host smart-8343e2ac-1f2b-4736-a7f5-0053921cf175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303539218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.303539218
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2935767096
Short name T554
Test name
Test status
Simulation time 39007689069 ps
CPU time 78.78 seconds
Started Jul 15 06:26:40 PM PDT 24
Finished Jul 15 06:27:59 PM PDT 24
Peak memory 252712 kb
Host smart-31c1c476-d681-4677-b6f5-b1795602c366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935767096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2935767096
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2672321222
Short name T136
Test name
Test status
Simulation time 3678198998 ps
CPU time 18.73 seconds
Started Jul 15 06:26:40 PM PDT 24
Finished Jul 15 06:27:00 PM PDT 24
Peak memory 225792 kb
Host smart-cddc4f59-4c50-4b61-bd5c-4fc2023babe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672321222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2672321222
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.852788492
Short name T291
Test name
Test status
Simulation time 7292220570 ps
CPU time 148.52 seconds
Started Jul 15 06:26:40 PM PDT 24
Finished Jul 15 06:29:09 PM PDT 24
Peak memory 271180 kb
Host smart-b0b715e3-3ec3-4e0f-a0e1-f472d26f781a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852788492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.852788492
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2818165808
Short name T312
Test name
Test status
Simulation time 1635391396 ps
CPU time 9.73 seconds
Started Jul 15 06:26:38 PM PDT 24
Finished Jul 15 06:26:48 PM PDT 24
Peak memory 237192 kb
Host smart-eae498d4-081b-4203-9006-a26936517be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818165808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2818165808
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3180841623
Short name T409
Test name
Test status
Simulation time 10854569404 ps
CPU time 72.85 seconds
Started Jul 15 06:26:38 PM PDT 24
Finished Jul 15 06:27:52 PM PDT 24
Peak memory 255776 kb
Host smart-e2b44faa-2d8f-44b9-b70e-6ecf79f8149f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180841623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3180841623
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1333871230
Short name T404
Test name
Test status
Simulation time 497752757 ps
CPU time 4.82 seconds
Started Jul 15 06:26:38 PM PDT 24
Finished Jul 15 06:26:44 PM PDT 24
Peak memory 225560 kb
Host smart-8a47dca5-ee58-4170-bb88-bfcceb8cb5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333871230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1333871230
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3536962011
Short name T271
Test name
Test status
Simulation time 6097463490 ps
CPU time 9.51 seconds
Started Jul 15 06:26:38 PM PDT 24
Finished Jul 15 06:26:49 PM PDT 24
Peak memory 236172 kb
Host smart-455ee77a-1efe-4d7a-a3e7-5e63ad837917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536962011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3536962011
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1252919716
Short name T666
Test name
Test status
Simulation time 10234869434 ps
CPU time 13.32 seconds
Started Jul 15 06:26:38 PM PDT 24
Finished Jul 15 06:26:52 PM PDT 24
Peak memory 225672 kb
Host smart-9e11b526-79fe-4154-b359-5d39b460cff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252919716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1252919716
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2086266673
Short name T170
Test name
Test status
Simulation time 4922650280 ps
CPU time 6.87 seconds
Started Jul 15 06:26:39 PM PDT 24
Finished Jul 15 06:26:47 PM PDT 24
Peak memory 233860 kb
Host smart-fd4204af-f8ef-468c-9cfc-f7391b95a5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086266673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2086266673
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.569000893
Short name T152
Test name
Test status
Simulation time 4734794615 ps
CPU time 11.17 seconds
Started Jul 15 06:26:39 PM PDT 24
Finished Jul 15 06:26:51 PM PDT 24
Peak memory 223200 kb
Host smart-aa3d1575-045b-4fb8-9527-8b378d6f9e88
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=569000893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.569000893
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1394214296
Short name T453
Test name
Test status
Simulation time 55276132 ps
CPU time 1.04 seconds
Started Jul 15 06:26:39 PM PDT 24
Finished Jul 15 06:26:41 PM PDT 24
Peak memory 216804 kb
Host smart-ca809f94-22ee-4fe6-ac2f-b6e97be6b97d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394214296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1394214296
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2643162728
Short name T805
Test name
Test status
Simulation time 3058102493 ps
CPU time 24.03 seconds
Started Jul 15 06:26:44 PM PDT 24
Finished Jul 15 06:27:09 PM PDT 24
Peak memory 217424 kb
Host smart-f5611601-b50c-4930-a0a4-db8e3ab02cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643162728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2643162728
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3288580109
Short name T365
Test name
Test status
Simulation time 27683102877 ps
CPU time 20.89 seconds
Started Jul 15 06:26:37 PM PDT 24
Finished Jul 15 06:26:59 PM PDT 24
Peak memory 217456 kb
Host smart-65d528f7-cc00-4d87-9c20-7ad089ba862c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288580109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3288580109
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.919978517
Short name T891
Test name
Test status
Simulation time 93456560 ps
CPU time 0.72 seconds
Started Jul 15 06:26:40 PM PDT 24
Finished Jul 15 06:26:41 PM PDT 24
Peak memory 206952 kb
Host smart-900bfffa-1967-477d-ab34-ecb9bf32a4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919978517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.919978517
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3885228100
Short name T342
Test name
Test status
Simulation time 132672418 ps
CPU time 0.92 seconds
Started Jul 15 06:26:39 PM PDT 24
Finished Jul 15 06:26:41 PM PDT 24
Peak memory 206956 kb
Host smart-e366b475-7abe-470a-a710-d53fa0186af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885228100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3885228100
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.4025654516
Short name T335
Test name
Test status
Simulation time 169437229 ps
CPU time 2.18 seconds
Started Jul 15 06:26:38 PM PDT 24
Finished Jul 15 06:26:41 PM PDT 24
Peak memory 225532 kb
Host smart-32a89f89-e845-49e8-a333-cbf9b8c670a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025654516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.4025654516
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2344785420
Short name T459
Test name
Test status
Simulation time 17588476 ps
CPU time 0.7 seconds
Started Jul 15 06:23:36 PM PDT 24
Finished Jul 15 06:23:37 PM PDT 24
Peak memory 206388 kb
Host smart-f92d1409-044b-4d31-9339-4c7a0b737a1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344785420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
344785420
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1098947977
Short name T847
Test name
Test status
Simulation time 52435998 ps
CPU time 2.89 seconds
Started Jul 15 06:23:38 PM PDT 24
Finished Jul 15 06:23:42 PM PDT 24
Peak memory 233760 kb
Host smart-280f8adf-bc4b-432b-9236-902978f13ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098947977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1098947977
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3397009468
Short name T349
Test name
Test status
Simulation time 31999806 ps
CPU time 0.76 seconds
Started Jul 15 06:23:37 PM PDT 24
Finished Jul 15 06:23:39 PM PDT 24
Peak memory 207492 kb
Host smart-0bff70ef-5393-427a-8084-53019678be03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397009468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3397009468
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2935461716
Short name T231
Test name
Test status
Simulation time 314640876 ps
CPU time 8.53 seconds
Started Jul 15 06:23:38 PM PDT 24
Finished Jul 15 06:23:47 PM PDT 24
Peak memory 239160 kb
Host smart-d41d0d70-c6fd-4189-81ed-61f327168974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935461716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2935461716
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3778532186
Short name T324
Test name
Test status
Simulation time 62188479160 ps
CPU time 30.08 seconds
Started Jul 15 06:23:40 PM PDT 24
Finished Jul 15 06:24:11 PM PDT 24
Peak memory 225772 kb
Host smart-dc20c4be-5a25-4312-a612-6ce70bc4c04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778532186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3778532186
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3141853192
Short name T31
Test name
Test status
Simulation time 14451801345 ps
CPU time 144.41 seconds
Started Jul 15 06:23:38 PM PDT 24
Finished Jul 15 06:26:03 PM PDT 24
Peak memory 253540 kb
Host smart-f109f796-d503-48d5-af4b-54609d66f603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141853192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3141853192
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3323801452
Short name T573
Test name
Test status
Simulation time 4535609514 ps
CPU time 24.95 seconds
Started Jul 15 06:23:35 PM PDT 24
Finished Jul 15 06:24:01 PM PDT 24
Peak memory 242092 kb
Host smart-e6448a28-b167-44ad-91ca-694e6e6f7efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323801452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3323801452
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.599149352
Short name T474
Test name
Test status
Simulation time 28590677 ps
CPU time 0.8 seconds
Started Jul 15 06:23:37 PM PDT 24
Finished Jul 15 06:23:38 PM PDT 24
Peak memory 217244 kb
Host smart-843dceff-9375-4a70-a9c0-03a7985ddd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599149352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
599149352
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3975993723
Short name T612
Test name
Test status
Simulation time 65228854 ps
CPU time 2.52 seconds
Started Jul 15 06:23:38 PM PDT 24
Finished Jul 15 06:23:42 PM PDT 24
Peak memory 233572 kb
Host smart-46367710-9ec3-4442-a19a-6a4be17e33a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975993723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3975993723
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1123805300
Short name T258
Test name
Test status
Simulation time 755681038 ps
CPU time 10.44 seconds
Started Jul 15 06:23:39 PM PDT 24
Finished Jul 15 06:23:50 PM PDT 24
Peak memory 233692 kb
Host smart-a0ae9535-cb16-423e-b4ab-d6c4e08ad3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123805300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1123805300
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1451023948
Short name T674
Test name
Test status
Simulation time 15255604 ps
CPU time 1.02 seconds
Started Jul 15 06:23:38 PM PDT 24
Finished Jul 15 06:23:40 PM PDT 24
Peak memory 218976 kb
Host smart-90b7f63d-3a4f-47f2-9640-688374f6307c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451023948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1451023948
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1647991107
Short name T200
Test name
Test status
Simulation time 2805626605 ps
CPU time 6.04 seconds
Started Jul 15 06:23:37 PM PDT 24
Finished Jul 15 06:23:44 PM PDT 24
Peak memory 233884 kb
Host smart-75e96d2c-11ff-4fb9-a2c5-70476d4b25a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647991107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1647991107
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3064596451
Short name T860
Test name
Test status
Simulation time 1478896599 ps
CPU time 7.16 seconds
Started Jul 15 06:23:42 PM PDT 24
Finished Jul 15 06:23:50 PM PDT 24
Peak memory 233732 kb
Host smart-abbfa2cc-bf92-44b4-8b51-5735fbb69a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064596451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3064596451
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1364604757
Short name T551
Test name
Test status
Simulation time 1694698136 ps
CPU time 6.42 seconds
Started Jul 15 06:23:36 PM PDT 24
Finished Jul 15 06:23:43 PM PDT 24
Peak memory 222936 kb
Host smart-041d690d-01a4-496a-b02c-f01804fd4b93
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1364604757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1364604757
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1698726761
Short name T52
Test name
Test status
Simulation time 119135845631 ps
CPU time 596.22 seconds
Started Jul 15 06:23:39 PM PDT 24
Finished Jul 15 06:33:36 PM PDT 24
Peak memory 273104 kb
Host smart-fbf93cfb-7cdf-43d5-bca5-67c3d8cc1349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698726761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1698726761
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.808298195
Short name T319
Test name
Test status
Simulation time 9156010024 ps
CPU time 16.38 seconds
Started Jul 15 06:23:40 PM PDT 24
Finished Jul 15 06:23:57 PM PDT 24
Peak memory 217412 kb
Host smart-5ed4c0f5-745b-4d5f-a6fc-ce688e0c37c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808298195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.808298195
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1307988984
Short name T169
Test name
Test status
Simulation time 1042895089 ps
CPU time 5.15 seconds
Started Jul 15 06:23:43 PM PDT 24
Finished Jul 15 06:23:48 PM PDT 24
Peak memory 217348 kb
Host smart-3c9f37ab-c410-4260-b716-0ec1045abce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307988984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1307988984
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3779596828
Short name T355
Test name
Test status
Simulation time 156805916 ps
CPU time 1.2 seconds
Started Jul 15 06:23:40 PM PDT 24
Finished Jul 15 06:23:42 PM PDT 24
Peak memory 208008 kb
Host smart-0df59ad2-779a-4e3b-b840-68f7f6005db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779596828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3779596828
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1630151402
Short name T627
Test name
Test status
Simulation time 66773168 ps
CPU time 0.86 seconds
Started Jul 15 06:23:37 PM PDT 24
Finished Jul 15 06:23:38 PM PDT 24
Peak memory 206892 kb
Host smart-0c2790ff-a61f-4f09-851d-3ce8c2720826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630151402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1630151402
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3274266048
Short name T250
Test name
Test status
Simulation time 5714598693 ps
CPU time 8.74 seconds
Started Jul 15 06:23:37 PM PDT 24
Finished Jul 15 06:23:47 PM PDT 24
Peak memory 225684 kb
Host smart-4300877f-80b7-452f-b857-809272b7efe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274266048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3274266048
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2508315696
Short name T898
Test name
Test status
Simulation time 139403382 ps
CPU time 0.72 seconds
Started Jul 15 06:23:47 PM PDT 24
Finished Jul 15 06:23:48 PM PDT 24
Peak memory 206376 kb
Host smart-61a87fac-03ca-40f5-b61e-39a8cb2c66f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508315696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
508315696
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3952007747
Short name T275
Test name
Test status
Simulation time 4558447052 ps
CPU time 8.53 seconds
Started Jul 15 06:23:44 PM PDT 24
Finished Jul 15 06:23:53 PM PDT 24
Peak memory 233852 kb
Host smart-a1be1a7d-ebe5-4f9b-b22a-5971914169f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952007747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3952007747
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.4006341219
Short name T587
Test name
Test status
Simulation time 31601265 ps
CPU time 0.8 seconds
Started Jul 15 06:23:46 PM PDT 24
Finished Jul 15 06:23:48 PM PDT 24
Peak memory 206472 kb
Host smart-2e9167bd-8f33-4db4-a81d-cf0757d75cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006341219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.4006341219
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.158257835
Short name T583
Test name
Test status
Simulation time 9599498702 ps
CPU time 18.92 seconds
Started Jul 15 06:23:46 PM PDT 24
Finished Jul 15 06:24:05 PM PDT 24
Peak memory 233860 kb
Host smart-e1aed292-1f47-4ea4-937d-b314732afa07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158257835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.158257835
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.615377245
Short name T515
Test name
Test status
Simulation time 56085430222 ps
CPU time 258.76 seconds
Started Jul 15 06:23:45 PM PDT 24
Finished Jul 15 06:28:04 PM PDT 24
Peak memory 250376 kb
Host smart-08907d02-91c9-4d13-b686-13759f77acac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615377245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.615377245
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.503301306
Short name T796
Test name
Test status
Simulation time 11557360583 ps
CPU time 68.23 seconds
Started Jul 15 06:23:49 PM PDT 24
Finished Jul 15 06:24:57 PM PDT 24
Peak memory 255292 kb
Host smart-e262a110-c632-4176-b55e-024218feafe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503301306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
503301306
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2758072174
Short name T307
Test name
Test status
Simulation time 2496863270 ps
CPU time 37.52 seconds
Started Jul 15 06:23:46 PM PDT 24
Finished Jul 15 06:24:24 PM PDT 24
Peak memory 242028 kb
Host smart-d208e1c1-10b7-4ec1-9133-56486f9f9c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758072174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2758072174
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.112490308
Short name T630
Test name
Test status
Simulation time 3868153328 ps
CPU time 12.44 seconds
Started Jul 15 06:23:45 PM PDT 24
Finished Jul 15 06:23:58 PM PDT 24
Peak memory 225660 kb
Host smart-d09dba6c-46c8-4771-aeb1-54865c0f5d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112490308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.112490308
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3904573676
Short name T232
Test name
Test status
Simulation time 239733968 ps
CPU time 7.18 seconds
Started Jul 15 06:23:47 PM PDT 24
Finished Jul 15 06:23:55 PM PDT 24
Peak memory 233720 kb
Host smart-88d933a7-d65e-4e52-8dd4-55d86a3b8e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904573676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3904573676
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2739507047
Short name T840
Test name
Test status
Simulation time 30677429 ps
CPU time 1.03 seconds
Started Jul 15 06:23:48 PM PDT 24
Finished Jul 15 06:23:49 PM PDT 24
Peak memory 218872 kb
Host smart-2245f31a-11b5-4f08-834f-0f6b4e027b7b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739507047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2739507047
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2530409325
Short name T263
Test name
Test status
Simulation time 205148602 ps
CPU time 2.26 seconds
Started Jul 15 06:23:44 PM PDT 24
Finished Jul 15 06:23:47 PM PDT 24
Peak memory 225588 kb
Host smart-44211d2d-f522-4bec-a50c-d6d99744090e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530409325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2530409325
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2018476300
Short name T562
Test name
Test status
Simulation time 361920582 ps
CPU time 4.42 seconds
Started Jul 15 06:23:45 PM PDT 24
Finished Jul 15 06:23:50 PM PDT 24
Peak memory 238376 kb
Host smart-8f98cca8-d9ad-4f79-adda-02b12ba6f4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018476300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2018476300
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.775124725
Short name T465
Test name
Test status
Simulation time 1922842407 ps
CPU time 8.65 seconds
Started Jul 15 06:23:46 PM PDT 24
Finished Jul 15 06:23:55 PM PDT 24
Peak memory 224104 kb
Host smart-c3b22772-e140-4e37-92e1-ec6773284ebf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=775124725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.775124725
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.115667512
Short name T198
Test name
Test status
Simulation time 1869313961 ps
CPU time 14.16 seconds
Started Jul 15 06:23:45 PM PDT 24
Finished Jul 15 06:24:00 PM PDT 24
Peak memory 225672 kb
Host smart-9877d5ef-54f4-4a50-a8ea-12cc64bbcb60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115667512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.115667512
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1132949001
Short name T822
Test name
Test status
Simulation time 1204758577 ps
CPU time 3.47 seconds
Started Jul 15 06:23:46 PM PDT 24
Finished Jul 15 06:23:50 PM PDT 24
Peak memory 217364 kb
Host smart-bca86468-7c5d-421a-af76-51933d711c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132949001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1132949001
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2034247625
Short name T27
Test name
Test status
Simulation time 4550348943 ps
CPU time 15.29 seconds
Started Jul 15 06:23:46 PM PDT 24
Finished Jul 15 06:24:01 PM PDT 24
Peak memory 217484 kb
Host smart-46690e98-9359-441c-8bb5-9d5ab4b7bd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034247625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2034247625
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1144642066
Short name T437
Test name
Test status
Simulation time 12596580 ps
CPU time 0.68 seconds
Started Jul 15 06:23:46 PM PDT 24
Finished Jul 15 06:23:48 PM PDT 24
Peak memory 206560 kb
Host smart-430af4b8-4f83-4cb5-930e-deeade8e9118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144642066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1144642066
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.839905187
Short name T497
Test name
Test status
Simulation time 162616267 ps
CPU time 0.88 seconds
Started Jul 15 06:23:47 PM PDT 24
Finished Jul 15 06:23:49 PM PDT 24
Peak memory 207440 kb
Host smart-a194169d-97fd-475b-a391-95a1014c8829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839905187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.839905187
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.122399753
Short name T793
Test name
Test status
Simulation time 19086469097 ps
CPU time 14.53 seconds
Started Jul 15 06:23:44 PM PDT 24
Finished Jul 15 06:23:59 PM PDT 24
Peak memory 233908 kb
Host smart-3ce695c6-76f1-4527-8acf-15858d260463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122399753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.122399753
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4148427106
Short name T331
Test name
Test status
Simulation time 45347563 ps
CPU time 0.76 seconds
Started Jul 15 06:23:54 PM PDT 24
Finished Jul 15 06:23:56 PM PDT 24
Peak memory 205784 kb
Host smart-119c9283-ad44-4522-a789-8a289da1f8d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148427106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
148427106
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.645704815
Short name T977
Test name
Test status
Simulation time 980824815 ps
CPU time 3.4 seconds
Started Jul 15 06:23:44 PM PDT 24
Finished Jul 15 06:23:48 PM PDT 24
Peak memory 225424 kb
Host smart-82627940-d63a-4ad3-8ccd-def820beff26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645704815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.645704815
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3752762792
Short name T452
Test name
Test status
Simulation time 20332794 ps
CPU time 0.77 seconds
Started Jul 15 06:23:48 PM PDT 24
Finished Jul 15 06:23:49 PM PDT 24
Peak memory 206488 kb
Host smart-29af400e-af7b-4b32-ad0f-0e84f3dc3f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752762792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3752762792
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1987679705
Short name T303
Test name
Test status
Simulation time 5481989682 ps
CPU time 34.7 seconds
Started Jul 15 06:23:58 PM PDT 24
Finished Jul 15 06:24:34 PM PDT 24
Peak memory 242084 kb
Host smart-df4dbbd8-85df-44f2-b519-4b3788832030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987679705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1987679705
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.821485073
Short name T224
Test name
Test status
Simulation time 79985648166 ps
CPU time 177.7 seconds
Started Jul 15 06:23:55 PM PDT 24
Finished Jul 15 06:26:54 PM PDT 24
Peak memory 250880 kb
Host smart-906fb74b-1fc7-4736-b8fe-5967def2e64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821485073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.821485073
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2672816523
Short name T228
Test name
Test status
Simulation time 54718663515 ps
CPU time 479.02 seconds
Started Jul 15 06:23:54 PM PDT 24
Finished Jul 15 06:31:55 PM PDT 24
Peak memory 262232 kb
Host smart-5a0a9423-0aef-48f7-b9c4-90a7c58294dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672816523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2672816523
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3939031
Short name T894
Test name
Test status
Simulation time 10116780363 ps
CPU time 100.74 seconds
Started Jul 15 06:23:46 PM PDT 24
Finished Jul 15 06:25:27 PM PDT 24
Peak memory 266656 kb
Host smart-a02c8891-291e-4832-8fa9-a9af9d4d5947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.3939031
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1732238970
Short name T865
Test name
Test status
Simulation time 42207890 ps
CPU time 2.32 seconds
Started Jul 15 06:23:46 PM PDT 24
Finished Jul 15 06:23:49 PM PDT 24
Peak memory 233476 kb
Host smart-4739bdcd-000a-4d8b-ba70-1e124cd909e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732238970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1732238970
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3779708183
Short name T817
Test name
Test status
Simulation time 3776263006 ps
CPU time 36.99 seconds
Started Jul 15 06:23:47 PM PDT 24
Finished Jul 15 06:24:25 PM PDT 24
Peak memory 238332 kb
Host smart-40b6e094-8d72-4b5d-ad31-c3e4def4b6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779708183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3779708183
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.127924954
Short name T962
Test name
Test status
Simulation time 20192461 ps
CPU time 1.01 seconds
Started Jul 15 06:23:45 PM PDT 24
Finished Jul 15 06:23:47 PM PDT 24
Peak memory 217716 kb
Host smart-53d182db-0089-4a5e-8576-ab6ea5c733ca
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127924954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.127924954
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.4184448706
Short name T517
Test name
Test status
Simulation time 333912093 ps
CPU time 3.02 seconds
Started Jul 15 06:23:49 PM PDT 24
Finished Jul 15 06:23:52 PM PDT 24
Peak memory 225484 kb
Host smart-43099d1c-8f25-4cf0-80a5-abc004829433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184448706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.4184448706
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1538649726
Short name T1000
Test name
Test status
Simulation time 2317654984 ps
CPU time 6.01 seconds
Started Jul 15 06:23:46 PM PDT 24
Finished Jul 15 06:23:53 PM PDT 24
Peak memory 233820 kb
Host smart-fa2dd37b-9e36-4a4f-b253-dbec6d0aa3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538649726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1538649726
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.711302722
Short name T156
Test name
Test status
Simulation time 305314957 ps
CPU time 4.26 seconds
Started Jul 15 06:23:47 PM PDT 24
Finished Jul 15 06:23:52 PM PDT 24
Peak memory 223560 kb
Host smart-795d1507-6734-4cc2-b73b-faa8f374b1cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=711302722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.711302722
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3894916182
Short name T948
Test name
Test status
Simulation time 147515665927 ps
CPU time 1288.18 seconds
Started Jul 15 06:23:58 PM PDT 24
Finished Jul 15 06:45:28 PM PDT 24
Peak memory 287716 kb
Host smart-b9494715-d225-464b-9f54-908ef92c8fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894916182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3894916182
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.138043052
Short name T475
Test name
Test status
Simulation time 834237727 ps
CPU time 3.39 seconds
Started Jul 15 06:23:47 PM PDT 24
Finished Jul 15 06:23:51 PM PDT 24
Peak memory 217480 kb
Host smart-4fb664bd-0caa-4827-a474-dc50c9e1f14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138043052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.138043052
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3762370029
Short name T428
Test name
Test status
Simulation time 89942221478 ps
CPU time 23.39 seconds
Started Jul 15 06:23:44 PM PDT 24
Finished Jul 15 06:24:09 PM PDT 24
Peak memory 219264 kb
Host smart-6d307236-3e55-4822-8584-304cf93088f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762370029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3762370029
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.636751196
Short name T343
Test name
Test status
Simulation time 40362159 ps
CPU time 0.99 seconds
Started Jul 15 06:23:45 PM PDT 24
Finished Jul 15 06:23:47 PM PDT 24
Peak memory 208384 kb
Host smart-efa5a41e-72ca-4877-8557-9ee2b1a68e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636751196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.636751196
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.611671464
Short name T24
Test name
Test status
Simulation time 21794102 ps
CPU time 0.71 seconds
Started Jul 15 06:23:47 PM PDT 24
Finished Jul 15 06:23:49 PM PDT 24
Peak memory 206496 kb
Host smart-febc1823-b29d-4c3d-ad79-b51d32e9c501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611671464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.611671464
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1398517065
Short name T999
Test name
Test status
Simulation time 1510896957 ps
CPU time 7.85 seconds
Started Jul 15 06:23:46 PM PDT 24
Finished Jul 15 06:23:54 PM PDT 24
Peak memory 233732 kb
Host smart-13830c4e-1133-4f25-8d88-6d1a05d3b411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398517065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1398517065
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2184235891
Short name T387
Test name
Test status
Simulation time 15924295 ps
CPU time 0.77 seconds
Started Jul 15 06:23:54 PM PDT 24
Finished Jul 15 06:23:56 PM PDT 24
Peak memory 206428 kb
Host smart-22db1149-c177-4b71-921f-8da40e2fe533
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184235891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
184235891
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1448938883
Short name T547
Test name
Test status
Simulation time 614404341 ps
CPU time 5.06 seconds
Started Jul 15 06:23:53 PM PDT 24
Finished Jul 15 06:23:59 PM PDT 24
Peak memory 233708 kb
Host smart-58a316e1-907f-4e09-bc00-2abbb6ec795a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448938883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1448938883
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3171352514
Short name T358
Test name
Test status
Simulation time 16800575 ps
CPU time 0.8 seconds
Started Jul 15 06:23:54 PM PDT 24
Finished Jul 15 06:23:55 PM PDT 24
Peak memory 207500 kb
Host smart-858c5aca-7b48-4a22-b48f-bfe02561a96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171352514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3171352514
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1881306071
Short name T699
Test name
Test status
Simulation time 12250554893 ps
CPU time 30.86 seconds
Started Jul 15 06:23:57 PM PDT 24
Finished Jul 15 06:24:29 PM PDT 24
Peak memory 242004 kb
Host smart-f7c7898c-14c3-46d4-8599-215191217043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881306071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1881306071
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3518807710
Short name T986
Test name
Test status
Simulation time 5039987314 ps
CPU time 58.17 seconds
Started Jul 15 06:23:58 PM PDT 24
Finished Jul 15 06:24:57 PM PDT 24
Peak memory 264712 kb
Host smart-7975b3b9-084b-4828-a5d6-e9b9234a29d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518807710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3518807710
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1058674013
Short name T636
Test name
Test status
Simulation time 11723638836 ps
CPU time 29.73 seconds
Started Jul 15 06:23:54 PM PDT 24
Finished Jul 15 06:24:24 PM PDT 24
Peak memory 218812 kb
Host smart-81e94c97-a8d8-4663-944a-669dc1dd9149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058674013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1058674013
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3952513261
Short name T490
Test name
Test status
Simulation time 513856080 ps
CPU time 8.81 seconds
Started Jul 15 06:23:59 PM PDT 24
Finished Jul 15 06:24:09 PM PDT 24
Peak memory 225564 kb
Host smart-f4e20471-5f15-4155-b349-6fea03e0fc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952513261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3952513261
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1000742746
Short name T384
Test name
Test status
Simulation time 12177102868 ps
CPU time 58.67 seconds
Started Jul 15 06:23:54 PM PDT 24
Finished Jul 15 06:24:54 PM PDT 24
Peak memory 239116 kb
Host smart-67ed1583-c4f0-4f07-a279-ab5964797a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000742746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1000742746
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.306031927
Short name T433
Test name
Test status
Simulation time 135581094 ps
CPU time 2.56 seconds
Started Jul 15 06:23:58 PM PDT 24
Finished Jul 15 06:24:02 PM PDT 24
Peak memory 233548 kb
Host smart-e4f95083-5591-40a5-996d-b8104cd03d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306031927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.306031927
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.230491586
Short name T425
Test name
Test status
Simulation time 151131073 ps
CPU time 4.03 seconds
Started Jul 15 06:23:59 PM PDT 24
Finished Jul 15 06:24:04 PM PDT 24
Peak memory 225564 kb
Host smart-dc61e07a-4247-40c7-928b-9c62b5c34b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230491586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.230491586
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.158333418
Short name T690
Test name
Test status
Simulation time 28811959 ps
CPU time 1.01 seconds
Started Jul 15 06:23:56 PM PDT 24
Finished Jul 15 06:23:58 PM PDT 24
Peak memory 217648 kb
Host smart-c5521c9a-78f4-41ac-9ceb-2b9fda491ad0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158333418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.158333418
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4291080119
Short name T989
Test name
Test status
Simulation time 923083883 ps
CPU time 5.57 seconds
Started Jul 15 06:23:58 PM PDT 24
Finished Jul 15 06:24:05 PM PDT 24
Peak memory 233788 kb
Host smart-e251ed83-fde8-4548-9e70-5453213db1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291080119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4291080119
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1719007419
Short name T892
Test name
Test status
Simulation time 2032832591 ps
CPU time 5.58 seconds
Started Jul 15 06:23:56 PM PDT 24
Finished Jul 15 06:24:03 PM PDT 24
Peak memory 225496 kb
Host smart-3abf94e4-1e1c-4d43-b2e5-fed74d6fefd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719007419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1719007419
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.339844786
Short name T695
Test name
Test status
Simulation time 1110859537 ps
CPU time 11.46 seconds
Started Jul 15 06:23:58 PM PDT 24
Finished Jul 15 06:24:11 PM PDT 24
Peak memory 220396 kb
Host smart-33664374-36fb-4102-a03f-a383cb6dbae8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=339844786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.339844786
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3030951379
Short name T795
Test name
Test status
Simulation time 25146986537 ps
CPU time 95.17 seconds
Started Jul 15 06:23:57 PM PDT 24
Finished Jul 15 06:25:34 PM PDT 24
Peak memory 258576 kb
Host smart-db56139c-a8db-4731-8c69-0aaddd750b6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030951379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3030951379
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2856303173
Short name T893
Test name
Test status
Simulation time 54386054 ps
CPU time 0.73 seconds
Started Jul 15 06:23:55 PM PDT 24
Finished Jul 15 06:23:57 PM PDT 24
Peak memory 206928 kb
Host smart-383e233d-061a-4d71-ad97-fbb153d75878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856303173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2856303173
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.102348741
Short name T441
Test name
Test status
Simulation time 93464560 ps
CPU time 1.22 seconds
Started Jul 15 06:23:55 PM PDT 24
Finished Jul 15 06:23:58 PM PDT 24
Peak memory 208068 kb
Host smart-4fc98ab3-4943-4de8-b56d-8a73294be7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102348741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.102348741
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3274094085
Short name T569
Test name
Test status
Simulation time 14248126 ps
CPU time 0.88 seconds
Started Jul 15 06:23:57 PM PDT 24
Finished Jul 15 06:23:59 PM PDT 24
Peak memory 207944 kb
Host smart-07eccb5f-c4ab-4dea-a7b9-2212c10940b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274094085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3274094085
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2337568900
Short name T534
Test name
Test status
Simulation time 179456252 ps
CPU time 0.71 seconds
Started Jul 15 06:23:55 PM PDT 24
Finished Jul 15 06:23:57 PM PDT 24
Peak memory 206956 kb
Host smart-ee19271a-1393-4321-8568-70b9dec7f12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337568900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2337568900
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.473221648
Short name T246
Test name
Test status
Simulation time 21945728819 ps
CPU time 38.89 seconds
Started Jul 15 06:23:53 PM PDT 24
Finished Jul 15 06:24:33 PM PDT 24
Peak memory 250304 kb
Host smart-2ee2ea56-261b-4bc7-aa87-31944213efa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473221648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.473221648
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.349925159
Short name T683
Test name
Test status
Simulation time 20114536 ps
CPU time 0.69 seconds
Started Jul 15 06:23:56 PM PDT 24
Finished Jul 15 06:23:58 PM PDT 24
Peak memory 205696 kb
Host smart-afdc384a-3a81-4d0a-b0a2-78d99bc036ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349925159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.349925159
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2487580453
Short name T435
Test name
Test status
Simulation time 434906795 ps
CPU time 4.54 seconds
Started Jul 15 06:23:56 PM PDT 24
Finished Jul 15 06:24:02 PM PDT 24
Peak memory 233692 kb
Host smart-89ce3e68-6e13-4dde-93ab-ffa0eb683860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487580453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2487580453
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2278748787
Short name T78
Test name
Test status
Simulation time 15435239 ps
CPU time 0.77 seconds
Started Jul 15 06:23:54 PM PDT 24
Finished Jul 15 06:23:55 PM PDT 24
Peak memory 207528 kb
Host smart-698a158d-95f3-4b04-9304-a291c5373e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278748787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2278748787
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3783226121
Short name T268
Test name
Test status
Simulation time 94514454514 ps
CPU time 305.41 seconds
Started Jul 15 06:23:58 PM PDT 24
Finished Jul 15 06:29:05 PM PDT 24
Peak memory 257784 kb
Host smart-fe934273-67b8-45d7-8a0e-9680c562cbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783226121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3783226121
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1792255380
Short name T870
Test name
Test status
Simulation time 8951530465 ps
CPU time 52.53 seconds
Started Jul 15 06:23:55 PM PDT 24
Finished Jul 15 06:24:49 PM PDT 24
Peak memory 252480 kb
Host smart-21a27717-ad11-49c0-8bd2-dfb5363e1bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792255380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1792255380
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1519289446
Short name T196
Test name
Test status
Simulation time 39566338251 ps
CPU time 110.6 seconds
Started Jul 15 06:23:56 PM PDT 24
Finished Jul 15 06:25:48 PM PDT 24
Peak memory 266776 kb
Host smart-dba9ae8a-488b-46a2-8dd6-65998687ce6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519289446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1519289446
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2385548806
Short name T317
Test name
Test status
Simulation time 3584514695 ps
CPU time 30.16 seconds
Started Jul 15 06:23:58 PM PDT 24
Finished Jul 15 06:24:30 PM PDT 24
Peak memory 242056 kb
Host smart-816dfd15-e3f1-4bfd-9d26-f210108c77c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385548806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2385548806
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1213295038
Short name T279
Test name
Test status
Simulation time 106919710530 ps
CPU time 376.53 seconds
Started Jul 15 06:23:54 PM PDT 24
Finished Jul 15 06:30:13 PM PDT 24
Peak memory 255440 kb
Host smart-62ecdbc7-c14d-4732-915b-15d884e63adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213295038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1213295038
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2905376883
Short name T867
Test name
Test status
Simulation time 73177911 ps
CPU time 3.42 seconds
Started Jul 15 06:23:57 PM PDT 24
Finished Jul 15 06:24:01 PM PDT 24
Peak memory 233652 kb
Host smart-108ae0ea-f229-4636-8305-0c778dfafd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905376883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2905376883
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1397882389
Short name T616
Test name
Test status
Simulation time 3416571631 ps
CPU time 15.53 seconds
Started Jul 15 06:23:54 PM PDT 24
Finished Jul 15 06:24:11 PM PDT 24
Peak memory 241828 kb
Host smart-6a4aced5-34b6-4661-81c5-60574c8f1831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397882389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1397882389
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2461073355
Short name T372
Test name
Test status
Simulation time 35453647 ps
CPU time 1.08 seconds
Started Jul 15 06:23:55 PM PDT 24
Finished Jul 15 06:23:57 PM PDT 24
Peak memory 217540 kb
Host smart-4cbd9214-7e03-4fca-b21a-559d1ad23de3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461073355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2461073355
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2438001568
Short name T385
Test name
Test status
Simulation time 121567006 ps
CPU time 2.59 seconds
Started Jul 15 06:23:54 PM PDT 24
Finished Jul 15 06:23:58 PM PDT 24
Peak memory 233448 kb
Host smart-de58d619-3b40-4c62-ae84-549a9ec56546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438001568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2438001568
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.346569275
Short name T527
Test name
Test status
Simulation time 790432463 ps
CPU time 2.97 seconds
Started Jul 15 06:23:57 PM PDT 24
Finished Jul 15 06:24:01 PM PDT 24
Peak memory 233708 kb
Host smart-66ba15b7-6c5c-4c78-9a49-446df08f5e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346569275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.346569275
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2308775802
Short name T864
Test name
Test status
Simulation time 1022922987 ps
CPU time 5.67 seconds
Started Jul 15 06:23:55 PM PDT 24
Finished Jul 15 06:24:02 PM PDT 24
Peak memory 224032 kb
Host smart-0bbbcd42-d8f5-456d-a447-343207a6496e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2308775802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2308775802
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2917094070
Short name T6
Test name
Test status
Simulation time 1283786696 ps
CPU time 12.08 seconds
Started Jul 15 06:23:58 PM PDT 24
Finished Jul 15 06:24:11 PM PDT 24
Peak memory 225684 kb
Host smart-084d3444-a127-4ca0-b432-3eb3f02f2ad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917094070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2917094070
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4285573845
Short name T973
Test name
Test status
Simulation time 6475803341 ps
CPU time 37.17 seconds
Started Jul 15 06:23:56 PM PDT 24
Finished Jul 15 06:24:34 PM PDT 24
Peak memory 217428 kb
Host smart-5dd24937-6eff-4309-98f5-f7352ae21f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285573845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4285573845
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2457308815
Short name T953
Test name
Test status
Simulation time 38085932 ps
CPU time 0.74 seconds
Started Jul 15 06:23:56 PM PDT 24
Finished Jul 15 06:23:58 PM PDT 24
Peak memory 206640 kb
Host smart-0ccc0a59-f46f-4030-9d46-dfc10fab4dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457308815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2457308815
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1088293424
Short name T964
Test name
Test status
Simulation time 442280772 ps
CPU time 7.75 seconds
Started Jul 15 06:23:57 PM PDT 24
Finished Jul 15 06:24:06 PM PDT 24
Peak memory 217348 kb
Host smart-5d680f5d-580c-4ea4-9ddf-7add418371ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088293424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1088293424
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3649404898
Short name T26
Test name
Test status
Simulation time 40059133 ps
CPU time 0.72 seconds
Started Jul 15 06:23:54 PM PDT 24
Finished Jul 15 06:23:56 PM PDT 24
Peak memory 207024 kb
Host smart-36e01bd4-ab9b-4fdf-8e44-acb343c712d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649404898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3649404898
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3992874787
Short name T504
Test name
Test status
Simulation time 764899363 ps
CPU time 4.87 seconds
Started Jul 15 06:23:52 PM PDT 24
Finished Jul 15 06:23:58 PM PDT 24
Peak memory 225556 kb
Host smart-60cd2ab4-863f-41c7-8f17-abdbcf1cf714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992874787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3992874787
Directory /workspace/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%