Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2230730	1			T1	1		T2	1		T3	664
all_values[1]	2230730	1			T1	1		T2	1		T3	664
all_values[2]	2230730	1			T1	1		T2	1		T3	664
all_values[3]	2230730	1			T1	1		T2	1		T3	664
all_values[4]	2230730	1			T1	1		T2	1		T3	664
all_values[5]	2230730	1			T1	1		T2	1		T3	664
all_values[6]	2230730	1			T1	1		T2	1		T3	664
all_values[7]	2230730	1			T1	1		T2	1		T3	664

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17642522

1

T1

8

T2

8

T3

5312

auto[1]

203318

1

T18

50

T19

60

T20

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17820704

1

T1

8

T2

8

T3

5312

auto[1]

25136

1

T5

211

T15

49

T17

184

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2181127	1			T1	1		T2	1		T3	664
all_values[0]	auto[0]	auto[1]	11935	1			T5	122		T15	49		T17	96
all_values[0]	auto[1]	auto[0]	37287	1			T18	1		T19	7		T160	4
all_values[0]	auto[1]	auto[1]	381	1			T18	3		T19	4		T20	5
all_values[1]	auto[0]	auto[0]	2216377	1			T1	1		T2	1		T3	664
all_values[1]	auto[0]	auto[1]	8092	1			T5	77		T17	71		T30	93
all_values[1]	auto[1]	auto[0]	6067	1			T18	2		T19	6		T21	4
all_values[1]	auto[1]	auto[1]	194	1			T18	3		T19	4		T20	5
all_values[2]	auto[0]	auto[0]	2202672	1			T1	1		T2	1		T3	664
all_values[2]	auto[0]	auto[1]	2446	1			T5	12		T17	17		T30	8
all_values[2]	auto[1]	auto[0]	25425	1			T18	3		T19	3		T20	2
all_values[2]	auto[1]	auto[1]	187	1			T18	3		T19	3		T20	3
all_values[3]	auto[0]	auto[0]	2187281	1			T1	1		T2	1		T3	664
all_values[3]	auto[0]	auto[1]	210	1			T18	3		T19	4		T20	7
all_values[3]	auto[1]	auto[0]	43055	1			T18	3		T19	5		T160	6
all_values[3]	auto[1]	auto[1]	184	1			T18	3		T19	1		T21	3
all_values[4]	auto[0]	auto[0]	2189625	1			T1	1		T2	1		T3	664
all_values[4]	auto[0]	auto[1]	184	1			T54	1		T18	1		T19	5
all_values[4]	auto[1]	auto[0]	40736	1			T18	6		T19	7		T20	1
all_values[4]	auto[1]	auto[1]	185	1			T18	2		T19	3		T20	3
all_values[5]	auto[0]	auto[0]	2199622	1			T1	1		T2	1		T3	664
all_values[5]	auto[0]	auto[1]	187	1			T18	4		T19	3		T160	2
all_values[5]	auto[1]	auto[0]	30760	1			T18	2		T19	4		T20	4
all_values[5]	auto[1]	auto[1]	161	1			T18	3		T19	3		T20	3
all_values[6]	auto[0]	auto[0]	2225981	1			T1	1		T2	1		T3	664
all_values[6]	auto[0]	auto[1]	206	1			T18	1		T19	1		T20	4
all_values[6]	auto[1]	auto[0]	4369	1			T18	6		T19	1		T20	2
all_values[6]	auto[1]	auto[1]	174	1			T18	2		T19	3		T20	2
all_values[7]	auto[0]	auto[0]	2216371	1			T1	1		T2	1		T3	664
all_values[7]	auto[0]	auto[1]	206	1			T18	2		T19	2		T20	5
all_values[7]	auto[1]	auto[0]	13949	1			T18	4		T19	6		T20	1
all_values[7]	auto[1]	auto[1]	204	1			T18	4		T20	4		T160	1