Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33840	1			T4	50		T5	197		T7	4
auto[SpiFlashAddrCfg]	7586	1			T4	14		T5	70		T7	2
auto[SpiFlashAddr3b]	8729	1			T4	17		T5	47		T15	7
auto[SpiFlashAddr4b]	7271	1			T2	1		T4	9		T5	56

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32364

1

T2

1

T4

69

T5

207

auto[1]

25062

1

T4

21

T5

163

T11

8

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30229

1

T4

57

T5

232

T11

6

auto[1]

27197

1

T2

1

T4

33

T5

138

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38359	1			T4	65		T5	210		T7	4
values[1]	1076	1			T5	11		T15	3		T17	2
values[2]	1438	1			T4	2		T5	12		T30	10
values[3]	1436	1			T4	4		T5	14		T17	2
values[4]	1395	1			T2	1		T5	5		T7	2
values[5]	1447	1			T4	2		T5	4		T15	4
values[6]	1409	1			T5	9		T15	8		T17	7
values[7]	1419	1			T4	2		T5	18		T15	4
values[8]	9447	1			T4	15		T5	87		T7	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31119

1

T5

370

T7

8

T11

8

auto[1]

26307

1

T2

1

T4

90

T15

82

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54255

1

T2

1

T4

85

T5

357

write

3171

1

T4

5

T5

13

T11

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18622

1

T2

1

T4

29

T5

134

valids[0x1]

38804

1

T4

61

T5

236

T7

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1525	1			T4	1		T5	12		T11	4
internal_process_ops[0x5a]	1489	1			T4	3		T5	6		T15	3
internal_process_ops[0x05]	20308	1			T4	32		T5	121		T7	2
internal_process_ops[0x35]	1616	1			T4	2		T5	11		T7	2
internal_process_ops[0x15]	1507	1			T5	10		T11	2		T15	3
internal_process_ops[0x03]	1038	1			T5	6		T16	4		T30	2
internal_process_ops[0x0b]	970	1			T5	10		T17	2		T30	4
internal_process_ops[0x3b]	1036	1			T5	10		T15	1		T17	1
internal_process_ops[0x6b]	1039	1			T5	10		T7	2		T15	2
internal_process_ops[0xbb]	995	1			T5	10		T7	2		T30	1
internal_process_ops[0xeb]	1031	1			T2	1		T4	1		T5	11

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55882

1

T2

1

T4

89

T5

361

auto[1]

1544

1

T4

1

T5

9

T11

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55129

1

T2

1

T4

85

T5

362

auto[1]

2297

1

T4

5

T5

8

T15

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10738

1

T5

119

T7

4

T13

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6687

1

T5

77

T11

6

T57

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2045

1

T5

26

T7

2

T16

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1841

1

T5

44

T57

2

T28

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2302

1

T5

23

T16

2

T39

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2163

1

T5

17

T57

2

T28

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1980

1

T5

30

T7

2

T39

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1741

1

T5

21

T57

2

T28

10

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

120

1

T5

1

T41

2

T51

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

80

1

T58

1

T64

1

T74

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

89

1

T51

7

T64

2

T181

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

108

1

T61

1

T51

2

T60

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

111

1

T63

1

T60

1

T193

6

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

80

1

T50

2

T74

1

T153

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

88

1

T51

2

T74

1

T181

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

121

1

T11

2

T58

1

T51

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

115

1

T5

1

T50

4

T116

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

98

1

T5

4

T61

1

T51

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

97

1

T5

1

T181

1

T160

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

103

1

T5

1

T60

1

T74

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

134

1

T5

1

T56

4

T41

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

68

1

T5

2

T181

2

T194

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

87

1

T51

3

T63

1

T181

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

123

1

T5

2

T58

1

T50

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9043

1

T4

42

T15

39

T17

95

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6549

1

T4

8

T15

5

T17

45

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1513

1

T4

3

T15

6

T17

12

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1403

1

T4

9

T15

6

T17

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1791

1

T4

10

T15

5

T17

16

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1675

1

T4

4

T15

1

T17

21

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1387

1

T2

1

T4

9

T15

8

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1397

1

T15

9

T17

13

T30

28

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

118

1

T17

1

T33

4

T65

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

103

1

T17

2

T33

2

T66

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

102

1

T15

2

T49

4

T67

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

103

1

T17

4

T30

1

T90

7

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

105

1

T4

1

T30

3

T49

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

91

1

T4

1

T17

1

T30

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

71

1

T30

2

T49

3

T33

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

117

1

T17

1

T30

2

T48

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

92

1

T4

3

T15

1

T49

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

81

1

T30

2

T33

1

T66

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

98

1

T17

2

T49

1

T33

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

114

1

T17

3

T48

2

T33

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

102

1

T49

1

T33

1

T67

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

67

1

T17

5

T30

1

T33

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

98

1

T30

1

T48

2

T90

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

87

1

T17

1

T48

3

T49

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3855	1			T5	36		T13	4		T59	8
auto[0]	values[0]	valids[0x1]	16461	1			T5	174		T7	4		T11	8
auto[0]	values[1]	valids[0x1]	570	1			T5	11		T57	2		T28	2
auto[0]	values[2]	valids[0x0]	555	1			T5	7		T39	4		T58	1
auto[0]	values[2]	valids[0x1]	296	1			T5	5		T40	2		T58	1
auto[0]	values[3]	valids[0x0]	533	1			T5	11		T58	1		T50	3
auto[0]	values[3]	valids[0x1]	306	1			T5	3		T50	4		T51	3
auto[0]	values[4]	valids[0x0]	528	1			T5	4		T7	2		T50	8
auto[0]	values[4]	valids[0x1]	260	1			T5	1		T16	2		T50	2
auto[0]	values[5]	valids[0x0]	519	1			T5	3		T28	2		T58	3
auto[0]	values[5]	valids[0x1]	287	1			T5	1		T50	3		T51	2
auto[0]	values[6]	valids[0x0]	464	1			T5	3		T61	1		T195	2
auto[0]	values[6]	valids[0x1]	279	1			T5	6		T50	4		T61	1
auto[0]	values[7]	valids[0x0]	534	1			T5	11		T40	2		T58	1
auto[0]	values[7]	valids[0x1]	286	1			T5	7		T50	2		T61	2
auto[0]	values[8]	valids[0x0]	3390	1			T5	59		T7	2		T57	2
auto[0]	values[8]	valids[0x1]	1996	1			T5	28		T57	2		T40	2
auto[1]	values[0]	valids[0x0]	3647	1			T4	18		T15	13		T17	51
auto[1]	values[0]	valids[0x1]	14396	1			T4	47		T15	34		T17	120
auto[1]	values[1]	valids[0x1]	506	1			T15	3		T17	2		T30	14
auto[1]	values[2]	valids[0x0]	323	1			T30	5		T48	3		T49	2
auto[1]	values[2]	valids[0x1]	264	1			T4	2		T30	5		T48	4
auto[1]	values[3]	valids[0x0]	350	1			T4	1		T17	2		T30	3
auto[1]	values[3]	valids[0x1]	247	1			T4	3		T48	1		T49	1
auto[1]	values[4]	valids[0x0]	372	1			T2	1		T15	4		T17	4
auto[1]	values[4]	valids[0x1]	235	1			T17	4		T30	2		T48	1
auto[1]	values[5]	valids[0x0]	392	1			T4	2		T15	2		T17	8
auto[1]	values[5]	valids[0x1]	249	1			T15	2		T30	6		T48	1
auto[1]	values[6]	valids[0x0]	392	1			T15	1		T17	5		T30	4
auto[1]	values[6]	valids[0x1]	274	1			T15	7		T17	2		T30	3
auto[1]	values[7]	valids[0x0]	369	1			T15	4		T17	9		T30	2
auto[1]	values[7]	valids[0x1]	230	1			T4	2		T30	6		T48	1
auto[1]	values[8]	valids[0x0]	2399	1			T4	8		T15	7		T17	20
auto[1]	values[8]	valids[0x1]	1662	1			T4	7		T15	5		T17	20