Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3194478

1

T1

1

T2

8277

T4

676

auto[1]

30113

1

T4

30

T5

110

T15

22

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

834861

1

T1

1

T2

8277

T4

25

auto[1]

2389730

1

T4

681

T5

22741

T7

1838

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	572608	1			T1	1		T2	1281		T4	5
auto[524288:1048575]	406949	1			T4	139		T5	267		T7	745
auto[1048576:1572863]	338266	1			T2	3		T4	4		T5	4138
auto[1572864:2097151]	362094	1			T5	11869		T7	105		T15	1
auto[2097152:2621439]	406375	1			T4	285		T5	641		T7	111
auto[2621440:3145727]	347558	1			T4	266		T5	1066		T7	454
auto[3145728:3670015]	375046	1			T2	6993		T4	6		T5	2156
auto[3670016:4194303]	415695	1			T4	1		T5	1509		T15	672

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2425125

1

T1

1

T2

7

T4

702

auto[1]

799466

1

T2

8270

T4

4

T5

1

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2763467

1

T1

1

T2

8277

T4

22

auto[1]

461124

1

T4

684

T5

3829

T17

2368

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	166602	1			T1	1		T2	1281		T4	5
auto[0]	auto[0]	auto[0:524287]	auto[1]	347395	1			T5	512		T7	936		T17	296
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	90913	1			T5	2		T7	348		T17	8
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	241367	1			T5	257		T7	397		T17	4068
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	70119	1			T2	3		T4	1		T5	8
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	210328	1			T4	1		T5	4081		T15	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	104268	1			T5	10		T7	105		T15	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	222375	1			T5	8940		T17	512		T30	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	87293	1			T5	1		T7	110		T30	7
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	236504	1			T5	640		T7	1		T17	128
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	101503	1			T4	4		T5	10		T7	451
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	206863	1			T4	1		T5	1030		T7	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	90257	1			T2	6993		T4	2		T5	4
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	217996	1			T4	1		T5	2152		T7	501
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	109860	1			T4	1		T5	4		T15	8
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	236036	1			T5	1221		T15	642		T17	1175
auto[0]	auto[1]	auto[0:524287]	auto[0]	2475	1			T5	3		T17	3		T48	12
auto[0]	auto[1]	auto[0:524287]	auto[1]	51855	1			T5	640		T17	729		T49	2994
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	667	1			T30	4		T49	51		T33	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	70256	1			T4	139		T30	1165		T49	700
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	926	1			T5	4		T17	4		T30	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	52121	1			T17	773		T30	258		T48	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1749	1			T5	3		T33	2		T67	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	29453	1			T5	2908		T33	1283		T67	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	668	1			T4	3		T17	1		T48	44
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	78546	1			T4	258		T48	3193		T49	665
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	693	1			T4	3		T17	7		T49	6
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	35008	1			T4	256		T17	517		T33	6
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2158	1			T4	1		T17	7		T30	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	60670	1			T17	300		T30	65		T33	2671
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	653	1			T5	3		T58	17		T50	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	66901	1			T5	258		T33	2835		T58	130
auto[1]	auto[0]	auto[0:524287]	auto[0]	479	1			T17	3		T48	3		T49	5
auto[1]	auto[0]	auto[0:524287]	auto[1]	3138	1			T17	17		T66	6		T41	55
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	361	1			T5	1		T49	24		T67	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1935	1			T5	7		T67	90		T65	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	450	1			T4	1		T5	1		T30	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3246	1			T4	1		T5	44		T30	6
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	403	1			T5	1		T30	1		T48	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2728	1			T5	7		T30	2		T33	5
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	411	1			T30	1		T49	34		T33	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2436	1			T30	1		T49	256		T33	8
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	381	1			T4	1		T5	2		T49	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2625	1			T4	1		T5	24		T33	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	461	1			T4	1		T30	4		T33	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2855	1			T4	1		T30	12		T33	9
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	333	1			T5	1		T15	2		T49	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1546	1			T5	12		T15	20		T49	32
auto[1]	auto[1]	auto[0:524287]	auto[0]	111	1			T17	2		T33	4		T58	3
auto[1]	auto[1]	auto[0:524287]	auto[1]	553	1			T17	11		T33	26		T245	6
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	84	1			T49	5		T33	2		T262	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1366	1			T33	17		T262	49		T260	18
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	95	1			T17	1		T30	2		T48	7
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	981	1			T30	3		T67	59		T90	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	115	1			T67	1		T246	1		T51	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1003	1			T67	9		T246	1		T51	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	122	1			T4	2		T48	5		T214	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	395	1			T4	22		T214	29		T224	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	87	1			T17	2		T33	2		T107	9
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	398	1			T17	7		T33	43		T260	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	100	1			T17	1		T33	1		T65	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	549	1			T17	3		T33	57		T65	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	64	1			T5	2		T50	1		T224	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	302	1			T5	8		T50	1		T224	5

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1945956	1			T1	1		T2	7		T4	14
auto[0]	auto[0]	auto[1]	793723	1			T2	8270		T4	2		T5	1
auto[0]	auto[1]	auto[0]	449658	1			T4	658		T5	3819		T17	2341
auto[0]	auto[1]	auto[1]	5141	1			T4	2		T33	4		T67	1
auto[1]	auto[0]	auto[0]	23281	1			T4	6		T5	100		T15	22
auto[1]	auto[0]	auto[1]	507	1			T48	2		T49	9		T67	1
auto[1]	auto[1]	auto[0]	6230	1			T4	24		T5	10		T17	27
auto[1]	auto[1]	auto[1]	95	1			T48	1		T49	1		T67	1