Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2230730	1			T1	1		T2	1		T3	664
all_pins[1]	2230730	1			T1	1		T2	1		T3	664
all_pins[2]	2230730	1			T1	1		T2	1		T3	664
all_pins[3]	2230730	1			T1	1		T2	1		T3	664
all_pins[4]	2230730	1			T1	1		T2	1		T3	664
all_pins[5]	2230730	1			T1	1		T2	1		T3	664
all_pins[6]	2230730	1			T1	1		T2	1		T3	664
all_pins[7]	2230730	1			T1	1		T2	1		T3	664

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	17838819	1			T1	8		T2	8		T3	5312
values[0x1]	7021	1			T18	23		T19	21		T20	25
transitions[0x0=>0x1]	6175	1			T18	16		T19	17		T20	14
transitions[0x1=>0x0]	6188	1			T18	17		T19	17		T20	14

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2230308	1			T1	1		T2	1		T3	664
all_pins[0]	values[0x1]	422	1			T18	3		T19	4		T20	5
all_pins[0]	transitions[0x0=>0x1]	362	1			T18	2		T19	3		T20	2
all_pins[0]	transitions[0x1=>0x0]	134	1			T18	2		T19	3		T20	2
all_pins[1]	values[0x0]	2230536	1			T1	1		T2	1		T3	664
all_pins[1]	values[0x1]	194	1			T18	3		T19	4		T20	5
all_pins[1]	transitions[0x0=>0x1]	147	1			T18	2		T19	2		T20	4
all_pins[1]	transitions[0x1=>0x0]	150	1			T18	2		T19	1		T20	2
all_pins[2]	values[0x0]	2230533	1			T1	1		T2	1		T3	664
all_pins[2]	values[0x1]	197	1			T18	3		T19	3		T20	3
all_pins[2]	transitions[0x0=>0x1]	154	1			T18	1		T19	3		T20	3
all_pins[2]	transitions[0x1=>0x0]	141	1			T18	1		T19	1		T21	1
all_pins[3]	values[0x0]	2230546	1			T1	1		T2	1		T3	664
all_pins[3]	values[0x1]	184	1			T18	3		T19	1		T21	3
all_pins[3]	transitions[0x0=>0x1]	140	1			T18	3		T19	1		T21	3
all_pins[3]	transitions[0x1=>0x0]	141	1			T18	2		T19	3		T20	3
all_pins[4]	values[0x0]	2230545	1			T1	1		T2	1		T3	664
all_pins[4]	values[0x1]	185	1			T18	2		T19	3		T20	3
all_pins[4]	transitions[0x0=>0x1]	156	1			T18	2		T19	3		T20	2
all_pins[4]	transitions[0x1=>0x0]	1300	1			T18	3		T19	3		T20	2
all_pins[5]	values[0x0]	2229401	1			T1	1		T2	1		T3	664
all_pins[5]	values[0x1]	1329	1			T18	3		T19	3		T20	3
all_pins[5]	transitions[0x0=>0x1]	826	1			T18	2		T19	2		T20	2
all_pins[5]	transitions[0x1=>0x0]	3803	1			T18	1		T19	2		T20	1
all_pins[6]	values[0x0]	2226424	1			T1	1		T2	1		T3	664
all_pins[6]	values[0x1]	4306	1			T18	2		T19	3		T20	2
all_pins[6]	transitions[0x0=>0x1]	4252	1			T18	2		T19	3		T21	2
all_pins[6]	transitions[0x1=>0x0]	150	1			T18	4		T20	2		T160	1
all_pins[7]	values[0x0]	2230526	1			T1	1		T2	1		T3	664
all_pins[7]	values[0x1]	204	1			T18	4		T20	4		T160	1
all_pins[7]	transitions[0x0=>0x1]	138	1			T18	2		T20	1		T160	1
all_pins[7]	transitions[0x1=>0x0]	369	1			T18	2		T19	4		T20	2