Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17871

1

T5

207

T7

8

T13

4

auto[1]

13248

1

T5

163

T11

8

T57

8

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3528	1			T5	28		T13	4		T56	6
values[1]	4279	1			T5	38		T7	8		T50	25
values[2]	3905	1			T5	105		T11	8		T100	20
values[3]	3704	1			T57	8		T28	18		T50	42
values[4]	3667	1			T5	60		T59	8		T41	69
values[5]	4016	1			T5	53		T16	12		T50	62
values[6]	3885	1			T130	6		T230	6		T62	8
values[7]	4135	1			T5	86		T58	40		T50	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4258	1			T56	6		T41	69		T58	40
values[1]	4487	1			T59	8		T130	6		T50	21
values[2]	3555	1			T5	48		T58	20		T61	40
values[3]	4252	1			T5	71		T11	8		T13	4
values[4]	3928	1			T5	92		T100	20		T39	10
values[5]	4089	1			T5	34		T28	18		T50	21
values[6]	3374	1			T5	40		T16	12		T50	20
values[7]	3176	1			T5	85		T7	8		T57	8

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	367	1			T56	6		T58	11		T51	6
auto[0]	values[0]	values[1]	228	1			T257	16		T221	11		T34	12
auto[0]	values[0]	values[2]	223	1			T5	11		T153	32		T194	14
auto[0]	values[0]	values[3]	253	1			T13	4		T61	11		T160	14
auto[0]	values[0]	values[4]	285	1			T39	10		T200	8		T199	14
auto[0]	values[0]	values[5]	274	1			T60	10		T199	13		T253	117
auto[0]	values[0]	values[6]	174	1			T64	14		T181	13		T199	20
auto[0]	values[0]	values[7]	193	1			T40	16		T50	8		T51	13
auto[0]	values[1]	values[0]	482	1			T74	11		T181	14		T219	114
auto[0]	values[1]	values[1]	219	1			T102	18		T194	17		T103	9
auto[0]	values[1]	values[2]	337	1			T61	12		T51	16		T221	16
auto[0]	values[1]	values[3]	397	1			T5	14		T261	10		T211	20
auto[0]	values[1]	values[4]	273	1			T50	21		T265	10		T253	11
auto[0]	values[1]	values[5]	267	1			T24	11		T212	9		T42	11
auto[0]	values[1]	values[6]	251	1			T266	16		T194	9		T239	9
auto[0]	values[1]	values[7]	139	1			T7	8		T74	12		T181	15
auto[0]	values[2]	values[0]	333	1			T267	14		T194	7		T103	11
auto[0]	values[2]	values[1]	297	1			T64	10		T268	4		T219	11
auto[0]	values[2]	values[2]	161	1			T5	16		T181	13		T103	13
auto[0]	values[2]	values[3]	350	1			T194	11		T269	4		T219	14
auto[0]	values[2]	values[4]	274	1			T5	9		T100	20		T50	9
auto[0]	values[2]	values[5]	259	1			T181	15		T194	12		T86	16
auto[0]	values[2]	values[6]	347	1			T259	10		T221	12		T263	44
auto[0]	values[2]	values[7]	265	1			T5	56		T88	14		T199	17
auto[0]	values[3]	values[0]	348	1			T74	13		T181	13		T236	15
auto[0]	values[3]	values[1]	420	1			T116	22		T86	11		T270	8
auto[0]	values[3]	values[2]	258	1			T51	8		T74	14		T236	11
auto[0]	values[3]	values[3]	216	1			T50	12		T271	6		T34	13
auto[0]	values[3]	values[4]	185	1			T86	9		T272	6		T273	7
auto[0]	values[3]	values[5]	214	1			T274	8		T153	15		T24	11
auto[0]	values[3]	values[6]	271	1			T275	12		T276	10		T219	8
auto[0]	values[3]	values[7]	319	1			T50	11		T51	20		T223	12
auto[0]	values[4]	values[0]	228	1			T41	69		T74	9		T277	12
auto[0]	values[4]	values[1]	328	1			T59	8		T194	11		T193	80
auto[0]	values[4]	values[2]	278	1			T278	12		T241	11		T42	57
auto[0]	values[4]	values[3]	293	1			T63	12		T185	6		T279	2
auto[0]	values[4]	values[4]	277	1			T5	23		T61	11		T60	8
auto[0]	values[4]	values[5]	165	1			T238	6		T153	37		T86	9
auto[0]	values[4]	values[6]	241	1			T231	14		T256	4		T203	4
auto[0]	values[4]	values[7]	173	1			T5	6		T160	13		T236	14
auto[0]	values[5]	values[0]	165	1			T153	10		T86	11		T199	11
auto[0]	values[5]	values[1]	309	1			T50	13		T24	118		T280	2
auto[0]	values[5]	values[2]	189	1			T61	9		T181	11		T236	10
auto[0]	values[5]	values[3]	332	1			T5	11		T50	11		T51	22
auto[0]	values[5]	values[4]	737	1			T229	18		T84	6		T199	12
auto[0]	values[5]	values[5]	242	1			T50	5		T60	13		T34	22
auto[0]	values[5]	values[6]	205	1			T5	13		T16	12		T51	23
auto[0]	values[5]	values[7]	216	1			T195	8		T194	12		T199	10
auto[0]	values[6]	values[0]	375	1			T152	10		T42	14		T281	4
auto[0]	values[6]	values[1]	552	1			T130	6		T51	11		T101	6
auto[0]	values[6]	values[2]	168	1			T221	12		T103	13		T282	9
auto[0]	values[6]	values[3]	371	1			T51	12		T283	6		T86	15
auto[0]	values[6]	values[4]	228	1			T253	26		T284	13		T285	77
auto[0]	values[6]	values[5]	272	1			T286	10		T60	7		T181	17
auto[0]	values[6]	values[6]	273	1			T230	6		T287	2		T74	10
auto[0]	values[6]	values[7]	162	1			T288	4		T181	31		T160	15
auto[0]	values[7]	values[0]	244	1			T58	12		T289	10		T86	10
auto[0]	values[7]	values[1]	328	1			T242	8		T219	13		T103	9
auto[0]	values[7]	values[2]	217	1			T58	14		T147	6		T241	12
auto[0]	values[7]	values[3]	309	1			T258	8		T34	16		T277	14
auto[0]	values[7]	values[4]	283	1			T5	13		T200	12		T204	12
auto[0]	values[7]	values[5]	252	1			T5	24		T74	14		T181	10
auto[0]	values[7]	values[6]	232	1			T5	11		T50	10		T181	12
auto[0]	values[7]	values[7]	348	1			T290	37		T64	17		T236	12
auto[1]	values[0]	values[0]	184	1			T58	9		T51	17		T263	10
auto[1]	values[0]	values[1]	159	1			T221	9		T34	8		T263	4
auto[1]	values[0]	values[2]	362	1			T5	17		T153	39		T194	58
auto[1]	values[0]	values[3]	181	1			T61	15		T160	6		T194	7
auto[1]	values[0]	values[4]	168	1			T200	12		T199	6		T277	6
auto[1]	values[0]	values[5]	217	1			T60	15		T199	7		T253	8
auto[1]	values[0]	values[6]	143	1			T64	6		T181	7		T199	20
auto[1]	values[0]	values[7]	117	1			T50	12		T51	13		T200	8
auto[1]	values[1]	values[0]	196	1			T74	9		T181	6		T219	10
auto[1]	values[1]	values[1]	170	1			T194	3		T103	11		T42	6
auto[1]	values[1]	values[2]	221	1			T61	8		T51	10		T221	4
auto[1]	values[1]	values[3]	217	1			T5	24		T181	12		T221	7
auto[1]	values[1]	values[4]	81	1			T50	4		T253	23		T291	7
auto[1]	values[1]	values[5]	808	1			T24	9		T212	11		T42	9
auto[1]	values[1]	values[6]	107	1			T194	38		T239	11		T253	9
auto[1]	values[1]	values[7]	114	1			T74	8		T181	5		T292	11
auto[1]	values[2]	values[0]	160	1			T194	25		T103	9		T252	6
auto[1]	values[2]	values[1]	292	1			T64	10		T219	9		T103	21
auto[1]	values[2]	values[2]	200	1			T5	4		T181	7		T103	7
auto[1]	values[2]	values[3]	226	1			T11	8		T194	9		T219	6
auto[1]	values[2]	values[4]	183	1			T5	11		T50	12		T293	12
auto[1]	values[2]	values[5]	183	1			T181	5		T194	8		T86	24
auto[1]	values[2]	values[6]	171	1			T221	8		T263	25		T208	28
auto[1]	values[2]	values[7]	204	1			T5	9		T199	3		T34	12
auto[1]	values[3]	values[0]	295	1			T74	7		T181	7		T236	7
auto[1]	values[3]	values[1]	192	1			T86	9		T294	14		T277	28
auto[1]	values[3]	values[2]	215	1			T51	12		T74	6		T236	10
auto[1]	values[3]	values[3]	118	1			T50	10		T34	7		T103	8
auto[1]	values[3]	values[4]	160	1			T86	11		T273	25		T295	5
auto[1]	values[3]	values[5]	104	1			T28	18		T153	5		T24	9
auto[1]	values[3]	values[6]	175	1			T219	12		T208	13		T253	13
auto[1]	values[3]	values[7]	214	1			T57	8		T50	9		T51	5
auto[1]	values[4]	values[0]	125	1			T74	11		T277	14		T208	9
auto[1]	values[4]	values[1]	271	1			T194	9		T209	8		T210	28
auto[1]	values[4]	values[2]	176	1			T241	9		T42	7		T296	8
auto[1]	values[4]	values[3]	260	1			T63	24		T194	4		T232	19
auto[1]	values[4]	values[4]	303	1			T5	17		T61	9		T60	12
auto[1]	values[4]	values[5]	205	1			T153	6		T86	11		T24	6
auto[1]	values[4]	values[6]	170	1			T294	8		T34	5		T250	8
auto[1]	values[4]	values[7]	174	1			T5	14		T160	11		T236	6
auto[1]	values[5]	values[0]	192	1			T153	10		T86	9		T199	9
auto[1]	values[5]	values[1]	186	1			T50	8		T24	8		T294	17
auto[1]	values[5]	values[2]	127	1			T61	11		T181	9		T236	13
auto[1]	values[5]	values[3]	146	1			T5	22		T50	9		T51	20
auto[1]	values[5]	values[4]	187	1			T199	8		T221	19		T210	3
auto[1]	values[5]	values[5]	302	1			T50	16		T60	27		T34	18
auto[1]	values[5]	values[6]	287	1			T5	7		T51	4		T199	11
auto[1]	values[5]	values[7]	194	1			T194	8		T199	10		T232	11
auto[1]	values[6]	values[0]	153	1			T42	6		T209	7		T297	13
auto[1]	values[6]	values[1]	366	1			T51	9		T64	5		T34	13
auto[1]	values[6]	values[2]	185	1			T221	8		T103	7		T282	11
auto[1]	values[6]	values[3]	252	1			T51	14		T86	5		T263	8
auto[1]	values[6]	values[4]	130	1			T253	10		T284	7		T285	5
auto[1]	values[6]	values[5]	150	1			T62	8		T60	18		T181	3
auto[1]	values[6]	values[6]	182	1			T74	10		T181	9		T219	9
auto[1]	values[6]	values[7]	66	1			T181	9		T160	10		T199	10
auto[1]	values[7]	values[0]	411	1			T58	8		T86	10		T24	7
auto[1]	values[7]	values[1]	170	1			T219	7		T103	11		T212	9
auto[1]	values[7]	values[2]	238	1			T58	6		T241	13		T220	10
auto[1]	values[7]	values[3]	331	1			T34	8		T277	6		T232	12
auto[1]	values[7]	values[4]	174	1			T5	19		T200	8		T253	8
auto[1]	values[7]	values[5]	175	1			T5	10		T74	6		T181	10
auto[1]	values[7]	values[6]	145	1			T5	9		T50	10		T181	8
auto[1]	values[7]	values[7]	278	1			T64	3		T236	8		T239	13