Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 66 0 66 100.00
Crosses 128 0 128 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_filtered 2 0 2 100.00 100 1 1 2
cp_opcode 64 0 64 100.00 100 1 1 64


Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 128 0 128 100.00 100 1 1 0


Summary for Variable cp_filtered

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_filtered

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 15659 1 T5 247 T7 4 T11 4
auto[1] 41767 1 T2 1 T4 90 T5 123



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 64 0 64 100.00


Automatically Generated Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:3] 1288 1 T5 6 T16 4 T30 2
auto[4:7] 23326 1 T4 34 T5 137 T7 2
auto[8:11] 1235 1 T5 10 T17 2 T30 7
auto[12:15] 266 1 T5 4 T15 2 T17 1
auto[16:19] 284 1 T5 1 T17 1 T48 1
auto[20:23] 1750 1 T5 11 T11 2 T15 3
auto[24:27] 357 1 T5 3 T30 2 T49 4
auto[28:31] 280 1 T5 1 T30 4 T49 2
auto[32:35] 297 1 T17 4 T30 2 T48 1
auto[36:39] 344 1 T4 4 T5 2 T15 1
auto[40:43] 336 1 T4 3 T17 3 T48 2
auto[44:47] 297 1 T4 1 T5 3 T15 1
auto[48:51] 345 1 T5 2 T17 1 T30 2
auto[52:55] 1852 1 T4 2 T5 11 T7 2
auto[56:59] 1270 1 T4 1 T5 14 T15 1
auto[60:63] 308 1 T4 2 T5 1 T17 5
auto[64:67] 292 1 T4 1 T5 3 T30 1
auto[68:71] 355 1 T5 3 T30 1 T48 2
auto[72:75] 318 1 T4 5 T30 2 T49 1
auto[76:79] 275 1 T5 2 T15 1 T17 2
auto[80:83] 334 1 T5 3 T15 5 T17 1
auto[84:87] 333 1 T4 1 T5 2 T17 5
auto[88:91] 1704 1 T4 3 T5 6 T15 3
auto[92:95] 281 1 T5 2 T48 1 T49 2
auto[96:99] 382 1 T4 1 T5 1 T15 2
auto[100:103] 319 1 T5 3 T30 3 T48 2
auto[104:107] 1313 1 T5 10 T7 2 T11 2
auto[108:111] 315 1 T5 5 T15 1 T17 2
auto[112:115] 278 1 T5 1 T15 1 T48 1
auto[116:119] 290 1 T5 5 T15 1 T49 2
auto[120:123] 322 1 T4 1 T5 1 T30 1
auto[124:127] 323 1 T4 1 T5 1 T15 1
auto[128:131] 342 1 T5 1 T15 5 T17 2
auto[132:135] 331 1 T4 2 T5 3 T17 2
auto[136:139] 283 1 T4 1 T49 1 T33 7
auto[140:143] 308 1 T5 5 T17 4 T30 2
auto[144:147] 303 1 T4 1 T5 1 T17 2
auto[148:151] 327 1 T4 2 T5 1 T15 1
auto[152:155] 328 1 T5 2 T30 7 T48 3
auto[156:159] 1764 1 T4 1 T5 12 T11 4
auto[160:163] 323 1 T4 1 T5 3 T15 1
auto[164:167] 310 1 T5 1 T15 1 T17 3
auto[168:171] 278 1 T49 1 T67 1 T90 3
auto[172:175] 281 1 T5 5 T15 3 T17 4
auto[176:179] 324 1 T5 5 T30 1 T48 5
auto[180:183] 1693 1 T4 8 T5 13 T15 4
auto[184:187] 1235 1 T5 12 T7 2 T15 1
auto[188:191] 299 1 T4 1 T5 3 T30 2
auto[192:195] 304 1 T5 4 T17 3 T30 1
auto[196:199] 326 1 T4 2 T5 1 T17 1
auto[200:203] 313 1 T5 3 T15 3 T17 4
auto[204:207] 306 1 T15 2 T17 1 T33 2
auto[208:211] 306 1 T5 3 T30 4 T48 1
auto[212:215] 333 1 T17 3 T49 4 T33 4
auto[216:219] 285 1 T5 2 T17 2 T30 1
auto[220:223] 267 1 T4 3 T5 1 T48 1
auto[224:227] 350 1 T5 1 T17 3 T30 5
auto[228:231] 325 1 T5 1 T30 5 T49 7
auto[232:235] 2712 1 T2 1 T4 4 T5 17
auto[236:239] 350 1 T4 2 T5 4 T48 5
auto[240:243] 339 1 T5 1 T15 1 T17 1
auto[244:247] 306 1 T5 5 T17 5 T30 1
auto[248:251] 311 1 T5 5 T17 7 T30 4
auto[252:255] 295 1 T4 2 T5 1 T30 4



Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_opcodecp_filteredCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:3] auto[0] 483 1 T5 3 T16 2 T40 2
auto[0:3] auto[1] 805 1 T5 3 T16 2 T30 2
auto[4:7] auto[0] 6287 1 T5 125 T7 1 T59 2
auto[4:7] auto[1] 17039 1 T4 34 T5 12 T7 1
auto[8:11] auto[0] 407 1 T5 5 T57 1 T50 4
auto[8:11] auto[1] 828 1 T5 5 T17 2 T30 7
auto[12:15] auto[0] 61 1 T5 2 T50 1 T51 1
auto[12:15] auto[1] 205 1 T5 2 T15 2 T17 1
auto[16:19] auto[0] 84 1 T50 2 T290 1 T181 2
auto[16:19] auto[1] 200 1 T5 1 T17 1 T48 1
auto[20:23] auto[0] 461 1 T5 3 T11 1 T16 1
auto[20:23] auto[1] 1289 1 T5 8 T11 1 T15 3
auto[24:27] auto[0] 85 1 T61 2 T74 1 T181 4
auto[24:27] auto[1] 272 1 T5 3 T30 2 T49 4
auto[28:31] auto[0] 59 1 T61 1 T51 1 T60 1
auto[28:31] auto[1] 221 1 T5 1 T30 4 T49 2
auto[32:35] auto[0] 79 1 T61 1 T51 1 T60 1
auto[32:35] auto[1] 218 1 T17 4 T30 2 T48 1
auto[36:39] auto[0] 91 1 T40 1 T61 1 T51 2
auto[36:39] auto[1] 253 1 T4 4 T5 2 T15 1
auto[40:43] auto[0] 77 1 T58 2 T236 2 T194 1
auto[40:43] auto[1] 259 1 T4 3 T17 3 T48 2
auto[44:47] auto[0] 80 1 T5 1 T50 1 T275 1
auto[44:47] auto[1] 217 1 T4 1 T5 2 T15 1
auto[48:51] auto[0] 96 1 T211 1 T223 1 T63 1
auto[48:51] auto[1] 249 1 T5 2 T17 1 T30 2
auto[52:55] auto[0] 458 1 T5 5 T7 1 T16 2
auto[52:55] auto[1] 1394 1 T4 2 T5 6 T7 1
auto[56:59] auto[0] 443 1 T5 6 T28 2 T39 2
auto[56:59] auto[1] 827 1 T4 1 T5 8 T15 1
auto[60:63] auto[0] 75 1 T50 2 T51 1 T60 1
auto[60:63] auto[1] 233 1 T4 2 T5 1 T17 5
auto[64:67] auto[0] 74 1 T51 1 T231 2 T229 1
auto[64:67] auto[1] 218 1 T4 1 T5 3 T30 1
auto[68:71] auto[0] 97 1 T5 2 T28 1 T261 1
auto[68:71] auto[1] 258 1 T5 1 T30 1 T48 2
auto[72:75] auto[0] 83 1 T61 1 T74 4 T194 1
auto[72:75] auto[1] 235 1 T4 5 T30 2 T49 1
auto[76:79] auto[0] 59 1 T50 2 T60 3 T181 1
auto[76:79] auto[1] 216 1 T5 2 T15 1 T17 2
auto[80:83] auto[0] 88 1 T5 2 T50 1 T51 1
auto[80:83] auto[1] 246 1 T5 1 T15 5 T17 1
auto[84:87] auto[0] 85 1 T5 2 T229 1 T181 2
auto[84:87] auto[1] 248 1 T4 1 T17 5 T48 1
auto[88:91] auto[0] 422 1 T5 2 T16 1 T50 2
auto[88:91] auto[1] 1282 1 T4 3 T5 4 T15 3
auto[92:95] auto[0] 53 1 T5 1 T74 4 T181 1
auto[92:95] auto[1] 228 1 T5 1 T48 1 T49 2
auto[96:99] auto[0] 103 1 T50 2 T211 1 T290 4
auto[96:99] auto[1] 279 1 T4 1 T5 1 T15 2
auto[100:103] auto[0] 69 1 T5 3 T51 1 T60 1
auto[100:103] auto[1] 250 1 T30 3 T48 2 T49 2
auto[104:107] auto[0] 477 1 T5 6 T7 1 T11 1
auto[104:107] auto[1] 836 1 T5 4 T7 1 T11 1
auto[108:111] auto[0] 75 1 T5 5 T50 2 T181 1
auto[108:111] auto[1] 240 1 T15 1 T17 2 T48 2
auto[112:115] auto[0] 83 1 T5 1 T50 2 T275 1
auto[112:115] auto[1] 195 1 T15 1 T48 1 T49 1
auto[116:119] auto[0] 63 1 T5 4 T200 1 T194 2
auto[116:119] auto[1] 227 1 T5 1 T15 1 T49 2
auto[120:123] auto[0] 69 1 T5 1 T61 1 T236 1
auto[120:123] auto[1] 253 1 T4 1 T30 1 T49 3
auto[124:127] auto[0] 70 1 T5 1 T51 1 T181 2
auto[124:127] auto[1] 253 1 T4 1 T15 1 T30 2
auto[128:131] auto[0] 68 1 T5 1 T74 1 T153 4
auto[128:131] auto[1] 274 1 T15 5 T17 2 T48 6
auto[132:135] auto[0] 84 1 T5 1 T63 1 T181 4
auto[132:135] auto[1] 247 1 T4 2 T5 2 T17 2
auto[136:139] auto[0] 70 1 T50 2 T51 2 T74 2
auto[136:139] auto[1] 213 1 T4 1 T49 1 T33 7
auto[140:143] auto[0] 83 1 T5 4 T275 1 T51 1
auto[140:143] auto[1] 225 1 T5 1 T17 4 T30 2
auto[144:147] auto[0] 82 1 T5 1 T51 1 T60 2
auto[144:147] auto[1] 221 1 T4 1 T17 2 T30 4
auto[148:151] auto[0] 91 1 T57 1 T50 1 T116 2
auto[148:151] auto[1] 236 1 T4 2 T5 1 T15 1
auto[152:155] auto[0] 79 1 T5 1 T275 1 T51 1
auto[152:155] auto[1] 249 1 T5 1 T30 7 T48 3
auto[156:159] auto[0] 480 1 T5 7 T11 2 T39 1
auto[156:159] auto[1] 1284 1 T4 1 T5 5 T11 2
auto[160:163] auto[0] 67 1 T5 2 T50 1 T116 1
auto[160:163] auto[1] 256 1 T4 1 T5 1 T15 1
auto[164:167] auto[0] 78 1 T50 6 T61 3 T51 3
auto[164:167] auto[1] 232 1 T5 1 T15 1 T17 3
auto[168:171] auto[0] 73 1 T50 2 T51 6 T74 1
auto[168:171] auto[1] 205 1 T49 1 T67 1 T90 3
auto[172:175] auto[0] 71 1 T5 5 T50 3 T61 2
auto[172:175] auto[1] 210 1 T15 3 T17 4 T30 1
auto[176:179] auto[0] 97 1 T5 3 T51 2 T223 1
auto[176:179] auto[1] 227 1 T5 2 T30 1 T48 5
auto[180:183] auto[0] 453 1 T5 8 T59 2 T100 5
auto[180:183] auto[1] 1240 1 T4 8 T5 5 T15 4
auto[184:187] auto[0] 432 1 T5 5 T7 1 T28 1
auto[184:187] auto[1] 803 1 T5 7 T7 1 T15 1
auto[188:191] auto[0] 64 1 T5 3 T50 1 T116 2
auto[188:191] auto[1] 235 1 T4 1 T30 2 T48 2
auto[192:195] auto[0] 87 1 T40 1 T60 2 T64 1
auto[192:195] auto[1] 217 1 T5 4 T17 3 T30 1
auto[196:199] auto[0] 90 1 T5 1 T74 2 T181 3
auto[196:199] auto[1] 236 1 T4 2 T17 1 T30 3
auto[200:203] auto[0] 70 1 T5 2 T50 1 T51 1
auto[200:203] auto[1] 243 1 T5 1 T15 3 T17 4
auto[204:207] auto[0] 68 1 T58 1 T61 1 T51 1
auto[204:207] auto[1] 238 1 T15 2 T17 1 T33 2
auto[208:211] auto[0] 92 1 T261 1 T64 1 T200 2
auto[208:211] auto[1] 214 1 T5 3 T30 4 T48 1
auto[212:215] auto[0] 82 1 T57 1 T51 2 T258 1
auto[212:215] auto[1] 251 1 T17 3 T49 4 T33 4
auto[216:219] auto[0] 75 1 T5 1 T50 2 T61 2
auto[216:219] auto[1] 210 1 T5 1 T17 2 T30 1
auto[220:223] auto[0] 63 1 T5 1 T58 1 T50 2
auto[220:223] auto[1] 204 1 T4 3 T48 1 T49 3
auto[224:227] auto[0] 88 1 T5 1 T64 1 T147 1
auto[224:227] auto[1] 262 1 T17 3 T30 5 T67 2
auto[228:231] auto[0] 78 1 T5 1 T56 2 T58 1
auto[228:231] auto[1] 247 1 T30 5 T49 7 T33 5
auto[232:235] auto[0] 811 1 T5 11 T13 2 T100 3
auto[232:235] auto[1] 1901 1 T2 1 T4 4 T5 6
auto[236:239] auto[0] 91 1 T5 2 T56 1 T41 2
auto[236:239] auto[1] 259 1 T4 2 T5 2 T48 5
auto[240:243] auto[0] 74 1 T5 1 T275 1 T51 3
auto[240:243] auto[1] 265 1 T15 1 T17 1 T30 4
auto[244:247] auto[0] 65 1 T5 1 T58 1 T275 1
auto[244:247] auto[1] 241 1 T5 4 T17 5 T30 1
auto[248:251] auto[0] 69 1 T5 3 T50 3 T51 1
auto[248:251] auto[1] 242 1 T5 2 T17 7 T30 4
auto[252:255] auto[0] 88 1 T5 1 T40 1 T51 3
auto[252:255] auto[1] 207 1 T4 2 T30 4 T49 1

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