Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	390	1			T5	11		T58	5		T50	3
auto[ReadAddrCrossIntoMailbox]	294	1			T5	5		T58	1		T50	7
auto[ReadAddrCrossOutOfMailbox]	282	1			T5	3		T50	3		T61	2
auto[ReadAddrCrossAllMailbox]	197	1			T5	5		T50	4		T61	2
auto[ReadAddrOutsideMailbox]	3503	1			T5	33		T7	4		T16	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2279

1

T5

32

T7

2

T16

2

auto[1]

2387

1

T5

25

T7

2

T16

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	814	1			T5	6		T16	4		T40	4
read_ops[0x0b]	714	1			T5	10		T57	2		T58	1
read_ops[0x3b]	802	1			T5	10		T28	2		T39	4
read_ops[0x6b]	802	1			T5	10		T7	2		T58	1
read_ops[0xbb]	773	1			T5	10		T7	2		T28	2
read_ops[0xeb]	761	1			T5	11		T28	6		T39	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T5	1		T195	2		T238	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T195	2		T60	1		T238	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T61	1		T160	1		T86	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T50	1		T200	1		T194	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T61	1		T160	1		T24	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T86	1		T219	2		T212	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T5	1		T50	1		T153	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T194	1		T199	1		T294	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	317	1			T5	1		T16	2		T40	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	313	1			T5	3		T16	2		T40	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T5	1		T64	1		T160	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T5	2		T58	1		T185	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T50	1		T61	1		T160	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T50	1		T200	1		T194	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T181	1		T86	1		T221	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T50	1		T194	1		T199	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T5	2		T34	1		T252	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T60	1		T236	1		T200	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	242	1			T5	2		T57	1		T50	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	277	1			T5	3		T57	1		T116	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T5	3		T61	2		T286	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T58	1		T286	1		T181	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T50	1		T81	1		T294	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T5	1		T61	2		T194	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T61	1		T51	1		T160	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T5	1		T50	1		T181	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T61	1		T51	1		T181	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T5	1		T181	1		T160	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T5	2		T28	1		T39	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T5	2		T28	1		T39	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T58	1		T50	1		T288	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T5	3		T50	1		T288	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T5	1		T51	1		T181	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T74	1		T181	1		T160	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T51	2		T278	1		T74	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T278	1		T64	1		T200	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T278	2		T86	1		T199	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T278	2		T181	2		T194	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	311	1			T5	5		T7	1		T50	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	304	1			T5	1		T7	1		T50	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T50	1		T195	1		T283	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T5	1		T195	1		T283	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T50	1		T86	1		T103	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	39	1			T5	1		T58	1		T51	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	14	1			T160	1		T194	1		T199	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T51	1		T194	1		T199	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T5	1		T50	2		T61	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T24	1		T34	1		T103	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	295	1			T5	3		T7	1		T28	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	285	1			T5	4		T7	1		T28	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T58	1		T195	1		T286	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T58	1		T195	1		T286	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T5	2		T50	2		T24	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T51	1		T74	1		T194	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T5	1		T50	1		T278	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T5	1		T278	2		T181	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T50	1		T278	1		T34	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T278	1		T86	1		T221	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	284	1			T5	6		T28	3		T39	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	279	1			T5	1		T28	3		T39	1