Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3905	1			T7	8		T274	8		T62	8
values[1]	3685	1			T5	20		T16	12		T58	20
values[2]	3289	1			T5	86		T57	8		T50	66
values[3]	4384	1			T5	20		T56	6		T40	16
values[4]	4032	1			T5	52		T100	20		T130	6
values[5]	3997	1			T5	65		T11	8		T39	10
values[6]	3730	1			T5	53		T13	4		T59	8
values[7]	4097	1			T5	74		T28	18		T58	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3567	1			T5	20		T59	8		T58	20
values[1]	3469	1			T5	34		T57	8		T51	70
values[2]	3646	1			T5	20		T13	4		T39	10
values[3]	3787	1			T5	38		T58	20		T50	41
values[4]	3977	1			T5	40		T11	8		T58	20
values[5]	4136	1			T5	80		T130	6		T56	6
values[6]	4878	1			T5	118		T7	8		T100	20
values[7]	3659	1			T5	20		T16	12		T50	42

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30338

1

T5

361

T7

8

T11

6

auto[1]

781

1

T5

9

T11

2

T58

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	519	1			T219	17		T253	34		T284	20
auto[0]	values[0]	values[1]	274	1			T181	19		T253	20		T282	22
auto[0]	values[0]	values[2]	395	1			T102	18		T268	4		T86	20
auto[0]	values[0]	values[3]	413	1			T194	20		T220	45		T218	37
auto[0]	values[0]	values[4]	634	1			T62	4		T287	2		T181	20
auto[0]	values[0]	values[5]	605	1			T261	10		T51	25		T289	10
auto[0]	values[0]	values[6]	729	1			T7	8		T60	24		T236	20
auto[0]	values[0]	values[7]	230	1			T274	8		T227	20		T24	20
auto[0]	values[1]	values[0]	364	1			T181	19		T219	19		T241	15
auto[0]	values[1]	values[1]	466	1			T298	6		T263	50		T42	21
auto[0]	values[1]	values[2]	410	1			T194	48		T24	70		T219	85
auto[0]	values[1]	values[3]	577	1			T58	19		T51	20		T194	19
auto[0]	values[1]	values[4]	322	1			T74	20		T103	20		T253	20
auto[0]	values[1]	values[5]	511	1			T50	20		T221	20		T299	4
auto[0]	values[1]	values[6]	467	1			T50	20		T256	4		T300	10
auto[0]	values[1]	values[7]	481	1			T5	20		T16	12		T101	6
auto[0]	values[2]	values[0]	308	1			T5	19		T50	20		T51	26
auto[0]	values[2]	values[1]	202	1			T57	8		T51	23		T194	20
auto[0]	values[2]	values[2]	338	1			T275	12		T74	20		T199	16
auto[0]	values[2]	values[3]	574	1			T5	38		T50	21		T266	16
auto[0]	values[2]	values[4]	499	1			T50	24		T61	24		T301	16
auto[0]	values[2]	values[5]	465	1			T5	25		T61	19		T231	14
auto[0]	values[2]	values[6]	394	1			T286	10		T64	17		T259	10
auto[0]	values[2]	values[7]	405	1			T51	26		T63	35		T181	20
auto[0]	values[3]	values[0]	499	1			T60	38		T302	14		T222	20
auto[0]	values[3]	values[1]	671	1			T51	23		T288	4		T153	20
auto[0]	values[3]	values[2]	589	1			T40	16		T195	8		T303	2
auto[0]	values[3]	values[3]	288	1			T50	20		T34	42		T103	19
auto[0]	values[3]	values[4]	663	1			T5	19		T152	10		T304	20
auto[0]	values[3]	values[5]	541	1			T56	6		T86	37		T199	19
auto[0]	values[3]	values[6]	589	1			T41	69		T221	20		T208	72
auto[0]	values[3]	values[7]	447	1			T50	20		T74	19		T216	42
auto[0]	values[4]	values[0]	379	1			T236	22		T199	18		T103	18
auto[0]	values[4]	values[1]	430	1			T181	40		T153	20		T81	14
auto[0]	values[4]	values[2]	611	1			T61	20		T223	12		T238	6
auto[0]	values[4]	values[3]	434	1			T200	18		T24	19		T103	20
auto[0]	values[4]	values[4]	500	1			T58	19		T116	22		T61	20
auto[0]	values[4]	values[5]	336	1			T5	32		T130	6		T211	20
auto[0]	values[4]	values[6]	600	1			T5	20		T100	20		T74	19
auto[0]	values[4]	values[7]	647	1			T229	18		T221	20		T253	125
auto[0]	values[5]	values[0]	448	1			T51	19		T236	20		T267	14
auto[0]	values[5]	values[1]	496	1			T258	8		T283	6		T84	6
auto[0]	values[5]	values[2]	415	1			T39	10		T64	20		T181	20
auto[0]	values[5]	values[3]	602	1			T51	26		T278	12		T86	18
auto[0]	values[5]	values[4]	268	1			T11	6		T230	6		T160	20
auto[0]	values[5]	values[5]	668	1			T181	18		T34	20		T277	35
auto[0]	values[5]	values[6]	595	1			T5	64		T153	38		T200	20
auto[0]	values[5]	values[7]	407	1			T193	80		T294	22		T263	20
auto[0]	values[6]	values[0]	466	1			T59	8		T181	38		T305	12
auto[0]	values[6]	values[1]	449	1			T185	6		T236	20		T194	44
auto[0]	values[6]	values[2]	430	1			T13	4		T74	20		T242	8
auto[0]	values[6]	values[3]	391	1			T181	20		T203	4		T241	19
auto[0]	values[6]	values[4]	413	1			T50	21		T153	43		T200	20
auto[0]	values[6]	values[5]	443	1			T5	20		T215	6		T64	19
auto[0]	values[6]	values[6]	743	1			T5	33		T153	28		T239	19
auto[0]	values[6]	values[7]	290	1			T74	20		T279	2		T243	8
auto[0]	values[7]	values[0]	464	1			T58	19		T199	20		T239	20
auto[0]	values[7]	values[1]	390	1			T5	34		T51	21		T74	20
auto[0]	values[7]	values[2]	360	1			T5	18		T60	24		T64	18
auto[0]	values[7]	values[3]	414	1			T199	19		T306	12		T307	20
auto[0]	values[7]	values[4]	589	1			T5	19		T51	20		T60	20
auto[0]	values[7]	values[5]	468	1			T28	18		T181	20		T88	14
auto[0]	values[7]	values[6]	659	1			T236	21		T221	20		T103	18
auto[0]	values[7]	values[7]	664	1			T50	21		T181	17		T293	8
auto[1]	values[0]	values[0]	11	1			T219	3		T253	2		T282	3
auto[1]	values[0]	values[1]	8	1			T181	1		T44	2		T308	2
auto[1]	values[0]	values[2]	13	1			T218	1		T209	3		T297	2
auto[1]	values[0]	values[3]	13	1			T309	1		T70	2		T234	2
auto[1]	values[0]	values[4]	12	1			T62	4		T253	2		T273	2
auto[1]	values[0]	values[5]	17	1			T51	1		T34	1		T212	1
auto[1]	values[0]	values[6]	18	1			T60	1		T194	2		T310	6
auto[1]	values[0]	values[7]	14	1			T103	1		T71	1		T311	4
auto[1]	values[1]	values[0]	15	1			T181	1		T219	1		T241	5
auto[1]	values[1]	values[1]	16	1			T263	1		T292	2		T312	2
auto[1]	values[1]	values[2]	6	1			T194	1		T291	1		T71	1
auto[1]	values[1]	values[3]	19	1			T58	1		T194	1		T24	1
auto[1]	values[1]	values[4]	6	1			T216	1		T295	2		T291	1
auto[1]	values[1]	values[5]	10	1			T209	5		T233	1		T313	2
auto[1]	values[1]	values[6]	9	1			T50	1		T34	1		T314	2
auto[1]	values[1]	values[7]	6	1			T235	4		T315	2		-	-
auto[1]	values[2]	values[0]	12	1			T5	1		T51	1		T199	1
auto[1]	values[2]	values[1]	6	1			T234	2		T316	4		-	-
auto[1]	values[2]	values[2]	11	1			T199	4		T273	2		T209	1
auto[1]	values[2]	values[3]	11	1			T86	1		T282	1		T317	2
auto[1]	values[2]	values[4]	16	1			T50	1		T61	2		T209	2
auto[1]	values[2]	values[5]	17	1			T5	3		T61	1		T160	1
auto[1]	values[2]	values[6]	12	1			T64	3		T86	1		T24	3
auto[1]	values[2]	values[7]	19	1			T63	1		T248	1		T210	1
auto[1]	values[3]	values[0]	16	1			T60	2		T24	2		T235	2
auto[1]	values[3]	values[1]	23	1			T51	2		T221	2		T220	1
auto[1]	values[3]	values[2]	10	1			T181	1		T252	2		T318	1
auto[1]	values[3]	values[3]	3	1			T34	2		T103	1		-	-
auto[1]	values[3]	values[4]	9	1			T5	1		T263	3		T296	1
auto[1]	values[3]	values[5]	14	1			T86	3		T199	1		T273	1
auto[1]	values[3]	values[6]	6	1			T92	1		T319	1		T320	3
auto[1]	values[3]	values[7]	16	1			T74	1		T216	1		T235	3
auto[1]	values[4]	values[0]	14	1			T236	1		T199	2		T103	2
auto[1]	values[4]	values[1]	4	1			T105	1		T234	1		T321	2
auto[1]	values[4]	values[2]	26	1			T74	1		T221	4		T322	2
auto[1]	values[4]	values[3]	16	1			T200	2		T24	1		T42	2
auto[1]	values[4]	values[4]	8	1			T58	1		T212	1		T323	4
auto[1]	values[4]	values[5]	9	1			T285	3		T324	2		T318	1
auto[1]	values[4]	values[6]	7	1			T74	1		T34	1		T68	1
auto[1]	values[4]	values[7]	11	1			T325	1		T319	2		T296	1
auto[1]	values[5]	values[0]	8	1			T51	1		T233	4		T311	1
auto[1]	values[5]	values[1]	12	1			T241	2		T216	3		T209	2
auto[1]	values[5]	values[2]	13	1			T239	2		T241	2		T212	1
auto[1]	values[5]	values[3]	19	1			T86	2		T277	2		T232	1
auto[1]	values[5]	values[4]	8	1			T11	2		T318	3		T326	1
auto[1]	values[5]	values[5]	18	1			T181	2		T277	4		T68	1
auto[1]	values[5]	values[6]	16	1			T5	1		T153	5		T199	1
auto[1]	values[5]	values[7]	4	1			T42	3		T295	1		-	-
auto[1]	values[6]	values[0]	37	1			T181	2		T103	3		T216	3
auto[1]	values[6]	values[1]	16	1			T236	1		T194	3		T199	1
auto[1]	values[6]	values[2]	6	1			T208	2		T220	2		T70	1
auto[1]	values[6]	values[3]	5	1			T241	1		T327	2		T320	1
auto[1]	values[6]	values[4]	8	1			T86	4		T176	3		T328	1
auto[1]	values[6]	values[5]	6	1			T64	1		T194	2		T253	1
auto[1]	values[6]	values[6]	25	1			T239	1		T219	5		T42	3
auto[1]	values[6]	values[7]	2	1			T252	1		T225	1		-	-
auto[1]	values[7]	values[0]	7	1			T58	1		T221	1		T220	1
auto[1]	values[7]	values[1]	6	1			T51	1		T70	2		T157	1
auto[1]	values[7]	values[2]	13	1			T5	2		T60	1		T64	2
auto[1]	values[7]	values[3]	8	1			T199	1		T248	1		T295	1
auto[1]	values[7]	values[4]	22	1			T5	1		T221	4		T294	2
auto[1]	values[7]	values[5]	8	1			T248	3		T235	2		T316	1
auto[1]	values[7]	values[6]	9	1			T236	2		T103	2		T329	2
auto[1]	values[7]	values[7]	16	1			T50	1		T181	3		T293	4