Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	790	1			T18	10		T19	14		T20	10
all_values[1]	790	1			T18	10		T19	14		T20	10
all_values[2]	790	1			T18	10		T19	14		T20	10
all_values[3]	790	1			T18	10		T19	14		T20	10
all_values[4]	790	1			T18	10		T19	14		T20	10
all_values[5]	790	1			T18	10		T19	14		T20	10
all_values[6]	790	1			T18	10		T19	14		T20	10
all_values[7]	790	1			T18	10		T19	14		T20	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3385

1

T18

34

T19

66

T20

43

auto[1]

2935

1

T18

46

T19

46

T20

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2441

1

T18

27

T19

36

T20

20

auto[1]

3879

1

T18

53

T19

76

T20

60

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3564

1

T18

39

T19

59

T20

41

auto[1]

2756

1

T18

41

T19

53

T20

39

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	123	1			T20	1		T34	1		T35	5
all_values[0]	auto[0]	auto[0]	auto[1]	86	1			T18	2		T19	3		T20	1
all_values[0]	auto[0]	auto[1]	auto[0]	129	1			T19	2		T160	1		T35	6
all_values[0]	auto[0]	auto[1]	auto[1]	84	1			T18	2		T20	2		T160	2
all_values[0]	auto[1]	auto[0]	auto[1]	192	1			T18	4		T19	5		T20	1
all_values[0]	auto[1]	auto[1]	auto[1]	176	1			T18	2		T19	4		T20	5
all_values[1]	auto[0]	auto[0]	auto[0]	158	1			T18	4		T19	1		T20	1
all_values[1]	auto[0]	auto[0]	auto[1]	98	1			T19	1		T20	2		T21	1
all_values[1]	auto[0]	auto[1]	auto[0]	111	1			T18	1		T19	2		T34	3
all_values[1]	auto[0]	auto[1]	auto[1]	80	1			T19	3		T20	2		T21	1
all_values[1]	auto[1]	auto[0]	auto[1]	175	1			T18	1		T19	4		T20	2
all_values[1]	auto[1]	auto[1]	auto[1]	168	1			T18	4		T19	3		T20	3
all_values[2]	auto[0]	auto[0]	auto[0]	172	1			T19	1		T20	1		T160	1
all_values[2]	auto[0]	auto[0]	auto[1]	75	1			T18	2		T19	2		T20	1
all_values[2]	auto[0]	auto[1]	auto[0]	144	1			T18	3		T19	1		T20	1
all_values[2]	auto[0]	auto[1]	auto[1]	75	1			T18	1		T19	3		T20	1
all_values[2]	auto[1]	auto[0]	auto[1]	182	1			T18	1		T19	5		T20	5
all_values[2]	auto[1]	auto[1]	auto[1]	142	1			T18	3		T19	2		T20	1
all_values[3]	auto[0]	auto[0]	auto[0]	143	1			T18	1		T19	2		T20	2
all_values[3]	auto[0]	auto[0]	auto[1]	92	1			T18	1		T19	2		T20	3
all_values[3]	auto[0]	auto[1]	auto[0]	150	1			T18	2		T19	2		T160	3
all_values[3]	auto[0]	auto[1]	auto[1]	66	1			T18	2		T19	1		T21	1
all_values[3]	auto[1]	auto[0]	auto[1]	191	1			T18	3		T19	5		T20	5
all_values[3]	auto[1]	auto[1]	auto[1]	148	1			T18	1		T19	2		T21	2
all_values[4]	auto[0]	auto[0]	auto[0]	138	1			T18	1		T19	1		T20	1
all_values[4]	auto[0]	auto[0]	auto[1]	72	1			T18	1		T19	3		T20	1
all_values[4]	auto[0]	auto[1]	auto[0]	151	1			T18	4		T19	2		T20	2
all_values[4]	auto[0]	auto[1]	auto[1]	86	1			T18	1		T19	2		T20	1
all_values[4]	auto[1]	auto[0]	auto[1]	185	1			T18	1		T19	3		T20	4
all_values[4]	auto[1]	auto[1]	auto[1]	158	1			T18	2		T19	3		T20	1
all_values[5]	auto[0]	auto[0]	auto[0]	241	1			T18	1		T19	5		T20	2
all_values[5]	auto[0]	auto[1]	auto[0]	201	1			T18	2		T19	3		T20	5
all_values[5]	auto[1]	auto[0]	auto[1]	195	1			T18	4		T19	2		T160	3
all_values[5]	auto[1]	auto[1]	auto[1]	153	1			T18	3		T19	4		T20	3
all_values[6]	auto[0]	auto[0]	auto[0]	185	1			T18	1		T19	7		T20	1
all_values[6]	auto[0]	auto[0]	auto[1]	73	1			T19	1		T20	1		T21	2
all_values[6]	auto[0]	auto[1]	auto[0]	119	1			T18	5		T20	2		T160	3
all_values[6]	auto[0]	auto[1]	auto[1]	65	1			T19	1		T20	2		T21	1
all_values[6]	auto[1]	auto[0]	auto[1]	188	1			T18	2		T19	4		T20	4
all_values[6]	auto[1]	auto[1]	auto[1]	160	1			T18	2		T19	1		T21	1
all_values[7]	auto[0]	auto[0]	auto[0]	155	1			T19	5		T160	1		T192	2
all_values[7]	auto[0]	auto[0]	auto[1]	88	1			T19	1		T20	2		T21	2
all_values[7]	auto[0]	auto[1]	auto[0]	121	1			T18	2		T19	2		T20	1
all_values[7]	auto[0]	auto[1]	auto[1]	83	1			T20	2		T21	1		T192	1
all_values[7]	auto[1]	auto[0]	auto[1]	178	1			T18	4		T19	3		T20	2
all_values[7]	auto[1]	auto[1]	auto[1]	165	1			T18	4		T19	3		T20	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal