Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1845

1

T5

7

T6

2

T12

1

auto[1]

1812

1

T5

5

T15

4

T29

12

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1974

1

T5

8

T6

2

T15

7

auto[1]

1683

1

T5

4

T12

1

T15

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2903

1

T5

7

T6

2

T12

1

auto[1]

754

1

T5

5

T15

4

T29

9

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	749	1			T5	3		T12	1		T15	3
valid[1]	719	1			T5	3		T6	1		T15	1
valid[2]	727	1			T5	1		T6	1		T15	3
valid[3]	707	1			T5	3		T29	3		T17	2
valid[4]	755	1			T5	2		T15	1		T29	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	121	1			T5	1		T15	1		T29	2
auto[0]	auto[0]	valid[0]	auto[1]	172	1			T12	1		T31	2		T32	1
auto[0]	auto[0]	valid[1]	auto[0]	130	1			T6	1		T29	3		T17	1
auto[0]	auto[0]	valid[1]	auto[1]	168	1			T15	1		T99	6		T353	1
auto[0]	auto[0]	valid[2]	auto[0]	117	1			T6	1		T15	1		T29	3
auto[0]	auto[0]	valid[2]	auto[1]	160	1			T5	1		T31	1		T99	2
auto[0]	auto[0]	valid[3]	auto[0]	128	1			T29	1		T65	1		T90	1
auto[0]	auto[0]	valid[3]	auto[1]	194	1			T31	1		T65	2		T99	4
auto[0]	auto[0]	valid[4]	auto[0]	119	1			T5	1		T29	1		T90	1
auto[0]	auto[0]	valid[4]	auto[1]	152	1			T30	1		T31	1		T32	2
auto[0]	auto[1]	valid[0]	auto[0]	115	1			T29	2		T18	1		T61	1
auto[0]	auto[1]	valid[0]	auto[1]	186	1			T5	2		T32	1		T65	1
auto[0]	auto[1]	valid[1]	auto[0]	125	1			T29	2		T30	1		T350	1
auto[0]	auto[1]	valid[1]	auto[1]	149	1			T5	1		T99	4		T38	1
auto[0]	auto[1]	valid[2]	auto[0]	137	1			T15	1		T29	1		T30	1
auto[0]	auto[1]	valid[2]	auto[1]	176	1			T32	1		T65	2		T99	1
auto[0]	auto[1]	valid[3]	auto[0]	95	1			T29	1		T30	1		T65	1
auto[0]	auto[1]	valid[3]	auto[1]	158	1			T30	1		T31	1		T32	3
auto[0]	auto[1]	valid[4]	auto[0]	133	1			T5	1		T29	1		T90	1
auto[0]	auto[1]	valid[4]	auto[1]	168	1			T30	1		T31	1		T32	1
auto[1]	auto[0]	valid[0]	auto[0]	81	1			T29	2		T90	1		T350	1
auto[1]	auto[0]	valid[1]	auto[0]	80	1			T5	2		T29	1		T17	1
auto[1]	auto[0]	valid[2]	auto[0]	76	1			T15	1		T33	1		T65	2
auto[1]	auto[0]	valid[3]	auto[0]	69	1			T5	2		T29	1		T50	1
auto[1]	auto[0]	valid[4]	auto[0]	78	1			T30	1		T33	1		T90	1
auto[1]	auto[1]	valid[0]	auto[0]	74	1			T15	2		T29	2		T17	1
auto[1]	auto[1]	valid[1]	auto[0]	67	1			T29	1		T341	2		T339	1
auto[1]	auto[1]	valid[2]	auto[0]	61	1			T30	1		T65	2		T63	1
auto[1]	auto[1]	valid[3]	auto[0]	63	1			T5	1		T17	2		T33	1
auto[1]	auto[1]	valid[4]	auto[0]	105	1			T15	1		T29	2		T30	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal