Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50600

1

T3

14

T5

333

T6

11

auto[1]

17172

1

T5

41

T12

1

T15

30

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49431

1

T3

4

T5

260

T6

5

auto[1]

18341

1

T3

10

T5

114

T6

6

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34861	1			T3	7		T5	202		T6	3
others[1]	5691	1			T3	2		T5	31		T15	29
others[2]	5784	1			T5	27		T6	2		T15	20
others[3]	6330	1			T5	40		T6	1		T15	20
interest[1]	3715	1			T3	1		T5	18		T6	1
interest[4]	22849	1			T3	4		T5	123		T6	3
interest[64]	11391	1			T3	4		T5	56		T6	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16549	1			T3	3		T5	124		T6	2
auto[0]	auto[0]	others[1]	2694	1			T5	20		T15	16		T29	28
auto[0]	auto[0]	others[2]	2775	1			T5	13		T15	10		T29	21
auto[0]	auto[0]	others[3]	3056	1			T5	27		T15	12		T29	30
auto[0]	auto[0]	interest[1]	1733	1			T5	5		T15	4		T29	29
auto[0]	auto[0]	interest[4]	10913	1			T3	2		T5	79		T6	2
auto[0]	auto[0]	interest[64]	5452	1			T3	1		T5	30		T6	3
auto[0]	auto[1]	others[0]	8947	1			T5	21		T12	1		T15	12
auto[0]	auto[1]	others[1]	1453	1			T5	5		T15	4		T30	5
auto[0]	auto[1]	others[2]	1416	1			T5	4		T15	4		T30	8
auto[0]	auto[1]	others[3]	1558	1			T5	2		T15	1		T30	4
auto[0]	auto[1]	interest[1]	949	1			T5	4		T15	2		T30	9
auto[0]	auto[1]	interest[4]	5881	1			T5	14		T12	1		T15	9
auto[0]	auto[1]	interest[64]	2849	1			T5	5		T15	7		T30	10
auto[1]	auto[0]	others[0]	9365	1			T3	4		T5	57		T6	1
auto[1]	auto[0]	others[1]	1544	1			T3	2		T5	6		T15	9
auto[1]	auto[0]	others[2]	1593	1			T5	10		T6	2		T15	6
auto[1]	auto[0]	others[3]	1716	1			T5	11		T6	1		T15	7
auto[1]	auto[0]	interest[1]	1033	1			T3	1		T5	9		T6	1
auto[1]	auto[0]	interest[4]	6055	1			T3	2		T5	30		T6	1
auto[1]	auto[0]	interest[64]	3090	1			T3	3		T5	21		T6	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal