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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.45 94.08 98.62 89.36 97.31 95.43 99.21


Total test records in report: 1150
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T1040 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1814130284 Jul 16 08:04:38 PM PDT 24 Jul 16 08:04:42 PM PDT 24 11099482 ps
T169 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3725259057 Jul 16 08:03:01 PM PDT 24 Jul 16 08:03:06 PM PDT 24 143285969 ps
T134 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3319118927 Jul 16 08:03:12 PM PDT 24 Jul 16 08:03:16 PM PDT 24 30761740 ps
T1041 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3621321290 Jul 16 08:03:46 PM PDT 24 Jul 16 08:03:49 PM PDT 24 289965733 ps
T1042 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1044520588 Jul 16 08:04:38 PM PDT 24 Jul 16 08:04:42 PM PDT 24 12686138 ps
T129 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1474775536 Jul 16 08:03:14 PM PDT 24 Jul 16 08:03:33 PM PDT 24 680972775 ps
T1043 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1337162354 Jul 16 08:03:13 PM PDT 24 Jul 16 08:03:18 PM PDT 24 223696566 ps
T1044 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.442247654 Jul 16 08:03:00 PM PDT 24 Jul 16 08:03:02 PM PDT 24 15634597 ps
T1045 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1315932974 Jul 16 08:02:58 PM PDT 24 Jul 16 08:03:00 PM PDT 24 67856160 ps
T127 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3848452648 Jul 16 08:03:12 PM PDT 24 Jul 16 08:03:15 PM PDT 24 87801758 ps
T135 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1781215717 Jul 16 08:03:50 PM PDT 24 Jul 16 08:03:55 PM PDT 24 135579018 ps
T170 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4052331686 Jul 16 08:03:47 PM PDT 24 Jul 16 08:03:49 PM PDT 24 133034738 ps
T96 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1729470778 Jul 16 08:03:13 PM PDT 24 Jul 16 08:03:17 PM PDT 24 36349125 ps
T1046 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2369069428 Jul 16 08:03:15 PM PDT 24 Jul 16 08:03:31 PM PDT 24 622367728 ps
T128 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1555082186 Jul 16 08:03:14 PM PDT 24 Jul 16 08:03:26 PM PDT 24 3805435023 ps
T124 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4277471939 Jul 16 08:03:19 PM PDT 24 Jul 16 08:03:23 PM PDT 24 72146780 ps
T1047 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2068928266 Jul 16 08:03:01 PM PDT 24 Jul 16 08:03:04 PM PDT 24 18673260 ps
T171 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.779447988 Jul 16 08:04:40 PM PDT 24 Jul 16 08:04:45 PM PDT 24 46507584 ps
T197 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.894799430 Jul 16 08:03:48 PM PDT 24 Jul 16 08:04:07 PM PDT 24 1195737545 ps
T117 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.413196201 Jul 16 08:03:16 PM PDT 24 Jul 16 08:03:23 PM PDT 24 146725187 ps
T1048 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3912378382 Jul 16 08:03:14 PM PDT 24 Jul 16 08:03:20 PM PDT 24 36475495 ps
T136 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3488749461 Jul 16 08:03:01 PM PDT 24 Jul 16 08:03:04 PM PDT 24 56616697 ps
T186 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2035673648 Jul 16 08:04:39 PM PDT 24 Jul 16 08:04:57 PM PDT 24 2253208900 ps
T188 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.567477359 Jul 16 08:03:01 PM PDT 24 Jul 16 08:03:10 PM PDT 24 114025612 ps
T1049 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.391452935 Jul 16 08:04:37 PM PDT 24 Jul 16 08:04:41 PM PDT 24 64198201 ps
T1050 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.4054335608 Jul 16 08:04:50 PM PDT 24 Jul 16 08:04:52 PM PDT 24 50504482 ps
T1051 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3594982678 Jul 16 08:03:47 PM PDT 24 Jul 16 08:03:49 PM PDT 24 18310246 ps
T1052 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3090140317 Jul 16 08:03:00 PM PDT 24 Jul 16 08:03:03 PM PDT 24 36418175 ps
T1053 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3787605439 Jul 16 08:04:57 PM PDT 24 Jul 16 08:05:00 PM PDT 24 14040310 ps
T1054 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.405150130 Jul 16 08:04:36 PM PDT 24 Jul 16 08:04:39 PM PDT 24 128884459 ps
T1055 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3586705470 Jul 16 08:03:19 PM PDT 24 Jul 16 08:03:24 PM PDT 24 46560047 ps
T172 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.641082154 Jul 16 08:03:13 PM PDT 24 Jul 16 08:03:24 PM PDT 24 714138807 ps
T137 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2667558358 Jul 16 08:03:16 PM PDT 24 Jul 16 08:03:27 PM PDT 24 415801242 ps
T1056 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2970585686 Jul 16 08:04:39 PM PDT 24 Jul 16 08:04:42 PM PDT 24 14128427 ps
T173 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2921283560 Jul 16 08:03:15 PM PDT 24 Jul 16 08:03:26 PM PDT 24 1200106806 ps
T1057 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2424759546 Jul 16 08:04:41 PM PDT 24 Jul 16 08:04:45 PM PDT 24 55972783 ps
T138 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.476501810 Jul 16 08:02:59 PM PDT 24 Jul 16 08:03:14 PM PDT 24 191579769 ps
T1058 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1725386850 Jul 16 08:03:51 PM PDT 24 Jul 16 08:03:57 PM PDT 24 227251442 ps
T118 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.673669539 Jul 16 08:03:49 PM PDT 24 Jul 16 08:03:54 PM PDT 24 29246460 ps
T1059 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3161014245 Jul 16 08:03:14 PM PDT 24 Jul 16 08:03:18 PM PDT 24 50517232 ps
T97 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1208960426 Jul 16 08:03:16 PM PDT 24 Jul 16 08:03:20 PM PDT 24 16344284 ps
T1060 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1722638613 Jul 16 08:03:15 PM PDT 24 Jul 16 08:03:20 PM PDT 24 19644793 ps
T121 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4112181140 Jul 16 08:03:17 PM PDT 24 Jul 16 08:03:22 PM PDT 24 27533379 ps
T1061 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.539306 Jul 16 08:03:16 PM PDT 24 Jul 16 08:03:37 PM PDT 24 1084940822 ps
T122 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.699175718 Jul 16 08:04:42 PM PDT 24 Jul 16 08:04:46 PM PDT 24 47606073 ps
T174 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.726684779 Jul 16 08:02:58 PM PDT 24 Jul 16 08:03:12 PM PDT 24 2594940700 ps
T1062 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1455819777 Jul 16 08:03:51 PM PDT 24 Jul 16 08:03:56 PM PDT 24 23569674 ps
T1063 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4288828306 Jul 16 08:04:57 PM PDT 24 Jul 16 08:04:59 PM PDT 24 26963374 ps
T1064 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1154229407 Jul 16 08:03:18 PM PDT 24 Jul 16 08:03:28 PM PDT 24 423238614 ps
T1065 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1840126622 Jul 16 08:03:18 PM PDT 24 Jul 16 08:03:22 PM PDT 24 28962107 ps
T139 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3037211744 Jul 16 08:03:01 PM PDT 24 Jul 16 08:03:10 PM PDT 24 104494028 ps
T140 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3769578722 Jul 16 08:03:18 PM PDT 24 Jul 16 08:03:54 PM PDT 24 12352277974 ps
T1066 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3436440203 Jul 16 08:04:37 PM PDT 24 Jul 16 08:04:40 PM PDT 24 14077189 ps
T119 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1218824454 Jul 16 08:04:37 PM PDT 24 Jul 16 08:04:42 PM PDT 24 238675705 ps
T1067 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.759621128 Jul 16 08:04:41 PM PDT 24 Jul 16 08:04:45 PM PDT 24 42543040 ps
T141 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.786239465 Jul 16 08:03:46 PM PDT 24 Jul 16 08:03:49 PM PDT 24 68396558 ps
T1068 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.4081134514 Jul 16 08:03:14 PM PDT 24 Jul 16 08:03:18 PM PDT 24 18874177 ps
T123 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.40858454 Jul 16 08:03:16 PM PDT 24 Jul 16 08:03:22 PM PDT 24 291718320 ps
T1069 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.540235043 Jul 16 08:03:17 PM PDT 24 Jul 16 08:03:23 PM PDT 24 108270012 ps
T1070 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2654538204 Jul 16 08:03:50 PM PDT 24 Jul 16 08:03:55 PM PDT 24 230316823 ps
T189 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1278650781 Jul 16 08:03:47 PM PDT 24 Jul 16 08:04:06 PM PDT 24 1014674221 ps
T1071 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2540567712 Jul 16 08:03:01 PM PDT 24 Jul 16 08:03:06 PM PDT 24 43564175 ps
T1072 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1285999843 Jul 16 08:03:17 PM PDT 24 Jul 16 08:03:22 PM PDT 24 60361817 ps
T1073 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3657747517 Jul 16 08:03:16 PM PDT 24 Jul 16 08:03:23 PM PDT 24 266933246 ps
T1074 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2603312570 Jul 16 08:04:39 PM PDT 24 Jul 16 08:04:43 PM PDT 24 186134750 ps
T1075 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1636360821 Jul 16 08:04:57 PM PDT 24 Jul 16 08:05:00 PM PDT 24 45915042 ps
T1076 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3453351736 Jul 16 08:03:51 PM PDT 24 Jul 16 08:03:57 PM PDT 24 51181941 ps
T1077 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2820133812 Jul 16 08:04:53 PM PDT 24 Jul 16 08:04:55 PM PDT 24 47622433 ps
T1078 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4141852776 Jul 16 08:03:00 PM PDT 24 Jul 16 08:03:03 PM PDT 24 27486789 ps
T1079 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2710979072 Jul 16 08:03:17 PM PDT 24 Jul 16 08:03:23 PM PDT 24 221048595 ps
T120 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2287503875 Jul 16 08:03:49 PM PDT 24 Jul 16 08:03:55 PM PDT 24 111886131 ps
T1080 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1441499491 Jul 16 08:04:37 PM PDT 24 Jul 16 08:04:40 PM PDT 24 14219906 ps
T1081 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.606286790 Jul 16 08:03:12 PM PDT 24 Jul 16 08:03:15 PM PDT 24 69108463 ps
T1082 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1042630119 Jul 16 08:03:16 PM PDT 24 Jul 16 08:03:22 PM PDT 24 85977678 ps
T1083 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.805185185 Jul 16 08:03:48 PM PDT 24 Jul 16 08:03:54 PM PDT 24 665220405 ps
T1084 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3379385782 Jul 16 08:04:52 PM PDT 24 Jul 16 08:04:54 PM PDT 24 36568702 ps
T125 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3008917103 Jul 16 08:03:50 PM PDT 24 Jul 16 08:03:55 PM PDT 24 87226609 ps
T1085 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3598459337 Jul 16 08:03:16 PM PDT 24 Jul 16 08:03:43 PM PDT 24 1212714625 ps
T142 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3996237137 Jul 16 08:03:51 PM PDT 24 Jul 16 08:03:56 PM PDT 24 147370755 ps
T1086 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.587381404 Jul 16 08:03:11 PM PDT 24 Jul 16 08:03:20 PM PDT 24 447560426 ps
T1087 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1984681019 Jul 16 08:03:11 PM PDT 24 Jul 16 08:03:16 PM PDT 24 1219367272 ps
T143 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1421590159 Jul 16 08:03:12 PM PDT 24 Jul 16 08:03:16 PM PDT 24 137421755 ps
T1088 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1621729530 Jul 16 08:03:15 PM PDT 24 Jul 16 08:03:40 PM PDT 24 3315007623 ps
T1089 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.35882564 Jul 16 08:04:55 PM PDT 24 Jul 16 08:04:58 PM PDT 24 34459923 ps
T1090 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2330303975 Jul 16 08:04:57 PM PDT 24 Jul 16 08:05:00 PM PDT 24 23618133 ps
T1091 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1090333782 Jul 16 08:03:14 PM PDT 24 Jul 16 08:03:20 PM PDT 24 65051650 ps
T191 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.846752167 Jul 16 08:03:48 PM PDT 24 Jul 16 08:04:04 PM PDT 24 2299020545 ps
T190 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2256310795 Jul 16 08:03:47 PM PDT 24 Jul 16 08:03:59 PM PDT 24 657280586 ps
T1092 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.992840882 Jul 16 08:03:14 PM PDT 24 Jul 16 08:03:20 PM PDT 24 112938912 ps
T1093 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2412556311 Jul 16 08:03:14 PM PDT 24 Jul 16 08:03:19 PM PDT 24 214401560 ps
T1094 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3019252340 Jul 16 08:04:36 PM PDT 24 Jul 16 08:04:40 PM PDT 24 56506173 ps
T1095 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.724258883 Jul 16 08:03:14 PM PDT 24 Jul 16 08:03:19 PM PDT 24 115744989 ps
T1096 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3672272314 Jul 16 08:04:41 PM PDT 24 Jul 16 08:04:45 PM PDT 24 22753783 ps
T1097 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2656004957 Jul 16 08:04:36 PM PDT 24 Jul 16 08:04:40 PM PDT 24 25887750 ps
T1098 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1010103263 Jul 16 08:04:42 PM PDT 24 Jul 16 08:04:46 PM PDT 24 73944142 ps
T1099 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.319051342 Jul 16 08:04:38 PM PDT 24 Jul 16 08:04:42 PM PDT 24 33534910 ps
T1100 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2363664614 Jul 16 08:03:50 PM PDT 24 Jul 16 08:03:55 PM PDT 24 426560313 ps
T1101 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3146001056 Jul 16 08:03:51 PM PDT 24 Jul 16 08:03:59 PM PDT 24 2002146180 ps
T1102 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.444131826 Jul 16 08:03:48 PM PDT 24 Jul 16 08:03:51 PM PDT 24 53779340 ps
T1103 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.187621628 Jul 16 08:03:50 PM PDT 24 Jul 16 08:03:55 PM PDT 24 13237890 ps
T1104 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1294538299 Jul 16 08:03:12 PM PDT 24 Jul 16 08:03:14 PM PDT 24 24066282 ps
T1105 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3434420965 Jul 16 08:03:48 PM PDT 24 Jul 16 08:03:51 PM PDT 24 44988263 ps
T1106 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1271557600 Jul 16 08:03:13 PM PDT 24 Jul 16 08:03:19 PM PDT 24 68679382 ps
T1107 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1069208605 Jul 16 08:04:56 PM PDT 24 Jul 16 08:04:58 PM PDT 24 19709381 ps
T144 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3297177112 Jul 16 08:03:15 PM PDT 24 Jul 16 08:03:34 PM PDT 24 1413882392 ps
T1108 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4150037699 Jul 16 08:03:48 PM PDT 24 Jul 16 08:03:51 PM PDT 24 275080666 ps
T1109 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2136451541 Jul 16 08:03:51 PM PDT 24 Jul 16 08:03:57 PM PDT 24 123141575 ps
T1110 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2995084862 Jul 16 08:03:19 PM PDT 24 Jul 16 08:03:23 PM PDT 24 63118977 ps
T1111 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2556742925 Jul 16 08:03:24 PM PDT 24 Jul 16 08:03:27 PM PDT 24 27699230 ps
T1112 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2855439857 Jul 16 08:05:01 PM PDT 24 Jul 16 08:05:03 PM PDT 24 26555321 ps
T1113 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1781494116 Jul 16 08:03:52 PM PDT 24 Jul 16 08:03:57 PM PDT 24 66837703 ps
T1114 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.723313348 Jul 16 08:03:48 PM PDT 24 Jul 16 08:03:50 PM PDT 24 163270366 ps
T1115 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1939687236 Jul 16 08:04:35 PM PDT 24 Jul 16 08:04:38 PM PDT 24 18063198 ps
T1116 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1462022043 Jul 16 08:03:50 PM PDT 24 Jul 16 08:03:56 PM PDT 24 95138470 ps
T1117 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3925487893 Jul 16 08:03:50 PM PDT 24 Jul 16 08:03:55 PM PDT 24 257281726 ps
T196 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2854873483 Jul 16 08:03:00 PM PDT 24 Jul 16 08:03:08 PM PDT 24 70152167 ps
T1118 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.305880436 Jul 16 08:03:13 PM PDT 24 Jul 16 08:03:15 PM PDT 24 57906960 ps
T1119 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2428458812 Jul 16 08:03:50 PM PDT 24 Jul 16 08:03:56 PM PDT 24 185412935 ps
T1120 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3001937364 Jul 16 08:03:50 PM PDT 24 Jul 16 08:03:56 PM PDT 24 99781002 ps
T1121 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4155058792 Jul 16 08:03:49 PM PDT 24 Jul 16 08:03:53 PM PDT 24 109425664 ps
T1122 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2928630262 Jul 16 08:03:15 PM PDT 24 Jul 16 08:03:21 PM PDT 24 25961847 ps
T1123 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3828436341 Jul 16 08:03:50 PM PDT 24 Jul 16 08:03:54 PM PDT 24 17898715 ps
T1124 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2911884470 Jul 16 08:04:57 PM PDT 24 Jul 16 08:04:59 PM PDT 24 14801355 ps
T1125 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3538010385 Jul 16 08:03:12 PM PDT 24 Jul 16 08:03:14 PM PDT 24 19244241 ps
T1126 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3649818248 Jul 16 08:04:38 PM PDT 24 Jul 16 08:04:42 PM PDT 24 55713026 ps
T1127 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3132706177 Jul 16 08:03:13 PM PDT 24 Jul 16 08:03:16 PM PDT 24 29976151 ps
T1128 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4102195035 Jul 16 08:03:48 PM PDT 24 Jul 16 08:03:54 PM PDT 24 372636249 ps
T1129 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1337292448 Jul 16 08:03:13 PM PDT 24 Jul 16 08:03:22 PM PDT 24 103861696 ps
T1130 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1545054835 Jul 16 08:03:15 PM PDT 24 Jul 16 08:03:21 PM PDT 24 103320231 ps
T1131 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4057582863 Jul 16 08:03:51 PM PDT 24 Jul 16 08:04:11 PM PDT 24 4642474519 ps
T1132 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.384199248 Jul 16 08:04:09 PM PDT 24 Jul 16 08:04:10 PM PDT 24 64995033 ps
T1133 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3543719905 Jul 16 08:03:14 PM PDT 24 Jul 16 08:03:21 PM PDT 24 65627472 ps
T187 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3767154807 Jul 16 08:03:50 PM PDT 24 Jul 16 08:04:01 PM PDT 24 250401528 ps
T1134 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3038928500 Jul 16 08:03:01 PM PDT 24 Jul 16 08:03:18 PM PDT 24 698618285 ps
T1135 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3109285585 Jul 16 08:03:49 PM PDT 24 Jul 16 08:03:55 PM PDT 24 486882283 ps
T1136 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3611815256 Jul 16 08:03:48 PM PDT 24 Jul 16 08:03:52 PM PDT 24 246174074 ps
T1137 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2359759389 Jul 16 08:03:00 PM PDT 24 Jul 16 08:03:06 PM PDT 24 652994558 ps
T1138 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.852171936 Jul 16 08:03:49 PM PDT 24 Jul 16 08:03:53 PM PDT 24 78859140 ps
T1139 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1411392203 Jul 16 08:03:01 PM PDT 24 Jul 16 08:03:09 PM PDT 24 420742322 ps
T1140 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3945353835 Jul 16 08:03:52 PM PDT 24 Jul 16 08:03:59 PM PDT 24 87035778 ps
T1141 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4137669376 Jul 16 08:04:55 PM PDT 24 Jul 16 08:04:57 PM PDT 24 29227389 ps
T1142 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1051513482 Jul 16 08:03:12 PM PDT 24 Jul 16 08:03:16 PM PDT 24 94169879 ps
T1143 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3396307899 Jul 16 08:02:58 PM PDT 24 Jul 16 08:03:00 PM PDT 24 83437318 ps
T1144 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3059448610 Jul 16 08:03:10 PM PDT 24 Jul 16 08:03:12 PM PDT 24 27508490 ps
T1145 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.739483021 Jul 16 08:04:42 PM PDT 24 Jul 16 08:04:45 PM PDT 24 19421528 ps
T1146 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3990998960 Jul 16 08:03:13 PM PDT 24 Jul 16 08:03:17 PM PDT 24 11375565 ps
T1147 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3642283664 Jul 16 08:03:17 PM PDT 24 Jul 16 08:03:21 PM PDT 24 87644424 ps
T1148 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2102444904 Jul 16 08:03:14 PM PDT 24 Jul 16 08:03:21 PM PDT 24 137770378 ps
T1149 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1594794970 Jul 16 08:04:56 PM PDT 24 Jul 16 08:04:58 PM PDT 24 11840152 ps
T1150 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4007508168 Jul 16 08:05:01 PM PDT 24 Jul 16 08:05:03 PM PDT 24 11859023 ps

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2632956844
Short name T5
Test name
Test status
Simulation time 28899237748 ps
CPU time 151.2 seconds
Started Jul 16 07:50:25 PM PDT 24
Finished Jul 16 07:52:59 PM PDT 24
Peak memory 266708 kb
Host smart-6e7f48ec-f8bb-4408-9c9b-6b48840619e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632956844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2632956844
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.480464518
Short name T17
Test name
Test status
Simulation time 14293290934 ps
CPU time 90.41 seconds
Started Jul 16 07:49:12 PM PDT 24
Finished Jul 16 07:50:43 PM PDT 24
Peak memory 256632 kb
Host smart-6f412397-5216-44ae-8e7b-9a783ac5a1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480464518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.480464518
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3628403099
Short name T20
Test name
Test status
Simulation time 46210122679 ps
CPU time 152.08 seconds
Started Jul 16 07:49:35 PM PDT 24
Finished Jul 16 07:52:09 PM PDT 24
Peak memory 263024 kb
Host smart-4f8e3311-78a0-4d32-aae7-7daff7f2bcd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628403099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3628403099
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1474775536
Short name T129
Test name
Test status
Simulation time 680972775 ps
CPU time 15.71 seconds
Started Jul 16 08:03:14 PM PDT 24
Finished Jul 16 08:03:33 PM PDT 24
Peak memory 215728 kb
Host smart-6371e130-1710-40fc-9ec9-48b2839bfecc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474775536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1474775536
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2537005721
Short name T30
Test name
Test status
Simulation time 65727191473 ps
CPU time 154.21 seconds
Started Jul 16 07:47:58 PM PDT 24
Finished Jul 16 07:50:35 PM PDT 24
Peak memory 250576 kb
Host smart-2fd85099-b501-4b26-8c0a-8ddf3d353026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537005721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2537005721
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3787307967
Short name T51
Test name
Test status
Simulation time 151985717951 ps
CPU time 384.14 seconds
Started Jul 16 07:50:47 PM PDT 24
Finished Jul 16 07:57:14 PM PDT 24
Peak memory 270856 kb
Host smart-2854fcb6-da62-4153-8048-a437a6e65a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787307967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3787307967
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3954967288
Short name T78
Test name
Test status
Simulation time 27857042 ps
CPU time 0.75 seconds
Started Jul 16 07:47:17 PM PDT 24
Finished Jul 16 07:47:21 PM PDT 24
Peak memory 217112 kb
Host smart-0e001700-fc56-47c2-a4ab-dab9686c4dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954967288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3954967288
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.4114687314
Short name T50
Test name
Test status
Simulation time 57746693007 ps
CPU time 574.69 seconds
Started Jul 16 07:51:27 PM PDT 24
Finished Jul 16 08:01:04 PM PDT 24
Peak memory 255820 kb
Host smart-a1978c2d-0beb-4f0b-a67e-5f1816f647a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114687314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4114687314
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.731735323
Short name T42
Test name
Test status
Simulation time 9283353060 ps
CPU time 167.9 seconds
Started Jul 16 07:48:12 PM PDT 24
Finished Jul 16 07:51:03 PM PDT 24
Peak memory 266840 kb
Host smart-68522f61-03d6-429a-b76b-fd7c5e588ce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731735323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.731735323
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1407556773
Short name T181
Test name
Test status
Simulation time 166674038027 ps
CPU time 335.03 seconds
Started Jul 16 07:49:24 PM PDT 24
Finished Jul 16 07:55:03 PM PDT 24
Peak memory 258076 kb
Host smart-f157cc67-e064-4a5a-b4b8-29d1f9c5488a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407556773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1407556773
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4034792125
Short name T108
Test name
Test status
Simulation time 620190453 ps
CPU time 3.62 seconds
Started Jul 16 08:03:13 PM PDT 24
Finished Jul 16 08:03:19 PM PDT 24
Peak memory 219816 kb
Host smart-ab15ea1f-aa89-45c5-a45e-74fc6cc9832b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034792125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
034792125
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2969128176
Short name T236
Test name
Test status
Simulation time 186426139902 ps
CPU time 437.45 seconds
Started Jul 16 07:50:45 PM PDT 24
Finished Jul 16 07:58:05 PM PDT 24
Peak memory 256152 kb
Host smart-ec1ba267-4b93-4646-a72f-1516db7f9362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969128176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2969128176
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.233529375
Short name T33
Test name
Test status
Simulation time 3604820951 ps
CPU time 91.12 seconds
Started Jul 16 07:50:23 PM PDT 24
Finished Jul 16 07:51:55 PM PDT 24
Peak memory 258612 kb
Host smart-7192ef49-8375-416a-bc41-7cef12aac051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233529375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.233529375
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2523908519
Short name T53
Test name
Test status
Simulation time 4251509236 ps
CPU time 29.3 seconds
Started Jul 16 07:48:43 PM PDT 24
Finished Jul 16 07:49:14 PM PDT 24
Peak memory 252416 kb
Host smart-8463c2f7-4ead-4556-94eb-3fe024dad9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523908519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2523908519
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2164319151
Short name T86
Test name
Test status
Simulation time 65766632882 ps
CPU time 155.96 seconds
Started Jul 16 07:49:22 PM PDT 24
Finished Jul 16 07:52:01 PM PDT 24
Peak memory 261152 kb
Host smart-0563d4d5-8428-4351-b706-ff1134dbb93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164319151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2164319151
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.901840821
Short name T72
Test name
Test status
Simulation time 28830723 ps
CPU time 0.73 seconds
Started Jul 16 07:48:46 PM PDT 24
Finished Jul 16 07:48:50 PM PDT 24
Peak memory 206412 kb
Host smart-0550f855-9bf4-46d9-a8f3-b4d933d9f3fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901840821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.901840821
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.681124052
Short name T209
Test name
Test status
Simulation time 334446714008 ps
CPU time 412.25 seconds
Started Jul 16 07:48:02 PM PDT 24
Finished Jul 16 07:54:55 PM PDT 24
Peak memory 271460 kb
Host smart-cc4413d5-02bb-4fa6-9bbb-ae92cd345265
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681124052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.681124052
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.4254509053
Short name T60
Test name
Test status
Simulation time 3499070781 ps
CPU time 68.96 seconds
Started Jul 16 07:48:44 PM PDT 24
Finished Jul 16 07:49:56 PM PDT 24
Peak memory 250412 kb
Host smart-12715d63-adf7-410c-8fad-4e0df1677d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254509053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.4254509053
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3374224137
Short name T92
Test name
Test status
Simulation time 10595655582 ps
CPU time 142.9 seconds
Started Jul 16 07:50:09 PM PDT 24
Finished Jul 16 07:52:34 PM PDT 24
Peak memory 273752 kb
Host smart-05c9db69-e678-4bdf-ac40-bcac96c8a5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374224137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3374224137
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.476501810
Short name T138
Test name
Test status
Simulation time 191579769 ps
CPU time 12.28 seconds
Started Jul 16 08:02:59 PM PDT 24
Finished Jul 16 08:03:14 PM PDT 24
Peak memory 216380 kb
Host smart-e89962a4-8ac3-4d15-a67b-f0ff61bee943
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476501810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.476501810
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.287040317
Short name T234
Test name
Test status
Simulation time 5344827212 ps
CPU time 140.87 seconds
Started Jul 16 07:51:17 PM PDT 24
Finished Jul 16 07:53:41 PM PDT 24
Peak memory 268772 kb
Host smart-faa31def-52ac-4ac2-9a6d-89866e537655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287040317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.287040317
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3626011615
Short name T221
Test name
Test status
Simulation time 30319320651 ps
CPU time 203.84 seconds
Started Jul 16 07:47:49 PM PDT 24
Finished Jul 16 07:51:14 PM PDT 24
Peak memory 257664 kb
Host smart-3904b69e-6d2c-4a37-8ae4-38d008d45ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626011615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3626011615
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1281620210
Short name T46
Test name
Test status
Simulation time 127621210 ps
CPU time 1.07 seconds
Started Jul 16 07:47:18 PM PDT 24
Finished Jul 16 07:47:22 PM PDT 24
Peak memory 217688 kb
Host smart-a7c3e983-d03b-4959-9d3a-da34e6ffa6ab
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281620210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1281620210
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.4288115003
Short name T252
Test name
Test status
Simulation time 12053239314 ps
CPU time 122.03 seconds
Started Jul 16 07:51:39 PM PDT 24
Finished Jul 16 07:53:47 PM PDT 24
Peak memory 263404 kb
Host smart-6c8779be-7ff6-4348-ab4b-8ee937efcfca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288115003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.4288115003
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2664777570
Short name T74
Test name
Test status
Simulation time 3441157649 ps
CPU time 56.96 seconds
Started Jul 16 07:47:57 PM PDT 24
Finished Jul 16 07:48:56 PM PDT 24
Peak memory 242064 kb
Host smart-6db9172c-b0e7-47df-b8b3-2a841d783294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664777570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2664777570
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2423330311
Short name T23
Test name
Test status
Simulation time 344691190 ps
CPU time 1.23 seconds
Started Jul 16 07:47:27 PM PDT 24
Finished Jul 16 07:47:30 PM PDT 24
Peak memory 236348 kb
Host smart-7e8d05ab-bd7a-4629-be9b-ff906b395060
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423330311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2423330311
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.365301309
Short name T315
Test name
Test status
Simulation time 102770927661 ps
CPU time 302.1 seconds
Started Jul 16 07:49:21 PM PDT 24
Finished Jul 16 07:54:25 PM PDT 24
Peak memory 264984 kb
Host smart-937328a5-4bd7-4014-b399-30adb3a75431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365301309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.365301309
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2897058228
Short name T224
Test name
Test status
Simulation time 38703688150 ps
CPU time 348.24 seconds
Started Jul 16 07:49:25 PM PDT 24
Finished Jul 16 07:55:17 PM PDT 24
Peak memory 250344 kb
Host smart-1c0589ce-0252-4af3-82fa-b9444ee44229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897058228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2897058228
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.254609800
Short name T103
Test name
Test status
Simulation time 43235078798 ps
CPU time 148.06 seconds
Started Jul 16 07:49:09 PM PDT 24
Finished Jul 16 07:51:39 PM PDT 24
Peak memory 255028 kb
Host smart-366777c9-4812-412c-93f6-5fb0249b85f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254609800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.254609800
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3291646606
Short name T636
Test name
Test status
Simulation time 11742937943 ps
CPU time 38.73 seconds
Started Jul 16 07:49:22 PM PDT 24
Finished Jul 16 07:50:04 PM PDT 24
Peak memory 249916 kb
Host smart-1232936e-e928-4c6a-be52-ee688bd5894e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291646606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3291646606
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1057684983
Short name T273
Test name
Test status
Simulation time 4638221898 ps
CPU time 99.01 seconds
Started Jul 16 07:50:08 PM PDT 24
Finished Jul 16 07:51:50 PM PDT 24
Peak memory 256552 kb
Host smart-e6014574-2718-4463-a078-ad6fcb99ad92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057684983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1057684983
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1553635081
Short name T99
Test name
Test status
Simulation time 23065370343 ps
CPU time 14.41 seconds
Started Jul 16 07:51:38 PM PDT 24
Finished Jul 16 07:51:59 PM PDT 24
Peak memory 218740 kb
Host smart-2c6c3a49-2e61-49f7-9255-5b9f1a47ff19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553635081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1553635081
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2152264627
Short name T331
Test name
Test status
Simulation time 1173173927 ps
CPU time 10.88 seconds
Started Jul 16 07:50:23 PM PDT 24
Finished Jul 16 07:50:35 PM PDT 24
Peak memory 233728 kb
Host smart-6f733741-628e-43cc-bf68-f918739fe4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152264627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2152264627
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.272030833
Short name T192
Test name
Test status
Simulation time 10005278999 ps
CPU time 57.66 seconds
Started Jul 16 07:50:48 PM PDT 24
Finished Jul 16 07:51:49 PM PDT 24
Peak memory 253976 kb
Host smart-558ddb67-ffb1-4531-b7d1-7a28606c13c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272030833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.272030833
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3955099895
Short name T291
Test name
Test status
Simulation time 11918957465 ps
CPU time 86.71 seconds
Started Jul 16 07:50:46 PM PDT 24
Finished Jul 16 07:52:16 PM PDT 24
Peak memory 258416 kb
Host smart-55afcd9b-7e03-4b6d-aea3-e1e4e5b0cf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955099895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3955099895
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3119688472
Short name T11
Test name
Test status
Simulation time 550974533 ps
CPU time 5.63 seconds
Started Jul 16 07:51:20 PM PDT 24
Finished Jul 16 07:51:28 PM PDT 24
Peak memory 240348 kb
Host smart-a5239b6e-078e-46dd-8d0a-a849d3a2ec7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119688472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3119688472
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.61882001
Short name T245
Test name
Test status
Simulation time 2115024185 ps
CPU time 48.86 seconds
Started Jul 16 07:49:23 PM PDT 24
Finished Jul 16 07:50:16 PM PDT 24
Peak memory 233852 kb
Host smart-25d5ad43-247d-4450-ba98-40ea532c6884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61882001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.61882001
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.21137007
Short name T58
Test name
Test status
Simulation time 35665882955 ps
CPU time 58.83 seconds
Started Jul 16 07:50:27 PM PDT 24
Finished Jul 16 07:51:28 PM PDT 24
Peak memory 236264 kb
Host smart-a7d3d93e-aa99-437b-9b72-8c7288fbaf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21137007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.21137007
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2854873483
Short name T196
Test name
Test status
Simulation time 70152167 ps
CPU time 4.79 seconds
Started Jul 16 08:03:00 PM PDT 24
Finished Jul 16 08:03:08 PM PDT 24
Peak memory 215660 kb
Host smart-acf93098-67fd-41b7-b67d-482a362ef1a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854873483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
854873483
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1278650781
Short name T189
Test name
Test status
Simulation time 1014674221 ps
CPU time 18.18 seconds
Started Jul 16 08:03:47 PM PDT 24
Finished Jul 16 08:04:06 PM PDT 24
Peak memory 215492 kb
Host smart-0ef6c03a-cf18-4d95-aa5a-ebf45a514cbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278650781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1278650781
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.799275422
Short name T203
Test name
Test status
Simulation time 215708063 ps
CPU time 5.14 seconds
Started Jul 16 07:47:27 PM PDT 24
Finished Jul 16 07:47:33 PM PDT 24
Peak memory 233756 kb
Host smart-8ded6aa6-bf22-4d6a-aa92-30cc2ce6b026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799275422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.799275422
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.82884688
Short name T248
Test name
Test status
Simulation time 14080124777 ps
CPU time 100.77 seconds
Started Jul 16 07:49:23 PM PDT 24
Finished Jul 16 07:51:07 PM PDT 24
Peak memory 267508 kb
Host smart-66684224-e25b-4c3b-bc85-756f1ac379ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82884688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.82884688
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2035981336
Short name T867
Test name
Test status
Simulation time 132295701006 ps
CPU time 212.24 seconds
Started Jul 16 07:49:50 PM PDT 24
Finished Jul 16 07:53:25 PM PDT 24
Peak memory 236184 kb
Host smart-a63cdfbb-129f-4c43-bf65-8508aa6a028c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035981336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2035981336
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3493918907
Short name T37
Test name
Test status
Simulation time 4804760269 ps
CPU time 18.68 seconds
Started Jul 16 07:48:16 PM PDT 24
Finished Jul 16 07:48:37 PM PDT 24
Peak memory 223556 kb
Host smart-0670e852-2251-4105-89de-3e13e22c97da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3493918907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3493918907
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3767154807
Short name T187
Test name
Test status
Simulation time 250401528 ps
CPU time 6.89 seconds
Started Jul 16 08:03:50 PM PDT 24
Finished Jul 16 08:04:01 PM PDT 24
Peak memory 215508 kb
Host smart-e6321f5f-1b01-4fa6-b5cb-0964c2a814d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767154807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3767154807
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.4138441272
Short name T83
Test name
Test status
Simulation time 3543918639 ps
CPU time 30.24 seconds
Started Jul 16 07:48:57 PM PDT 24
Finished Jul 16 07:49:31 PM PDT 24
Peak memory 251532 kb
Host smart-ea9f009b-8259-489a-bb95-6cd175c07254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138441272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.4138441272
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2166711820
Short name T318
Test name
Test status
Simulation time 13512892263 ps
CPU time 101.48 seconds
Started Jul 16 07:49:22 PM PDT 24
Finished Jul 16 07:51:06 PM PDT 24
Peak memory 267664 kb
Host smart-8df41da2-fa99-4e04-99cc-35b9309535a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166711820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2166711820
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1271557600
Short name T1106
Test name
Test status
Simulation time 68679382 ps
CPU time 2.16 seconds
Started Jul 16 08:03:13 PM PDT 24
Finished Jul 16 08:03:19 PM PDT 24
Peak memory 215760 kb
Host smart-fc5eb6b5-1421-463d-935c-b857ac041152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271557600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
271557600
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1812072790
Short name T98
Test name
Test status
Simulation time 14009743841 ps
CPU time 110.28 seconds
Started Jul 16 07:50:28 PM PDT 24
Finished Jul 16 07:52:20 PM PDT 24
Peak memory 252628 kb
Host smart-0c273ba9-26ce-4952-a5f1-f95647d32255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812072790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1812072790
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1819320332
Short name T95
Test name
Test status
Simulation time 30864151 ps
CPU time 1.2 seconds
Started Jul 16 08:03:02 PM PDT 24
Finished Jul 16 08:03:05 PM PDT 24
Peak memory 207280 kb
Host smart-3f50a864-5330-4196-87e5-3d3bf20a6951
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819320332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1819320332
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.957833837
Short name T106
Test name
Test status
Simulation time 1144723619 ps
CPU time 27.22 seconds
Started Jul 16 07:50:08 PM PDT 24
Finished Jul 16 07:50:37 PM PDT 24
Peak memory 237340 kb
Host smart-bb538062-c327-4552-a3de-336af489e0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957833837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.957833837
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3038928500
Short name T1134
Test name
Test status
Simulation time 698618285 ps
CPU time 15.13 seconds
Started Jul 16 08:03:01 PM PDT 24
Finished Jul 16 08:03:18 PM PDT 24
Peak memory 215532 kb
Host smart-01478229-48db-407f-b526-d008527f7977
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038928500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3038928500
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3396307899
Short name T1143
Test name
Test status
Simulation time 83437318 ps
CPU time 1.46 seconds
Started Jul 16 08:02:58 PM PDT 24
Finished Jul 16 08:03:00 PM PDT 24
Peak memory 216424 kb
Host smart-99168990-a5c2-45d6-ae8d-c1e8bf4b5d74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396307899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3396307899
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2540567712
Short name T1071
Test name
Test status
Simulation time 43564175 ps
CPU time 2.6 seconds
Started Jul 16 08:03:01 PM PDT 24
Finished Jul 16 08:03:06 PM PDT 24
Peak memory 218140 kb
Host smart-7944dd88-819e-4a46-b8d6-b4f0507886d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540567712 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2540567712
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1315932974
Short name T1045
Test name
Test status
Simulation time 67856160 ps
CPU time 1.22 seconds
Started Jul 16 08:02:58 PM PDT 24
Finished Jul 16 08:03:00 PM PDT 24
Peak memory 207368 kb
Host smart-a94714f1-13d3-4e4e-a637-1391a5bc0eb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315932974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
315932974
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2068928266
Short name T1047
Test name
Test status
Simulation time 18673260 ps
CPU time 0.7 seconds
Started Jul 16 08:03:01 PM PDT 24
Finished Jul 16 08:03:04 PM PDT 24
Peak memory 204284 kb
Host smart-5cc5cf35-91a7-430b-9957-d393df163837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068928266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
068928266
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.716038383
Short name T131
Test name
Test status
Simulation time 68090675 ps
CPU time 2.25 seconds
Started Jul 16 08:03:00 PM PDT 24
Finished Jul 16 08:03:04 PM PDT 24
Peak memory 215316 kb
Host smart-6fddea9f-5e75-4536-a346-511370135348
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716038383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.716038383
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3090140317
Short name T1052
Test name
Test status
Simulation time 36418175 ps
CPU time 0.68 seconds
Started Jul 16 08:03:00 PM PDT 24
Finished Jul 16 08:03:03 PM PDT 24
Peak memory 203836 kb
Host smart-0f7cce89-3376-4ed5-bbaa-88ceab6e2b38
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090140317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3090140317
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3725259057
Short name T169
Test name
Test status
Simulation time 143285969 ps
CPU time 3.26 seconds
Started Jul 16 08:03:01 PM PDT 24
Finished Jul 16 08:03:06 PM PDT 24
Peak memory 215312 kb
Host smart-cbde2fe8-83cf-46be-a2fa-be2800f776c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725259057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3725259057
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2359759389
Short name T1137
Test name
Test status
Simulation time 652994558 ps
CPU time 4 seconds
Started Jul 16 08:03:00 PM PDT 24
Finished Jul 16 08:03:06 PM PDT 24
Peak memory 216840 kb
Host smart-4669af32-6bb9-40e0-acfc-2758320596e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359759389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
359759389
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1411392203
Short name T1139
Test name
Test status
Simulation time 420742322 ps
CPU time 6.38 seconds
Started Jul 16 08:03:01 PM PDT 24
Finished Jul 16 08:03:09 PM PDT 24
Peak memory 215620 kb
Host smart-fe786340-83aa-482a-9151-5ea36f459a51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411392203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1411392203
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3037211744
Short name T139
Test name
Test status
Simulation time 104494028 ps
CPU time 7.17 seconds
Started Jul 16 08:03:01 PM PDT 24
Finished Jul 16 08:03:10 PM PDT 24
Peak memory 207140 kb
Host smart-b7d71899-200b-4b4d-a3a0-7dc8d5bea33b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037211744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3037211744
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.726684779
Short name T174
Test name
Test status
Simulation time 2594940700 ps
CPU time 13.3 seconds
Started Jul 16 08:02:58 PM PDT 24
Finished Jul 16 08:03:12 PM PDT 24
Peak memory 207224 kb
Host smart-c27ffd80-0c1b-4506-873f-df5278c29a1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726684779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.726684779
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4277471939
Short name T124
Test name
Test status
Simulation time 72146780 ps
CPU time 2.64 seconds
Started Jul 16 08:03:19 PM PDT 24
Finished Jul 16 08:03:23 PM PDT 24
Peak memory 216604 kb
Host smart-7455138a-8725-4365-82d4-24998df1be8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277471939 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4277471939
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3335512731
Short name T168
Test name
Test status
Simulation time 253260556 ps
CPU time 2.92 seconds
Started Jul 16 08:03:00 PM PDT 24
Finished Jul 16 08:03:05 PM PDT 24
Peak memory 215580 kb
Host smart-f41209aa-7fb8-4435-812a-b9145f903d0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335512731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
335512731
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4141852776
Short name T1078
Test name
Test status
Simulation time 27486789 ps
CPU time 0.81 seconds
Started Jul 16 08:03:00 PM PDT 24
Finished Jul 16 08:03:03 PM PDT 24
Peak memory 204388 kb
Host smart-abfc5aca-0b21-4c17-bf3a-3ac9fe622cef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141852776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.4
141852776
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3488749461
Short name T136
Test name
Test status
Simulation time 56616697 ps
CPU time 1.27 seconds
Started Jul 16 08:03:01 PM PDT 24
Finished Jul 16 08:03:04 PM PDT 24
Peak memory 215632 kb
Host smart-f333f1cb-1194-41b2-84ce-3ebecc634f2e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488749461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3488749461
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.442247654
Short name T1044
Test name
Test status
Simulation time 15634597 ps
CPU time 0.67 seconds
Started Jul 16 08:03:00 PM PDT 24
Finished Jul 16 08:03:02 PM PDT 24
Peak memory 203848 kb
Host smart-95085b18-f8d2-4d82-b060-cece0bc81965
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442247654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.442247654
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1390351094
Short name T1035
Test name
Test status
Simulation time 24204660 ps
CPU time 1.49 seconds
Started Jul 16 08:03:01 PM PDT 24
Finished Jul 16 08:03:05 PM PDT 24
Peak memory 215484 kb
Host smart-3b4e841c-3f44-41bb-846c-3dead76297d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390351094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1390351094
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.567477359
Short name T188
Test name
Test status
Simulation time 114025612 ps
CPU time 7.11 seconds
Started Jul 16 08:03:01 PM PDT 24
Finished Jul 16 08:03:10 PM PDT 24
Peak memory 215608 kb
Host smart-3093f8f8-3a5e-463c-88e9-ad1bf5692aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567477359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.567477359
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.723313348
Short name T1114
Test name
Test status
Simulation time 163270366 ps
CPU time 1.72 seconds
Started Jul 16 08:03:48 PM PDT 24
Finished Jul 16 08:03:50 PM PDT 24
Peak memory 215792 kb
Host smart-7e6885e5-56c1-482e-97d6-86afd36cd53f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723313348 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.723313348
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1781215717
Short name T135
Test name
Test status
Simulation time 135579018 ps
CPU time 1.79 seconds
Started Jul 16 08:03:50 PM PDT 24
Finished Jul 16 08:03:55 PM PDT 24
Peak memory 207460 kb
Host smart-470e01dc-4400-466e-9266-9ef1e32511e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781215717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1781215717
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3828436341
Short name T1123
Test name
Test status
Simulation time 17898715 ps
CPU time 0.76 seconds
Started Jul 16 08:03:50 PM PDT 24
Finished Jul 16 08:03:54 PM PDT 24
Peak memory 204104 kb
Host smart-9895bdef-e3ac-48d8-98b3-acf77ea47672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828436341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3828436341
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3001937364
Short name T1120
Test name
Test status
Simulation time 99781002 ps
CPU time 3.52 seconds
Started Jul 16 08:03:50 PM PDT 24
Finished Jul 16 08:03:56 PM PDT 24
Peak memory 215476 kb
Host smart-f0f0850b-a4fd-4ebe-8a24-63d1ee3d414a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001937364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3001937364
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3008917103
Short name T125
Test name
Test status
Simulation time 87226609 ps
CPU time 1.43 seconds
Started Jul 16 08:03:50 PM PDT 24
Finished Jul 16 08:03:55 PM PDT 24
Peak memory 215772 kb
Host smart-d39d3cc9-2aca-492c-8b6a-c31c77e5f6e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008917103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3008917103
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3453351736
Short name T1076
Test name
Test status
Simulation time 51181941 ps
CPU time 1.72 seconds
Started Jul 16 08:03:51 PM PDT 24
Finished Jul 16 08:03:57 PM PDT 24
Peak memory 215628 kb
Host smart-4a8415f3-a11e-43cc-879a-af3065f2c948
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453351736 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3453351736
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.852171936
Short name T1138
Test name
Test status
Simulation time 78859140 ps
CPU time 1.33 seconds
Started Jul 16 08:03:49 PM PDT 24
Finished Jul 16 08:03:53 PM PDT 24
Peak memory 215484 kb
Host smart-5bbbae9d-ff78-46c0-9aa5-ded87268347c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852171936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.852171936
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.923607485
Short name T1031
Test name
Test status
Simulation time 17482306 ps
CPU time 0.74 seconds
Started Jul 16 08:03:48 PM PDT 24
Finished Jul 16 08:03:49 PM PDT 24
Peak memory 203988 kb
Host smart-20da2f9a-d779-4695-8fa9-32a53ea4c8a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923607485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.923607485
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3621321290
Short name T1041
Test name
Test status
Simulation time 289965733 ps
CPU time 2.63 seconds
Started Jul 16 08:03:46 PM PDT 24
Finished Jul 16 08:03:49 PM PDT 24
Peak memory 215396 kb
Host smart-fa7dbdae-bfd9-4264-866a-d5171cdbc181
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621321290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3621321290
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.673669539
Short name T118
Test name
Test status
Simulation time 29246460 ps
CPU time 1.89 seconds
Started Jul 16 08:03:49 PM PDT 24
Finished Jul 16 08:03:54 PM PDT 24
Peak memory 215672 kb
Host smart-07fd8658-547b-42f4-bf5d-7d686e173e94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673669539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.673669539
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1064135001
Short name T113
Test name
Test status
Simulation time 597065412 ps
CPU time 18.15 seconds
Started Jul 16 08:03:48 PM PDT 24
Finished Jul 16 08:04:09 PM PDT 24
Peak memory 215744 kb
Host smart-da681f71-fb6c-4f40-b9d8-291eec8bedf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064135001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1064135001
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4150037699
Short name T1108
Test name
Test status
Simulation time 275080666 ps
CPU time 1.75 seconds
Started Jul 16 08:03:48 PM PDT 24
Finished Jul 16 08:03:51 PM PDT 24
Peak memory 215516 kb
Host smart-450d936c-4a4c-4daa-b734-57311a47dcce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150037699 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4150037699
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1781494116
Short name T1113
Test name
Test status
Simulation time 66837703 ps
CPU time 1.36 seconds
Started Jul 16 08:03:52 PM PDT 24
Finished Jul 16 08:03:57 PM PDT 24
Peak memory 215564 kb
Host smart-83581d09-d29d-4ab0-bf7e-d386c7200998
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781494116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1781494116
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3434420965
Short name T1105
Test name
Test status
Simulation time 44988263 ps
CPU time 0.76 seconds
Started Jul 16 08:03:48 PM PDT 24
Finished Jul 16 08:03:51 PM PDT 24
Peak memory 204040 kb
Host smart-9254be84-89f0-4b38-86f5-35af7597719c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434420965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3434420965
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3611815256
Short name T1136
Test name
Test status
Simulation time 246174074 ps
CPU time 1.73 seconds
Started Jul 16 08:03:48 PM PDT 24
Finished Jul 16 08:03:52 PM PDT 24
Peak memory 215488 kb
Host smart-819e177c-e037-4c44-b306-0487b8649216
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611815256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3611815256
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2363664614
Short name T1100
Test name
Test status
Simulation time 426560313 ps
CPU time 2.02 seconds
Started Jul 16 08:03:50 PM PDT 24
Finished Jul 16 08:03:55 PM PDT 24
Peak memory 215860 kb
Host smart-0cd22313-0622-497a-bd3b-e1c017184c75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363664614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2363664614
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4131594642
Short name T110
Test name
Test status
Simulation time 399844572 ps
CPU time 6.69 seconds
Started Jul 16 08:03:49 PM PDT 24
Finished Jul 16 08:03:59 PM PDT 24
Peak memory 215544 kb
Host smart-527e08d2-ea2c-4c65-b7aa-590bc31ec178
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131594642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.4131594642
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2654538204
Short name T1070
Test name
Test status
Simulation time 230316823 ps
CPU time 1.79 seconds
Started Jul 16 08:03:50 PM PDT 24
Finished Jul 16 08:03:55 PM PDT 24
Peak memory 216564 kb
Host smart-a2cf2458-76ce-4f10-884e-21fc77ed9026
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654538204 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2654538204
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3594982678
Short name T1051
Test name
Test status
Simulation time 18310246 ps
CPU time 1.17 seconds
Started Jul 16 08:03:47 PM PDT 24
Finished Jul 16 08:03:49 PM PDT 24
Peak memory 215620 kb
Host smart-05a47951-cbfd-4796-af34-d3a2d2a02a37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594982678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3594982678
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1455819777
Short name T1062
Test name
Test status
Simulation time 23569674 ps
CPU time 0.74 seconds
Started Jul 16 08:03:51 PM PDT 24
Finished Jul 16 08:03:56 PM PDT 24
Peak memory 203952 kb
Host smart-aed8d3b2-7d14-4b03-a307-07bcf4c11d02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455819777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1455819777
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3109285585
Short name T1135
Test name
Test status
Simulation time 486882283 ps
CPU time 2.64 seconds
Started Jul 16 08:03:49 PM PDT 24
Finished Jul 16 08:03:55 PM PDT 24
Peak memory 215416 kb
Host smart-fa150c95-0f66-40a0-8d41-2a602455df6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109285585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3109285585
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1752321825
Short name T109
Test name
Test status
Simulation time 115922460 ps
CPU time 1.67 seconds
Started Jul 16 08:03:48 PM PDT 24
Finished Jul 16 08:03:52 PM PDT 24
Peak memory 215696 kb
Host smart-dc70bd31-d1ac-4f86-aa5f-54b5d08e7a14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752321825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1752321825
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.894799430
Short name T197
Test name
Test status
Simulation time 1195737545 ps
CPU time 18.13 seconds
Started Jul 16 08:03:48 PM PDT 24
Finished Jul 16 08:04:07 PM PDT 24
Peak memory 215572 kb
Host smart-cd562b23-bc7f-4a84-9866-df9061eb232a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894799430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.894799430
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3146001056
Short name T1101
Test name
Test status
Simulation time 2002146180 ps
CPU time 3.64 seconds
Started Jul 16 08:03:51 PM PDT 24
Finished Jul 16 08:03:59 PM PDT 24
Peak memory 217260 kb
Host smart-1bd495de-a544-4443-8763-74d745f7a42e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146001056 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3146001056
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2428458812
Short name T1119
Test name
Test status
Simulation time 185412935 ps
CPU time 2.3 seconds
Started Jul 16 08:03:50 PM PDT 24
Finished Jul 16 08:03:56 PM PDT 24
Peak memory 207288 kb
Host smart-de99781a-054c-401a-a2f5-20dd212507f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428458812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2428458812
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.444131826
Short name T1102
Test name
Test status
Simulation time 53779340 ps
CPU time 0.73 seconds
Started Jul 16 08:03:48 PM PDT 24
Finished Jul 16 08:03:51 PM PDT 24
Peak memory 203980 kb
Host smart-78a06647-2a91-4c97-b1f8-94846e1daad9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444131826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.444131826
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2136451541
Short name T1109
Test name
Test status
Simulation time 123141575 ps
CPU time 3.13 seconds
Started Jul 16 08:03:51 PM PDT 24
Finished Jul 16 08:03:57 PM PDT 24
Peak memory 215508 kb
Host smart-d2833b27-9dbf-4e30-bad9-3ea2cb2996bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136451541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2136451541
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3718156698
Short name T112
Test name
Test status
Simulation time 128782053 ps
CPU time 4.55 seconds
Started Jul 16 08:03:52 PM PDT 24
Finished Jul 16 08:04:00 PM PDT 24
Peak memory 215720 kb
Host smart-3404bd57-e7aa-4009-850c-5eb9559b205f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718156698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3718156698
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4057582863
Short name T1131
Test name
Test status
Simulation time 4642474519 ps
CPU time 16.81 seconds
Started Jul 16 08:03:51 PM PDT 24
Finished Jul 16 08:04:11 PM PDT 24
Peak memory 215560 kb
Host smart-1e437ef3-cda3-4ed6-9ac2-40a7edf989fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057582863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.4057582863
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3925487893
Short name T1117
Test name
Test status
Simulation time 257281726 ps
CPU time 1.72 seconds
Started Jul 16 08:03:50 PM PDT 24
Finished Jul 16 08:03:55 PM PDT 24
Peak memory 215500 kb
Host smart-00a05032-d635-430c-9841-16f3e43c56f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925487893 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3925487893
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.786239465
Short name T141
Test name
Test status
Simulation time 68396558 ps
CPU time 2.01 seconds
Started Jul 16 08:03:46 PM PDT 24
Finished Jul 16 08:03:49 PM PDT 24
Peak memory 215544 kb
Host smart-45c0bf5b-4596-4cc0-84b3-899ff4e6dd0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786239465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.786239465
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2492298246
Short name T1037
Test name
Test status
Simulation time 21208225 ps
CPU time 0.74 seconds
Started Jul 16 08:03:50 PM PDT 24
Finished Jul 16 08:03:54 PM PDT 24
Peak memory 204000 kb
Host smart-7712a42d-2d1d-4fd8-a0ba-3961c0b0735f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492298246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2492298246
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4052331686
Short name T170
Test name
Test status
Simulation time 133034738 ps
CPU time 1.76 seconds
Started Jul 16 08:03:47 PM PDT 24
Finished Jul 16 08:03:49 PM PDT 24
Peak memory 215484 kb
Host smart-163e74e2-bb64-4de7-ba7b-acf3f9165d41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052331686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4052331686
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4102195035
Short name T1128
Test name
Test status
Simulation time 372636249 ps
CPU time 4.4 seconds
Started Jul 16 08:03:48 PM PDT 24
Finished Jul 16 08:03:54 PM PDT 24
Peak memory 215820 kb
Host smart-5b4a992c-3c51-4cf0-b4bf-f9c606c0e1ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102195035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
4102195035
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2256310795
Short name T190
Test name
Test status
Simulation time 657280586 ps
CPU time 11.27 seconds
Started Jul 16 08:03:47 PM PDT 24
Finished Jul 16 08:03:59 PM PDT 24
Peak memory 215564 kb
Host smart-518e4b3e-0ae6-465b-8a4e-c4c6dec8889c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256310795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2256310795
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.805185185
Short name T1083
Test name
Test status
Simulation time 665220405 ps
CPU time 3.7 seconds
Started Jul 16 08:03:48 PM PDT 24
Finished Jul 16 08:03:54 PM PDT 24
Peak memory 217468 kb
Host smart-b9d6b66f-7f31-4a63-b8db-412a9d21fb78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805185185 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.805185185
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3996237137
Short name T142
Test name
Test status
Simulation time 147370755 ps
CPU time 2.36 seconds
Started Jul 16 08:03:51 PM PDT 24
Finished Jul 16 08:03:56 PM PDT 24
Peak memory 215452 kb
Host smart-edbc7d83-9fe9-45e9-80f5-5498f0938458
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996237137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3996237137
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.384199248
Short name T1132
Test name
Test status
Simulation time 64995033 ps
CPU time 0.74 seconds
Started Jul 16 08:04:09 PM PDT 24
Finished Jul 16 08:04:10 PM PDT 24
Peak memory 204028 kb
Host smart-a0352131-028a-4b4b-a745-d8d0c198a255
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384199248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.384199248
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3301512407
Short name T1039
Test name
Test status
Simulation time 114122472 ps
CPU time 3.33 seconds
Started Jul 16 08:03:50 PM PDT 24
Finished Jul 16 08:03:57 PM PDT 24
Peak memory 215436 kb
Host smart-fd925b6e-297e-44f0-b5a2-fa4c91363b94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301512407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3301512407
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2287503875
Short name T120
Test name
Test status
Simulation time 111886131 ps
CPU time 3.08 seconds
Started Jul 16 08:03:49 PM PDT 24
Finished Jul 16 08:03:55 PM PDT 24
Peak memory 215660 kb
Host smart-f881bcc1-3cbc-462a-b440-2a9d2cfbfee8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287503875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2287503875
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1462022043
Short name T1116
Test name
Test status
Simulation time 95138470 ps
CPU time 1.77 seconds
Started Jul 16 08:03:50 PM PDT 24
Finished Jul 16 08:03:56 PM PDT 24
Peak memory 216492 kb
Host smart-0dae177e-a0a0-4f42-9c88-3feb9aef34c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462022043 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1462022043
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4155058792
Short name T1121
Test name
Test status
Simulation time 109425664 ps
CPU time 1.26 seconds
Started Jul 16 08:03:49 PM PDT 24
Finished Jul 16 08:03:53 PM PDT 24
Peak memory 207240 kb
Host smart-5390785f-4eac-4e1b-9a9d-f1e3614e5f21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155058792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
4155058792
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.187621628
Short name T1103
Test name
Test status
Simulation time 13237890 ps
CPU time 0.72 seconds
Started Jul 16 08:03:50 PM PDT 24
Finished Jul 16 08:03:55 PM PDT 24
Peak memory 204384 kb
Host smart-d598b3d7-eb3f-456a-bde7-64a097bcf52c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187621628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.187621628
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1725386850
Short name T1058
Test name
Test status
Simulation time 227251442 ps
CPU time 1.77 seconds
Started Jul 16 08:03:51 PM PDT 24
Finished Jul 16 08:03:57 PM PDT 24
Peak memory 215452 kb
Host smart-f4fb8432-bbff-46f6-bfe2-aa2545787d92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725386850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1725386850
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3945353835
Short name T1140
Test name
Test status
Simulation time 87035778 ps
CPU time 3.03 seconds
Started Jul 16 08:03:52 PM PDT 24
Finished Jul 16 08:03:59 PM PDT 24
Peak memory 215816 kb
Host smart-1aa527bc-7d66-4996-b23a-a6ac79eb0f92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945353835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3945353835
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.846752167
Short name T191
Test name
Test status
Simulation time 2299020545 ps
CPU time 14.67 seconds
Started Jul 16 08:03:48 PM PDT 24
Finished Jul 16 08:04:04 PM PDT 24
Peak memory 215852 kb
Host smart-99549562-8842-4075-a1ee-1035aa086f0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846752167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.846752167
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3019252340
Short name T1094
Test name
Test status
Simulation time 56506173 ps
CPU time 1.78 seconds
Started Jul 16 08:04:36 PM PDT 24
Finished Jul 16 08:04:40 PM PDT 24
Peak memory 215708 kb
Host smart-46b462e6-79f4-4780-8b2a-e4df18348176
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019252340 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3019252340
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1010103263
Short name T1098
Test name
Test status
Simulation time 73944142 ps
CPU time 1.33 seconds
Started Jul 16 08:04:42 PM PDT 24
Finished Jul 16 08:04:46 PM PDT 24
Peak memory 207372 kb
Host smart-16d7c2aa-e42b-4a4c-9c65-8cd763ba850f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010103263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1010103263
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3436440203
Short name T1066
Test name
Test status
Simulation time 14077189 ps
CPU time 0.82 seconds
Started Jul 16 08:04:37 PM PDT 24
Finished Jul 16 08:04:40 PM PDT 24
Peak memory 204308 kb
Host smart-54636428-e7f3-4c5f-a57f-dc1502d12715
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436440203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3436440203
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2937504538
Short name T1036
Test name
Test status
Simulation time 179215908 ps
CPU time 1.66 seconds
Started Jul 16 08:04:38 PM PDT 24
Finished Jul 16 08:04:43 PM PDT 24
Peak memory 215404 kb
Host smart-61c27d92-8eb2-4c7d-b7a1-7dccfb7a6fa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937504538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2937504538
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1218824454
Short name T119
Test name
Test status
Simulation time 238675705 ps
CPU time 3.38 seconds
Started Jul 16 08:04:37 PM PDT 24
Finished Jul 16 08:04:42 PM PDT 24
Peak memory 215716 kb
Host smart-878d9d0d-e098-4750-ada3-85e227c8bbd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218824454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1218824454
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1262663375
Short name T114
Test name
Test status
Simulation time 554843665 ps
CPU time 7 seconds
Started Jul 16 08:04:41 PM PDT 24
Finished Jul 16 08:04:51 PM PDT 24
Peak memory 215504 kb
Host smart-65224a65-45b6-4840-87a0-04fb8e52175c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262663375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1262663375
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2656004957
Short name T1097
Test name
Test status
Simulation time 25887750 ps
CPU time 1.59 seconds
Started Jul 16 08:04:36 PM PDT 24
Finished Jul 16 08:04:40 PM PDT 24
Peak memory 215644 kb
Host smart-22e0a395-4bb2-4942-836f-f3b5a53a1c5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656004957 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2656004957
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.779447988
Short name T171
Test name
Test status
Simulation time 46507584 ps
CPU time 1.37 seconds
Started Jul 16 08:04:40 PM PDT 24
Finished Jul 16 08:04:45 PM PDT 24
Peak memory 215416 kb
Host smart-224266ad-2972-4f71-98d5-9248d42da451
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779447988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.779447988
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2047090559
Short name T1033
Test name
Test status
Simulation time 16682882 ps
CPU time 0.82 seconds
Started Jul 16 08:04:37 PM PDT 24
Finished Jul 16 08:04:40 PM PDT 24
Peak memory 204316 kb
Host smart-67ab8dba-4ebc-46fa-977d-6232f8c4d3bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047090559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2047090559
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3380824291
Short name T166
Test name
Test status
Simulation time 923693578 ps
CPU time 4.9 seconds
Started Jul 16 08:04:46 PM PDT 24
Finished Jul 16 08:04:52 PM PDT 24
Peak memory 215520 kb
Host smart-8867f156-af1f-4614-9882-d215c38a5c2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380824291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3380824291
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.699175718
Short name T122
Test name
Test status
Simulation time 47606073 ps
CPU time 1.51 seconds
Started Jul 16 08:04:42 PM PDT 24
Finished Jul 16 08:04:46 PM PDT 24
Peak memory 215708 kb
Host smart-9d3c7b96-c9ea-4026-a8ee-22600b89825e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699175718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.699175718
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2035673648
Short name T186
Test name
Test status
Simulation time 2253208900 ps
CPU time 15.82 seconds
Started Jul 16 08:04:39 PM PDT 24
Finished Jul 16 08:04:57 PM PDT 24
Peak memory 223792 kb
Host smart-3e2f3a49-0768-43a7-be26-29554edd075b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035673648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2035673648
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.587381404
Short name T1086
Test name
Test status
Simulation time 447560426 ps
CPU time 7.51 seconds
Started Jul 16 08:03:11 PM PDT 24
Finished Jul 16 08:03:20 PM PDT 24
Peak memory 215568 kb
Host smart-fbb90a9e-5e12-4042-a16c-085da63032f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587381404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.587381404
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2369069428
Short name T1046
Test name
Test status
Simulation time 622367728 ps
CPU time 12.58 seconds
Started Jul 16 08:03:15 PM PDT 24
Finished Jul 16 08:03:31 PM PDT 24
Peak memory 207320 kb
Host smart-668209da-84f5-4899-ad9d-2ba82e5271d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369069428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2369069428
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1208960426
Short name T97
Test name
Test status
Simulation time 16344284 ps
CPU time 0.93 seconds
Started Jul 16 08:03:16 PM PDT 24
Finished Jul 16 08:03:20 PM PDT 24
Peak memory 206960 kb
Host smart-be5e8828-cb73-4c60-8dde-f4eff70fb015
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208960426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1208960426
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1285999843
Short name T1072
Test name
Test status
Simulation time 60361817 ps
CPU time 1.82 seconds
Started Jul 16 08:03:17 PM PDT 24
Finished Jul 16 08:03:22 PM PDT 24
Peak memory 215644 kb
Host smart-691e9b40-cddc-4035-8537-140d8a22c192
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285999843 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1285999843
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3912378382
Short name T1048
Test name
Test status
Simulation time 36475495 ps
CPU time 1.22 seconds
Started Jul 16 08:03:14 PM PDT 24
Finished Jul 16 08:03:20 PM PDT 24
Peak memory 215380 kb
Host smart-3068ab2e-14bf-465a-9174-e25591d2a296
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912378382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
912378382
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3132706177
Short name T1127
Test name
Test status
Simulation time 29976151 ps
CPU time 0.69 seconds
Started Jul 16 08:03:13 PM PDT 24
Finished Jul 16 08:03:16 PM PDT 24
Peak memory 204228 kb
Host smart-2e877346-7eed-4e67-910f-9c8c1a45e75b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132706177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
132706177
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.992840882
Short name T1092
Test name
Test status
Simulation time 112938912 ps
CPU time 2.28 seconds
Started Jul 16 08:03:14 PM PDT 24
Finished Jul 16 08:03:20 PM PDT 24
Peak memory 215380 kb
Host smart-0aea0cfc-bcc7-4869-a797-f4f7f2546a2f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992840882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.992840882
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3990998960
Short name T1146
Test name
Test status
Simulation time 11375565 ps
CPU time 0.65 seconds
Started Jul 16 08:03:13 PM PDT 24
Finished Jul 16 08:03:17 PM PDT 24
Peak memory 204232 kb
Host smart-808147ee-d25c-451a-a551-816f5f88287e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990998960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3990998960
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1565325588
Short name T167
Test name
Test status
Simulation time 68782988 ps
CPU time 1.8 seconds
Started Jul 16 08:03:12 PM PDT 24
Finished Jul 16 08:03:16 PM PDT 24
Peak memory 215552 kb
Host smart-83d09dbd-a21e-4404-8bd8-45d8ec19a9bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565325588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1565325588
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.413196201
Short name T117
Test name
Test status
Simulation time 146725187 ps
CPU time 3.87 seconds
Started Jul 16 08:03:16 PM PDT 24
Finished Jul 16 08:03:23 PM PDT 24
Peak memory 215616 kb
Host smart-60663063-9387-45f8-9235-9059ac9d3547
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413196201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.413196201
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.759621128
Short name T1067
Test name
Test status
Simulation time 42543040 ps
CPU time 0.71 seconds
Started Jul 16 08:04:41 PM PDT 24
Finished Jul 16 08:04:45 PM PDT 24
Peak memory 203872 kb
Host smart-c7c2cc05-0501-44e0-ac02-fa4d9e5afed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759621128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.759621128
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.391452935
Short name T1049
Test name
Test status
Simulation time 64198201 ps
CPU time 0.71 seconds
Started Jul 16 08:04:37 PM PDT 24
Finished Jul 16 08:04:41 PM PDT 24
Peak memory 203952 kb
Host smart-53b0d24f-f00e-4f82-b2a0-d8194dbca70d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391452935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.391452935
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3672272314
Short name T1096
Test name
Test status
Simulation time 22753783 ps
CPU time 0.72 seconds
Started Jul 16 08:04:41 PM PDT 24
Finished Jul 16 08:04:45 PM PDT 24
Peak memory 203868 kb
Host smart-74c461f0-1bfe-41e1-87c7-ac5f20448748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672272314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3672272314
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2970585686
Short name T1056
Test name
Test status
Simulation time 14128427 ps
CPU time 0.74 seconds
Started Jul 16 08:04:39 PM PDT 24
Finished Jul 16 08:04:42 PM PDT 24
Peak memory 204020 kb
Host smart-fd24f71b-67db-4220-a912-3f27185a8d4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970585686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2970585686
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4251732517
Short name T1032
Test name
Test status
Simulation time 15637943 ps
CPU time 0.7 seconds
Started Jul 16 08:04:38 PM PDT 24
Finished Jul 16 08:04:42 PM PDT 24
Peak memory 203976 kb
Host smart-7d4ffffa-133d-499d-95fd-c7323b9a41ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251732517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4251732517
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3649818248
Short name T1126
Test name
Test status
Simulation time 55713026 ps
CPU time 0.73 seconds
Started Jul 16 08:04:38 PM PDT 24
Finished Jul 16 08:04:42 PM PDT 24
Peak memory 204028 kb
Host smart-4a1da26c-31ac-42e0-87ea-71c980524e6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649818248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3649818248
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1814130284
Short name T1040
Test name
Test status
Simulation time 11099482 ps
CPU time 0.71 seconds
Started Jul 16 08:04:38 PM PDT 24
Finished Jul 16 08:04:42 PM PDT 24
Peak memory 203904 kb
Host smart-d89ab970-77c1-48e5-8389-2f1f82c49385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814130284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1814130284
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.405150130
Short name T1054
Test name
Test status
Simulation time 128884459 ps
CPU time 0.76 seconds
Started Jul 16 08:04:36 PM PDT 24
Finished Jul 16 08:04:39 PM PDT 24
Peak memory 204004 kb
Host smart-2df62d8a-1fa7-4ba6-a877-9b8537bb365a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405150130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.405150130
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.739483021
Short name T1145
Test name
Test status
Simulation time 19421528 ps
CPU time 0.75 seconds
Started Jul 16 08:04:42 PM PDT 24
Finished Jul 16 08:04:45 PM PDT 24
Peak memory 203992 kb
Host smart-2ae0036c-8a47-4a8c-9862-7404d978e0d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739483021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.739483021
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2424759546
Short name T1057
Test name
Test status
Simulation time 55972783 ps
CPU time 0.71 seconds
Started Jul 16 08:04:41 PM PDT 24
Finished Jul 16 08:04:45 PM PDT 24
Peak memory 203944 kb
Host smart-cca664d3-b6a6-4bc4-833f-0920c8436b1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424759546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2424759546
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3297177112
Short name T144
Test name
Test status
Simulation time 1413882392 ps
CPU time 15.33 seconds
Started Jul 16 08:03:15 PM PDT 24
Finished Jul 16 08:03:34 PM PDT 24
Peak memory 216652 kb
Host smart-fc061316-6a2d-4716-8bb8-ff7be92859b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297177112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3297177112
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3769578722
Short name T140
Test name
Test status
Simulation time 12352277974 ps
CPU time 33.9 seconds
Started Jul 16 08:03:18 PM PDT 24
Finished Jul 16 08:03:54 PM PDT 24
Peak memory 215444 kb
Host smart-0ecf31db-c2ae-484e-b7dc-f9e24c71241d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769578722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3769578722
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1729470778
Short name T96
Test name
Test status
Simulation time 36349125 ps
CPU time 0.95 seconds
Started Jul 16 08:03:13 PM PDT 24
Finished Jul 16 08:03:17 PM PDT 24
Peak memory 207080 kb
Host smart-23ac1bd1-c75c-4fec-8636-bfa826e5db24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729470778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1729470778
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2710979072
Short name T1079
Test name
Test status
Simulation time 221048595 ps
CPU time 3.36 seconds
Started Jul 16 08:03:17 PM PDT 24
Finished Jul 16 08:03:23 PM PDT 24
Peak memory 217484 kb
Host smart-9144dfcc-6032-4528-a54b-6f8a5e6d8205
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710979072 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2710979072
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3319118927
Short name T134
Test name
Test status
Simulation time 30761740 ps
CPU time 1.97 seconds
Started Jul 16 08:03:12 PM PDT 24
Finished Jul 16 08:03:16 PM PDT 24
Peak memory 215560 kb
Host smart-d72f2432-e5f3-40db-bd83-ee65f1ec484f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319118927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
319118927
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.305880436
Short name T1118
Test name
Test status
Simulation time 57906960 ps
CPU time 0.74 seconds
Started Jul 16 08:03:13 PM PDT 24
Finished Jul 16 08:03:15 PM PDT 24
Peak memory 204320 kb
Host smart-a1dd31dc-2225-413e-8063-10f354929d1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305880436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.305880436
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2928630262
Short name T1122
Test name
Test status
Simulation time 25961847 ps
CPU time 2.12 seconds
Started Jul 16 08:03:15 PM PDT 24
Finished Jul 16 08:03:21 PM PDT 24
Peak memory 215424 kb
Host smart-2afeb3ca-9898-4c86-8170-a2e06112827c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928630262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2928630262
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.606286790
Short name T1081
Test name
Test status
Simulation time 69108463 ps
CPU time 0.63 seconds
Started Jul 16 08:03:12 PM PDT 24
Finished Jul 16 08:03:15 PM PDT 24
Peak memory 203884 kb
Host smart-767e3baf-01cf-4a39-987d-0fb166ca9800
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606286790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.606286790
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1840126622
Short name T1065
Test name
Test status
Simulation time 28962107 ps
CPU time 1.77 seconds
Started Jul 16 08:03:18 PM PDT 24
Finished Jul 16 08:03:22 PM PDT 24
Peak memory 215588 kb
Host smart-06e0a5b9-8445-4a9a-82cd-b515ed155bca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840126622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1840126622
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1154229407
Short name T1064
Test name
Test status
Simulation time 423238614 ps
CPU time 8.05 seconds
Started Jul 16 08:03:18 PM PDT 24
Finished Jul 16 08:03:28 PM PDT 24
Peak memory 215912 kb
Host smart-5e85d239-d7ec-4917-a4a6-e99a8f678b00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154229407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1154229407
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1441499491
Short name T1080
Test name
Test status
Simulation time 14219906 ps
CPU time 0.72 seconds
Started Jul 16 08:04:37 PM PDT 24
Finished Jul 16 08:04:40 PM PDT 24
Peak memory 204324 kb
Host smart-3522eb65-ec9b-4d1c-9dc7-fd363f514d07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441499491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1441499491
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1939687236
Short name T1115
Test name
Test status
Simulation time 18063198 ps
CPU time 0.75 seconds
Started Jul 16 08:04:35 PM PDT 24
Finished Jul 16 08:04:38 PM PDT 24
Peak memory 204012 kb
Host smart-0d5cf9e4-83da-41a7-9188-f8967ae730c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939687236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1939687236
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2603312570
Short name T1074
Test name
Test status
Simulation time 186134750 ps
CPU time 0.72 seconds
Started Jul 16 08:04:39 PM PDT 24
Finished Jul 16 08:04:43 PM PDT 24
Peak memory 203964 kb
Host smart-12c2edf2-af1a-44c4-9ae9-6e74325a6d4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603312570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2603312570
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.319051342
Short name T1099
Test name
Test status
Simulation time 33534910 ps
CPU time 0.73 seconds
Started Jul 16 08:04:38 PM PDT 24
Finished Jul 16 08:04:42 PM PDT 24
Peak memory 204296 kb
Host smart-badf4b01-afeb-4a77-b567-5a8bb224101e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319051342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.319051342
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1044520588
Short name T1042
Test name
Test status
Simulation time 12686138 ps
CPU time 0.71 seconds
Started Jul 16 08:04:38 PM PDT 24
Finished Jul 16 08:04:42 PM PDT 24
Peak memory 203948 kb
Host smart-b1d2e9cb-9321-42a0-8d4c-b5d03140ae4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044520588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1044520588
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2855439857
Short name T1112
Test name
Test status
Simulation time 26555321 ps
CPU time 0.75 seconds
Started Jul 16 08:05:01 PM PDT 24
Finished Jul 16 08:05:03 PM PDT 24
Peak memory 204392 kb
Host smart-68890fe3-01f6-4a27-bbc5-941ef8596af6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855439857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2855439857
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2911884470
Short name T1124
Test name
Test status
Simulation time 14801355 ps
CPU time 0.7 seconds
Started Jul 16 08:04:57 PM PDT 24
Finished Jul 16 08:04:59 PM PDT 24
Peak memory 203928 kb
Host smart-ce7df0c9-4811-4e18-a2c1-9a85cf4107b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911884470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2911884470
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.35882564
Short name T1089
Test name
Test status
Simulation time 34459923 ps
CPU time 0.71 seconds
Started Jul 16 08:04:55 PM PDT 24
Finished Jul 16 08:04:58 PM PDT 24
Peak memory 203976 kb
Host smart-8fc63ae4-81f8-4d35-8900-268f810f2034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35882564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.35882564
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3379385782
Short name T1084
Test name
Test status
Simulation time 36568702 ps
CPU time 0.69 seconds
Started Jul 16 08:04:52 PM PDT 24
Finished Jul 16 08:04:54 PM PDT 24
Peak memory 204320 kb
Host smart-137d6b28-dbaf-442d-b1fc-e4b9bf16f3f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379385782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3379385782
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1594794970
Short name T1149
Test name
Test status
Simulation time 11840152 ps
CPU time 0.74 seconds
Started Jul 16 08:04:56 PM PDT 24
Finished Jul 16 08:04:58 PM PDT 24
Peak memory 204020 kb
Host smart-2755815c-51eb-4363-9768-5bcd541df9e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594794970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1594794970
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2667558358
Short name T137
Test name
Test status
Simulation time 415801242 ps
CPU time 7.97 seconds
Started Jul 16 08:03:16 PM PDT 24
Finished Jul 16 08:03:27 PM PDT 24
Peak memory 207280 kb
Host smart-8abdf9b0-4935-42b9-b8cd-d6c52eb1073d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667558358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2667558358
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3598459337
Short name T1085
Test name
Test status
Simulation time 1212714625 ps
CPU time 23.36 seconds
Started Jul 16 08:03:16 PM PDT 24
Finished Jul 16 08:03:43 PM PDT 24
Peak memory 215492 kb
Host smart-073c688e-5018-49dd-b6b1-7d7d2417e725
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598459337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3598459337
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3059448610
Short name T1144
Test name
Test status
Simulation time 27508490 ps
CPU time 0.92 seconds
Started Jul 16 08:03:10 PM PDT 24
Finished Jul 16 08:03:12 PM PDT 24
Peak memory 207040 kb
Host smart-ed6ab130-ebc0-49fe-bb13-9b7932e4c52d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059448610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3059448610
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2412556311
Short name T1093
Test name
Test status
Simulation time 214401560 ps
CPU time 1.56 seconds
Started Jul 16 08:03:14 PM PDT 24
Finished Jul 16 08:03:19 PM PDT 24
Peak memory 215508 kb
Host smart-20c73c70-fb6b-42de-985c-3e1aed0411c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412556311 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2412556311
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1051513482
Short name T1142
Test name
Test status
Simulation time 94169879 ps
CPU time 1.35 seconds
Started Jul 16 08:03:12 PM PDT 24
Finished Jul 16 08:03:16 PM PDT 24
Peak memory 207348 kb
Host smart-c8c2fd67-bbaf-487b-a591-5a4587cbe2a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051513482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
051513482
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1833820248
Short name T1034
Test name
Test status
Simulation time 42148069 ps
CPU time 0.7 seconds
Started Jul 16 08:03:13 PM PDT 24
Finished Jul 16 08:03:16 PM PDT 24
Peak memory 203940 kb
Host smart-b2cd1a24-95a9-4807-a025-1ac7043dc47a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833820248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
833820248
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2172940039
Short name T133
Test name
Test status
Simulation time 236446753 ps
CPU time 2.07 seconds
Started Jul 16 08:03:17 PM PDT 24
Finished Jul 16 08:03:22 PM PDT 24
Peak memory 215528 kb
Host smart-1799c011-5e9e-4f87-8dcd-0d481be95867
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172940039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2172940039
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3642283664
Short name T1147
Test name
Test status
Simulation time 87644424 ps
CPU time 0.65 seconds
Started Jul 16 08:03:17 PM PDT 24
Finished Jul 16 08:03:21 PM PDT 24
Peak memory 203972 kb
Host smart-88462ea2-02c4-422a-bb55-e247f53e2fda
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642283664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3642283664
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1984681019
Short name T1087
Test name
Test status
Simulation time 1219367272 ps
CPU time 4.11 seconds
Started Jul 16 08:03:11 PM PDT 24
Finished Jul 16 08:03:16 PM PDT 24
Peak memory 215528 kb
Host smart-f1552e9b-c96c-47e8-9f56-a67dbdccce46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984681019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1984681019
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4112181140
Short name T121
Test name
Test status
Simulation time 27533379 ps
CPU time 1.78 seconds
Started Jul 16 08:03:17 PM PDT 24
Finished Jul 16 08:03:22 PM PDT 24
Peak memory 216628 kb
Host smart-1b43d3eb-b75f-4662-9940-4b39331153c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112181140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4
112181140
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1337292448
Short name T1129
Test name
Test status
Simulation time 103861696 ps
CPU time 6.67 seconds
Started Jul 16 08:03:13 PM PDT 24
Finished Jul 16 08:03:22 PM PDT 24
Peak memory 215536 kb
Host smart-aed75b13-7ee1-4e28-95c3-e6397644a43b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337292448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1337292448
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3787605439
Short name T1053
Test name
Test status
Simulation time 14040310 ps
CPU time 0.71 seconds
Started Jul 16 08:04:57 PM PDT 24
Finished Jul 16 08:05:00 PM PDT 24
Peak memory 203948 kb
Host smart-05f1e63d-ddcd-412b-b453-3387625aba55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787605439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3787605439
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2454844044
Short name T1038
Test name
Test status
Simulation time 15154198 ps
CPU time 0.73 seconds
Started Jul 16 08:05:00 PM PDT 24
Finished Jul 16 08:05:02 PM PDT 24
Peak memory 203996 kb
Host smart-f665b282-f0eb-4fff-9a2c-89219309b4f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454844044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2454844044
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4288828306
Short name T1063
Test name
Test status
Simulation time 26963374 ps
CPU time 0.79 seconds
Started Jul 16 08:04:57 PM PDT 24
Finished Jul 16 08:04:59 PM PDT 24
Peak memory 203960 kb
Host smart-bdbdd7a6-8ae2-402d-82ed-705cd3f58879
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288828306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4288828306
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2820133812
Short name T1077
Test name
Test status
Simulation time 47622433 ps
CPU time 0.7 seconds
Started Jul 16 08:04:53 PM PDT 24
Finished Jul 16 08:04:55 PM PDT 24
Peak memory 204284 kb
Host smart-bea8dacf-09c8-468b-9323-5afd01de6e85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820133812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2820133812
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.4054335608
Short name T1050
Test name
Test status
Simulation time 50504482 ps
CPU time 0.72 seconds
Started Jul 16 08:04:50 PM PDT 24
Finished Jul 16 08:04:52 PM PDT 24
Peak memory 204012 kb
Host smart-e128140b-2603-4891-80a7-69cac701d8ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054335608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
4054335608
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4007508168
Short name T1150
Test name
Test status
Simulation time 11859023 ps
CPU time 0.76 seconds
Started Jul 16 08:05:01 PM PDT 24
Finished Jul 16 08:05:03 PM PDT 24
Peak memory 203996 kb
Host smart-a6e475fe-0412-44b3-b2f3-b63b9304d7bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007508168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
4007508168
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1636360821
Short name T1075
Test name
Test status
Simulation time 45915042 ps
CPU time 0.71 seconds
Started Jul 16 08:04:57 PM PDT 24
Finished Jul 16 08:05:00 PM PDT 24
Peak memory 203940 kb
Host smart-46ca51fe-0a2d-4b47-80be-4fb6a419d318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636360821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1636360821
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4137669376
Short name T1141
Test name
Test status
Simulation time 29227389 ps
CPU time 0.77 seconds
Started Jul 16 08:04:55 PM PDT 24
Finished Jul 16 08:04:57 PM PDT 24
Peak memory 203992 kb
Host smart-7797bbf1-8539-4b09-88e4-4966773025b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137669376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
4137669376
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2330303975
Short name T1090
Test name
Test status
Simulation time 23618133 ps
CPU time 0.79 seconds
Started Jul 16 08:04:57 PM PDT 24
Finished Jul 16 08:05:00 PM PDT 24
Peak memory 204004 kb
Host smart-09908a7d-048b-471c-9c6b-60f9d23fa73c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330303975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2330303975
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1069208605
Short name T1107
Test name
Test status
Simulation time 19709381 ps
CPU time 0.76 seconds
Started Jul 16 08:04:56 PM PDT 24
Finished Jul 16 08:04:58 PM PDT 24
Peak memory 203988 kb
Host smart-449f4f90-6677-43a7-b5da-56044b9e5260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069208605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1069208605
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3543719905
Short name T1133
Test name
Test status
Simulation time 65627472 ps
CPU time 2.52 seconds
Started Jul 16 08:03:14 PM PDT 24
Finished Jul 16 08:03:21 PM PDT 24
Peak memory 216880 kb
Host smart-cd90dced-e456-46ab-ac0f-d826785e4a5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543719905 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3543719905
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1421590159
Short name T143
Test name
Test status
Simulation time 137421755 ps
CPU time 2.36 seconds
Started Jul 16 08:03:12 PM PDT 24
Finished Jul 16 08:03:16 PM PDT 24
Peak memory 215116 kb
Host smart-84b465dc-7522-4b2b-9a0a-b1fd19fd728d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421590159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
421590159
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3161014245
Short name T1059
Test name
Test status
Simulation time 50517232 ps
CPU time 0.72 seconds
Started Jul 16 08:03:14 PM PDT 24
Finished Jul 16 08:03:18 PM PDT 24
Peak memory 204300 kb
Host smart-8e49b118-b249-4516-8907-004af5320fe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161014245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
161014245
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2102444904
Short name T1148
Test name
Test status
Simulation time 137770378 ps
CPU time 2.99 seconds
Started Jul 16 08:03:14 PM PDT 24
Finished Jul 16 08:03:21 PM PDT 24
Peak memory 215360 kb
Host smart-29ec30c5-e782-40a6-b131-17763052c5fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102444904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2102444904
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3848452648
Short name T127
Test name
Test status
Simulation time 87801758 ps
CPU time 1.57 seconds
Started Jul 16 08:03:12 PM PDT 24
Finished Jul 16 08:03:15 PM PDT 24
Peak memory 215672 kb
Host smart-448ae3c8-71cb-41cf-b9f1-aaa000b3b90d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848452648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
848452648
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1621729530
Short name T1088
Test name
Test status
Simulation time 3315007623 ps
CPU time 21.51 seconds
Started Jul 16 08:03:15 PM PDT 24
Finished Jul 16 08:03:40 PM PDT 24
Peak memory 215544 kb
Host smart-0f40afc5-4781-4406-9895-f3643d50ba2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621729530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1621729530
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1406183072
Short name T115
Test name
Test status
Simulation time 195328528 ps
CPU time 1.68 seconds
Started Jul 16 08:03:12 PM PDT 24
Finished Jul 16 08:03:15 PM PDT 24
Peak memory 215552 kb
Host smart-f65217b8-908d-4449-920c-70f7890f7d30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406183072 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1406183072
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.540235043
Short name T1069
Test name
Test status
Simulation time 108270012 ps
CPU time 2.6 seconds
Started Jul 16 08:03:17 PM PDT 24
Finished Jul 16 08:03:23 PM PDT 24
Peak memory 207372 kb
Host smart-bf26734f-24ee-4f93-be4e-4946e6843bb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540235043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.540235043
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1294538299
Short name T1104
Test name
Test status
Simulation time 24066282 ps
CPU time 0.71 seconds
Started Jul 16 08:03:12 PM PDT 24
Finished Jul 16 08:03:14 PM PDT 24
Peak memory 204300 kb
Host smart-2bea9e45-ac83-4eca-830c-37af47ecd6cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294538299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
294538299
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.724258883
Short name T1095
Test name
Test status
Simulation time 115744989 ps
CPU time 1.95 seconds
Started Jul 16 08:03:14 PM PDT 24
Finished Jul 16 08:03:19 PM PDT 24
Peak memory 215544 kb
Host smart-a3db6511-001a-483a-8014-15a126501f4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724258883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.724258883
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1555082186
Short name T128
Test name
Test status
Simulation time 3805435023 ps
CPU time 8.35 seconds
Started Jul 16 08:03:14 PM PDT 24
Finished Jul 16 08:03:26 PM PDT 24
Peak memory 215576 kb
Host smart-6b857e7e-cb67-49ba-ab9f-81ab02e49957
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555082186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1555082186
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3657747517
Short name T1073
Test name
Test status
Simulation time 266933246 ps
CPU time 3.83 seconds
Started Jul 16 08:03:16 PM PDT 24
Finished Jul 16 08:03:23 PM PDT 24
Peak memory 217168 kb
Host smart-65d6a7c5-562c-4444-b02e-1c05c991be9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657747517 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3657747517
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1545054835
Short name T1130
Test name
Test status
Simulation time 103320231 ps
CPU time 2.52 seconds
Started Jul 16 08:03:15 PM PDT 24
Finished Jul 16 08:03:21 PM PDT 24
Peak memory 207292 kb
Host smart-f804dd1f-a146-4a2c-ac37-b264b6f859d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545054835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
545054835
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3538010385
Short name T1125
Test name
Test status
Simulation time 19244241 ps
CPU time 0.77 seconds
Started Jul 16 08:03:12 PM PDT 24
Finished Jul 16 08:03:14 PM PDT 24
Peak memory 204000 kb
Host smart-08576894-5c4c-4da3-a941-853b64c1232d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538010385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
538010385
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1337162354
Short name T1043
Test name
Test status
Simulation time 223696566 ps
CPU time 1.81 seconds
Started Jul 16 08:03:13 PM PDT 24
Finished Jul 16 08:03:18 PM PDT 24
Peak memory 215552 kb
Host smart-868939d6-efae-4867-a171-2484dbca41fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337162354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1337162354
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.40858454
Short name T123
Test name
Test status
Simulation time 291718320 ps
CPU time 2.58 seconds
Started Jul 16 08:03:16 PM PDT 24
Finished Jul 16 08:03:22 PM PDT 24
Peak memory 215660 kb
Host smart-74cd92bf-aa25-4936-b64c-7a95e10799b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40858454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.40858454
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.539306
Short name T1061
Test name
Test status
Simulation time 1084940822 ps
CPU time 17.93 seconds
Started Jul 16 08:03:16 PM PDT 24
Finished Jul 16 08:03:37 PM PDT 24
Peak memory 215740 kb
Host smart-08300f9c-a611-48ff-9c07-718f578a015a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_
intg_err.539306
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3469766975
Short name T126
Test name
Test status
Simulation time 120950283 ps
CPU time 3.26 seconds
Started Jul 16 08:03:17 PM PDT 24
Finished Jul 16 08:03:23 PM PDT 24
Peak memory 217120 kb
Host smart-6fe73c8e-fcd3-4419-87ab-f224e674111b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469766975 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3469766975
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2515202592
Short name T132
Test name
Test status
Simulation time 183454558 ps
CPU time 2.69 seconds
Started Jul 16 08:03:12 PM PDT 24
Finished Jul 16 08:03:16 PM PDT 24
Peak memory 207064 kb
Host smart-c85f8e8a-eda8-402e-a2a3-165de24ce4a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515202592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
515202592
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.4081134514
Short name T1068
Test name
Test status
Simulation time 18874177 ps
CPU time 0.69 seconds
Started Jul 16 08:03:14 PM PDT 24
Finished Jul 16 08:03:18 PM PDT 24
Peak memory 203932 kb
Host smart-de1fe38d-6952-4a86-91ad-55150223fa8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081134514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.4
081134514
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2995084862
Short name T1110
Test name
Test status
Simulation time 63118977 ps
CPU time 1.84 seconds
Started Jul 16 08:03:19 PM PDT 24
Finished Jul 16 08:03:23 PM PDT 24
Peak memory 215416 kb
Host smart-d2b7bb72-506f-43d6-ac86-40898d78ea46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995084862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2995084862
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1090333782
Short name T1091
Test name
Test status
Simulation time 65051650 ps
CPU time 2 seconds
Started Jul 16 08:03:14 PM PDT 24
Finished Jul 16 08:03:20 PM PDT 24
Peak memory 215668 kb
Host smart-02bde715-8779-4647-ae5a-2f422ba2eff2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090333782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
090333782
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2921283560
Short name T173
Test name
Test status
Simulation time 1200106806 ps
CPU time 7.19 seconds
Started Jul 16 08:03:15 PM PDT 24
Finished Jul 16 08:03:26 PM PDT 24
Peak memory 215520 kb
Host smart-4f33b45f-ea6b-4d16-bb6b-bed33373e0b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921283560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2921283560
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2581310555
Short name T111
Test name
Test status
Simulation time 88651297 ps
CPU time 2.55 seconds
Started Jul 16 08:03:16 PM PDT 24
Finished Jul 16 08:03:22 PM PDT 24
Peak memory 216544 kb
Host smart-c1f3c0d5-90c9-4ba5-92f7-820969f587d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581310555 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2581310555
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2556742925
Short name T1111
Test name
Test status
Simulation time 27699230 ps
CPU time 1.89 seconds
Started Jul 16 08:03:24 PM PDT 24
Finished Jul 16 08:03:27 PM PDT 24
Peak memory 215488 kb
Host smart-14d13f1b-c255-4dc4-ae66-2de9ed2f072e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556742925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
556742925
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1722638613
Short name T1060
Test name
Test status
Simulation time 19644793 ps
CPU time 0.78 seconds
Started Jul 16 08:03:15 PM PDT 24
Finished Jul 16 08:03:20 PM PDT 24
Peak memory 203932 kb
Host smart-5fa2e655-4621-4381-8d2b-711803ca5f33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722638613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
722638613
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3586705470
Short name T1055
Test name
Test status
Simulation time 46560047 ps
CPU time 2.79 seconds
Started Jul 16 08:03:19 PM PDT 24
Finished Jul 16 08:03:24 PM PDT 24
Peak memory 215464 kb
Host smart-f3e93455-bee7-480c-975e-6222758d68c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586705470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3586705470
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1042630119
Short name T1082
Test name
Test status
Simulation time 85977678 ps
CPU time 2.17 seconds
Started Jul 16 08:03:16 PM PDT 24
Finished Jul 16 08:03:22 PM PDT 24
Peak memory 215744 kb
Host smart-88b1b2fd-8ea8-44a5-9de5-ae521960169e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042630119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
042630119
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.641082154
Short name T172
Test name
Test status
Simulation time 714138807 ps
CPU time 8.03 seconds
Started Jul 16 08:03:13 PM PDT 24
Finished Jul 16 08:03:24 PM PDT 24
Peak memory 215448 kb
Host smart-f85e7d5d-da77-40ff-a653-6e13fb70ef62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641082154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.641082154
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2084223627
Short name T782
Test name
Test status
Simulation time 13904513 ps
CPU time 0.76 seconds
Started Jul 16 07:47:29 PM PDT 24
Finished Jul 16 07:47:32 PM PDT 24
Peak memory 206344 kb
Host smart-7054d721-0d5e-4001-91a0-50f3cc71f773
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084223627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
084223627
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.651780434
Short name T130
Test name
Test status
Simulation time 689609339 ps
CPU time 3.82 seconds
Started Jul 16 07:47:29 PM PDT 24
Finished Jul 16 07:47:35 PM PDT 24
Peak memory 225504 kb
Host smart-8c63fa90-a6b6-4d24-8da1-60e6731624ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651780434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.651780434
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2211879323
Short name T687
Test name
Test status
Simulation time 45206663 ps
CPU time 0.79 seconds
Started Jul 16 07:47:18 PM PDT 24
Finished Jul 16 07:47:22 PM PDT 24
Peak memory 206504 kb
Host smart-045bdb46-23d4-4080-a1e8-9e147e76839e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211879323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2211879323
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4130000518
Short name T821
Test name
Test status
Simulation time 2532968320 ps
CPU time 18.06 seconds
Started Jul 16 07:47:30 PM PDT 24
Finished Jul 16 07:47:50 PM PDT 24
Peak memory 225664 kb
Host smart-927fc674-46c5-4798-84d0-099b9d01d809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130000518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4130000518
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.502289803
Short name T182
Test name
Test status
Simulation time 37565411501 ps
CPU time 153.08 seconds
Started Jul 16 07:47:32 PM PDT 24
Finished Jul 16 07:50:07 PM PDT 24
Peak memory 250784 kb
Host smart-c7284668-24ce-4bc3-bdd3-2f006250ef1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502289803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.502289803
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3325661171
Short name T505
Test name
Test status
Simulation time 10368848154 ps
CPU time 15.71 seconds
Started Jul 16 07:47:30 PM PDT 24
Finished Jul 16 07:47:48 PM PDT 24
Peak memory 218744 kb
Host smart-95f7314d-2d32-4a2f-8a8f-aeebd0671fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325661171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3325661171
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.127969183
Short name T540
Test name
Test status
Simulation time 6651722273 ps
CPU time 84.44 seconds
Started Jul 16 07:47:27 PM PDT 24
Finished Jul 16 07:48:52 PM PDT 24
Peak memory 235688 kb
Host smart-619554e3-587f-4dba-af5f-6b8fc7a9ffd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127969183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.127969183
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1482026336
Short name T961
Test name
Test status
Simulation time 4752528754 ps
CPU time 48.57 seconds
Started Jul 16 07:47:27 PM PDT 24
Finished Jul 16 07:48:17 PM PDT 24
Peak memory 256884 kb
Host smart-9a7354eb-76af-4b46-8114-473ebb57cb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482026336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1482026336
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2145369357
Short name T306
Test name
Test status
Simulation time 101857171 ps
CPU time 3.96 seconds
Started Jul 16 07:47:29 PM PDT 24
Finished Jul 16 07:47:35 PM PDT 24
Peak memory 233708 kb
Host smart-78b3c62a-b9e3-48bc-b611-2ceff77e107a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145369357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2145369357
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1975318747
Short name T228
Test name
Test status
Simulation time 9516284919 ps
CPU time 57.16 seconds
Started Jul 16 07:47:26 PM PDT 24
Finished Jul 16 07:48:25 PM PDT 24
Peak memory 233816 kb
Host smart-cd5ce123-a480-456e-b7b4-ffa7ffdea273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975318747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1975318747
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.247539353
Short name T639
Test name
Test status
Simulation time 521257726 ps
CPU time 4.01 seconds
Started Jul 16 07:47:27 PM PDT 24
Finished Jul 16 07:47:33 PM PDT 24
Peak memory 225528 kb
Host smart-460b3a88-9107-444a-9328-699d8a96b6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247539353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
247539353
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3826902058
Short name T16
Test name
Test status
Simulation time 2365634533 ps
CPU time 9.81 seconds
Started Jul 16 07:47:29 PM PDT 24
Finished Jul 16 07:47:41 PM PDT 24
Peak memory 225708 kb
Host smart-5914312a-1440-4294-80ff-1d1241341ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826902058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3826902058
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2782787457
Short name T561
Test name
Test status
Simulation time 4283459979 ps
CPU time 11.28 seconds
Started Jul 16 07:47:32 PM PDT 24
Finished Jul 16 07:47:45 PM PDT 24
Peak memory 220392 kb
Host smart-626f1022-a713-45dc-9208-ceeef4d4a307
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2782787457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2782787457
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1960527213
Short name T160
Test name
Test status
Simulation time 20432208124 ps
CPU time 188.86 seconds
Started Jul 16 07:47:26 PM PDT 24
Finished Jul 16 07:50:35 PM PDT 24
Peak memory 258268 kb
Host smart-119494b4-d18f-49ec-922e-0eb4d95f77ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960527213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1960527213
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2253926785
Short name T345
Test name
Test status
Simulation time 351900097 ps
CPU time 2.11 seconds
Started Jul 16 07:47:19 PM PDT 24
Finished Jul 16 07:47:25 PM PDT 24
Peak memory 217488 kb
Host smart-43ff67ec-09de-474a-a667-f1edfaedd4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253926785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2253926785
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1121850426
Short name T148
Test name
Test status
Simulation time 63299959 ps
CPU time 0.73 seconds
Started Jul 16 07:47:19 PM PDT 24
Finished Jul 16 07:47:24 PM PDT 24
Peak memory 206584 kb
Host smart-343b139d-d686-4406-a2c1-06480137b7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121850426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1121850426
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2084256577
Short name T426
Test name
Test status
Simulation time 12319836 ps
CPU time 0.71 seconds
Started Jul 16 07:47:27 PM PDT 24
Finished Jul 16 07:47:29 PM PDT 24
Peak memory 206528 kb
Host smart-0fd85561-009f-44d7-b03c-1655650ddf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084256577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2084256577
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2998483254
Short name T703
Test name
Test status
Simulation time 27289496 ps
CPU time 0.84 seconds
Started Jul 16 07:47:29 PM PDT 24
Finished Jul 16 07:47:32 PM PDT 24
Peak memory 207008 kb
Host smart-25b55851-f5d6-47dd-afbd-9988a9c99202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998483254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2998483254
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3517889206
Short name T943
Test name
Test status
Simulation time 46762730933 ps
CPU time 24.87 seconds
Started Jul 16 07:47:27 PM PDT 24
Finished Jul 16 07:47:53 PM PDT 24
Peak memory 250284 kb
Host smart-4973dcd7-6845-4645-ae08-2b0ea5c9c59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517889206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3517889206
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2114332320
Short name T993
Test name
Test status
Simulation time 45291594 ps
CPU time 0.73 seconds
Started Jul 16 07:47:43 PM PDT 24
Finished Jul 16 07:47:46 PM PDT 24
Peak memory 206688 kb
Host smart-59e12f09-b7dd-4519-9f81-214bb53ccaaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114332320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
114332320
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3221809430
Short name T958
Test name
Test status
Simulation time 45581719 ps
CPU time 0.77 seconds
Started Jul 16 07:47:28 PM PDT 24
Finished Jul 16 07:47:32 PM PDT 24
Peak memory 207852 kb
Host smart-56b3f6c6-927e-4fb6-baca-8c62f16c4239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221809430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3221809430
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2531956471
Short name T892
Test name
Test status
Simulation time 3700451750 ps
CPU time 31.6 seconds
Started Jul 16 07:47:44 PM PDT 24
Finished Jul 16 07:48:18 PM PDT 24
Peak memory 238380 kb
Host smart-3619b19f-2748-445a-89e2-e4017c9bc3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531956471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2531956471
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.218623335
Short name T246
Test name
Test status
Simulation time 21662128391 ps
CPU time 59.97 seconds
Started Jul 16 07:47:44 PM PDT 24
Finished Jul 16 07:48:45 PM PDT 24
Peak memory 235152 kb
Host smart-9effb554-7ad6-4b90-9166-7fce6b560404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218623335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.218623335
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3757392276
Short name T816
Test name
Test status
Simulation time 44397359852 ps
CPU time 85.71 seconds
Started Jul 16 07:47:42 PM PDT 24
Finished Jul 16 07:49:08 PM PDT 24
Peak memory 250400 kb
Host smart-12e92ba4-57b2-48bc-b8b4-168bbefe3b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757392276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3757392276
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3966284480
Short name T338
Test name
Test status
Simulation time 703835270 ps
CPU time 9.27 seconds
Started Jul 16 07:47:28 PM PDT 24
Finished Jul 16 07:47:40 PM PDT 24
Peak memory 241912 kb
Host smart-7251a24f-6f53-4532-b8a1-649593ea36ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966284480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3966284480
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2897220450
Short name T619
Test name
Test status
Simulation time 49871306352 ps
CPU time 92.02 seconds
Started Jul 16 07:47:46 PM PDT 24
Finished Jul 16 07:49:19 PM PDT 24
Peak memory 242108 kb
Host smart-7b2342f2-2f05-4d00-ab72-335cf17bbb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897220450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2897220450
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.4123951636
Short name T760
Test name
Test status
Simulation time 194705546 ps
CPU time 2.33 seconds
Started Jul 16 07:47:31 PM PDT 24
Finished Jul 16 07:47:35 PM PDT 24
Peak memory 224760 kb
Host smart-a22afe9d-5f70-4fa6-ae0a-956d17b78352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123951636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.4123951636
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2751118459
Short name T227
Test name
Test status
Simulation time 14286089154 ps
CPU time 43.99 seconds
Started Jul 16 07:47:28 PM PDT 24
Finished Jul 16 07:48:14 PM PDT 24
Peak memory 235880 kb
Host smart-c5b367ff-a95b-4ec8-a1b1-ce74a7770d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751118459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2751118459
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2799597635
Short name T874
Test name
Test status
Simulation time 31829554 ps
CPU time 1.04 seconds
Started Jul 16 07:47:30 PM PDT 24
Finished Jul 16 07:47:33 PM PDT 24
Peak memory 218948 kb
Host smart-58669941-89a6-450e-92a0-b9c54bf27136
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799597635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2799597635
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3263141005
Short name T479
Test name
Test status
Simulation time 23183238289 ps
CPU time 8.44 seconds
Started Jul 16 07:47:27 PM PDT 24
Finished Jul 16 07:47:37 PM PDT 24
Peak memory 225704 kb
Host smart-3dc7b8e8-dd8d-4847-8760-b87619b51275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263141005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3263141005
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1064562601
Short name T257
Test name
Test status
Simulation time 2592049855 ps
CPU time 11.58 seconds
Started Jul 16 07:47:27 PM PDT 24
Finished Jul 16 07:47:39 PM PDT 24
Peak memory 233888 kb
Host smart-ea59bd46-5b0a-41ed-8ec1-ae9c452a59c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064562601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1064562601
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.162033489
Short name T559
Test name
Test status
Simulation time 3424891997 ps
CPU time 13.83 seconds
Started Jul 16 07:47:42 PM PDT 24
Finished Jul 16 07:47:57 PM PDT 24
Peak memory 220424 kb
Host smart-4a490237-532c-4fa7-ab8a-c555d2b8126c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=162033489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.162033489
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2155819590
Short name T36
Test name
Test status
Simulation time 350386780 ps
CPU time 1.21 seconds
Started Jul 16 07:47:46 PM PDT 24
Finished Jul 16 07:47:49 PM PDT 24
Peak memory 236740 kb
Host smart-fc8d653a-036b-4aa8-8921-c93c9dedafb4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155819590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2155819590
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2935296712
Short name T606
Test name
Test status
Simulation time 4430992227 ps
CPU time 26.39 seconds
Started Jul 16 07:47:45 PM PDT 24
Finished Jul 16 07:48:13 PM PDT 24
Peak memory 218744 kb
Host smart-df8bdf73-91ec-484f-91a3-69a52b804a19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935296712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2935296712
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.4036308098
Short name T477
Test name
Test status
Simulation time 419393513 ps
CPU time 3.79 seconds
Started Jul 16 07:47:28 PM PDT 24
Finished Jul 16 07:47:35 PM PDT 24
Peak memory 217412 kb
Host smart-4fba6edb-2a1c-4397-aa85-a0009426b3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036308098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4036308098
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.320098021
Short name T532
Test name
Test status
Simulation time 1102607955 ps
CPU time 7.64 seconds
Started Jul 16 07:47:28 PM PDT 24
Finished Jul 16 07:47:38 PM PDT 24
Peak memory 217340 kb
Host smart-e899a7b9-3142-4d2f-8c70-ac634572ed06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320098021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.320098021
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2091565068
Short name T984
Test name
Test status
Simulation time 183223360 ps
CPU time 2.82 seconds
Started Jul 16 07:47:30 PM PDT 24
Finished Jul 16 07:47:35 PM PDT 24
Peak memory 217344 kb
Host smart-7a80d478-e8f2-443c-995f-d2d5cd712584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091565068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2091565068
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.4041714852
Short name T720
Test name
Test status
Simulation time 25575735 ps
CPU time 0.76 seconds
Started Jul 16 07:47:31 PM PDT 24
Finished Jul 16 07:47:34 PM PDT 24
Peak memory 206940 kb
Host smart-7b747a0d-9a95-40c1-b62d-ce8dbdba4a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041714852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.4041714852
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1386446168
Short name T514
Test name
Test status
Simulation time 716287233 ps
CPU time 6.93 seconds
Started Jul 16 07:47:30 PM PDT 24
Finished Jul 16 07:47:39 PM PDT 24
Peak memory 233684 kb
Host smart-dfdd1dbe-fa9d-4b01-b61f-4cec6df94d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386446168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1386446168
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1097780058
Short name T775
Test name
Test status
Simulation time 15114434 ps
CPU time 0.75 seconds
Started Jul 16 07:48:31 PM PDT 24
Finished Jul 16 07:48:34 PM PDT 24
Peak memory 206400 kb
Host smart-65708ffb-d716-4e74-946e-3e2cf2d59cd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097780058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1097780058
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1923852469
Short name T884
Test name
Test status
Simulation time 739230522 ps
CPU time 5.37 seconds
Started Jul 16 07:48:15 PM PDT 24
Finished Jul 16 07:48:23 PM PDT 24
Peak memory 225512 kb
Host smart-74127632-46b5-4129-8f12-24cf208e11af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923852469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1923852469
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1125818432
Short name T526
Test name
Test status
Simulation time 139505858 ps
CPU time 0.8 seconds
Started Jul 16 07:48:14 PM PDT 24
Finished Jul 16 07:48:18 PM PDT 24
Peak memory 207812 kb
Host smart-b23b314f-0c88-4aa8-9265-ca91f1276482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125818432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1125818432
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2683404232
Short name T320
Test name
Test status
Simulation time 15634117368 ps
CPU time 153.98 seconds
Started Jul 16 07:48:30 PM PDT 24
Finished Jul 16 07:51:06 PM PDT 24
Peak memory 257588 kb
Host smart-b1b56a14-2e0f-41ff-969e-8853602d7461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683404232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2683404232
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.804658640
Short name T282
Test name
Test status
Simulation time 26331976363 ps
CPU time 124.49 seconds
Started Jul 16 07:48:29 PM PDT 24
Finished Jul 16 07:50:35 PM PDT 24
Peak memory 268828 kb
Host smart-725cc273-fb5c-4c2f-8578-763427dbaa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804658640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.804658640
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1820565203
Short name T159
Test name
Test status
Simulation time 3047058765 ps
CPU time 66.09 seconds
Started Jul 16 07:48:29 PM PDT 24
Finished Jul 16 07:49:37 PM PDT 24
Peak memory 254024 kb
Host smart-741c375b-e9a6-44c7-94bd-9295e34949aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820565203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1820565203
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3481921587
Short name T180
Test name
Test status
Simulation time 813766422 ps
CPU time 13.65 seconds
Started Jul 16 07:48:29 PM PDT 24
Finished Jul 16 07:48:45 PM PDT 24
Peak memory 234932 kb
Host smart-68c7ff6c-5840-4cb6-b05c-3ae984748969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481921587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3481921587
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.373552044
Short name T49
Test name
Test status
Simulation time 20038341913 ps
CPU time 59.89 seconds
Started Jul 16 07:48:29 PM PDT 24
Finished Jul 16 07:49:31 PM PDT 24
Peak memory 251336 kb
Host smart-1d060386-c049-4623-9d8c-f777af6b5711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373552044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.373552044
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.436779579
Short name T941
Test name
Test status
Simulation time 459624026 ps
CPU time 3.38 seconds
Started Jul 16 07:48:13 PM PDT 24
Finished Jul 16 07:48:20 PM PDT 24
Peak memory 233700 kb
Host smart-4ded27d7-d644-4eb0-8242-fc248695f7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436779579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.436779579
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4175349478
Short name T693
Test name
Test status
Simulation time 61906621 ps
CPU time 2.21 seconds
Started Jul 16 07:48:14 PM PDT 24
Finished Jul 16 07:48:19 PM PDT 24
Peak memory 233516 kb
Host smart-c67abb15-bd11-469e-8687-1f9fe31c18c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175349478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4175349478
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2093454250
Short name T854
Test name
Test status
Simulation time 54249977 ps
CPU time 1.05 seconds
Started Jul 16 07:48:12 PM PDT 24
Finished Jul 16 07:48:16 PM PDT 24
Peak memory 217792 kb
Host smart-00b7a9ea-35d5-40e0-9fb7-5d196af6a2db
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093454250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2093454250
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2517902574
Short name T925
Test name
Test status
Simulation time 176022728 ps
CPU time 3.37 seconds
Started Jul 16 07:48:19 PM PDT 24
Finished Jul 16 07:48:23 PM PDT 24
Peak memory 233808 kb
Host smart-2b6003c5-34d2-4bdf-b44b-13eca7d0226b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517902574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2517902574
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3929210711
Short name T862
Test name
Test status
Simulation time 15205279162 ps
CPU time 14.64 seconds
Started Jul 16 07:48:13 PM PDT 24
Finished Jul 16 07:48:31 PM PDT 24
Peak memory 250848 kb
Host smart-0cbf1f08-f72d-40e2-a0e6-e7133d0eb4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929210711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3929210711
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2848007384
Short name T436
Test name
Test status
Simulation time 5304330245 ps
CPU time 11.63 seconds
Started Jul 16 07:48:29 PM PDT 24
Finished Jul 16 07:48:42 PM PDT 24
Peak memory 220172 kb
Host smart-48c16d0a-d35a-428a-bd3b-faf875098923
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2848007384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2848007384
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.4216411683
Short name T176
Test name
Test status
Simulation time 82981120403 ps
CPU time 354.32 seconds
Started Jul 16 07:48:29 PM PDT 24
Finished Jul 16 07:54:25 PM PDT 24
Peak memory 263216 kb
Host smart-525e89c7-4932-42e6-afb1-ea60347bc406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216411683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.4216411683
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2543777515
Short name T504
Test name
Test status
Simulation time 8147072402 ps
CPU time 25.45 seconds
Started Jul 16 07:48:14 PM PDT 24
Finished Jul 16 07:48:42 PM PDT 24
Peak memory 217440 kb
Host smart-be1f13d1-5560-4213-887d-c8efa65796c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543777515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2543777515
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2812894554
Short name T1009
Test name
Test status
Simulation time 3754913298 ps
CPU time 6.2 seconds
Started Jul 16 07:48:13 PM PDT 24
Finished Jul 16 07:48:22 PM PDT 24
Peak memory 217588 kb
Host smart-056568b6-4bf7-4130-bf3c-1bc040749751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812894554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2812894554
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2682985777
Short name T406
Test name
Test status
Simulation time 152281363 ps
CPU time 5.69 seconds
Started Jul 16 07:48:19 PM PDT 24
Finished Jul 16 07:48:26 PM PDT 24
Peak memory 217436 kb
Host smart-9f5b1078-f95d-4eeb-b900-09df611c24c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682985777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2682985777
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2524985330
Short name T38
Test name
Test status
Simulation time 64168334 ps
CPU time 0.74 seconds
Started Jul 16 07:48:19 PM PDT 24
Finished Jul 16 07:48:21 PM PDT 24
Peak memory 207016 kb
Host smart-feee5f9a-7941-4965-8880-45a9238d80b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524985330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2524985330
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.4050087161
Short name T700
Test name
Test status
Simulation time 248501987 ps
CPU time 2.89 seconds
Started Jul 16 07:48:16 PM PDT 24
Finished Jul 16 07:48:21 PM PDT 24
Peak memory 233464 kb
Host smart-476a76df-cf33-44d1-a971-121cf2c76710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050087161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.4050087161
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.648716240
Short name T766
Test name
Test status
Simulation time 20672323 ps
CPU time 0.72 seconds
Started Jul 16 07:48:31 PM PDT 24
Finished Jul 16 07:48:34 PM PDT 24
Peak memory 205776 kb
Host smart-5c7e9f96-f86c-4cf0-b4a7-63fa066a8696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648716240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.648716240
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.4040336546
Short name T683
Test name
Test status
Simulation time 205245295 ps
CPU time 2.78 seconds
Started Jul 16 07:48:32 PM PDT 24
Finished Jul 16 07:48:36 PM PDT 24
Peak memory 233728 kb
Host smart-aea8d614-b83b-42de-b528-919dbab0b046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040336546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4040336546
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.711279202
Short name T391
Test name
Test status
Simulation time 37127544 ps
CPU time 0.83 seconds
Started Jul 16 07:48:31 PM PDT 24
Finished Jul 16 07:48:34 PM PDT 24
Peak memory 207536 kb
Host smart-338e1f60-868c-4119-bbff-7425c3a470af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711279202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.711279202
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.4010370875
Short name T970
Test name
Test status
Simulation time 2913148328 ps
CPU time 22.17 seconds
Started Jul 16 07:48:32 PM PDT 24
Finished Jul 16 07:48:56 PM PDT 24
Peak memory 225640 kb
Host smart-3d1e4875-f3b3-460b-bca2-4dd094d585b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010370875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.4010370875
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3907251592
Short name T986
Test name
Test status
Simulation time 37241515211 ps
CPU time 139.52 seconds
Started Jul 16 07:48:28 PM PDT 24
Finished Jul 16 07:50:49 PM PDT 24
Peak memory 256816 kb
Host smart-e7397c54-39e5-4ac1-bdff-039a98031be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907251592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3907251592
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.977755589
Short name T557
Test name
Test status
Simulation time 32081182963 ps
CPU time 137.88 seconds
Started Jul 16 07:48:20 PM PDT 24
Finished Jul 16 07:50:39 PM PDT 24
Peak memory 258108 kb
Host smart-4f81218c-809a-4a48-9a4b-00b4be64d49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977755589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.977755589
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4038977105
Short name T865
Test name
Test status
Simulation time 1976449738 ps
CPU time 10.11 seconds
Started Jul 16 07:48:29 PM PDT 24
Finished Jul 16 07:48:41 PM PDT 24
Peak memory 235644 kb
Host smart-6ebab413-c60d-4252-8476-cf0912cc736d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038977105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4038977105
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3068732234
Short name T838
Test name
Test status
Simulation time 8620682610 ps
CPU time 45.38 seconds
Started Jul 16 07:48:30 PM PDT 24
Finished Jul 16 07:49:18 PM PDT 24
Peak memory 251668 kb
Host smart-e7ca1437-fdca-46df-91cb-d420d31fe61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068732234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3068732234
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1104479787
Short name T904
Test name
Test status
Simulation time 135672745 ps
CPU time 4.65 seconds
Started Jul 16 07:48:32 PM PDT 24
Finished Jul 16 07:48:38 PM PDT 24
Peak memory 233716 kb
Host smart-6f33ef34-2f68-47da-805d-0fa02267b6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104479787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1104479787
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2957565750
Short name T727
Test name
Test status
Simulation time 10256815261 ps
CPU time 44.92 seconds
Started Jul 16 07:48:27 PM PDT 24
Finished Jul 16 07:49:13 PM PDT 24
Peak memory 241688 kb
Host smart-f08add92-a95e-4d84-a339-3769016b0995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957565750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2957565750
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2079450116
Short name T634
Test name
Test status
Simulation time 140003312 ps
CPU time 1.04 seconds
Started Jul 16 07:48:28 PM PDT 24
Finished Jul 16 07:48:31 PM PDT 24
Peak memory 218864 kb
Host smart-d6315e5d-4410-4c71-8659-a7708b4db3d9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079450116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2079450116
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3217704762
Short name T891
Test name
Test status
Simulation time 2505169443 ps
CPU time 7.59 seconds
Started Jul 16 07:48:28 PM PDT 24
Finished Jul 16 07:48:37 PM PDT 24
Peak memory 233900 kb
Host smart-9e792e7f-d6ab-44fe-959f-6107fbcc3ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217704762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3217704762
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3442813854
Short name T644
Test name
Test status
Simulation time 599627037 ps
CPU time 3.74 seconds
Started Jul 16 07:48:28 PM PDT 24
Finished Jul 16 07:48:32 PM PDT 24
Peak memory 225520 kb
Host smart-b1fc7cba-828c-4d2f-9433-b9e42801f80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442813854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3442813854
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1626477194
Short name T846
Test name
Test status
Simulation time 4153428765 ps
CPU time 10.66 seconds
Started Jul 16 07:48:29 PM PDT 24
Finished Jul 16 07:48:41 PM PDT 24
Peak memory 222784 kb
Host smart-bcf0af9b-dcb4-4c90-83fc-0c0ad0710077
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1626477194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1626477194
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.135175339
Short name T19
Test name
Test status
Simulation time 37572661 ps
CPU time 0.93 seconds
Started Jul 16 07:48:28 PM PDT 24
Finished Jul 16 07:48:30 PM PDT 24
Peak memory 207828 kb
Host smart-d61de860-b4ba-4384-ae60-dad95e7f6e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135175339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.135175339
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.583326335
Short name T915
Test name
Test status
Simulation time 28190226 ps
CPU time 0.76 seconds
Started Jul 16 07:48:28 PM PDT 24
Finished Jul 16 07:48:31 PM PDT 24
Peak memory 206652 kb
Host smart-a72af9c3-b651-4b53-b553-b33a8a77e0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583326335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.583326335
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.299713347
Short name T762
Test name
Test status
Simulation time 1952935042 ps
CPU time 3.47 seconds
Started Jul 16 07:48:28 PM PDT 24
Finished Jul 16 07:48:34 PM PDT 24
Peak memory 217276 kb
Host smart-0f853ac6-347b-4328-94c1-c28762b093bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299713347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.299713347
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3305848534
Short name T794
Test name
Test status
Simulation time 29665126 ps
CPU time 0.8 seconds
Started Jul 16 07:48:28 PM PDT 24
Finished Jul 16 07:48:30 PM PDT 24
Peak memory 207008 kb
Host smart-297cb07b-95b4-45d1-b9e0-75de2350f47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305848534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3305848534
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3538321003
Short name T964
Test name
Test status
Simulation time 65453659 ps
CPU time 0.82 seconds
Started Jul 16 07:48:30 PM PDT 24
Finished Jul 16 07:48:33 PM PDT 24
Peak memory 206996 kb
Host smart-5393611a-fd23-4a43-b06c-7f0487695544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538321003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3538321003
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.4101571440
Short name T487
Test name
Test status
Simulation time 257674057 ps
CPU time 2.54 seconds
Started Jul 16 07:48:30 PM PDT 24
Finished Jul 16 07:48:34 PM PDT 24
Peak memory 233764 kb
Host smart-ad047646-8717-4ec5-835f-23a8274ad32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101571440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4101571440
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1388697644
Short name T359
Test name
Test status
Simulation time 40579918 ps
CPU time 0.72 seconds
Started Jul 16 07:48:46 PM PDT 24
Finished Jul 16 07:48:50 PM PDT 24
Peak memory 205820 kb
Host smart-e926c34c-668d-4e77-98a1-316583b11bef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388697644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1388697644
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.947511072
Short name T798
Test name
Test status
Simulation time 612749616 ps
CPU time 4.72 seconds
Started Jul 16 07:48:45 PM PDT 24
Finished Jul 16 07:48:53 PM PDT 24
Peak memory 233728 kb
Host smart-25afc96e-a223-4c99-a551-46bd2798ae21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947511072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.947511072
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1999013730
Short name T553
Test name
Test status
Simulation time 64930923 ps
CPU time 0.82 seconds
Started Jul 16 07:48:29 PM PDT 24
Finished Jul 16 07:48:32 PM PDT 24
Peak memory 207472 kb
Host smart-745d94b4-2092-451f-a11c-c677c0c6bb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999013730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1999013730
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.609698791
Short name T554
Test name
Test status
Simulation time 11810764544 ps
CPU time 79.07 seconds
Started Jul 16 07:48:46 PM PDT 24
Finished Jul 16 07:50:08 PM PDT 24
Peak memory 251828 kb
Host smart-659861ea-3140-4cb7-b36b-c95164501bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609698791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.609698791
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.998648452
Short name T66
Test name
Test status
Simulation time 5099254033 ps
CPU time 39.26 seconds
Started Jul 16 07:48:46 PM PDT 24
Finished Jul 16 07:49:28 PM PDT 24
Peak memory 250392 kb
Host smart-d8e8d205-7335-4c85-8127-f22d0b0ff5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998648452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.998648452
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.133151402
Short name T342
Test name
Test status
Simulation time 46036098708 ps
CPU time 77.37 seconds
Started Jul 16 07:48:43 PM PDT 24
Finished Jul 16 07:50:02 PM PDT 24
Peak memory 250440 kb
Host smart-66a8f757-afab-4331-a4f8-606be0552d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133151402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.133151402
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3100068937
Short name T484
Test name
Test status
Simulation time 107541357 ps
CPU time 5.8 seconds
Started Jul 16 07:48:44 PM PDT 24
Finished Jul 16 07:48:52 PM PDT 24
Peak memory 234952 kb
Host smart-71c28044-e55a-4cda-aa3d-6b165bc2e4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100068937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3100068937
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2733201193
Short name T751
Test name
Test status
Simulation time 2122968514 ps
CPU time 25.61 seconds
Started Jul 16 07:48:43 PM PDT 24
Finished Jul 16 07:49:10 PM PDT 24
Peak memory 241064 kb
Host smart-e6db9b47-a0b0-48e4-afde-9af480b15f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733201193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2733201193
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1077212238
Short name T638
Test name
Test status
Simulation time 34084880 ps
CPU time 2.54 seconds
Started Jul 16 07:48:31 PM PDT 24
Finished Jul 16 07:48:35 PM PDT 24
Peak memory 233752 kb
Host smart-7b292dd1-21f1-48c0-a752-09a62d8f72ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077212238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1077212238
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2727350788
Short name T206
Test name
Test status
Simulation time 20549926558 ps
CPU time 80.36 seconds
Started Jul 16 07:48:48 PM PDT 24
Finished Jul 16 07:50:11 PM PDT 24
Peak memory 239344 kb
Host smart-5ded9f43-8946-4447-a099-8c28340b4276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727350788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2727350788
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3666673904
Short name T801
Test name
Test status
Simulation time 14151283 ps
CPU time 1.05 seconds
Started Jul 16 07:48:30 PM PDT 24
Finished Jul 16 07:48:33 PM PDT 24
Peak memory 217668 kb
Host smart-95445ae3-1cc0-4c52-9895-084035260f15
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666673904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3666673904
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1930358878
Short name T470
Test name
Test status
Simulation time 222866599 ps
CPU time 3.83 seconds
Started Jul 16 07:48:30 PM PDT 24
Finished Jul 16 07:48:36 PM PDT 24
Peak memory 225476 kb
Host smart-b2ed0b18-a111-4645-93c6-5332c7151e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930358878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1930358878
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2702192658
Short name T223
Test name
Test status
Simulation time 430277436 ps
CPU time 3.83 seconds
Started Jul 16 07:48:30 PM PDT 24
Finished Jul 16 07:48:36 PM PDT 24
Peak memory 233780 kb
Host smart-0fbc0abc-8943-49e8-9a55-eba16e8a7fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702192658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2702192658
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3280957374
Short name T183
Test name
Test status
Simulation time 965951540 ps
CPU time 12.72 seconds
Started Jul 16 07:48:43 PM PDT 24
Finished Jul 16 07:48:57 PM PDT 24
Peak memory 221556 kb
Host smart-796de42a-14f6-4750-baae-a1b66b31b797
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3280957374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3280957374
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.744398123
Short name T175
Test name
Test status
Simulation time 47373250 ps
CPU time 0.95 seconds
Started Jul 16 07:48:46 PM PDT 24
Finished Jul 16 07:48:50 PM PDT 24
Peak memory 207908 kb
Host smart-9115a71e-cb05-469d-ae67-dbc258f56ceb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744398123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.744398123
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.601840332
Short name T911
Test name
Test status
Simulation time 2427307524 ps
CPU time 23.43 seconds
Started Jul 16 07:48:29 PM PDT 24
Finished Jul 16 07:48:55 PM PDT 24
Peak memory 217644 kb
Host smart-ce768c8a-7e99-43bf-9f22-78c5db4b5d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601840332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.601840332
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2350943645
Short name T898
Test name
Test status
Simulation time 19384857466 ps
CPU time 9.93 seconds
Started Jul 16 07:48:27 PM PDT 24
Finished Jul 16 07:48:37 PM PDT 24
Peak memory 218620 kb
Host smart-9cc243a5-04f3-4326-8d46-bcdd56def854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350943645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2350943645
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.965204517
Short name T664
Test name
Test status
Simulation time 78329418 ps
CPU time 1.42 seconds
Started Jul 16 07:48:29 PM PDT 24
Finished Jul 16 07:48:32 PM PDT 24
Peak memory 217384 kb
Host smart-5b55b3a1-5dc0-4b24-8e64-5b45feb17805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965204517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.965204517
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3646146274
Short name T562
Test name
Test status
Simulation time 63212339 ps
CPU time 0.98 seconds
Started Jul 16 07:48:28 PM PDT 24
Finished Jul 16 07:48:31 PM PDT 24
Peak memory 207140 kb
Host smart-72baa81d-1c14-4ace-8c1a-ba212bceb4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646146274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3646146274
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2701151202
Short name T738
Test name
Test status
Simulation time 1089455467 ps
CPU time 7.66 seconds
Started Jul 16 07:48:45 PM PDT 24
Finished Jul 16 07:48:55 PM PDT 24
Peak memory 233800 kb
Host smart-7bf8baae-0380-49ef-af02-00f661485824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701151202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2701151202
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.791445520
Short name T820
Test name
Test status
Simulation time 44522044 ps
CPU time 0.72 seconds
Started Jul 16 07:48:45 PM PDT 24
Finished Jul 16 07:48:48 PM PDT 24
Peak memory 206748 kb
Host smart-c69e30e3-4c8e-40da-80da-b2c3a23885ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791445520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.791445520
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3913280008
Short name T13
Test name
Test status
Simulation time 3314993464 ps
CPU time 5.28 seconds
Started Jul 16 07:48:42 PM PDT 24
Finished Jul 16 07:48:49 PM PDT 24
Peak memory 225636 kb
Host smart-f8b00d2a-27f0-429c-ab15-1da63e3e9a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913280008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3913280008
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3692157367
Short name T917
Test name
Test status
Simulation time 14951734 ps
CPU time 0.79 seconds
Started Jul 16 07:48:45 PM PDT 24
Finished Jul 16 07:48:48 PM PDT 24
Peak memory 207500 kb
Host smart-66c9027d-bf86-471d-affb-689fc46a655a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692157367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3692157367
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3014419566
Short name T214
Test name
Test status
Simulation time 7744629405 ps
CPU time 39.51 seconds
Started Jul 16 07:48:44 PM PDT 24
Finished Jul 16 07:49:26 PM PDT 24
Peak memory 250304 kb
Host smart-8a85ce11-a200-46aa-83f8-9e33f18ceee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014419566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3014419566
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.870029563
Short name T43
Test name
Test status
Simulation time 161240424698 ps
CPU time 353.61 seconds
Started Jul 16 07:48:44 PM PDT 24
Finished Jul 16 07:54:41 PM PDT 24
Peak memory 251588 kb
Host smart-c2600db3-30db-4e89-adc9-29060532915c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870029563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.870029563
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.373908558
Short name T589
Test name
Test status
Simulation time 8243840633 ps
CPU time 37.64 seconds
Started Jul 16 07:48:45 PM PDT 24
Finished Jul 16 07:49:26 PM PDT 24
Peak memory 256260 kb
Host smart-410847aa-4c45-436f-a5c4-7dcfb46ae39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373908558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.373908558
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3756007781
Short name T883
Test name
Test status
Simulation time 35754387949 ps
CPU time 250.37 seconds
Started Jul 16 07:48:45 PM PDT 24
Finished Jul 16 07:52:58 PM PDT 24
Peak memory 254256 kb
Host smart-420cba95-a211-4371-b2ca-5650014683ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756007781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3756007781
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2352107463
Short name T1023
Test name
Test status
Simulation time 95122001 ps
CPU time 3.63 seconds
Started Jul 16 07:48:44 PM PDT 24
Finished Jul 16 07:48:51 PM PDT 24
Peak memory 233728 kb
Host smart-caab54d1-355d-49cf-8fc0-35f91e656205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352107463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2352107463
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.381340554
Short name T878
Test name
Test status
Simulation time 2815468870 ps
CPU time 10.04 seconds
Started Jul 16 07:48:43 PM PDT 24
Finished Jul 16 07:48:55 PM PDT 24
Peak memory 233820 kb
Host smart-d641ebbd-3ae9-4528-9b28-60a083f99046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381340554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.381340554
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2492690114
Short name T467
Test name
Test status
Simulation time 36275680 ps
CPU time 1.08 seconds
Started Jul 16 07:48:43 PM PDT 24
Finished Jul 16 07:48:46 PM PDT 24
Peak memory 217636 kb
Host smart-9871de2d-bc89-4912-8099-b55a84bb40db
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492690114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2492690114
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.873818913
Short name T243
Test name
Test status
Simulation time 2412530036 ps
CPU time 8.68 seconds
Started Jul 16 07:48:44 PM PDT 24
Finished Jul 16 07:48:56 PM PDT 24
Peak memory 225676 kb
Host smart-ddc3dbff-1bc7-4a07-9c59-ab7765f1adec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873818913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.873818913
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2335244720
Short name T674
Test name
Test status
Simulation time 543374809 ps
CPU time 3.82 seconds
Started Jul 16 07:48:46 PM PDT 24
Finished Jul 16 07:48:53 PM PDT 24
Peak memory 233752 kb
Host smart-1354d645-0c43-4e19-a692-7a5e038d3a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335244720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2335244720
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1752484603
Short name T945
Test name
Test status
Simulation time 7315011855 ps
CPU time 15.23 seconds
Started Jul 16 07:48:43 PM PDT 24
Finished Jul 16 07:48:59 PM PDT 24
Peak memory 220104 kb
Host smart-bc6f2d6a-63ba-4471-8cd5-352bf27236c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1752484603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1752484603
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.4097379593
Short name T178
Test name
Test status
Simulation time 15198001787 ps
CPU time 104.9 seconds
Started Jul 16 07:48:44 PM PDT 24
Finished Jul 16 07:50:30 PM PDT 24
Peak memory 225744 kb
Host smart-b21b6785-c83e-4a98-acb1-3bb85579b455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097379593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.4097379593
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.632824421
Short name T744
Test name
Test status
Simulation time 2567397407 ps
CPU time 8.76 seconds
Started Jul 16 07:48:42 PM PDT 24
Finished Jul 16 07:48:53 PM PDT 24
Peak memory 217484 kb
Host smart-ff8b1480-6b88-41e8-81f7-01e79695e74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632824421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.632824421
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3405137251
Short name T772
Test name
Test status
Simulation time 10185012661 ps
CPU time 9.87 seconds
Started Jul 16 07:48:45 PM PDT 24
Finished Jul 16 07:48:58 PM PDT 24
Peak memory 217492 kb
Host smart-5fa53a9a-3063-40fb-bdda-26e1f666cf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405137251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3405137251
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2970508996
Short name T600
Test name
Test status
Simulation time 117756208 ps
CPU time 2.36 seconds
Started Jul 16 07:48:45 PM PDT 24
Finished Jul 16 07:48:50 PM PDT 24
Peak memory 217308 kb
Host smart-77c2452e-5343-4b54-b3a2-f12b5dd09bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970508996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2970508996
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1036663435
Short name T401
Test name
Test status
Simulation time 59796937 ps
CPU time 0.95 seconds
Started Jul 16 07:48:45 PM PDT 24
Finished Jul 16 07:48:48 PM PDT 24
Peak memory 207940 kb
Host smart-751a2daf-18d8-4511-9701-c8d0e35570b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036663435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1036663435
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2003954268
Short name T261
Test name
Test status
Simulation time 1981317780 ps
CPU time 5.73 seconds
Started Jul 16 07:48:45 PM PDT 24
Finished Jul 16 07:48:54 PM PDT 24
Peak memory 233720 kb
Host smart-6ff2c745-6f64-4bef-a57b-8b822ff34bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003954268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2003954268
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.724306804
Short name T409
Test name
Test status
Simulation time 220321388 ps
CPU time 4.03 seconds
Started Jul 16 07:48:46 PM PDT 24
Finished Jul 16 07:48:53 PM PDT 24
Peak memory 233752 kb
Host smart-d1a970fa-a34a-4b93-b282-541ad757471a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724306804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.724306804
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1395409739
Short name T746
Test name
Test status
Simulation time 20573181 ps
CPU time 0.77 seconds
Started Jul 16 07:48:43 PM PDT 24
Finished Jul 16 07:48:45 PM PDT 24
Peak memory 207876 kb
Host smart-b36b4795-6cbc-4809-a295-a5f8cc0edb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395409739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1395409739
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1731053129
Short name T519
Test name
Test status
Simulation time 47975152 ps
CPU time 0.84 seconds
Started Jul 16 07:48:47 PM PDT 24
Finished Jul 16 07:48:51 PM PDT 24
Peak memory 217076 kb
Host smart-27fdb2a5-af9f-454c-89c1-f62da51ed377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731053129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1731053129
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2755709674
Short name T863
Test name
Test status
Simulation time 7872482955 ps
CPU time 24.94 seconds
Started Jul 16 07:48:44 PM PDT 24
Finished Jul 16 07:49:11 PM PDT 24
Peak memory 225844 kb
Host smart-1e39b407-9339-4c76-bb24-f811331cb746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755709674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2755709674
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2549794270
Short name T753
Test name
Test status
Simulation time 694904826 ps
CPU time 9.48 seconds
Started Jul 16 07:48:45 PM PDT 24
Finished Jul 16 07:48:57 PM PDT 24
Peak memory 241940 kb
Host smart-fe33747a-4110-43d4-b2e6-84586d59266c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549794270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2549794270
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.43407670
Short name T105
Test name
Test status
Simulation time 15990364734 ps
CPU time 73.77 seconds
Started Jul 16 07:48:46 PM PDT 24
Finished Jul 16 07:50:03 PM PDT 24
Peak memory 253360 kb
Host smart-838b0c4f-9397-47eb-83e1-ca79f448f421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43407670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.43407670
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2127078582
Short name T226
Test name
Test status
Simulation time 2488412306 ps
CPU time 23.78 seconds
Started Jul 16 07:48:47 PM PDT 24
Finished Jul 16 07:49:14 PM PDT 24
Peak memory 225640 kb
Host smart-9813fb58-f753-40c4-85a1-bb36b8857b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127078582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2127078582
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3046269477
Short name T416
Test name
Test status
Simulation time 73636191 ps
CPU time 2.08 seconds
Started Jul 16 07:48:44 PM PDT 24
Finished Jul 16 07:48:48 PM PDT 24
Peak memory 224604 kb
Host smart-bea88580-69f2-468b-aabb-5aa11943ade4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046269477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3046269477
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1200574651
Short name T498
Test name
Test status
Simulation time 17506585 ps
CPU time 1.1 seconds
Started Jul 16 07:48:48 PM PDT 24
Finished Jul 16 07:48:52 PM PDT 24
Peak memory 217656 kb
Host smart-9da01f71-1626-4a38-b2dd-ff1d89e651e1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200574651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1200574651
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2393792263
Short name T872
Test name
Test status
Simulation time 3063101561 ps
CPU time 10.68 seconds
Started Jul 16 07:48:42 PM PDT 24
Finished Jul 16 07:48:53 PM PDT 24
Peak memory 225728 kb
Host smart-4d24e583-fa12-44d3-89aa-a29c4b97a9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393792263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2393792263
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3553510484
Short name T959
Test name
Test status
Simulation time 420664915 ps
CPU time 6.57 seconds
Started Jul 16 07:48:42 PM PDT 24
Finished Jul 16 07:48:49 PM PDT 24
Peak memory 233764 kb
Host smart-2566cc88-9981-4b3c-a640-0e8c4d2b7407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553510484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3553510484
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2638191817
Short name T955
Test name
Test status
Simulation time 3828814674 ps
CPU time 11.22 seconds
Started Jul 16 07:48:44 PM PDT 24
Finished Jul 16 07:48:58 PM PDT 24
Peak memory 219908 kb
Host smart-37468878-2eb9-4466-9bbe-97fe4c01fffd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2638191817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2638191817
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1046402001
Short name T813
Test name
Test status
Simulation time 26179799327 ps
CPU time 130.98 seconds
Started Jul 16 07:48:43 PM PDT 24
Finished Jul 16 07:50:55 PM PDT 24
Peak memory 255844 kb
Host smart-72885eac-5e71-472e-8db6-d272a54b8758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046402001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1046402001
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3442131714
Short name T777
Test name
Test status
Simulation time 1342175168 ps
CPU time 4.21 seconds
Started Jul 16 07:48:45 PM PDT 24
Finished Jul 16 07:48:52 PM PDT 24
Peak memory 217536 kb
Host smart-da844f32-a666-4441-90e2-82f256333eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442131714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3442131714
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1597049399
Short name T570
Test name
Test status
Simulation time 11405140 ps
CPU time 0.75 seconds
Started Jul 16 07:48:42 PM PDT 24
Finished Jul 16 07:48:43 PM PDT 24
Peak memory 206796 kb
Host smart-a6c2880a-6500-44dc-92e3-e44ab9dc404e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597049399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1597049399
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.413017172
Short name T3
Test name
Test status
Simulation time 117248751 ps
CPU time 2.03 seconds
Started Jul 16 07:48:45 PM PDT 24
Finished Jul 16 07:48:50 PM PDT 24
Peak memory 217360 kb
Host smart-b0ec4816-374f-4181-9ff8-1461fb59e3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413017172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.413017172
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1771276785
Short name T932
Test name
Test status
Simulation time 92642818 ps
CPU time 0.82 seconds
Started Jul 16 07:48:45 PM PDT 24
Finished Jul 16 07:48:49 PM PDT 24
Peak memory 207008 kb
Host smart-25e1b381-8e76-43f7-9277-0b5097a028cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771276785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1771276785
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.749395735
Short name T675
Test name
Test status
Simulation time 129621350 ps
CPU time 2.79 seconds
Started Jul 16 07:48:45 PM PDT 24
Finished Jul 16 07:48:51 PM PDT 24
Peak memory 233812 kb
Host smart-4c90ad66-71a9-425b-901c-34f98f0acd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749395735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.749395735
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.793444046
Short name T421
Test name
Test status
Simulation time 83328948 ps
CPU time 0.71 seconds
Started Jul 16 07:48:55 PM PDT 24
Finished Jul 16 07:48:59 PM PDT 24
Peak memory 205748 kb
Host smart-0c8947c0-24bc-4110-adce-2c96cc3c5737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793444046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.793444046
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3446210065
Short name T573
Test name
Test status
Simulation time 75103119 ps
CPU time 2.54 seconds
Started Jul 16 07:48:57 PM PDT 24
Finished Jul 16 07:49:03 PM PDT 24
Peak memory 233784 kb
Host smart-9cd3c719-0c55-442c-8bee-8a816add962c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446210065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3446210065
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1066419690
Short name T75
Test name
Test status
Simulation time 60927965 ps
CPU time 0.79 seconds
Started Jul 16 07:48:42 PM PDT 24
Finished Jul 16 07:48:44 PM PDT 24
Peak memory 207528 kb
Host smart-1e65a2c3-0fe7-420b-86aa-feb9e23f8bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066419690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1066419690
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2666780910
Short name T219
Test name
Test status
Simulation time 104269835881 ps
CPU time 137.79 seconds
Started Jul 16 07:48:58 PM PDT 24
Finished Jul 16 07:51:20 PM PDT 24
Peak memory 250540 kb
Host smart-159d7396-2661-45ed-abbe-94a41b01cd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666780910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2666780910
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1006406435
Short name T277
Test name
Test status
Simulation time 24802210423 ps
CPU time 84.96 seconds
Started Jul 16 07:48:55 PM PDT 24
Finished Jul 16 07:50:23 PM PDT 24
Peak memory 252624 kb
Host smart-a8749134-8207-4ba5-8dcb-b88bfb7cae93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006406435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1006406435
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.4001489416
Short name T346
Test name
Test status
Simulation time 8307558032 ps
CPU time 118.9 seconds
Started Jul 16 07:48:58 PM PDT 24
Finished Jul 16 07:51:01 PM PDT 24
Peak memory 256636 kb
Host smart-38143cfa-ef99-452f-b98f-386fdd085326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001489416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.4001489416
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2753140062
Short name T448
Test name
Test status
Simulation time 260741122 ps
CPU time 7.06 seconds
Started Jul 16 07:48:54 PM PDT 24
Finished Jul 16 07:49:03 PM PDT 24
Peak memory 233776 kb
Host smart-ff1f4bbb-4b2b-45dd-b8be-096f5f0bf2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753140062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2753140062
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2137325266
Short name T328
Test name
Test status
Simulation time 169971538756 ps
CPU time 303.98 seconds
Started Jul 16 07:48:57 PM PDT 24
Finished Jul 16 07:54:05 PM PDT 24
Peak memory 268488 kb
Host smart-9d8aca8e-d87f-44a6-9e48-921db9948d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137325266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2137325266
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.4129973152
Short name T240
Test name
Test status
Simulation time 2261111162 ps
CPU time 7 seconds
Started Jul 16 07:48:46 PM PDT 24
Finished Jul 16 07:48:56 PM PDT 24
Peak memory 225588 kb
Host smart-a2b2dfad-b242-4021-a467-58558e991714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129973152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.4129973152
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3505837332
Short name T886
Test name
Test status
Simulation time 2159676118 ps
CPU time 11.47 seconds
Started Jul 16 07:48:56 PM PDT 24
Finished Jul 16 07:49:11 PM PDT 24
Peak memory 233808 kb
Host smart-4e4ad7f8-46c4-4c8a-bc70-93db0dd71b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505837332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3505837332
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3384166688
Short name T149
Test name
Test status
Simulation time 81800976 ps
CPU time 1.06 seconds
Started Jul 16 07:48:42 PM PDT 24
Finished Jul 16 07:48:45 PM PDT 24
Peak memory 217628 kb
Host smart-08bfadb3-5750-4f5c-834c-2aea081e9f7c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384166688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3384166688
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3761129642
Short name T681
Test name
Test status
Simulation time 106847587 ps
CPU time 2.24 seconds
Started Jul 16 07:48:44 PM PDT 24
Finished Jul 16 07:48:49 PM PDT 24
Peak memory 224252 kb
Host smart-85ee7000-c24b-4514-8e3e-5456cf830bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761129642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3761129642
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.889298804
Short name T733
Test name
Test status
Simulation time 3756067815 ps
CPU time 9.67 seconds
Started Jul 16 07:48:47 PM PDT 24
Finished Jul 16 07:48:59 PM PDT 24
Peak memory 234592 kb
Host smart-01c58b21-d735-4115-b54a-09994cba2163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889298804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.889298804
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3307579110
Short name T592
Test name
Test status
Simulation time 999599395 ps
CPU time 9.35 seconds
Started Jul 16 07:48:54 PM PDT 24
Finished Jul 16 07:49:06 PM PDT 24
Peak memory 219792 kb
Host smart-0cf9af32-708d-4ce8-b63b-b925925044a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3307579110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3307579110
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3228216809
Short name T70
Test name
Test status
Simulation time 12552300476 ps
CPU time 231.8 seconds
Started Jul 16 07:48:59 PM PDT 24
Finished Jul 16 07:52:55 PM PDT 24
Peak memory 283164 kb
Host smart-94a58530-686d-4b77-a919-d42bb8bcbc9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228216809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3228216809
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3681517915
Short name T499
Test name
Test status
Simulation time 145145388390 ps
CPU time 44.09 seconds
Started Jul 16 07:48:44 PM PDT 24
Finished Jul 16 07:49:31 PM PDT 24
Peak memory 217420 kb
Host smart-a976158d-eb98-49c5-acdb-ff0a57bf8aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681517915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3681517915
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2136640578
Short name T966
Test name
Test status
Simulation time 6767995587 ps
CPU time 21.38 seconds
Started Jul 16 07:48:45 PM PDT 24
Finished Jul 16 07:49:09 PM PDT 24
Peak memory 217480 kb
Host smart-57692bb7-1b8e-4d28-a05f-7e613d7fe1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136640578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2136640578
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1831569655
Short name T659
Test name
Test status
Simulation time 1756736266 ps
CPU time 2.74 seconds
Started Jul 16 07:48:46 PM PDT 24
Finished Jul 16 07:48:52 PM PDT 24
Peak memory 217356 kb
Host smart-415d9d1d-ecd8-4b7a-8e7c-08491879c309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831569655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1831569655
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.4144390967
Short name T405
Test name
Test status
Simulation time 94073732 ps
CPU time 0.75 seconds
Started Jul 16 07:48:45 PM PDT 24
Finished Jul 16 07:48:49 PM PDT 24
Peak memory 206916 kb
Host smart-d9046f20-d7ec-4136-a5fd-7c2ee11ccc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144390967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.4144390967
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2925412364
Short name T951
Test name
Test status
Simulation time 4680617205 ps
CPU time 17.87 seconds
Started Jul 16 07:48:56 PM PDT 24
Finished Jul 16 07:49:17 PM PDT 24
Peak memory 241800 kb
Host smart-a52800f2-5834-4b44-81d6-efa1b4095b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925412364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2925412364
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3864940263
Short name T814
Test name
Test status
Simulation time 73267894 ps
CPU time 0.72 seconds
Started Jul 16 07:48:56 PM PDT 24
Finished Jul 16 07:49:01 PM PDT 24
Peak memory 205764 kb
Host smart-69de58af-8899-4de8-820d-4d3e703695f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864940263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3864940263
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.710817799
Short name T289
Test name
Test status
Simulation time 4030021647 ps
CPU time 19.88 seconds
Started Jul 16 07:48:55 PM PDT 24
Finished Jul 16 07:49:18 PM PDT 24
Peak memory 233852 kb
Host smart-e9de3c63-25d6-40b7-ba6d-b0bdc2aa7779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710817799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.710817799
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2562787047
Short name T420
Test name
Test status
Simulation time 65962203 ps
CPU time 0.77 seconds
Started Jul 16 07:48:59 PM PDT 24
Finished Jul 16 07:49:04 PM PDT 24
Peak memory 206484 kb
Host smart-31c16ac0-756f-469e-ac89-4913eb21a1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562787047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2562787047
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2646664673
Short name T94
Test name
Test status
Simulation time 48520954271 ps
CPU time 163.8 seconds
Started Jul 16 07:48:55 PM PDT 24
Finished Jul 16 07:51:42 PM PDT 24
Peak memory 250404 kb
Host smart-76c17467-84d4-4af7-a9a5-2f94a2c14230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646664673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2646664673
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1120381973
Short name T65
Test name
Test status
Simulation time 9973031181 ps
CPU time 66.41 seconds
Started Jul 16 07:49:00 PM PDT 24
Finished Jul 16 07:50:10 PM PDT 24
Peak memory 250404 kb
Host smart-452c9f8e-49da-4b1c-b4c7-7b5890141bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120381973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1120381973
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.461141221
Short name T701
Test name
Test status
Simulation time 27324320644 ps
CPU time 257.38 seconds
Started Jul 16 07:48:56 PM PDT 24
Finished Jul 16 07:53:17 PM PDT 24
Peak memory 258556 kb
Host smart-7d255c40-d989-40bc-85fc-ac42eb60e8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461141221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.461141221
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2227094508
Short name T332
Test name
Test status
Simulation time 5563456515 ps
CPU time 61.61 seconds
Started Jul 16 07:48:58 PM PDT 24
Finished Jul 16 07:50:04 PM PDT 24
Peak memory 250288 kb
Host smart-e9e5fc7a-5334-458d-931d-53ae4c4d96f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227094508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2227094508
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.817679076
Short name T723
Test name
Test status
Simulation time 13546921 ps
CPU time 0.77 seconds
Started Jul 16 07:49:00 PM PDT 24
Finished Jul 16 07:49:05 PM PDT 24
Peak memory 216908 kb
Host smart-5846e79b-9448-4e10-88e3-b5838a9e6459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817679076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.817679076
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4154971861
Short name T916
Test name
Test status
Simulation time 166242912 ps
CPU time 2.65 seconds
Started Jul 16 07:49:01 PM PDT 24
Finished Jul 16 07:49:07 PM PDT 24
Peak memory 233692 kb
Host smart-ffb664ef-c123-426d-9c33-e17bfc3551e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154971861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4154971861
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1721200729
Short name T564
Test name
Test status
Simulation time 1210093721 ps
CPU time 12.78 seconds
Started Jul 16 07:49:00 PM PDT 24
Finished Jul 16 07:49:17 PM PDT 24
Peak memory 233748 kb
Host smart-b4eaae56-6f8f-41df-8fb4-dfeba0a6a420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721200729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1721200729
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2384618622
Short name T461
Test name
Test status
Simulation time 28100790 ps
CPU time 1.03 seconds
Started Jul 16 07:48:56 PM PDT 24
Finished Jul 16 07:49:01 PM PDT 24
Peak memory 218960 kb
Host smart-b29f0406-d1c3-401c-a08b-70a485024514
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384618622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2384618622
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2509443647
Short name T790
Test name
Test status
Simulation time 25877116135 ps
CPU time 20.96 seconds
Started Jul 16 07:48:59 PM PDT 24
Finished Jul 16 07:49:24 PM PDT 24
Peak memory 233892 kb
Host smart-957b008d-f2e6-4142-a184-3253c0a6ea2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509443647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2509443647
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2319997055
Short name T412
Test name
Test status
Simulation time 158812024 ps
CPU time 3.79 seconds
Started Jul 16 07:48:57 PM PDT 24
Finished Jul 16 07:49:04 PM PDT 24
Peak memory 233752 kb
Host smart-2cc8f915-25ca-4bf3-9535-cf2062a954e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319997055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2319997055
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2292287733
Short name T860
Test name
Test status
Simulation time 929137689 ps
CPU time 13.99 seconds
Started Jul 16 07:48:55 PM PDT 24
Finished Jul 16 07:49:13 PM PDT 24
Peak memory 221476 kb
Host smart-98b87345-3fb4-4524-b929-dcfc21450208
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2292287733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2292287733
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1631622696
Short name T18
Test name
Test status
Simulation time 158492053 ps
CPU time 3.18 seconds
Started Jul 16 07:49:01 PM PDT 24
Finished Jul 16 07:49:07 PM PDT 24
Peak memory 223512 kb
Host smart-d2326cb3-b1a4-4a1b-a74f-fb49c2b6c1fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631622696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1631622696
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.116008297
Short name T341
Test name
Test status
Simulation time 5687080838 ps
CPU time 18.81 seconds
Started Jul 16 07:49:00 PM PDT 24
Finished Jul 16 07:49:22 PM PDT 24
Peak memory 217456 kb
Host smart-00fdf31c-e505-4db8-a85f-0595a67355a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116008297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.116008297
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.784648688
Short name T861
Test name
Test status
Simulation time 3569207163 ps
CPU time 11.64 seconds
Started Jul 16 07:48:57 PM PDT 24
Finished Jul 16 07:49:13 PM PDT 24
Peak memory 217476 kb
Host smart-c6e27cd7-a369-4e2f-a737-5db45d50431c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784648688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.784648688
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.702605595
Short name T618
Test name
Test status
Simulation time 151046205 ps
CPU time 1.24 seconds
Started Jul 16 07:48:56 PM PDT 24
Finished Jul 16 07:49:01 PM PDT 24
Peak memory 217316 kb
Host smart-c2db623d-8b9b-4dca-b371-f7dbe35cfd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702605595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.702605595
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2172515799
Short name T981
Test name
Test status
Simulation time 33320601 ps
CPU time 0.78 seconds
Started Jul 16 07:49:01 PM PDT 24
Finished Jul 16 07:49:05 PM PDT 24
Peak memory 206912 kb
Host smart-64c1b4dc-d841-4cde-9e7c-7cc8780ed4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172515799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2172515799
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.722912388
Short name T495
Test name
Test status
Simulation time 41619097 ps
CPU time 2.54 seconds
Started Jul 16 07:49:01 PM PDT 24
Finished Jul 16 07:49:06 PM PDT 24
Peak memory 233508 kb
Host smart-3c6b9b77-0141-480e-8db7-82c5a409c162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722912388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.722912388
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.366176164
Short name T811
Test name
Test status
Simulation time 36362184 ps
CPU time 0.69 seconds
Started Jul 16 07:49:08 PM PDT 24
Finished Jul 16 07:49:11 PM PDT 24
Peak memory 206392 kb
Host smart-f4fdf210-0f86-4755-b8f2-0d3c5ae03759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366176164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.366176164
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.4276294138
Short name T100
Test name
Test status
Simulation time 365729768 ps
CPU time 3.6 seconds
Started Jul 16 07:48:59 PM PDT 24
Finished Jul 16 07:49:07 PM PDT 24
Peak memory 233788 kb
Host smart-cd9c4cda-fc57-400b-b68b-3a715e4024a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276294138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.4276294138
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.458862869
Short name T14
Test name
Test status
Simulation time 31036551 ps
CPU time 0.79 seconds
Started Jul 16 07:49:00 PM PDT 24
Finished Jul 16 07:49:04 PM PDT 24
Peak memory 207504 kb
Host smart-a12d5242-e3e3-420b-ae85-61f10174f487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458862869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.458862869
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2628744319
Short name T853
Test name
Test status
Simulation time 23206924347 ps
CPU time 45.25 seconds
Started Jul 16 07:49:05 PM PDT 24
Finished Jul 16 07:49:51 PM PDT 24
Peak memory 242080 kb
Host smart-61d57c25-75c9-46a6-a888-d7d562078e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628744319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2628744319
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1328117441
Short name T923
Test name
Test status
Simulation time 9495743606 ps
CPU time 45.68 seconds
Started Jul 16 07:48:58 PM PDT 24
Finished Jul 16 07:49:48 PM PDT 24
Peak memory 251904 kb
Host smart-c7a394b6-5d81-4d5a-81c5-1931957da4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328117441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1328117441
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1138572527
Short name T1000
Test name
Test status
Simulation time 24790025908 ps
CPU time 90.31 seconds
Started Jul 16 07:49:01 PM PDT 24
Finished Jul 16 07:50:35 PM PDT 24
Peak memory 263388 kb
Host smart-c366f48f-ae88-46cc-9ef9-5145a6bd2b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138572527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1138572527
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3217142337
Short name T200
Test name
Test status
Simulation time 29354253945 ps
CPU time 60.33 seconds
Started Jul 16 07:49:00 PM PDT 24
Finished Jul 16 07:50:04 PM PDT 24
Peak memory 242040 kb
Host smart-cda1bffe-a418-469d-8d54-7c9d5765101e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217142337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3217142337
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1478100695
Short name T256
Test name
Test status
Simulation time 1628201312 ps
CPU time 13.73 seconds
Started Jul 16 07:48:56 PM PDT 24
Finished Jul 16 07:49:13 PM PDT 24
Peak memory 233840 kb
Host smart-d4e8c89e-bdd4-4d85-911a-9c6bf2a262ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478100695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1478100695
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2557518726
Short name T1
Test name
Test status
Simulation time 33112588 ps
CPU time 2.26 seconds
Started Jul 16 07:48:55 PM PDT 24
Finished Jul 16 07:49:00 PM PDT 24
Peak memory 233524 kb
Host smart-c9cd35c1-cd05-45fd-9d83-6071f65b1729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557518726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2557518726
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.4214112061
Short name T45
Test name
Test status
Simulation time 128070794 ps
CPU time 1.07 seconds
Started Jul 16 07:48:57 PM PDT 24
Finished Jul 16 07:49:02 PM PDT 24
Peak memory 217664 kb
Host smart-955d946d-e229-42fd-a750-21949d62abc2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214112061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.4214112061
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1512818310
Short name T839
Test name
Test status
Simulation time 7129202473 ps
CPU time 20.7 seconds
Started Jul 16 07:48:55 PM PDT 24
Finished Jul 16 07:49:18 PM PDT 24
Peak memory 238904 kb
Host smart-3bb55507-1d54-4f1b-81c8-4582884d5164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512818310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1512818310
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.881794159
Short name T578
Test name
Test status
Simulation time 783619552 ps
CPU time 7.99 seconds
Started Jul 16 07:48:56 PM PDT 24
Finished Jul 16 07:49:08 PM PDT 24
Peak memory 252464 kb
Host smart-0ae50cd3-512e-4a31-8f7a-babafa14f8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881794159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.881794159
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.360924547
Short name T1013
Test name
Test status
Simulation time 1346855866 ps
CPU time 14.1 seconds
Started Jul 16 07:48:57 PM PDT 24
Finished Jul 16 07:49:15 PM PDT 24
Peak memory 223132 kb
Host smart-80e8500b-8cdc-481f-9e2d-04062e31b695
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=360924547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.360924547
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1858044837
Short name T809
Test name
Test status
Simulation time 503592639487 ps
CPU time 425.28 seconds
Started Jul 16 07:48:58 PM PDT 24
Finished Jul 16 07:56:07 PM PDT 24
Peak memory 258252 kb
Host smart-b1dd3e37-3bdf-499d-9a31-8cb8f07360dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858044837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1858044837
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1685713493
Short name T642
Test name
Test status
Simulation time 5675605565 ps
CPU time 40.42 seconds
Started Jul 16 07:48:57 PM PDT 24
Finished Jul 16 07:49:41 PM PDT 24
Peak memory 217480 kb
Host smart-a5d4ab30-6b38-4a97-b39c-75e244aa40ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685713493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1685713493
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2990636950
Short name T145
Test name
Test status
Simulation time 15078222591 ps
CPU time 13.44 seconds
Started Jul 16 07:49:00 PM PDT 24
Finished Jul 16 07:49:17 PM PDT 24
Peak memory 217440 kb
Host smart-c31aaf67-2938-4645-83ed-5f03bebd2f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990636950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2990636950
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2861800867
Short name T684
Test name
Test status
Simulation time 29520062 ps
CPU time 1.04 seconds
Started Jul 16 07:48:58 PM PDT 24
Finished Jul 16 07:49:03 PM PDT 24
Peak memory 208076 kb
Host smart-2587469f-5733-4e1e-b0e3-ac53dea6cb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861800867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2861800867
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1327975028
Short name T386
Test name
Test status
Simulation time 82662537 ps
CPU time 0.87 seconds
Started Jul 16 07:48:54 PM PDT 24
Finished Jul 16 07:48:56 PM PDT 24
Peak memory 207984 kb
Host smart-98cdda1e-7d5a-44f1-84c9-56c87ad2f013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327975028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1327975028
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2837903122
Short name T629
Test name
Test status
Simulation time 433488103 ps
CPU time 7.51 seconds
Started Jul 16 07:48:59 PM PDT 24
Finished Jul 16 07:49:11 PM PDT 24
Peak memory 249452 kb
Host smart-ddd4c824-a705-482a-ae0f-4eb7b7e9c0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837903122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2837903122
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3215731248
Short name T928
Test name
Test status
Simulation time 39764981 ps
CPU time 0.82 seconds
Started Jul 16 07:49:08 PM PDT 24
Finished Jul 16 07:49:11 PM PDT 24
Peak memory 205824 kb
Host smart-18378063-6def-4f59-8e5e-c355e1417ef4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215731248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3215731248
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2953215456
Short name T274
Test name
Test status
Simulation time 590549534 ps
CPU time 8.9 seconds
Started Jul 16 07:49:14 PM PDT 24
Finished Jul 16 07:49:25 PM PDT 24
Peak memory 225628 kb
Host smart-f117a79c-e7f2-4795-8f63-cdcff522c89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953215456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2953215456
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2326924894
Short name T879
Test name
Test status
Simulation time 18080734 ps
CPU time 0.79 seconds
Started Jul 16 07:49:08 PM PDT 24
Finished Jul 16 07:49:10 PM PDT 24
Peak memory 207500 kb
Host smart-06bccab8-a23f-4aab-b515-8acc90c8238c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326924894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2326924894
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.752408389
Short name T575
Test name
Test status
Simulation time 32392378 ps
CPU time 0.9 seconds
Started Jul 16 07:49:14 PM PDT 24
Finished Jul 16 07:49:16 PM PDT 24
Peak memory 218668 kb
Host smart-01205c1b-5642-4a25-9ef2-304e2bab9454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752408389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.752408389
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2616305125
Short name T992
Test name
Test status
Simulation time 474847687 ps
CPU time 4.45 seconds
Started Jul 16 07:49:13 PM PDT 24
Finished Jul 16 07:49:19 PM PDT 24
Peak memory 234604 kb
Host smart-e5f31473-9d21-4a32-9536-15c3823bf681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616305125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2616305125
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3962351673
Short name T259
Test name
Test status
Simulation time 957239208 ps
CPU time 10.43 seconds
Started Jul 16 07:49:21 PM PDT 24
Finished Jul 16 07:49:35 PM PDT 24
Peak memory 225528 kb
Host smart-0dae50a5-9fc5-42d0-95c9-c05c81235492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962351673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3962351673
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.684568243
Short name T548
Test name
Test status
Simulation time 5980089561 ps
CPU time 7.6 seconds
Started Jul 16 07:49:08 PM PDT 24
Finished Jul 16 07:49:16 PM PDT 24
Peak memory 225596 kb
Host smart-b4aad173-7275-4c37-9d52-8cd4f3cf9562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684568243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.684568243
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1506988766
Short name T47
Test name
Test status
Simulation time 25605961 ps
CPU time 1.01 seconds
Started Jul 16 07:49:08 PM PDT 24
Finished Jul 16 07:49:11 PM PDT 24
Peak memory 218972 kb
Host smart-df14fb16-56ce-4b20-bc60-a02e8533843b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506988766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1506988766
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2520045119
Short name T503
Test name
Test status
Simulation time 52890014 ps
CPU time 2.39 seconds
Started Jul 16 07:49:12 PM PDT 24
Finished Jul 16 07:49:15 PM PDT 24
Peak memory 225516 kb
Host smart-6fb4a178-7074-4a5f-b44e-1c164e85f029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520045119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2520045119
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1331618405
Short name T662
Test name
Test status
Simulation time 570759279 ps
CPU time 5.12 seconds
Started Jul 16 07:49:09 PM PDT 24
Finished Jul 16 07:49:16 PM PDT 24
Peak memory 225512 kb
Host smart-9ed5b68b-c871-4ec7-ae64-f02b61c41324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331618405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1331618405
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3724699092
Short name T432
Test name
Test status
Simulation time 364360844 ps
CPU time 6.49 seconds
Started Jul 16 07:49:10 PM PDT 24
Finished Jul 16 07:49:19 PM PDT 24
Peak memory 223964 kb
Host smart-4bf0f4de-0e6e-40f5-94a3-f19f0eae95bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3724699092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3724699092
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1784544079
Short name T641
Test name
Test status
Simulation time 9815671051 ps
CPU time 71.62 seconds
Started Jul 16 07:49:09 PM PDT 24
Finished Jul 16 07:50:23 PM PDT 24
Peak memory 233984 kb
Host smart-810bbb52-f3ff-4ab2-9467-82b0f27ee19b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784544079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1784544079
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1020260026
Short name T550
Test name
Test status
Simulation time 17073063103 ps
CPU time 8.52 seconds
Started Jul 16 07:49:07 PM PDT 24
Finished Jul 16 07:49:16 PM PDT 24
Peak memory 217588 kb
Host smart-3d7f36eb-d5b5-4bb4-a09f-74df9fd2d34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020260026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1020260026
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2515589108
Short name T437
Test name
Test status
Simulation time 4598609766 ps
CPU time 13.33 seconds
Started Jul 16 07:49:09 PM PDT 24
Finished Jul 16 07:49:25 PM PDT 24
Peak memory 217464 kb
Host smart-2e3449d2-3071-4f2e-9f6c-fdd33a77eda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515589108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2515589108
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.724305877
Short name T375
Test name
Test status
Simulation time 177375335 ps
CPU time 1.09 seconds
Started Jul 16 07:49:08 PM PDT 24
Finished Jul 16 07:49:10 PM PDT 24
Peak memory 208956 kb
Host smart-dc3a1de3-42c4-4db1-bdf9-c766345a9cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724305877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.724305877
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1204261588
Short name T686
Test name
Test status
Simulation time 122392804 ps
CPU time 1.07 seconds
Started Jul 16 07:49:16 PM PDT 24
Finished Jul 16 07:49:18 PM PDT 24
Peak memory 207964 kb
Host smart-eed15531-22be-4c02-8df6-2c26c3c1b629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204261588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1204261588
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2057890352
Short name T268
Test name
Test status
Simulation time 687202223 ps
CPU time 4.27 seconds
Started Jul 16 07:49:09 PM PDT 24
Finished Jul 16 07:49:16 PM PDT 24
Peak memory 233772 kb
Host smart-50610dd3-bbd8-4317-8417-8c0ad1e02f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057890352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2057890352
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2875138347
Short name T640
Test name
Test status
Simulation time 40111498 ps
CPU time 0.76 seconds
Started Jul 16 07:49:12 PM PDT 24
Finished Jul 16 07:49:15 PM PDT 24
Peak memory 206352 kb
Host smart-d0f6444c-3cef-4470-9415-41def4918cbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875138347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2875138347
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1073350912
Short name T146
Test name
Test status
Simulation time 832946841 ps
CPU time 4.38 seconds
Started Jul 16 07:49:22 PM PDT 24
Finished Jul 16 07:49:31 PM PDT 24
Peak memory 233716 kb
Host smart-40689842-8748-4c3f-a13c-900aabe0d577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073350912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1073350912
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3634095447
Short name T385
Test name
Test status
Simulation time 15625717 ps
CPU time 0.81 seconds
Started Jul 16 07:49:10 PM PDT 24
Finished Jul 16 07:49:13 PM PDT 24
Peak memory 207472 kb
Host smart-a3c42281-133d-4135-862c-2aaa5d2424d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634095447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3634095447
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1947453535
Short name T679
Test name
Test status
Simulation time 44223757616 ps
CPU time 170.63 seconds
Started Jul 16 07:49:14 PM PDT 24
Finished Jul 16 07:52:06 PM PDT 24
Peak memory 266764 kb
Host smart-87a141f7-ae6b-4aa8-8cc2-5f6d0dd8d0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947453535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1947453535
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2546541903
Short name T194
Test name
Test status
Simulation time 84565824927 ps
CPU time 118.76 seconds
Started Jul 16 07:49:12 PM PDT 24
Finished Jul 16 07:51:12 PM PDT 24
Peak memory 257048 kb
Host smart-e859e212-7be4-4cdc-ad79-2f1a466b018b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546541903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2546541903
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2793923607
Short name T297
Test name
Test status
Simulation time 81259989063 ps
CPU time 170.39 seconds
Started Jul 16 07:49:12 PM PDT 24
Finished Jul 16 07:52:04 PM PDT 24
Peak memory 250528 kb
Host smart-b6eec86b-a1c2-4c66-bbfe-3a2cc8f29429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793923607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2793923607
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3109959773
Short name T333
Test name
Test status
Simulation time 3450416011 ps
CPU time 17.02 seconds
Started Jul 16 07:49:10 PM PDT 24
Finished Jul 16 07:49:29 PM PDT 24
Peak memory 225840 kb
Host smart-6b247fe0-d091-4063-8105-13998ae3961d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109959773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3109959773
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2767110597
Short name T627
Test name
Test status
Simulation time 25814607906 ps
CPU time 88.07 seconds
Started Jul 16 07:49:13 PM PDT 24
Finished Jul 16 07:50:43 PM PDT 24
Peak memory 257420 kb
Host smart-8850cfea-2e1e-448a-acec-c1c93ea43b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767110597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2767110597
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.949720260
Short name T985
Test name
Test status
Simulation time 1289990393 ps
CPU time 4.54 seconds
Started Jul 16 07:49:10 PM PDT 24
Finished Jul 16 07:49:17 PM PDT 24
Peak memory 233700 kb
Host smart-54b24951-f607-4c77-9f66-6b5c0c15eeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949720260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.949720260
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1296327200
Short name T280
Test name
Test status
Simulation time 782907768 ps
CPU time 17.92 seconds
Started Jul 16 07:49:08 PM PDT 24
Finished Jul 16 07:49:27 PM PDT 24
Peak memory 249840 kb
Host smart-576d429a-708d-44bf-b7dd-941c5f959cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296327200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1296327200
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2574972380
Short name T781
Test name
Test status
Simulation time 159073822 ps
CPU time 1.05 seconds
Started Jul 16 07:49:06 PM PDT 24
Finished Jul 16 07:49:08 PM PDT 24
Peak memory 217544 kb
Host smart-fc0d5218-d407-4949-a19f-7be9adff5900
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574972380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2574972380
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3624843935
Short name T314
Test name
Test status
Simulation time 966275864 ps
CPU time 4.37 seconds
Started Jul 16 07:49:16 PM PDT 24
Finished Jul 16 07:49:22 PM PDT 24
Peak memory 233720 kb
Host smart-324fcddf-3dba-4da3-b7d7-948fdbde6ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624843935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3624843935
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.320040152
Short name T56
Test name
Test status
Simulation time 327921986 ps
CPU time 5.73 seconds
Started Jul 16 07:49:08 PM PDT 24
Finished Jul 16 07:49:15 PM PDT 24
Peak memory 241964 kb
Host smart-3b9dbbbb-c3f3-4c1d-9c79-955a89b3e2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320040152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.320040152
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3162784299
Short name T472
Test name
Test status
Simulation time 994730874 ps
CPU time 5.08 seconds
Started Jul 16 07:49:11 PM PDT 24
Finished Jul 16 07:49:17 PM PDT 24
Peak memory 220320 kb
Host smart-e51074dc-aa72-4602-b343-26ec073dc113
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3162784299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3162784299
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.96584415
Short name T947
Test name
Test status
Simulation time 7310702453 ps
CPU time 20 seconds
Started Jul 16 07:49:14 PM PDT 24
Finished Jul 16 07:49:36 PM PDT 24
Peak memory 225800 kb
Host smart-e712f1a4-f3db-4e33-8bd0-4d29ed5d62d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96584415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress
_all.96584415
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2791778691
Short name T433
Test name
Test status
Simulation time 30812068259 ps
CPU time 24.14 seconds
Started Jul 16 07:49:20 PM PDT 24
Finished Jul 16 07:49:45 PM PDT 24
Peak memory 217512 kb
Host smart-4680d755-6bd6-4ea1-b210-71266710478f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791778691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2791778691
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.372821560
Short name T451
Test name
Test status
Simulation time 7706385589 ps
CPU time 15.09 seconds
Started Jul 16 07:49:10 PM PDT 24
Finished Jul 16 07:49:27 PM PDT 24
Peak memory 217456 kb
Host smart-0a27e145-e445-4a3b-9d2e-0807af855417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372821560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.372821560
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2199510476
Short name T518
Test name
Test status
Simulation time 144699964 ps
CPU time 1.63 seconds
Started Jul 16 07:49:09 PM PDT 24
Finished Jul 16 07:49:13 PM PDT 24
Peak memory 217556 kb
Host smart-75ce7495-234a-48e3-b712-a3fc69877b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199510476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2199510476
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2671202726
Short name T87
Test name
Test status
Simulation time 137449301 ps
CPU time 0.85 seconds
Started Jul 16 07:49:08 PM PDT 24
Finished Jul 16 07:49:11 PM PDT 24
Peak memory 206996 kb
Host smart-b106b5ab-85b0-4e48-8ef2-16b1cca8ee61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671202726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2671202726
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1805859751
Short name T914
Test name
Test status
Simulation time 7801455643 ps
CPU time 11.48 seconds
Started Jul 16 07:49:12 PM PDT 24
Finished Jul 16 07:49:25 PM PDT 24
Peak memory 233948 kb
Host smart-23efd622-cd5c-4fcb-8da5-f5907b3f775e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805859751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1805859751
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2977526177
Short name T954
Test name
Test status
Simulation time 11670686 ps
CPU time 0.73 seconds
Started Jul 16 07:47:44 PM PDT 24
Finished Jul 16 07:47:47 PM PDT 24
Peak memory 206308 kb
Host smart-9115e086-bce9-4473-aa53-57d022e8a542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977526177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
977526177
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2858619433
Short name T697
Test name
Test status
Simulation time 394754156 ps
CPU time 3.95 seconds
Started Jul 16 07:47:47 PM PDT 24
Finished Jul 16 07:47:52 PM PDT 24
Peak memory 233824 kb
Host smart-174743b2-ef08-4aa0-832e-f463e5df7ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858619433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2858619433
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2258715775
Short name T427
Test name
Test status
Simulation time 15487858 ps
CPU time 0.75 seconds
Started Jul 16 07:47:43 PM PDT 24
Finished Jul 16 07:47:45 PM PDT 24
Peak memory 206516 kb
Host smart-65eaf84e-2503-4d6a-a8c5-92beb3372020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258715775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2258715775
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2240572009
Short name T752
Test name
Test status
Simulation time 29922128406 ps
CPU time 90.35 seconds
Started Jul 16 07:47:45 PM PDT 24
Finished Jul 16 07:49:17 PM PDT 24
Peak memory 250244 kb
Host smart-74be2413-6700-47a3-8f89-dd76545c6430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240572009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2240572009
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2181337327
Short name T732
Test name
Test status
Simulation time 12207860221 ps
CPU time 78.33 seconds
Started Jul 16 07:47:45 PM PDT 24
Finished Jul 16 07:49:05 PM PDT 24
Peak memory 250364 kb
Host smart-9ce28420-727c-4f7b-92cf-40ff21105e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181337327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2181337327
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3903836977
Short name T937
Test name
Test status
Simulation time 26177972911 ps
CPU time 241.09 seconds
Started Jul 16 07:47:47 PM PDT 24
Finished Jul 16 07:51:50 PM PDT 24
Peak memory 236328 kb
Host smart-07051b98-1528-44c1-97e5-8c096a0e81f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903836977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3903836977
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2907252518
Short name T779
Test name
Test status
Simulation time 58656638 ps
CPU time 2.67 seconds
Started Jul 16 07:47:48 PM PDT 24
Finished Jul 16 07:47:52 PM PDT 24
Peak memory 233732 kb
Host smart-12c450da-42f6-4037-940d-4b554d3c3fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907252518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2907252518
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1398886035
Short name T848
Test name
Test status
Simulation time 17430289 ps
CPU time 0.82 seconds
Started Jul 16 07:47:46 PM PDT 24
Finished Jul 16 07:47:48 PM PDT 24
Peak memory 216944 kb
Host smart-29a1611b-2f75-4866-93de-669b78c8b76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398886035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1398886035
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.650426547
Short name T533
Test name
Test status
Simulation time 206673905 ps
CPU time 3.47 seconds
Started Jul 16 07:47:49 PM PDT 24
Finished Jul 16 07:47:54 PM PDT 24
Peak memory 225556 kb
Host smart-2c70bcfe-140c-409d-9412-1e923d052663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650426547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.650426547
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3127087229
Short name T288
Test name
Test status
Simulation time 44966294128 ps
CPU time 103.63 seconds
Started Jul 16 07:47:48 PM PDT 24
Finished Jul 16 07:49:33 PM PDT 24
Peak memory 249976 kb
Host smart-8d579ff3-aebb-45d5-9684-d7e7dc93cecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127087229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3127087229
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1704120769
Short name T815
Test name
Test status
Simulation time 67609708 ps
CPU time 1.02 seconds
Started Jul 16 07:47:44 PM PDT 24
Finished Jul 16 07:47:47 PM PDT 24
Peak memory 218932 kb
Host smart-075d24e0-a360-45a6-88db-d6426143f8e2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704120769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1704120769
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.4012065961
Short name T590
Test name
Test status
Simulation time 2740671420 ps
CPU time 5.09 seconds
Started Jul 16 07:47:46 PM PDT 24
Finished Jul 16 07:47:52 PM PDT 24
Peak memory 233912 kb
Host smart-41a0f9e7-56cc-4523-a28e-29464d0ecfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012065961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.4012065961
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.150822803
Short name T88
Test name
Test status
Simulation time 6356039921 ps
CPU time 18.64 seconds
Started Jul 16 07:47:42 PM PDT 24
Finished Jul 16 07:48:01 PM PDT 24
Peak memory 233900 kb
Host smart-7a2bef3a-8351-40ad-adf1-42b911b2303a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150822803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.150822803
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.4032347834
Short name T767
Test name
Test status
Simulation time 4785912147 ps
CPU time 13.2 seconds
Started Jul 16 07:47:44 PM PDT 24
Finished Jul 16 07:47:59 PM PDT 24
Peak memory 220272 kb
Host smart-5c353e93-76a3-4716-a81c-78a442d6133d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4032347834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.4032347834
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.808035430
Short name T79
Test name
Test status
Simulation time 138390083 ps
CPU time 0.99 seconds
Started Jul 16 07:47:45 PM PDT 24
Finished Jul 16 07:47:48 PM PDT 24
Peak memory 236284 kb
Host smart-f5d96d14-ed8a-4a80-b335-9b0f23f29cdf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808035430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.808035430
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3835862263
Short name T759
Test name
Test status
Simulation time 41945927147 ps
CPU time 528.78 seconds
Started Jul 16 07:47:45 PM PDT 24
Finished Jul 16 07:56:36 PM PDT 24
Peak memory 298840 kb
Host smart-34484b04-8fd2-42da-bd7f-6f975b66735f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835862263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3835862263
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3466103343
Short name T1021
Test name
Test status
Simulation time 48033849 ps
CPU time 0.73 seconds
Started Jul 16 07:47:42 PM PDT 24
Finished Jul 16 07:47:44 PM PDT 24
Peak memory 207156 kb
Host smart-a24aee51-f89b-4ce0-8c4e-31d06099a42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466103343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3466103343
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1816129083
Short name T541
Test name
Test status
Simulation time 21333843057 ps
CPU time 16.16 seconds
Started Jul 16 07:47:43 PM PDT 24
Finished Jul 16 07:48:01 PM PDT 24
Peak memory 217488 kb
Host smart-307b8c70-8dfd-4e10-858c-eb49adad358a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816129083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1816129083
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2333965446
Short name T710
Test name
Test status
Simulation time 11924093 ps
CPU time 0.71 seconds
Started Jul 16 07:47:52 PM PDT 24
Finished Jul 16 07:47:54 PM PDT 24
Peak memory 206512 kb
Host smart-64152096-1b62-4183-93b2-3c21dd39cb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333965446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2333965446
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2459769257
Short name T631
Test name
Test status
Simulation time 49625781 ps
CPU time 0.92 seconds
Started Jul 16 07:47:43 PM PDT 24
Finished Jul 16 07:47:46 PM PDT 24
Peak memory 206924 kb
Host smart-1e381adc-8b6e-45aa-ac90-61fae00bdde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459769257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2459769257
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.903785036
Short name T204
Test name
Test status
Simulation time 1088548394 ps
CPU time 9.08 seconds
Started Jul 16 07:47:49 PM PDT 24
Finished Jul 16 07:47:59 PM PDT 24
Peak memory 241756 kb
Host smart-83e65794-9138-442a-94e2-191cccd3624a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903785036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.903785036
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.790210813
Short name T355
Test name
Test status
Simulation time 12908448 ps
CPU time 0.73 seconds
Started Jul 16 07:49:24 PM PDT 24
Finished Jul 16 07:49:29 PM PDT 24
Peak memory 206392 kb
Host smart-90fc3135-0315-433a-ac99-1b4329831520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790210813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.790210813
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2677529079
Short name T764
Test name
Test status
Simulation time 295408842 ps
CPU time 3 seconds
Started Jul 16 07:49:09 PM PDT 24
Finished Jul 16 07:49:15 PM PDT 24
Peak memory 233728 kb
Host smart-f441da14-a621-4013-8773-e629770749ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677529079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2677529079
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.4259789191
Short name T647
Test name
Test status
Simulation time 28603499 ps
CPU time 0.77 seconds
Started Jul 16 07:49:08 PM PDT 24
Finished Jul 16 07:49:10 PM PDT 24
Peak memory 207872 kb
Host smart-6fe50663-252e-4f2e-a67e-6724eb753612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259789191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.4259789191
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3457418580
Short name T233
Test name
Test status
Simulation time 161302658479 ps
CPU time 201 seconds
Started Jul 16 07:49:23 PM PDT 24
Finished Jul 16 07:52:48 PM PDT 24
Peak memory 266504 kb
Host smart-9452e826-bc93-4862-a410-184a8f9cf213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457418580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3457418580
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3937514505
Short name T54
Test name
Test status
Simulation time 114735053 ps
CPU time 5.49 seconds
Started Jul 16 07:49:09 PM PDT 24
Finished Jul 16 07:49:16 PM PDT 24
Peak memory 233756 kb
Host smart-ce0e2a38-fd56-4118-9e82-5998c020b0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937514505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3937514505
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1940781500
Short name T510
Test name
Test status
Simulation time 4587968970 ps
CPU time 10.86 seconds
Started Jul 16 07:49:22 PM PDT 24
Finished Jul 16 07:49:37 PM PDT 24
Peak memory 233880 kb
Host smart-d0ce47e3-b20e-408f-b8b5-ba303103c290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940781500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1940781500
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3416049559
Short name T763
Test name
Test status
Simulation time 516445532 ps
CPU time 5.47 seconds
Started Jul 16 07:49:12 PM PDT 24
Finished Jul 16 07:49:19 PM PDT 24
Peak memory 233700 kb
Host smart-dc4db623-04a5-48ff-acda-304ef569b834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416049559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3416049559
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.48829066
Short name T57
Test name
Test status
Simulation time 2142877801 ps
CPU time 8.33 seconds
Started Jul 16 07:49:16 PM PDT 24
Finished Jul 16 07:49:25 PM PDT 24
Peak memory 233688 kb
Host smart-35907ff8-1a07-42ae-96a8-4c8460a4a83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48829066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.48829066
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2481615519
Short name T1025
Test name
Test status
Simulation time 3033327945 ps
CPU time 3.57 seconds
Started Jul 16 07:49:21 PM PDT 24
Finished Jul 16 07:49:26 PM PDT 24
Peak memory 225724 kb
Host smart-5af420f1-ffd5-48b2-83e3-41d95693d1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481615519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2481615519
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.319635268
Short name T585
Test name
Test status
Simulation time 134649280 ps
CPU time 3.81 seconds
Started Jul 16 07:49:22 PM PDT 24
Finished Jul 16 07:49:29 PM PDT 24
Peak memory 223592 kb
Host smart-a2b6f50f-bb25-451d-8f61-0299f50b5bbb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=319635268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.319635268
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3875470413
Short name T329
Test name
Test status
Simulation time 167339975126 ps
CPU time 189.04 seconds
Started Jul 16 07:49:22 PM PDT 24
Finished Jul 16 07:52:35 PM PDT 24
Peak memory 254116 kb
Host smart-f4511a8d-02b1-454d-8da5-2a14ffa6334c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875470413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3875470413
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2493242984
Short name T351
Test name
Test status
Simulation time 22892310635 ps
CPU time 27.62 seconds
Started Jul 16 07:49:08 PM PDT 24
Finished Jul 16 07:49:37 PM PDT 24
Peak memory 217396 kb
Host smart-89186536-8c70-4320-a7de-d45b6261e26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493242984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2493242984
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.296759983
Short name T566
Test name
Test status
Simulation time 240676351 ps
CPU time 1.62 seconds
Started Jul 16 07:49:09 PM PDT 24
Finished Jul 16 07:49:13 PM PDT 24
Peak memory 208888 kb
Host smart-b5e340fd-574e-479a-9943-30aaff4ba76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296759983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.296759983
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2489262138
Short name T456
Test name
Test status
Simulation time 2034291915 ps
CPU time 3.83 seconds
Started Jul 16 07:49:09 PM PDT 24
Finished Jul 16 07:49:15 PM PDT 24
Peak memory 217344 kb
Host smart-4ba84afb-e894-4a65-a96e-9021836e79f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489262138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2489262138
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.904774641
Short name T371
Test name
Test status
Simulation time 75215065 ps
CPU time 0.76 seconds
Started Jul 16 07:49:15 PM PDT 24
Finished Jul 16 07:49:17 PM PDT 24
Peak memory 207028 kb
Host smart-4b9e4133-030b-4075-9a53-b367e7ba21af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904774641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.904774641
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3843178289
Short name T1008
Test name
Test status
Simulation time 2421532456 ps
CPU time 10.94 seconds
Started Jul 16 07:49:13 PM PDT 24
Finished Jul 16 07:49:25 PM PDT 24
Peak memory 233816 kb
Host smart-6760dde9-802f-47b1-a49b-fc6bb4a5e0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843178289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3843178289
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3552321317
Short name T637
Test name
Test status
Simulation time 33025763 ps
CPU time 0.8 seconds
Started Jul 16 07:49:22 PM PDT 24
Finished Jul 16 07:49:27 PM PDT 24
Peak memory 205776 kb
Host smart-6e3a05df-eb3d-4a88-963a-d168e1f593e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552321317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3552321317
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3936375443
Short name T594
Test name
Test status
Simulation time 1914207443 ps
CPU time 19.32 seconds
Started Jul 16 07:49:22 PM PDT 24
Finished Jul 16 07:49:45 PM PDT 24
Peak memory 225488 kb
Host smart-8f39761c-0e4b-46aa-846d-418867053215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936375443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3936375443
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3583470676
Short name T761
Test name
Test status
Simulation time 15812156 ps
CPU time 0.8 seconds
Started Jul 16 07:49:22 PM PDT 24
Finished Jul 16 07:49:26 PM PDT 24
Peak memory 207476 kb
Host smart-452444dd-6606-4c4d-9d46-c6333d23d91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583470676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3583470676
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3862842336
Short name T61
Test name
Test status
Simulation time 3943415683 ps
CPU time 69.03 seconds
Started Jul 16 07:49:23 PM PDT 24
Finished Jul 16 07:50:36 PM PDT 24
Peak memory 250400 kb
Host smart-dd37105b-0ede-4f8d-b1e7-0d5857f55e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862842336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3862842336
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3151782695
Short name T309
Test name
Test status
Simulation time 5677332635 ps
CPU time 56.85 seconds
Started Jul 16 07:49:20 PM PDT 24
Finished Jul 16 07:50:17 PM PDT 24
Peak memory 255248 kb
Host smart-f517f9f2-a95f-4b68-a3b2-abfaf6151406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151782695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3151782695
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.958777914
Short name T335
Test name
Test status
Simulation time 6691707453 ps
CPU time 13.27 seconds
Started Jul 16 07:49:22 PM PDT 24
Finished Jul 16 07:49:38 PM PDT 24
Peak memory 242296 kb
Host smart-784dc6a9-87e8-443c-83e1-3347a81b4e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958777914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.958777914
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2758486704
Short name T488
Test name
Test status
Simulation time 1133129554 ps
CPU time 7.81 seconds
Started Jul 16 07:49:27 PM PDT 24
Finished Jul 16 07:49:37 PM PDT 24
Peak memory 224968 kb
Host smart-938b1871-9102-4a9b-95a7-61859431963d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758486704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2758486704
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2376253238
Short name T919
Test name
Test status
Simulation time 6894527693 ps
CPU time 25.32 seconds
Started Jul 16 07:49:21 PM PDT 24
Finished Jul 16 07:49:47 PM PDT 24
Peak memory 233848 kb
Host smart-4f4200b0-004b-4c94-b1e1-8a4599f0012f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376253238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2376253238
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1892834068
Short name T545
Test name
Test status
Simulation time 281172580 ps
CPU time 3.08 seconds
Started Jul 16 07:49:23 PM PDT 24
Finished Jul 16 07:49:30 PM PDT 24
Peak memory 233744 kb
Host smart-84c04ead-3f3b-4566-879b-43f8534d0e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892834068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1892834068
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3411197131
Short name T116
Test name
Test status
Simulation time 2928378443 ps
CPU time 12.17 seconds
Started Jul 16 07:49:21 PM PDT 24
Finished Jul 16 07:49:36 PM PDT 24
Peak memory 250292 kb
Host smart-1287f3a4-c5e6-474f-a3c2-b818d6c9adf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411197131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3411197131
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1961913224
Short name T419
Test name
Test status
Simulation time 1521724356 ps
CPU time 4.81 seconds
Started Jul 16 07:49:22 PM PDT 24
Finished Jul 16 07:49:30 PM PDT 24
Peak memory 221488 kb
Host smart-ea604044-586b-40ab-8a8c-6c3f667a9730
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1961913224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1961913224
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.4224976267
Short name T795
Test name
Test status
Simulation time 8851987386 ps
CPU time 109.15 seconds
Started Jul 16 07:49:24 PM PDT 24
Finished Jul 16 07:51:17 PM PDT 24
Peak memory 253704 kb
Host smart-2abf907b-70ad-4514-a01f-a038e9959c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224976267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.4224976267
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3053669982
Short name T808
Test name
Test status
Simulation time 7491384174 ps
CPU time 5.79 seconds
Started Jul 16 07:49:22 PM PDT 24
Finished Jul 16 07:49:32 PM PDT 24
Peak memory 217624 kb
Host smart-82f319be-e786-471d-a529-3fc860a54f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053669982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3053669982
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1687445200
Short name T952
Test name
Test status
Simulation time 7572006517 ps
CPU time 11.14 seconds
Started Jul 16 07:49:20 PM PDT 24
Finished Jul 16 07:49:32 PM PDT 24
Peak memory 217508 kb
Host smart-243a20f8-d5f2-4f07-866a-21ea71d2914b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687445200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1687445200
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3051016601
Short name T417
Test name
Test status
Simulation time 104236100 ps
CPU time 1.07 seconds
Started Jul 16 07:49:21 PM PDT 24
Finished Jul 16 07:49:25 PM PDT 24
Peak memory 209000 kb
Host smart-be367ff5-56b2-4047-8a36-3efce4edbb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051016601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3051016601
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.816909445
Short name T358
Test name
Test status
Simulation time 67696190 ps
CPU time 0.88 seconds
Started Jul 16 07:49:29 PM PDT 24
Finished Jul 16 07:49:31 PM PDT 24
Peak memory 207008 kb
Host smart-4b77a13e-9d1e-490c-ba85-b53d18c2e668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816909445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.816909445
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2520290470
Short name T822
Test name
Test status
Simulation time 2342176741 ps
CPU time 4.84 seconds
Started Jul 16 07:49:22 PM PDT 24
Finished Jul 16 07:49:31 PM PDT 24
Peak memory 233916 kb
Host smart-cace0edb-7ace-44ae-b882-d51ddba29f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520290470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2520290470
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2221860514
Short name T443
Test name
Test status
Simulation time 38079876 ps
CPU time 0.72 seconds
Started Jul 16 07:49:21 PM PDT 24
Finished Jul 16 07:49:24 PM PDT 24
Peak memory 206384 kb
Host smart-f282883c-c760-46ae-a701-4f875ce396e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221860514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2221860514
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.4143032961
Short name T201
Test name
Test status
Simulation time 713578652 ps
CPU time 2.35 seconds
Started Jul 16 07:49:23 PM PDT 24
Finished Jul 16 07:49:30 PM PDT 24
Peak memory 225508 kb
Host smart-7d27e970-cbac-4522-b668-ad8c1c214f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143032961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.4143032961
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3184367217
Short name T76
Test name
Test status
Simulation time 36915065 ps
CPU time 0.79 seconds
Started Jul 16 07:49:20 PM PDT 24
Finished Jul 16 07:49:22 PM PDT 24
Peak memory 207516 kb
Host smart-922c7872-f6b0-4726-92a7-88401f0a574a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184367217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3184367217
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2554326707
Short name T90
Test name
Test status
Simulation time 343923578299 ps
CPU time 351.54 seconds
Started Jul 16 07:49:23 PM PDT 24
Finished Jul 16 07:55:19 PM PDT 24
Peak memory 257080 kb
Host smart-1d554ce3-bf21-42b3-88bf-291cb3fbc92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554326707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2554326707
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1626911720
Short name T428
Test name
Test status
Simulation time 553847815 ps
CPU time 4.84 seconds
Started Jul 16 07:49:27 PM PDT 24
Finished Jul 16 07:49:34 PM PDT 24
Peak memory 225476 kb
Host smart-770cdc2c-b30f-4b07-bca1-43e86123f656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626911720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1626911720
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.4120786284
Short name T292
Test name
Test status
Simulation time 9861716417 ps
CPU time 23.43 seconds
Started Jul 16 07:49:21 PM PDT 24
Finished Jul 16 07:49:46 PM PDT 24
Peak memory 252256 kb
Host smart-60c373b8-8c92-416e-ad95-4ced11f85197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120786284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.4120786284
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3647748424
Short name T238
Test name
Test status
Simulation time 3264009291 ps
CPU time 14.58 seconds
Started Jul 16 07:49:23 PM PDT 24
Finished Jul 16 07:49:42 PM PDT 24
Peak memory 225612 kb
Host smart-91bdf66a-2894-426a-9268-b7982217dd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647748424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3647748424
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3338356227
Short name T785
Test name
Test status
Simulation time 575894991 ps
CPU time 5.11 seconds
Started Jul 16 07:49:23 PM PDT 24
Finished Jul 16 07:49:32 PM PDT 24
Peak memory 225504 kb
Host smart-d5bcbfd2-9d9b-40c8-b350-1e8681e1d0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338356227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3338356227
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2595233470
Short name T743
Test name
Test status
Simulation time 2683859737 ps
CPU time 9.54 seconds
Started Jul 16 07:49:22 PM PDT 24
Finished Jul 16 07:49:36 PM PDT 24
Peak memory 233900 kb
Host smart-27a826b5-0930-4426-b5f9-732236373223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595233470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2595233470
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.838769597
Short name T893
Test name
Test status
Simulation time 416496141 ps
CPU time 9.39 seconds
Started Jul 16 07:49:21 PM PDT 24
Finished Jul 16 07:49:32 PM PDT 24
Peak memory 241840 kb
Host smart-55ea6d9f-5aaf-41ab-b2df-0bf11fd91af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838769597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.838769597
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2507516112
Short name T162
Test name
Test status
Simulation time 1083767953 ps
CPU time 4.33 seconds
Started Jul 16 07:49:23 PM PDT 24
Finished Jul 16 07:49:31 PM PDT 24
Peak memory 221124 kb
Host smart-1ff784ea-a122-4ee6-9f13-fa6a8ae23b24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2507516112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2507516112
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3104190315
Short name T21
Test name
Test status
Simulation time 159323534 ps
CPU time 1.11 seconds
Started Jul 16 07:49:24 PM PDT 24
Finished Jul 16 07:49:29 PM PDT 24
Peak memory 208136 kb
Host smart-267cdda5-22e1-49dd-90ee-f21963f9c3b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104190315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3104190315
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2798891320
Short name T926
Test name
Test status
Simulation time 6986545393 ps
CPU time 40.02 seconds
Started Jul 16 07:49:21 PM PDT 24
Finished Jul 16 07:50:04 PM PDT 24
Peak memory 217556 kb
Host smart-a11ff289-96ac-48cc-85db-898a6228f2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798891320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2798891320
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3872182721
Short name T404
Test name
Test status
Simulation time 797898870 ps
CPU time 1.95 seconds
Started Jul 16 07:49:21 PM PDT 24
Finished Jul 16 07:49:26 PM PDT 24
Peak memory 208892 kb
Host smart-6c9e01a9-efc4-44c4-a164-67eae6a7a064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872182721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3872182721
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.966632028
Short name T685
Test name
Test status
Simulation time 50450411 ps
CPU time 1.37 seconds
Started Jul 16 07:49:23 PM PDT 24
Finished Jul 16 07:49:28 PM PDT 24
Peak memory 217452 kb
Host smart-9ed5c621-6c6f-4ba0-ab57-0e0f80b7b2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966632028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.966632028
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2483712378
Short name T599
Test name
Test status
Simulation time 91333893 ps
CPU time 0.88 seconds
Started Jul 16 07:49:22 PM PDT 24
Finished Jul 16 07:49:27 PM PDT 24
Peak memory 206988 kb
Host smart-105a9c5d-74e4-4f11-9415-ada08ddb1236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483712378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2483712378
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1134823944
Short name T929
Test name
Test status
Simulation time 312870774 ps
CPU time 2.4 seconds
Started Jul 16 07:49:27 PM PDT 24
Finished Jul 16 07:49:32 PM PDT 24
Peak memory 224632 kb
Host smart-8db5f9c2-bc34-40ba-ac4f-8928e6d49a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134823944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1134823944
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3120447793
Short name T356
Test name
Test status
Simulation time 146717413 ps
CPU time 0.71 seconds
Started Jul 16 07:49:34 PM PDT 24
Finished Jul 16 07:49:35 PM PDT 24
Peak memory 205776 kb
Host smart-53ac34d6-2465-4b4f-993f-7c4cc567cd06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120447793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3120447793
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3860953358
Short name T584
Test name
Test status
Simulation time 4624301509 ps
CPU time 10.46 seconds
Started Jul 16 07:49:36 PM PDT 24
Finished Jul 16 07:49:49 PM PDT 24
Peak memory 233852 kb
Host smart-3b454f88-8d4d-4098-8089-2d35f134698c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860953358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3860953358
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1791397432
Short name T460
Test name
Test status
Simulation time 123250335 ps
CPU time 0.75 seconds
Started Jul 16 07:49:23 PM PDT 24
Finished Jul 16 07:49:27 PM PDT 24
Peak memory 206792 kb
Host smart-a159829b-6326-484e-b401-8df979e429bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791397432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1791397432
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.75770365
Short name T235
Test name
Test status
Simulation time 17243800292 ps
CPU time 111.04 seconds
Started Jul 16 07:49:39 PM PDT 24
Finished Jul 16 07:51:31 PM PDT 24
Peak memory 270104 kb
Host smart-2165f134-8983-4f97-a62f-79249860d9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75770365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.75770365
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.630361194
Short name T154
Test name
Test status
Simulation time 38615003172 ps
CPU time 227.15 seconds
Started Jul 16 07:49:34 PM PDT 24
Finished Jul 16 07:53:23 PM PDT 24
Peak memory 266848 kb
Host smart-db57947b-13b8-4331-b74f-e75ce7e6002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630361194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.630361194
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3539668055
Short name T326
Test name
Test status
Simulation time 27205993533 ps
CPU time 49.28 seconds
Started Jul 16 07:49:36 PM PDT 24
Finished Jul 16 07:50:28 PM PDT 24
Peak memory 233996 kb
Host smart-2169f15c-1783-4958-a194-118bb981ef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539668055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3539668055
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2441408202
Short name T1002
Test name
Test status
Simulation time 1865374414 ps
CPU time 10.03 seconds
Started Jul 16 07:49:38 PM PDT 24
Finished Jul 16 07:49:50 PM PDT 24
Peak memory 233744 kb
Host smart-9a9df757-4572-4d7c-96aa-20d4b6a964b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441408202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2441408202
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1655912458
Short name T89
Test name
Test status
Simulation time 30485188 ps
CPU time 0.71 seconds
Started Jul 16 07:49:41 PM PDT 24
Finished Jul 16 07:49:42 PM PDT 24
Peak memory 216856 kb
Host smart-1314ff4e-af30-4a3c-bb4a-8bf299a5889e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655912458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1655912458
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.45427815
Short name T969
Test name
Test status
Simulation time 385056759 ps
CPU time 3.24 seconds
Started Jul 16 07:49:36 PM PDT 24
Finished Jul 16 07:49:42 PM PDT 24
Peak memory 233772 kb
Host smart-3dd68d17-bc30-48f0-9137-1854932784d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45427815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.45427815
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.247922109
Short name T870
Test name
Test status
Simulation time 14601671881 ps
CPU time 42.8 seconds
Started Jul 16 07:49:34 PM PDT 24
Finished Jul 16 07:50:18 PM PDT 24
Peak memory 225708 kb
Host smart-a9072011-3707-4412-84b6-7677c6ec873e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247922109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.247922109
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2968861109
Short name T323
Test name
Test status
Simulation time 966414296 ps
CPU time 7.12 seconds
Started Jul 16 07:49:37 PM PDT 24
Finished Jul 16 07:49:46 PM PDT 24
Peak memory 225520 kb
Host smart-61c10375-e276-487d-86e7-a27c7e754721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968861109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2968861109
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4008771493
Short name T525
Test name
Test status
Simulation time 497344190 ps
CPU time 5.46 seconds
Started Jul 16 07:49:38 PM PDT 24
Finished Jul 16 07:49:45 PM PDT 24
Peak memory 236784 kb
Host smart-dbb688ca-1711-4ac3-b8bd-3dc1812f5e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008771493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4008771493
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1974749077
Short name T667
Test name
Test status
Simulation time 515525596 ps
CPU time 4.42 seconds
Started Jul 16 07:49:35 PM PDT 24
Finished Jul 16 07:49:41 PM PDT 24
Peak memory 224060 kb
Host smart-65893f5c-4b7d-478c-9da2-ea78025bf421
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1974749077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1974749077
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2213819990
Short name T912
Test name
Test status
Simulation time 39285155539 ps
CPU time 51.69 seconds
Started Jul 16 07:49:34 PM PDT 24
Finished Jul 16 07:50:26 PM PDT 24
Peak memory 240932 kb
Host smart-eff85d4c-5dc9-4475-9b0a-d1796d2aa744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213819990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2213819990
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.511825874
Short name T392
Test name
Test status
Simulation time 40613343 ps
CPU time 0.7 seconds
Started Jul 16 07:49:34 PM PDT 24
Finished Jul 16 07:49:35 PM PDT 24
Peak memory 206672 kb
Host smart-2a3deba5-d686-4e3e-9d3b-1cdad5223bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511825874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.511825874
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3173181172
Short name T423
Test name
Test status
Simulation time 12553032510 ps
CPU time 10.47 seconds
Started Jul 16 07:49:34 PM PDT 24
Finished Jul 16 07:49:45 PM PDT 24
Peak memory 217476 kb
Host smart-a18a0f24-431f-4a21-bb59-f614082ba4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173181172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3173181172
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.353256870
Short name T1017
Test name
Test status
Simulation time 663838176 ps
CPU time 3.31 seconds
Started Jul 16 07:49:38 PM PDT 24
Finished Jul 16 07:49:43 PM PDT 24
Peak memory 217348 kb
Host smart-48c2de9d-bb74-481f-9327-a88d9c3bf44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353256870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.353256870
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.552716471
Short name T841
Test name
Test status
Simulation time 65819977 ps
CPU time 0.78 seconds
Started Jul 16 07:49:38 PM PDT 24
Finished Jul 16 07:49:40 PM PDT 24
Peak memory 207008 kb
Host smart-f13095f6-ea8a-4db9-a8f7-adfa9b875986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552716471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.552716471
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.433305472
Short name T888
Test name
Test status
Simulation time 5633663976 ps
CPU time 20.31 seconds
Started Jul 16 07:49:36 PM PDT 24
Finished Jul 16 07:49:59 PM PDT 24
Peak memory 225652 kb
Host smart-c46ed642-560e-433e-816a-5d8670825e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433305472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.433305472
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.242108503
Short name T677
Test name
Test status
Simulation time 13670639 ps
CPU time 0.75 seconds
Started Jul 16 07:49:38 PM PDT 24
Finished Jul 16 07:49:41 PM PDT 24
Peak memory 205764 kb
Host smart-def6870a-882e-4e7c-a9de-68b64d1072de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242108503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.242108503
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.416214930
Short name T866
Test name
Test status
Simulation time 95091983 ps
CPU time 2.16 seconds
Started Jul 16 07:49:35 PM PDT 24
Finished Jul 16 07:49:38 PM PDT 24
Peak memory 225164 kb
Host smart-c12af540-b3ff-458d-b991-13d48a814c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416214930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.416214930
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2278035712
Short name T1005
Test name
Test status
Simulation time 19111527 ps
CPU time 0.79 seconds
Started Jul 16 07:49:36 PM PDT 24
Finished Jul 16 07:49:39 PM PDT 24
Peak memory 207488 kb
Host smart-17d1efd6-e2d6-48be-b425-0e05ad65ae8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278035712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2278035712
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2631401613
Short name T678
Test name
Test status
Simulation time 2821964948 ps
CPU time 26.47 seconds
Started Jul 16 07:49:38 PM PDT 24
Finished Jul 16 07:50:06 PM PDT 24
Peak memory 236876 kb
Host smart-b6bc9cc7-093b-4b21-930c-d06173c1a6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631401613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2631401613
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2447867637
Short name T153
Test name
Test status
Simulation time 14709568777 ps
CPU time 74.4 seconds
Started Jul 16 07:49:37 PM PDT 24
Finished Jul 16 07:50:54 PM PDT 24
Peak memory 257268 kb
Host smart-904b40f4-cb11-4969-8ebe-eaa9c14aa953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447867637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2447867637
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.209075876
Short name T284
Test name
Test status
Simulation time 193665818615 ps
CPU time 424.43 seconds
Started Jul 16 07:49:38 PM PDT 24
Finished Jul 16 07:56:44 PM PDT 24
Peak memory 258592 kb
Host smart-ed57ab25-0761-4dbb-bed7-4fea7458bd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209075876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.209075876
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3479290202
Short name T434
Test name
Test status
Simulation time 630669138 ps
CPU time 10.94 seconds
Started Jul 16 07:49:35 PM PDT 24
Finished Jul 16 07:49:48 PM PDT 24
Peak memory 234872 kb
Host smart-7ccbc274-b1ad-4b94-b1eb-eeb2704d19db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479290202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3479290202
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3250194456
Short name T852
Test name
Test status
Simulation time 11110271630 ps
CPU time 17.08 seconds
Started Jul 16 07:49:37 PM PDT 24
Finished Jul 16 07:49:56 PM PDT 24
Peak memory 251264 kb
Host smart-53be4f89-469f-49e0-9a7f-7a9fbab63dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250194456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3250194456
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1955230912
Short name T286
Test name
Test status
Simulation time 213331840 ps
CPU time 3.56 seconds
Started Jul 16 07:49:37 PM PDT 24
Finished Jul 16 07:49:43 PM PDT 24
Peak memory 225608 kb
Host smart-f4acc239-e8ed-4fc8-816f-5e17b8daeebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955230912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1955230912
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.4059614867
Short name T976
Test name
Test status
Simulation time 126234675 ps
CPU time 2.43 seconds
Started Jul 16 07:49:42 PM PDT 24
Finished Jul 16 07:49:45 PM PDT 24
Peak memory 225452 kb
Host smart-5157c102-31e5-4431-b677-3b92e236affc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059614867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.4059614867
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2960818223
Short name T845
Test name
Test status
Simulation time 5833421430 ps
CPU time 6.11 seconds
Started Jul 16 07:49:35 PM PDT 24
Finished Jul 16 07:49:44 PM PDT 24
Peak memory 233932 kb
Host smart-049f67cd-0fc0-49ab-8cfc-6747e2f6142f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960818223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2960818223
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2557523730
Short name T699
Test name
Test status
Simulation time 3304841142 ps
CPU time 4.93 seconds
Started Jul 16 07:49:36 PM PDT 24
Finished Jul 16 07:49:43 PM PDT 24
Peak memory 233900 kb
Host smart-b29b8f3f-ee21-40ee-859c-77b83cd211c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557523730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2557523730
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2172590984
Short name T713
Test name
Test status
Simulation time 179170803 ps
CPU time 3.82 seconds
Started Jul 16 07:49:39 PM PDT 24
Finished Jul 16 07:49:44 PM PDT 24
Peak memory 221472 kb
Host smart-95d2f73e-ea5c-477f-ab9d-cdaba110b050
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2172590984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2172590984
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.50936435
Short name T991
Test name
Test status
Simulation time 15983478495 ps
CPU time 25.49 seconds
Started Jul 16 07:49:35 PM PDT 24
Finished Jul 16 07:50:03 PM PDT 24
Peak memory 217544 kb
Host smart-be0a8215-8949-4025-9bc1-986d3415ba15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50936435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.50936435
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1639821268
Short name T890
Test name
Test status
Simulation time 2181821973 ps
CPU time 5.24 seconds
Started Jul 16 07:49:36 PM PDT 24
Finished Jul 16 07:49:43 PM PDT 24
Peak memory 217412 kb
Host smart-0fcda23c-b27d-4631-bd02-f33fca04b897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639821268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1639821268
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2827380419
Short name T935
Test name
Test status
Simulation time 772340267 ps
CPU time 2.35 seconds
Started Jul 16 07:49:36 PM PDT 24
Finished Jul 16 07:49:40 PM PDT 24
Peak memory 217368 kb
Host smart-19542e90-481f-4a19-a61c-594fd5988be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827380419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2827380419
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2988657735
Short name T897
Test name
Test status
Simulation time 104373330 ps
CPU time 0.83 seconds
Started Jul 16 07:49:34 PM PDT 24
Finished Jul 16 07:49:36 PM PDT 24
Peak memory 206928 kb
Host smart-bf741324-fe3c-4be2-8c16-e6d29b41876b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988657735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2988657735
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1742900228
Short name T899
Test name
Test status
Simulation time 1568371323 ps
CPU time 7.15 seconds
Started Jul 16 07:49:34 PM PDT 24
Finished Jul 16 07:49:43 PM PDT 24
Peak memory 241936 kb
Host smart-7d4c57a1-5abd-41f8-9878-9b689cfe5b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742900228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1742900228
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.703314262
Short name T835
Test name
Test status
Simulation time 15977549 ps
CPU time 0.76 seconds
Started Jul 16 07:49:51 PM PDT 24
Finished Jul 16 07:49:54 PM PDT 24
Peak memory 205880 kb
Host smart-2c4f9644-deeb-4c4e-9a59-94b9ada6bc98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703314262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.703314262
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1914652791
Short name T757
Test name
Test status
Simulation time 1970270804 ps
CPU time 13.82 seconds
Started Jul 16 07:49:52 PM PDT 24
Finished Jul 16 07:50:08 PM PDT 24
Peak memory 225604 kb
Host smart-47cc79ee-570f-4c93-8439-87dc95dae31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914652791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1914652791
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4193046326
Short name T756
Test name
Test status
Simulation time 34568772 ps
CPU time 0.77 seconds
Started Jul 16 07:49:38 PM PDT 24
Finished Jul 16 07:49:41 PM PDT 24
Peak memory 206520 kb
Host smart-8e907567-45fd-4ea0-afc0-4ae574ead0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193046326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4193046326
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1986495322
Short name T1024
Test name
Test status
Simulation time 30554534219 ps
CPU time 56.51 seconds
Started Jul 16 07:49:50 PM PDT 24
Finished Jul 16 07:50:47 PM PDT 24
Peak memory 236112 kb
Host smart-44317fd7-e13f-4f91-a183-7ff2820578ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986495322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1986495322
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.656250748
Short name T210
Test name
Test status
Simulation time 7616837159 ps
CPU time 106.36 seconds
Started Jul 16 07:49:50 PM PDT 24
Finished Jul 16 07:51:38 PM PDT 24
Peak memory 269376 kb
Host smart-a9683641-5b2c-42a5-a2f1-c25fbf859125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656250748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.656250748
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2941338279
Short name T63
Test name
Test status
Simulation time 5132152186 ps
CPU time 38.23 seconds
Started Jul 16 07:49:51 PM PDT 24
Finished Jul 16 07:50:31 PM PDT 24
Peak memory 250420 kb
Host smart-fa19712d-7c1f-4cb3-b425-cf7136c2c62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941338279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2941338279
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2341992271
Short name T633
Test name
Test status
Simulation time 5873565278 ps
CPU time 36.33 seconds
Started Jul 16 07:49:52 PM PDT 24
Finished Jul 16 07:50:30 PM PDT 24
Peak memory 238408 kb
Host smart-26111016-e7d8-4e53-8b11-6ff115b70f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341992271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2341992271
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1933397288
Short name T666
Test name
Test status
Simulation time 53360791397 ps
CPU time 222.8 seconds
Started Jul 16 07:49:51 PM PDT 24
Finished Jul 16 07:53:35 PM PDT 24
Peak memory 254700 kb
Host smart-e64a9666-aa26-4608-8003-ea3125be618e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933397288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1933397288
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.988062781
Short name T299
Test name
Test status
Simulation time 3595088170 ps
CPU time 10.07 seconds
Started Jul 16 07:49:38 PM PDT 24
Finished Jul 16 07:49:50 PM PDT 24
Peak memory 230952 kb
Host smart-7c176f3d-56c9-4bc8-bc33-0a55d5718687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988062781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.988062781
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1893162026
Short name T967
Test name
Test status
Simulation time 2067817269 ps
CPU time 20.78 seconds
Started Jul 16 07:49:36 PM PDT 24
Finished Jul 16 07:49:59 PM PDT 24
Peak memory 233728 kb
Host smart-2a644223-173f-4dbb-94c7-edda2afa9d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893162026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1893162026
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3419459866
Short name T792
Test name
Test status
Simulation time 10158036413 ps
CPU time 6.43 seconds
Started Jul 16 07:49:34 PM PDT 24
Finished Jul 16 07:49:42 PM PDT 24
Peak memory 225612 kb
Host smart-52c5e66b-9da9-4bbb-8839-c2f2f0c451a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419459866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3419459866
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3559059881
Short name T304
Test name
Test status
Simulation time 45259751910 ps
CPU time 10.23 seconds
Started Jul 16 07:49:37 PM PDT 24
Finished Jul 16 07:49:49 PM PDT 24
Peak memory 233828 kb
Host smart-7b0f288f-8942-4ca9-ad6e-2a2bcd0e29f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559059881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3559059881
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1666303665
Short name T812
Test name
Test status
Simulation time 1673521563 ps
CPU time 10.71 seconds
Started Jul 16 07:49:52 PM PDT 24
Finished Jul 16 07:50:05 PM PDT 24
Peak memory 219872 kb
Host smart-05d06022-667b-4fc2-8429-ebcf8301127b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1666303665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1666303665
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2533561861
Short name T296
Test name
Test status
Simulation time 27264855250 ps
CPU time 91.9 seconds
Started Jul 16 07:49:54 PM PDT 24
Finished Jul 16 07:51:27 PM PDT 24
Peak memory 258248 kb
Host smart-b024185d-b5fd-4521-b239-ef48298de654
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533561861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2533561861
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2590839704
Short name T695
Test name
Test status
Simulation time 7885395764 ps
CPU time 28.2 seconds
Started Jul 16 07:49:36 PM PDT 24
Finished Jul 16 07:50:07 PM PDT 24
Peak memory 217512 kb
Host smart-ae34a77a-edc8-4dcc-801a-e01e6e6422d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590839704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2590839704
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3210704202
Short name T411
Test name
Test status
Simulation time 1346262873 ps
CPU time 1.91 seconds
Started Jul 16 07:49:41 PM PDT 24
Finished Jul 16 07:49:44 PM PDT 24
Peak memory 208076 kb
Host smart-6464b44c-4140-4d51-b9d7-a91054ca3fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210704202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3210704202
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1542568642
Short name T377
Test name
Test status
Simulation time 110404330 ps
CPU time 1.8 seconds
Started Jul 16 07:49:36 PM PDT 24
Finished Jul 16 07:49:41 PM PDT 24
Peak memory 217308 kb
Host smart-3121374b-d766-4cdb-bb5f-750b9f79fc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542568642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1542568642
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1530456538
Short name T441
Test name
Test status
Simulation time 18643495 ps
CPU time 0.73 seconds
Started Jul 16 07:49:34 PM PDT 24
Finished Jul 16 07:49:36 PM PDT 24
Peak memory 206904 kb
Host smart-4f82b84f-0407-4739-9294-598df2c5dfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530456538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1530456538
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2454378837
Short name T615
Test name
Test status
Simulation time 4607251903 ps
CPU time 17.34 seconds
Started Jul 16 07:49:36 PM PDT 24
Finished Jul 16 07:49:56 PM PDT 24
Peak memory 233848 kb
Host smart-907078e3-b336-445b-a5b7-ba15e09628b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454378837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2454378837
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2349802898
Short name T574
Test name
Test status
Simulation time 11790006 ps
CPU time 0.74 seconds
Started Jul 16 07:49:51 PM PDT 24
Finished Jul 16 07:49:54 PM PDT 24
Peak memory 206368 kb
Host smart-63cff8f7-63ac-4f14-b627-e3fc462dc8ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349802898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2349802898
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1433233366
Short name T793
Test name
Test status
Simulation time 2054661330 ps
CPU time 5.84 seconds
Started Jul 16 07:49:53 PM PDT 24
Finished Jul 16 07:50:01 PM PDT 24
Peak memory 233736 kb
Host smart-875c1ca1-12ae-43bc-b5e7-3541ae0602e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433233366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1433233366
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1893443683
Short name T462
Test name
Test status
Simulation time 20390417 ps
CPU time 0.81 seconds
Started Jul 16 07:49:49 PM PDT 24
Finished Jul 16 07:49:51 PM PDT 24
Peak memory 207548 kb
Host smart-1730eebd-a4ad-45d3-aab2-be0ac7876825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893443683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1893443683
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2036452803
Short name T285
Test name
Test status
Simulation time 10188527788 ps
CPU time 129.56 seconds
Started Jul 16 07:49:50 PM PDT 24
Finished Jul 16 07:52:01 PM PDT 24
Peak memory 256836 kb
Host smart-99a218ce-3107-42b6-b739-8b0dfe1c76c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036452803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2036452803
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.4143804971
Short name T232
Test name
Test status
Simulation time 6999489337 ps
CPU time 104.13 seconds
Started Jul 16 07:49:51 PM PDT 24
Finished Jul 16 07:51:38 PM PDT 24
Peak memory 250680 kb
Host smart-64be5dd0-128e-4df4-9863-d7212da191f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143804971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.4143804971
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.525408923
Short name T579
Test name
Test status
Simulation time 209500521 ps
CPU time 5.8 seconds
Started Jul 16 07:49:47 PM PDT 24
Finished Jul 16 07:49:54 PM PDT 24
Peak memory 241996 kb
Host smart-4512a06a-2984-4ad8-b932-00da67031c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525408923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.525408923
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2060528477
Short name T64
Test name
Test status
Simulation time 68625990167 ps
CPU time 71.47 seconds
Started Jul 16 07:49:48 PM PDT 24
Finished Jul 16 07:51:00 PM PDT 24
Peak memory 251668 kb
Host smart-c5827e68-a0b7-4120-8263-af927947a533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060528477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2060528477
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4009708891
Short name T521
Test name
Test status
Simulation time 6980871065 ps
CPU time 16.22 seconds
Started Jul 16 07:49:51 PM PDT 24
Finished Jul 16 07:50:09 PM PDT 24
Peak memory 233876 kb
Host smart-6a49b733-968e-443e-b74b-bb043df77e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009708891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4009708891
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3256660767
Short name T689
Test name
Test status
Simulation time 17037589037 ps
CPU time 24.82 seconds
Started Jul 16 07:49:50 PM PDT 24
Finished Jul 16 07:50:16 PM PDT 24
Peak memory 236548 kb
Host smart-0524189f-65eb-4bb4-829a-03190ad16f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256660767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3256660767
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3416172278
Short name T529
Test name
Test status
Simulation time 157075114 ps
CPU time 2.85 seconds
Started Jul 16 07:49:49 PM PDT 24
Finished Jul 16 07:49:53 PM PDT 24
Peak memory 233720 kb
Host smart-aa4e4694-2702-4d08-be6f-7d5920e4b522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416172278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3416172278
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.200258246
Short name T702
Test name
Test status
Simulation time 304635592 ps
CPU time 3.06 seconds
Started Jul 16 07:49:51 PM PDT 24
Finished Jul 16 07:49:56 PM PDT 24
Peak memory 233800 kb
Host smart-b7e35396-92f4-40a0-822d-3b3f300ace24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200258246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.200258246
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1822964188
Short name T163
Test name
Test status
Simulation time 6604350429 ps
CPU time 18.78 seconds
Started Jul 16 07:49:49 PM PDT 24
Finished Jul 16 07:50:08 PM PDT 24
Peak memory 223748 kb
Host smart-b7bcf0f3-5b30-403a-a93c-ac9b5d1179ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1822964188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1822964188
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.227657483
Short name T972
Test name
Test status
Simulation time 6701934791 ps
CPU time 92.53 seconds
Started Jul 16 07:49:48 PM PDT 24
Finished Jul 16 07:51:21 PM PDT 24
Peak memory 256816 kb
Host smart-8dc30aec-7681-4b4a-ac18-6a82e0bc1ba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227657483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.227657483
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.639654752
Short name T29
Test name
Test status
Simulation time 5025536326 ps
CPU time 39.4 seconds
Started Jul 16 07:49:48 PM PDT 24
Finished Jul 16 07:50:28 PM PDT 24
Peak memory 217524 kb
Host smart-5048ba12-4c5e-4d7c-a427-cae0f20640ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639654752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.639654752
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.682807208
Short name T469
Test name
Test status
Simulation time 6861234616 ps
CPU time 20.27 seconds
Started Jul 16 07:49:52 PM PDT 24
Finished Jul 16 07:50:14 PM PDT 24
Peak memory 217508 kb
Host smart-e6407261-1699-4a45-85d9-acb5352a5c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682807208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.682807208
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.296194292
Short name T1019
Test name
Test status
Simulation time 78786359 ps
CPU time 1.4 seconds
Started Jul 16 07:49:53 PM PDT 24
Finished Jul 16 07:49:56 PM PDT 24
Peak memory 217308 kb
Host smart-4c440915-0c15-4ad3-9fa7-a53ecd2c340d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296194292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.296194292
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2652352555
Short name T938
Test name
Test status
Simulation time 88492865 ps
CPU time 0.89 seconds
Started Jul 16 07:49:52 PM PDT 24
Finished Jul 16 07:49:55 PM PDT 24
Peak memory 206924 kb
Host smart-4d56ace4-3b92-4f95-8e0f-6d425e64a572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652352555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2652352555
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3263804266
Short name T650
Test name
Test status
Simulation time 672084124 ps
CPU time 2.21 seconds
Started Jul 16 07:49:49 PM PDT 24
Finished Jul 16 07:49:52 PM PDT 24
Peak memory 225068 kb
Host smart-be152c33-28fd-436c-a231-2c64fcbefecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263804266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3263804266
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.109822744
Short name T396
Test name
Test status
Simulation time 13174262 ps
CPU time 0.77 seconds
Started Jul 16 07:49:51 PM PDT 24
Finished Jul 16 07:49:53 PM PDT 24
Peak memory 206336 kb
Host smart-ffb4faab-2703-4500-8da6-a07973d34af1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109822744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.109822744
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2725752728
Short name T265
Test name
Test status
Simulation time 1101974350 ps
CPU time 5.25 seconds
Started Jul 16 07:49:50 PM PDT 24
Finished Jul 16 07:49:56 PM PDT 24
Peak memory 233772 kb
Host smart-3b0bca26-af63-41da-8da4-43279d8cc8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725752728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2725752728
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1440302570
Short name T567
Test name
Test status
Simulation time 14873048 ps
CPU time 0.8 seconds
Started Jul 16 07:49:48 PM PDT 24
Finished Jul 16 07:49:50 PM PDT 24
Peak memory 207480 kb
Host smart-6a3d7718-35e2-4a1b-8050-e11baacbea47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440302570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1440302570
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.733229638
Short name T208
Test name
Test status
Simulation time 18187268878 ps
CPU time 116.6 seconds
Started Jul 16 07:49:51 PM PDT 24
Finished Jul 16 07:51:49 PM PDT 24
Peak memory 251416 kb
Host smart-0e676d12-9064-4c6a-a129-0318a94f9637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733229638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.733229638
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.168196517
Short name T728
Test name
Test status
Simulation time 9970198483 ps
CPU time 57.3 seconds
Started Jul 16 07:49:51 PM PDT 24
Finished Jul 16 07:50:50 PM PDT 24
Peak memory 258584 kb
Host smart-d995d194-c38e-4178-80b4-b3f799bc86cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168196517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.168196517
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1099674599
Short name T876
Test name
Test status
Simulation time 20637768502 ps
CPU time 138.24 seconds
Started Jul 16 07:49:50 PM PDT 24
Finished Jul 16 07:52:09 PM PDT 24
Peak memory 266036 kb
Host smart-30b9802f-5c21-4ea1-8965-02015644d53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099674599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1099674599
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.607907523
Short name T576
Test name
Test status
Simulation time 493150903 ps
CPU time 3.62 seconds
Started Jul 16 07:49:50 PM PDT 24
Finished Jul 16 07:49:54 PM PDT 24
Peak memory 233844 kb
Host smart-f0cd7623-0d7b-423d-a06a-96013496da0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607907523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.607907523
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1508646623
Short name T910
Test name
Test status
Simulation time 39001697 ps
CPU time 0.72 seconds
Started Jul 16 07:49:50 PM PDT 24
Finished Jul 16 07:49:53 PM PDT 24
Peak memory 216852 kb
Host smart-f87e296a-62c7-461e-aade-d8a624be1ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508646623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1508646623
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.326457382
Short name T705
Test name
Test status
Simulation time 909136531 ps
CPU time 4.74 seconds
Started Jul 16 07:49:50 PM PDT 24
Finished Jul 16 07:49:57 PM PDT 24
Peak memory 233736 kb
Host smart-f1623141-0fec-48bd-b5d0-c3d9e280a264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326457382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.326457382
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2053831691
Short name T302
Test name
Test status
Simulation time 948348114 ps
CPU time 17.23 seconds
Started Jul 16 07:49:48 PM PDT 24
Finished Jul 16 07:50:07 PM PDT 24
Peak memory 234984 kb
Host smart-3ce8cda8-4149-4512-8693-66189b33a13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053831691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2053831691
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3079875020
Short name T596
Test name
Test status
Simulation time 1126169955 ps
CPU time 8.56 seconds
Started Jul 16 07:49:51 PM PDT 24
Finished Jul 16 07:50:02 PM PDT 24
Peak memory 240608 kb
Host smart-28d54502-1770-4859-9e5c-9671495a70c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079875020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3079875020
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.799703358
Short name T464
Test name
Test status
Simulation time 2003082954 ps
CPU time 4.96 seconds
Started Jul 16 07:49:51 PM PDT 24
Finished Jul 16 07:49:58 PM PDT 24
Peak memory 233740 kb
Host smart-bad7ec3d-6367-45dd-81af-a1a16a1e382e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799703358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.799703358
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.924560944
Short name T486
Test name
Test status
Simulation time 1512110818 ps
CPU time 4.03 seconds
Started Jul 16 07:49:51 PM PDT 24
Finished Jul 16 07:49:58 PM PDT 24
Peak memory 219740 kb
Host smart-91136276-ea06-4e89-876e-faf60d71d5c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=924560944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.924560944
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2678540286
Short name T1001
Test name
Test status
Simulation time 29109056872 ps
CPU time 108.14 seconds
Started Jul 16 07:49:49 PM PDT 24
Finished Jul 16 07:51:38 PM PDT 24
Peak memory 250404 kb
Host smart-83e92d32-a32f-411d-b919-17596ecdbbc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678540286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2678540286
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1924895174
Short name T546
Test name
Test status
Simulation time 17126028368 ps
CPU time 16.23 seconds
Started Jul 16 07:49:51 PM PDT 24
Finished Jul 16 07:50:09 PM PDT 24
Peak memory 217624 kb
Host smart-cbd370de-42b7-4015-88d4-de520bc911de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924895174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1924895174
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.930181686
Short name T378
Test name
Test status
Simulation time 305436314 ps
CPU time 1.4 seconds
Started Jul 16 07:49:53 PM PDT 24
Finished Jul 16 07:49:56 PM PDT 24
Peak memory 208876 kb
Host smart-06d3a4ba-7b1d-4947-a3b7-ae5e1b375e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930181686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.930181686
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1290773920
Short name T82
Test name
Test status
Simulation time 988495760 ps
CPU time 3.12 seconds
Started Jul 16 07:49:48 PM PDT 24
Finished Jul 16 07:49:52 PM PDT 24
Peak memory 217344 kb
Host smart-4cad361e-180d-4dca-bfe0-d519469ee4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290773920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1290773920
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3331160268
Short name T366
Test name
Test status
Simulation time 288039853 ps
CPU time 0.99 seconds
Started Jul 16 07:49:54 PM PDT 24
Finished Jul 16 07:49:56 PM PDT 24
Peak memory 206800 kb
Host smart-22c2ad29-5892-4849-8cab-ab5649409554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331160268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3331160268
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.739090671
Short name T41
Test name
Test status
Simulation time 38368441982 ps
CPU time 31.87 seconds
Started Jul 16 07:49:50 PM PDT 24
Finished Jul 16 07:50:23 PM PDT 24
Peak memory 251924 kb
Host smart-236daf52-500e-4c0e-8552-f8b8d605db02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739090671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.739090671
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1224095621
Short name T613
Test name
Test status
Simulation time 12613849 ps
CPU time 0.72 seconds
Started Jul 16 07:50:07 PM PDT 24
Finished Jul 16 07:50:10 PM PDT 24
Peak memory 206368 kb
Host smart-4ef2fd79-a0e3-46a6-bcfe-076ce71bae53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224095621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1224095621
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1408132459
Short name T271
Test name
Test status
Simulation time 571000977 ps
CPU time 6.87 seconds
Started Jul 16 07:50:04 PM PDT 24
Finished Jul 16 07:50:13 PM PDT 24
Peak memory 225516 kb
Host smart-ba0202c6-c2ef-452b-a772-6fe3ae5f06cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408132459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1408132459
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1589281489
Short name T583
Test name
Test status
Simulation time 27400782 ps
CPU time 0.75 seconds
Started Jul 16 07:49:53 PM PDT 24
Finished Jul 16 07:49:55 PM PDT 24
Peak memory 207468 kb
Host smart-ea5b433a-abee-4a3a-9fb0-81dcf7b09d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589281489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1589281489
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2023100490
Short name T295
Test name
Test status
Simulation time 30296832004 ps
CPU time 103.68 seconds
Started Jul 16 07:50:07 PM PDT 24
Finished Jul 16 07:51:53 PM PDT 24
Peak memory 266244 kb
Host smart-5c529b8b-f1dd-443e-bc5c-06ff7336cdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023100490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2023100490
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1793897156
Short name T1007
Test name
Test status
Simulation time 46017265437 ps
CPU time 151.16 seconds
Started Jul 16 07:50:05 PM PDT 24
Finished Jul 16 07:52:38 PM PDT 24
Peak memory 257032 kb
Host smart-2001bf8e-afef-4cfd-b724-603cd7712219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793897156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1793897156
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.994937599
Short name T551
Test name
Test status
Simulation time 3324892813 ps
CPU time 14.38 seconds
Started Jul 16 07:50:03 PM PDT 24
Finished Jul 16 07:50:18 PM PDT 24
Peak memory 233972 kb
Host smart-6dbf1216-7cd9-443f-80cf-d056472fd0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994937599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.994937599
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3385529402
Short name T107
Test name
Test status
Simulation time 15788166131 ps
CPU time 125.49 seconds
Started Jul 16 07:50:05 PM PDT 24
Finished Jul 16 07:52:12 PM PDT 24
Peak memory 250260 kb
Host smart-fb68507b-ab41-416e-aec0-a7730c2cb831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385529402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3385529402
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1913071590
Short name T771
Test name
Test status
Simulation time 492802209 ps
CPU time 7.2 seconds
Started Jul 16 07:50:05 PM PDT 24
Finished Jul 16 07:50:13 PM PDT 24
Peak memory 233788 kb
Host smart-41838892-73b9-4477-909f-c7a6a121bdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913071590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1913071590
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.141516405
Short name T608
Test name
Test status
Simulation time 1565193875 ps
CPU time 5.7 seconds
Started Jul 16 07:50:09 PM PDT 24
Finished Jul 16 07:50:17 PM PDT 24
Peak memory 233720 kb
Host smart-7c3e9390-bd1e-45a0-9ced-50bd33caa1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141516405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.141516405
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2589224725
Short name T324
Test name
Test status
Simulation time 44167524 ps
CPU time 2.72 seconds
Started Jul 16 07:50:04 PM PDT 24
Finished Jul 16 07:50:08 PM PDT 24
Peak memory 233724 kb
Host smart-200ba53b-7e78-4ff4-9bcb-da334e75218f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589224725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2589224725
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.596471728
Short name T604
Test name
Test status
Simulation time 3176815741 ps
CPU time 8.91 seconds
Started Jul 16 07:50:03 PM PDT 24
Finished Jul 16 07:50:13 PM PDT 24
Peak memory 225732 kb
Host smart-fcf80654-44c5-4817-989c-ac6422c6539d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596471728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.596471728
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1920519419
Short name T602
Test name
Test status
Simulation time 200909042 ps
CPU time 3.87 seconds
Started Jul 16 07:50:04 PM PDT 24
Finished Jul 16 07:50:10 PM PDT 24
Peak memory 221332 kb
Host smart-062cc506-4d4b-422f-9490-3b94a1693580
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1920519419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1920519419
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3548351601
Short name T670
Test name
Test status
Simulation time 1688809424 ps
CPU time 17.15 seconds
Started Jul 16 07:50:07 PM PDT 24
Finished Jul 16 07:50:26 PM PDT 24
Peak memory 225788 kb
Host smart-6f11bbb0-f72c-4abf-812b-8e42e05749e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548351601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3548351601
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3435175640
Short name T587
Test name
Test status
Simulation time 1034511138 ps
CPU time 6.41 seconds
Started Jul 16 07:49:49 PM PDT 24
Finished Jul 16 07:49:56 PM PDT 24
Peak memory 219916 kb
Host smart-688b7865-7c98-4f33-8295-9b24bf41818d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435175640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3435175640
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.982282495
Short name T363
Test name
Test status
Simulation time 681594324 ps
CPU time 4.68 seconds
Started Jul 16 07:49:52 PM PDT 24
Finished Jul 16 07:49:59 PM PDT 24
Peak memory 217356 kb
Host smart-9d410817-a01b-4fa0-bd5d-bce9716d43d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982282495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.982282495
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3949713914
Short name T658
Test name
Test status
Simulation time 1788911016 ps
CPU time 3.11 seconds
Started Jul 16 07:50:08 PM PDT 24
Finished Jul 16 07:50:14 PM PDT 24
Peak memory 217220 kb
Host smart-b7f5a08f-116b-4cfc-9649-ad5e51ad82a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949713914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3949713914
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.4245016115
Short name T369
Test name
Test status
Simulation time 90267196 ps
CPU time 0.95 seconds
Started Jul 16 07:50:04 PM PDT 24
Finished Jul 16 07:50:06 PM PDT 24
Peak memory 206940 kb
Host smart-8a391599-719b-4ef1-b283-c5ca3d9f4251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245016115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.4245016115
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.496251310
Short name T617
Test name
Test status
Simulation time 236261486 ps
CPU time 2.25 seconds
Started Jul 16 07:50:07 PM PDT 24
Finished Jul 16 07:50:12 PM PDT 24
Peak memory 225212 kb
Host smart-7322fd83-2b19-41f9-9ecc-fde9ea33ee4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496251310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.496251310
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.4222963053
Short name T485
Test name
Test status
Simulation time 11784790 ps
CPU time 0.73 seconds
Started Jul 16 07:50:06 PM PDT 24
Finished Jul 16 07:50:08 PM PDT 24
Peak memory 206668 kb
Host smart-f3ce88eb-cdb1-428a-8e6c-2732aa7d350b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222963053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
4222963053
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.767982454
Short name T298
Test name
Test status
Simulation time 38095391 ps
CPU time 2.41 seconds
Started Jul 16 07:50:05 PM PDT 24
Finished Jul 16 07:50:09 PM PDT 24
Peak memory 233796 kb
Host smart-f55b8aa2-0001-4f81-b7f3-24ba4fd8ae49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767982454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.767982454
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3627034805
Short name T508
Test name
Test status
Simulation time 14771921 ps
CPU time 0.8 seconds
Started Jul 16 07:50:08 PM PDT 24
Finished Jul 16 07:50:11 PM PDT 24
Peak memory 207488 kb
Host smart-6467eb3c-6cfd-411f-9f3f-ad68580c830f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627034805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3627034805
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3759504739
Short name T67
Test name
Test status
Simulation time 1788011839 ps
CPU time 29.62 seconds
Started Jul 16 07:50:08 PM PDT 24
Finished Jul 16 07:50:41 PM PDT 24
Peak memory 251032 kb
Host smart-a5c2cc97-b71f-4aa3-b5df-62562d716d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759504739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3759504739
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2346740344
Short name T253
Test name
Test status
Simulation time 62140425035 ps
CPU time 150.85 seconds
Started Jul 16 07:50:08 PM PDT 24
Finished Jul 16 07:52:41 PM PDT 24
Peak memory 269432 kb
Host smart-11cb426d-5441-4426-89c8-facf0880a77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346740344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2346740344
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1529856570
Short name T220
Test name
Test status
Simulation time 100683989341 ps
CPU time 240.3 seconds
Started Jul 16 07:50:06 PM PDT 24
Finished Jul 16 07:54:08 PM PDT 24
Peak memory 253532 kb
Host smart-7924f2df-04eb-40f5-ba1a-7efc2c3e27db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529856570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1529856570
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1116571018
Short name T336
Test name
Test status
Simulation time 1001936531 ps
CPU time 21.04 seconds
Started Jul 16 07:50:07 PM PDT 24
Finished Jul 16 07:50:30 PM PDT 24
Peak memory 250648 kb
Host smart-359ec0fb-c5f0-47da-9fa0-3105dad19bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116571018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1116571018
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.423762507
Short name T308
Test name
Test status
Simulation time 13954359368 ps
CPU time 186.42 seconds
Started Jul 16 07:50:04 PM PDT 24
Finished Jul 16 07:53:11 PM PDT 24
Peak memory 283556 kb
Host smart-0553d23f-aa50-4f61-9de6-927ad553f892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423762507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.423762507
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3310355808
Short name T7
Test name
Test status
Simulation time 866459770 ps
CPU time 9.39 seconds
Started Jul 16 07:50:08 PM PDT 24
Finished Jul 16 07:50:19 PM PDT 24
Peak memory 225472 kb
Host smart-663c9a58-d57d-4595-9871-b89cf19435c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310355808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3310355808
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1420227662
Short name T278
Test name
Test status
Simulation time 1846655883 ps
CPU time 10.62 seconds
Started Jul 16 07:50:13 PM PDT 24
Finished Jul 16 07:50:25 PM PDT 24
Peak memory 225480 kb
Host smart-0ef3c49e-73f3-44a0-b574-7c0819befbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420227662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1420227662
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1596979267
Short name T977
Test name
Test status
Simulation time 4940922485 ps
CPU time 6.45 seconds
Started Jul 16 07:50:10 PM PDT 24
Finished Jul 16 07:50:19 PM PDT 24
Peak memory 225696 kb
Host smart-bc460ae4-0fb0-415e-a3c4-32878debd729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596979267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1596979267
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3068996245
Short name T231
Test name
Test status
Simulation time 104966894608 ps
CPU time 20.33 seconds
Started Jul 16 07:50:04 PM PDT 24
Finished Jul 16 07:50:25 PM PDT 24
Peak memory 238828 kb
Host smart-a350f08b-aa4a-45c3-9966-2fe7ed4856f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068996245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3068996245
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3085108783
Short name T531
Test name
Test status
Simulation time 595639513 ps
CPU time 9.79 seconds
Started Jul 16 07:50:08 PM PDT 24
Finished Jul 16 07:50:20 PM PDT 24
Peak memory 221500 kb
Host smart-09885fbe-7044-4566-9540-0cab0659e096
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3085108783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3085108783
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.4287701982
Short name T818
Test name
Test status
Simulation time 83537494 ps
CPU time 1.15 seconds
Started Jul 16 07:50:07 PM PDT 24
Finished Jul 16 07:50:10 PM PDT 24
Peak memory 208044 kb
Host smart-765a7023-fff3-4a8b-856d-c5caa08c9772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287701982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.4287701982
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3529696734
Short name T725
Test name
Test status
Simulation time 3243090022 ps
CPU time 13.14 seconds
Started Jul 16 07:50:04 PM PDT 24
Finished Jul 16 07:50:18 PM PDT 24
Peak memory 217580 kb
Host smart-d9e942b4-ebe4-49be-babd-edd1d03c30b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529696734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3529696734
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3275694057
Short name T649
Test name
Test status
Simulation time 1346966200 ps
CPU time 3.41 seconds
Started Jul 16 07:50:06 PM PDT 24
Finished Jul 16 07:50:11 PM PDT 24
Peak memory 217376 kb
Host smart-ed2c7b18-c80c-44e1-9f4a-38b09e9276de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275694057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3275694057
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3078918113
Short name T988
Test name
Test status
Simulation time 305855079 ps
CPU time 1.74 seconds
Started Jul 16 07:50:08 PM PDT 24
Finished Jul 16 07:50:12 PM PDT 24
Peak memory 217312 kb
Host smart-d567b67d-c331-47c2-8c0e-00fbe1d9721c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078918113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3078918113
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2064247170
Short name T873
Test name
Test status
Simulation time 52158677 ps
CPU time 0.78 seconds
Started Jul 16 07:50:05 PM PDT 24
Finished Jul 16 07:50:07 PM PDT 24
Peak memory 206908 kb
Host smart-233d23e9-64a5-4253-b51b-b59aac2d39e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064247170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2064247170
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3376124743
Short name T660
Test name
Test status
Simulation time 989211304 ps
CPU time 3.38 seconds
Started Jul 16 07:50:05 PM PDT 24
Finished Jul 16 07:50:10 PM PDT 24
Peak memory 233764 kb
Host smart-c6a055c3-72c3-4df7-8587-cc50e32bb979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376124743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3376124743
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3299051961
Short name T655
Test name
Test status
Simulation time 39889972 ps
CPU time 0.72 seconds
Started Jul 16 07:47:46 PM PDT 24
Finished Jul 16 07:47:48 PM PDT 24
Peak memory 206628 kb
Host smart-32d87bd7-21cf-4dba-9daa-fcefd2484325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299051961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
299051961
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1801012766
Short name T722
Test name
Test status
Simulation time 185294608 ps
CPU time 3.96 seconds
Started Jul 16 07:47:46 PM PDT 24
Finished Jul 16 07:47:51 PM PDT 24
Peak memory 225588 kb
Host smart-7063a96c-c50a-435f-8a69-863fc2b72fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801012766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1801012766
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.52497080
Short name T376
Test name
Test status
Simulation time 137183264 ps
CPU time 0.77 seconds
Started Jul 16 07:47:43 PM PDT 24
Finished Jul 16 07:47:44 PM PDT 24
Peak memory 207828 kb
Host smart-82b6cc0d-a4d7-4f1e-b88d-760f9694fd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52497080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.52497080
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2201846943
Short name T207
Test name
Test status
Simulation time 1620192939 ps
CPU time 15.13 seconds
Started Jul 16 07:47:42 PM PDT 24
Finished Jul 16 07:47:58 PM PDT 24
Peak memory 225588 kb
Host smart-88687017-44aa-4713-a007-2203f35f9f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201846943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2201846943
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3258271885
Short name T995
Test name
Test status
Simulation time 26377522469 ps
CPU time 72.01 seconds
Started Jul 16 07:47:44 PM PDT 24
Finished Jul 16 07:48:58 PM PDT 24
Peak memory 242024 kb
Host smart-26eb1f8f-c7c4-403f-abe9-96c965847c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258271885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3258271885
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.4150959644
Short name T225
Test name
Test status
Simulation time 158659301874 ps
CPU time 359.74 seconds
Started Jul 16 07:47:51 PM PDT 24
Finished Jul 16 07:53:52 PM PDT 24
Peak memory 253660 kb
Host smart-4c0f67ac-9481-4196-adfe-b0f74209ddc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150959644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.4150959644
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1425995817
Short name T370
Test name
Test status
Simulation time 57084508 ps
CPU time 2.8 seconds
Started Jul 16 07:47:43 PM PDT 24
Finished Jul 16 07:47:46 PM PDT 24
Peak memory 233740 kb
Host smart-00873d08-a1de-429e-9581-8b09d83c4799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425995817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1425995817
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.604703173
Short name T313
Test name
Test status
Simulation time 31405951797 ps
CPU time 275.02 seconds
Started Jul 16 07:47:44 PM PDT 24
Finished Jul 16 07:52:20 PM PDT 24
Peak memory 257036 kb
Host smart-b7685db2-0246-45fb-8afc-2fdf335b1c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604703173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
604703173
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2543842324
Short name T858
Test name
Test status
Simulation time 763129749 ps
CPU time 9.34 seconds
Started Jul 16 07:47:43 PM PDT 24
Finished Jul 16 07:47:54 PM PDT 24
Peak memory 233740 kb
Host smart-a24fed8c-0e14-4563-be4c-d6778e01e1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543842324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2543842324
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.791714997
Short name T787
Test name
Test status
Simulation time 145273299 ps
CPU time 5.82 seconds
Started Jul 16 07:47:45 PM PDT 24
Finished Jul 16 07:47:53 PM PDT 24
Peak memory 225544 kb
Host smart-0c13105e-5cb3-4934-b803-37dc4d038a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791714997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.791714997
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.391075588
Short name T407
Test name
Test status
Simulation time 34702417 ps
CPU time 1.17 seconds
Started Jul 16 07:47:52 PM PDT 24
Finished Jul 16 07:47:54 PM PDT 24
Peak memory 217608 kb
Host smart-67aa1ed3-47fd-4a5f-8e69-6a6f9ef048ac
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391075588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.391075588
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2607809248
Short name T598
Test name
Test status
Simulation time 13200345713 ps
CPU time 10.74 seconds
Started Jul 16 07:47:51 PM PDT 24
Finished Jul 16 07:48:03 PM PDT 24
Peak memory 233900 kb
Host smart-0d68517f-e5d7-484f-8593-13068d66022f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607809248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2607809248
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2554745397
Short name T272
Test name
Test status
Simulation time 1337437404 ps
CPU time 4.52 seconds
Started Jul 16 07:47:48 PM PDT 24
Finished Jul 16 07:47:53 PM PDT 24
Peak memory 225472 kb
Host smart-d36426d2-3bf5-4d5e-83e3-35513ca851f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554745397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2554745397
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.56737796
Short name T877
Test name
Test status
Simulation time 945865707 ps
CPU time 4.07 seconds
Started Jul 16 07:47:44 PM PDT 24
Finished Jul 16 07:47:50 PM PDT 24
Peak memory 219836 kb
Host smart-1940e91e-92fc-4d4b-bea7-0e428b7d9352
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=56737796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct
.56737796
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1660577017
Short name T22
Test name
Test status
Simulation time 319148051 ps
CPU time 1.19 seconds
Started Jul 16 07:47:44 PM PDT 24
Finished Jul 16 07:47:47 PM PDT 24
Peak memory 236404 kb
Host smart-abc6ce33-ca45-46ae-bfd5-6a03f418fb7b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660577017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1660577017
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1327614166
Short name T35
Test name
Test status
Simulation time 41584823327 ps
CPU time 412.55 seconds
Started Jul 16 07:47:45 PM PDT 24
Finished Jul 16 07:54:39 PM PDT 24
Peak memory 274032 kb
Host smart-06c01fc6-5e8d-4811-9b08-a238ff2e9545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327614166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1327614166
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.167978653
Short name T765
Test name
Test status
Simulation time 766915406 ps
CPU time 12.28 seconds
Started Jul 16 07:47:41 PM PDT 24
Finished Jul 16 07:47:54 PM PDT 24
Peak memory 220172 kb
Host smart-97c6d7e0-3b77-4bd0-859c-d7a3a654a699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167978653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.167978653
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3657341200
Short name T789
Test name
Test status
Simulation time 1769171517 ps
CPU time 4.62 seconds
Started Jul 16 07:47:45 PM PDT 24
Finished Jul 16 07:47:51 PM PDT 24
Peak memory 217344 kb
Host smart-1afb4396-7d12-4613-8631-e703c383a8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657341200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3657341200
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.796114204
Short name T352
Test name
Test status
Simulation time 481560898 ps
CPU time 2.41 seconds
Started Jul 16 07:47:43 PM PDT 24
Finished Jul 16 07:47:47 PM PDT 24
Peak memory 217420 kb
Host smart-78baac13-f20b-4c71-bd6d-5aaf993fa15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796114204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.796114204
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2346311401
Short name T791
Test name
Test status
Simulation time 199691405 ps
CPU time 0.87 seconds
Started Jul 16 07:47:49 PM PDT 24
Finished Jul 16 07:47:51 PM PDT 24
Peak memory 206972 kb
Host smart-2842b6cb-bc20-4783-a567-6cfdec8a82cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346311401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2346311401
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3802561311
Short name T803
Test name
Test status
Simulation time 48891501330 ps
CPU time 17.01 seconds
Started Jul 16 07:47:49 PM PDT 24
Finished Jul 16 07:48:08 PM PDT 24
Peak memory 233880 kb
Host smart-2fc3b694-621b-4ba5-82bc-978e6ec58183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802561311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3802561311
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.4228748148
Short name T735
Test name
Test status
Simulation time 29481519 ps
CPU time 0.76 seconds
Started Jul 16 07:50:08 PM PDT 24
Finished Jul 16 07:50:11 PM PDT 24
Peak memory 206332 kb
Host smart-d653ca16-df9a-4f8c-beef-4b2a77d880f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228748148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
4228748148
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2324415713
Short name T506
Test name
Test status
Simulation time 371570919 ps
CPU time 2.92 seconds
Started Jul 16 07:50:07 PM PDT 24
Finished Jul 16 07:50:12 PM PDT 24
Peak memory 233708 kb
Host smart-d6f1cbef-6f1a-4b32-aa35-7a66a274e805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324415713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2324415713
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1501392804
Short name T930
Test name
Test status
Simulation time 75390306 ps
CPU time 0.78 seconds
Started Jul 16 07:50:06 PM PDT 24
Finished Jul 16 07:50:09 PM PDT 24
Peak memory 207808 kb
Host smart-285e57a5-54f9-46c3-8826-42bc12cd0a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501392804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1501392804
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1406020160
Short name T851
Test name
Test status
Simulation time 53208825075 ps
CPU time 215.44 seconds
Started Jul 16 07:50:07 PM PDT 24
Finished Jul 16 07:53:45 PM PDT 24
Peak memory 253736 kb
Host smart-338631c1-73ae-466c-830b-32add3ec3b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406020160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1406020160
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3932190023
Short name T758
Test name
Test status
Simulation time 15821204488 ps
CPU time 86.55 seconds
Started Jul 16 07:50:07 PM PDT 24
Finished Jul 16 07:51:36 PM PDT 24
Peak memory 225808 kb
Host smart-b2c1f310-bcb1-480b-8f5b-169a8b2ef855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932190023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3932190023
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2447826042
Short name T537
Test name
Test status
Simulation time 3196239241 ps
CPU time 11.99 seconds
Started Jul 16 07:50:05 PM PDT 24
Finished Jul 16 07:50:19 PM PDT 24
Peak memory 225680 kb
Host smart-f2aec226-5f65-40ad-8beb-a8cd9b0c16c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447826042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2447826042
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2237015443
Short name T399
Test name
Test status
Simulation time 296773955 ps
CPU time 2.17 seconds
Started Jul 16 07:50:08 PM PDT 24
Finished Jul 16 07:50:12 PM PDT 24
Peak memory 224892 kb
Host smart-b55e64d7-e0f2-49c8-81cd-ea94d5fadc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237015443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2237015443
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1621209863
Short name T524
Test name
Test status
Simulation time 415465866 ps
CPU time 7.74 seconds
Started Jul 16 07:50:05 PM PDT 24
Finished Jul 16 07:50:14 PM PDT 24
Peak memory 233800 kb
Host smart-e3844042-d60a-4a0a-8830-a459af47bea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621209863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1621209863
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3861572951
Short name T322
Test name
Test status
Simulation time 718720411 ps
CPU time 3.92 seconds
Started Jul 16 07:50:06 PM PDT 24
Finished Jul 16 07:50:12 PM PDT 24
Peak memory 225588 kb
Host smart-f664dfae-2bc8-4aa4-b3fe-96e5e6586a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861572951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3861572951
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.550062107
Short name T414
Test name
Test status
Simulation time 140520065 ps
CPU time 2.15 seconds
Started Jul 16 07:50:06 PM PDT 24
Finished Jul 16 07:50:10 PM PDT 24
Peak memory 225236 kb
Host smart-b5957dcf-8ee5-44d7-bd91-ac92dd602c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550062107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.550062107
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3754001771
Short name T980
Test name
Test status
Simulation time 8774446464 ps
CPU time 8.25 seconds
Started Jul 16 07:50:08 PM PDT 24
Finished Jul 16 07:50:19 PM PDT 24
Peak memory 223520 kb
Host smart-b738cacd-2e61-4971-bb73-7de1b7a3013c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3754001771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3754001771
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1846037344
Short name T979
Test name
Test status
Simulation time 144062486344 ps
CPU time 312.99 seconds
Started Jul 16 07:50:05 PM PDT 24
Finished Jul 16 07:55:20 PM PDT 24
Peak memory 268548 kb
Host smart-ce79073a-a69b-472f-adaa-4d04476a8d9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846037344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1846037344
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.4058562294
Short name T680
Test name
Test status
Simulation time 5839340287 ps
CPU time 23.77 seconds
Started Jul 16 07:50:05 PM PDT 24
Finished Jul 16 07:50:31 PM PDT 24
Peak memory 217736 kb
Host smart-2bd737cf-fd59-47a4-a758-5395aa08c276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058562294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4058562294
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2768209640
Short name T398
Test name
Test status
Simulation time 3153667851 ps
CPU time 7.03 seconds
Started Jul 16 07:50:04 PM PDT 24
Finished Jul 16 07:50:12 PM PDT 24
Peak memory 217412 kb
Host smart-adfb4a8a-830a-4e73-8981-ec2414230b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768209640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2768209640
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2767189980
Short name T880
Test name
Test status
Simulation time 30212868 ps
CPU time 1.52 seconds
Started Jul 16 07:50:04 PM PDT 24
Finished Jul 16 07:50:07 PM PDT 24
Peak memory 217392 kb
Host smart-1b702fb0-dc28-441f-b0c7-0beda1aa19e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767189980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2767189980
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.372382010
Short name T755
Test name
Test status
Simulation time 79964872 ps
CPU time 0.89 seconds
Started Jul 16 07:50:08 PM PDT 24
Finished Jul 16 07:50:11 PM PDT 24
Peak memory 206944 kb
Host smart-615e7795-a620-4aac-8e2e-75d7b40315e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372382010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.372382010
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2789229189
Short name T734
Test name
Test status
Simulation time 1291694752 ps
CPU time 10.87 seconds
Started Jul 16 07:50:08 PM PDT 24
Finished Jul 16 07:50:21 PM PDT 24
Peak memory 233652 kb
Host smart-5ce90b83-1f62-4b9a-a1ad-37bb01b46db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789229189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2789229189
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1429310312
Short name T374
Test name
Test status
Simulation time 22520883 ps
CPU time 0.73 seconds
Started Jul 16 07:50:23 PM PDT 24
Finished Jul 16 07:50:25 PM PDT 24
Peak memory 205776 kb
Host smart-53b0f3bb-5334-4a53-ac87-9d10eb158cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429310312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1429310312
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2272123737
Short name T840
Test name
Test status
Simulation time 199563804 ps
CPU time 2.34 seconds
Started Jul 16 07:50:13 PM PDT 24
Finished Jul 16 07:50:17 PM PDT 24
Peak memory 225544 kb
Host smart-cbcf10a9-2817-486e-98a7-e172048b444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272123737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2272123737
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3355238227
Short name T528
Test name
Test status
Simulation time 54604786 ps
CPU time 0.76 seconds
Started Jul 16 07:50:03 PM PDT 24
Finished Jul 16 07:50:05 PM PDT 24
Peak memory 207560 kb
Host smart-84e309c1-a70a-43f2-a096-b1860c6d47ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355238227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3355238227
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2628098638
Short name T491
Test name
Test status
Simulation time 22208833 ps
CPU time 0.74 seconds
Started Jul 16 07:50:22 PM PDT 24
Finished Jul 16 07:50:24 PM PDT 24
Peak memory 216932 kb
Host smart-92bea0d7-c94d-4451-a715-079b766be1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628098638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2628098638
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1031419040
Short name T2
Test name
Test status
Simulation time 30766568206 ps
CPU time 23.89 seconds
Started Jul 16 07:50:12 PM PDT 24
Finished Jul 16 07:50:37 PM PDT 24
Peak memory 233948 kb
Host smart-f3d804f7-4da0-4bbe-863a-16921704b094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031419040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1031419040
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1763669143
Short name T783
Test name
Test status
Simulation time 300057412983 ps
CPU time 163.29 seconds
Started Jul 16 07:50:09 PM PDT 24
Finished Jul 16 07:52:55 PM PDT 24
Peak memory 250308 kb
Host smart-efd427a9-1b5a-4e73-830e-1275c2a44d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763669143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1763669143
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3044649494
Short name T802
Test name
Test status
Simulation time 30642768 ps
CPU time 2.67 seconds
Started Jul 16 07:50:10 PM PDT 24
Finished Jul 16 07:50:15 PM PDT 24
Peak memory 233560 kb
Host smart-03a213ee-5edc-413f-bc71-43327dbf5300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044649494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3044649494
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3086096800
Short name T305
Test name
Test status
Simulation time 681223626 ps
CPU time 14.19 seconds
Started Jul 16 07:50:13 PM PDT 24
Finished Jul 16 07:50:29 PM PDT 24
Peak memory 233752 kb
Host smart-42cc1e68-7c51-4bcb-848d-e2d8a9e70f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086096800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3086096800
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2840781908
Short name T28
Test name
Test status
Simulation time 2561452322 ps
CPU time 6.56 seconds
Started Jul 16 07:50:11 PM PDT 24
Finished Jul 16 07:50:20 PM PDT 24
Peak memory 225712 kb
Host smart-42d57b7a-cbef-4ebd-adba-49462d35a86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840781908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2840781908
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.380585270
Short name T582
Test name
Test status
Simulation time 5140695606 ps
CPU time 18.24 seconds
Started Jul 16 07:50:11 PM PDT 24
Finished Jul 16 07:50:31 PM PDT 24
Peak memory 233876 kb
Host smart-216d6c1a-c2b8-44ab-b96a-395b4040b199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380585270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.380585270
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3647905746
Short name T539
Test name
Test status
Simulation time 263628214 ps
CPU time 4.81 seconds
Started Jul 16 07:50:06 PM PDT 24
Finished Jul 16 07:50:13 PM PDT 24
Peak memory 220316 kb
Host smart-13c84436-428b-4799-83bc-88f6fc65c5d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3647905746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3647905746
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1459926719
Short name T44
Test name
Test status
Simulation time 61478683464 ps
CPU time 162.04 seconds
Started Jul 16 07:50:23 PM PDT 24
Finished Jul 16 07:53:06 PM PDT 24
Peak memory 272088 kb
Host smart-f1094a8d-1e9b-4e5d-a76d-7e117780da54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459926719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1459926719
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2446391051
Short name T450
Test name
Test status
Simulation time 4554535155 ps
CPU time 36.86 seconds
Started Jul 16 07:50:08 PM PDT 24
Finished Jul 16 07:50:47 PM PDT 24
Peak memory 217492 kb
Host smart-4e11d0e8-fe87-4d07-a7c4-e2f7be158df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446391051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2446391051
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2277071916
Short name T960
Test name
Test status
Simulation time 1767631967 ps
CPU time 3.45 seconds
Started Jul 16 07:50:07 PM PDT 24
Finished Jul 16 07:50:13 PM PDT 24
Peak memory 217344 kb
Host smart-5863a568-a3ef-4d73-bc39-468affb9fa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277071916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2277071916
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3414753567
Short name T349
Test name
Test status
Simulation time 15014459 ps
CPU time 0.82 seconds
Started Jul 16 07:50:11 PM PDT 24
Finished Jul 16 07:50:14 PM PDT 24
Peak memory 207596 kb
Host smart-4c547f51-8ca8-4505-ac5e-96d3959d9722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414753567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3414753567
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2623011761
Short name T12
Test name
Test status
Simulation time 19661304 ps
CPU time 0.72 seconds
Started Jul 16 07:50:12 PM PDT 24
Finished Jul 16 07:50:14 PM PDT 24
Peak memory 206972 kb
Host smart-42e4ceaf-2b18-4f45-8422-b26b61c7ce66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623011761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2623011761
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.546819422
Short name T718
Test name
Test status
Simulation time 278580237 ps
CPU time 5.56 seconds
Started Jul 16 07:50:11 PM PDT 24
Finished Jul 16 07:50:18 PM PDT 24
Peak memory 233712 kb
Host smart-54d88985-7364-42d8-8828-832f796d731b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546819422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.546819422
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3808609561
Short name T368
Test name
Test status
Simulation time 26432568 ps
CPU time 0.79 seconds
Started Jul 16 07:50:23 PM PDT 24
Finished Jul 16 07:50:25 PM PDT 24
Peak memory 205760 kb
Host smart-62be920d-1b90-4099-9120-4db4e091fd0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808609561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3808609561
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.850859495
Short name T507
Test name
Test status
Simulation time 5721018363 ps
CPU time 6.3 seconds
Started Jul 16 07:50:25 PM PDT 24
Finished Jul 16 07:50:33 PM PDT 24
Peak memory 225600 kb
Host smart-8780d24b-384b-47d7-826a-4d7f70a9eb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850859495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.850859495
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2058598183
Short name T871
Test name
Test status
Simulation time 54655689 ps
CPU time 0.76 seconds
Started Jul 16 07:50:24 PM PDT 24
Finished Jul 16 07:50:27 PM PDT 24
Peak memory 206480 kb
Host smart-1f0c8dbf-862f-459e-a6c1-108064112645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058598183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2058598183
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.4172416179
Short name T857
Test name
Test status
Simulation time 20906793478 ps
CPU time 135.1 seconds
Started Jul 16 07:50:24 PM PDT 24
Finished Jul 16 07:52:41 PM PDT 24
Peak memory 250332 kb
Host smart-20989e56-e6ea-4e7e-8259-161342adf199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172416179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.4172416179
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1459299630
Short name T15
Test name
Test status
Simulation time 5431931092 ps
CPU time 28.22 seconds
Started Jul 16 07:50:24 PM PDT 24
Finished Jul 16 07:50:55 PM PDT 24
Peak memory 240540 kb
Host smart-450cbed8-2011-44bd-a015-48ed8aa3fca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459299630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1459299630
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.74732186
Short name T971
Test name
Test status
Simulation time 1535152055 ps
CPU time 39.58 seconds
Started Jul 16 07:50:25 PM PDT 24
Finished Jul 16 07:51:07 PM PDT 24
Peak memory 249752 kb
Host smart-2eae41a9-de00-4ed4-a49e-87a829233af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74732186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.74732186
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.334097796
Short name T1020
Test name
Test status
Simulation time 1933227708 ps
CPU time 12.89 seconds
Started Jul 16 07:50:26 PM PDT 24
Finished Jul 16 07:50:41 PM PDT 24
Peak memory 238400 kb
Host smart-5bdab09e-6e4f-400a-b9f2-1668b11f1e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334097796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.334097796
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.564043480
Short name T586
Test name
Test status
Simulation time 8775989851 ps
CPU time 82.18 seconds
Started Jul 16 07:50:30 PM PDT 24
Finished Jul 16 07:51:53 PM PDT 24
Peak memory 250352 kb
Host smart-103f02c4-4ba6-42c2-addc-207155e0c591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564043480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.564043480
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3386445026
Short name T101
Test name
Test status
Simulation time 967871589 ps
CPU time 5.11 seconds
Started Jul 16 07:50:29 PM PDT 24
Finished Jul 16 07:50:35 PM PDT 24
Peak memory 225528 kb
Host smart-6a491941-ce65-4ddf-9232-37ace0584482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386445026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3386445026
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2048497474
Short name T104
Test name
Test status
Simulation time 842908665 ps
CPU time 17.15 seconds
Started Jul 16 07:50:24 PM PDT 24
Finished Jul 16 07:50:44 PM PDT 24
Peak memory 237012 kb
Host smart-47e21717-6ff9-4188-8bc8-bf7b9391254f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048497474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2048497474
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1040942698
Short name T983
Test name
Test status
Simulation time 3570111005 ps
CPU time 6.04 seconds
Started Jul 16 07:50:25 PM PDT 24
Finished Jul 16 07:50:33 PM PDT 24
Peak memory 241104 kb
Host smart-a723c1c9-cf1e-418a-abcf-412f6b6c32ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040942698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1040942698
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3613349004
Short name T726
Test name
Test status
Simulation time 110013565 ps
CPU time 2.31 seconds
Started Jul 16 07:50:25 PM PDT 24
Finished Jul 16 07:50:30 PM PDT 24
Peak memory 233528 kb
Host smart-5ece9df7-901e-45c4-a88c-3c602c22daff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613349004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3613349004
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3124999993
Short name T817
Test name
Test status
Simulation time 451443211 ps
CPU time 3.52 seconds
Started Jul 16 07:50:23 PM PDT 24
Finished Jul 16 07:50:28 PM PDT 24
Peak memory 223876 kb
Host smart-a48bfdf5-32f4-4a38-9421-afae64e5908e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3124999993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3124999993
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.4011421259
Short name T864
Test name
Test status
Simulation time 137864604 ps
CPU time 1.02 seconds
Started Jul 16 07:50:28 PM PDT 24
Finished Jul 16 07:50:31 PM PDT 24
Peak memory 208080 kb
Host smart-9ea7b21c-3596-437d-9321-b59a4bbb4f37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011421259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.4011421259
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.86517058
Short name T671
Test name
Test status
Simulation time 7957914496 ps
CPU time 51.44 seconds
Started Jul 16 07:50:23 PM PDT 24
Finished Jul 16 07:51:15 PM PDT 24
Peak memory 217572 kb
Host smart-913b726f-3558-4dbc-bcd4-37cd6c8f8547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86517058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.86517058
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1602398385
Short name T934
Test name
Test status
Simulation time 1567586128 ps
CPU time 3.85 seconds
Started Jul 16 07:50:27 PM PDT 24
Finished Jul 16 07:50:32 PM PDT 24
Peak memory 217068 kb
Host smart-b04be550-c734-4ae3-a556-025f3df042d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602398385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1602398385
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1378565156
Short name T646
Test name
Test status
Simulation time 45565124 ps
CPU time 1.04 seconds
Started Jul 16 07:50:23 PM PDT 24
Finished Jul 16 07:50:25 PM PDT 24
Peak memory 208208 kb
Host smart-73d27007-55e7-4c7b-b9ea-004c73ad72b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378565156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1378565156
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.4085413846
Short name T786
Test name
Test status
Simulation time 69531373 ps
CPU time 0.91 seconds
Started Jul 16 07:50:29 PM PDT 24
Finished Jul 16 07:50:31 PM PDT 24
Peak memory 206928 kb
Host smart-1c5730c7-2754-4b38-a9a2-885d662190d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085413846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.4085413846
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3689965839
Short name T939
Test name
Test status
Simulation time 51923774 ps
CPU time 2.23 seconds
Started Jul 16 07:50:24 PM PDT 24
Finished Jul 16 07:50:29 PM PDT 24
Peak memory 225244 kb
Host smart-aa304d28-d123-4088-a8f6-b331ed841ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689965839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3689965839
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2733659063
Short name T457
Test name
Test status
Simulation time 60052346 ps
CPU time 0.76 seconds
Started Jul 16 07:50:26 PM PDT 24
Finished Jul 16 07:50:28 PM PDT 24
Peak memory 206384 kb
Host smart-631c5857-9112-4117-a335-f6d9e897a652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733659063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2733659063
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3411273691
Short name T59
Test name
Test status
Simulation time 209997651 ps
CPU time 3.84 seconds
Started Jul 16 07:50:24 PM PDT 24
Finished Jul 16 07:50:29 PM PDT 24
Peak memory 233744 kb
Host smart-7ff0683b-3724-4107-a99a-eef26c849d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411273691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3411273691
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.882978893
Short name T361
Test name
Test status
Simulation time 41288775 ps
CPU time 0.76 seconds
Started Jul 16 07:50:26 PM PDT 24
Finished Jul 16 07:50:28 PM PDT 24
Peak memory 207512 kb
Host smart-5bb328f7-8163-47c1-8137-5f76d0c44760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882978893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.882978893
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1861614857
Short name T263
Test name
Test status
Simulation time 27576346408 ps
CPU time 105.81 seconds
Started Jul 16 07:50:28 PM PDT 24
Finished Jul 16 07:52:15 PM PDT 24
Peak memory 258584 kb
Host smart-333add30-fc74-46d3-86cf-d5a5d340e281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861614857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1861614857
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2705420335
Short name T294
Test name
Test status
Simulation time 23748506821 ps
CPU time 95.55 seconds
Started Jul 16 07:50:28 PM PDT 24
Finished Jul 16 07:52:05 PM PDT 24
Peak memory 254680 kb
Host smart-1c756c97-b4ff-4aab-9189-e966291fdc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705420335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2705420335
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3456541008
Short name T73
Test name
Test status
Simulation time 5035373582 ps
CPU time 17.99 seconds
Started Jul 16 07:50:25 PM PDT 24
Finished Jul 16 07:50:45 PM PDT 24
Peak memory 225672 kb
Host smart-6942f376-8593-41b7-9000-e7bcb95d0c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456541008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3456541008
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2250890306
Short name T212
Test name
Test status
Simulation time 675682219640 ps
CPU time 463.99 seconds
Started Jul 16 07:50:24 PM PDT 24
Finished Jul 16 07:58:10 PM PDT 24
Peak memory 258524 kb
Host smart-71688e30-78c4-4075-b205-690400ebc4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250890306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2250890306
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.973162671
Short name T509
Test name
Test status
Simulation time 2911097091 ps
CPU time 11.04 seconds
Started Jul 16 07:50:27 PM PDT 24
Finished Jul 16 07:50:39 PM PDT 24
Peak memory 225336 kb
Host smart-d339cad8-b717-417d-9d4a-df1979996fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973162671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.973162671
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3310650286
Short name T357
Test name
Test status
Simulation time 262966709 ps
CPU time 3.26 seconds
Started Jul 16 07:50:24 PM PDT 24
Finished Jul 16 07:50:28 PM PDT 24
Peak memory 233732 kb
Host smart-9df5d0a1-fc64-4270-8080-4e00915c8c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310650286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3310650286
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2022981142
Short name T251
Test name
Test status
Simulation time 6638688584 ps
CPU time 7.96 seconds
Started Jul 16 07:50:23 PM PDT 24
Finished Jul 16 07:50:31 PM PDT 24
Peak memory 225672 kb
Host smart-360744b8-3be2-4f4b-87dd-0255e6252fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022981142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2022981142
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1345269088
Short name T266
Test name
Test status
Simulation time 3173515348 ps
CPU time 10.23 seconds
Started Jul 16 07:50:23 PM PDT 24
Finished Jul 16 07:50:34 PM PDT 24
Peak memory 238764 kb
Host smart-dd6953ca-f653-41f4-aa8f-028b76636e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345269088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1345269088
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3097905864
Short name T676
Test name
Test status
Simulation time 583651180 ps
CPU time 4.98 seconds
Started Jul 16 07:50:27 PM PDT 24
Finished Jul 16 07:50:34 PM PDT 24
Peak memory 220060 kb
Host smart-669570ac-b7d2-4135-a35f-1b6185a06b5e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3097905864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3097905864
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.130769473
Short name T799
Test name
Test status
Simulation time 209783978 ps
CPU time 1.08 seconds
Started Jul 16 07:50:24 PM PDT 24
Finished Jul 16 07:50:26 PM PDT 24
Peak memory 207976 kb
Host smart-7081622f-6a56-4769-8ce3-5b6743ef6fdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130769473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.130769473
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3718969375
Short name T936
Test name
Test status
Simulation time 2083319175 ps
CPU time 14.09 seconds
Started Jul 16 07:50:27 PM PDT 24
Finished Jul 16 07:50:43 PM PDT 24
Peak memory 217336 kb
Host smart-5558ee57-1518-469a-a550-fc22d67fd427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718969375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3718969375
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.4247924765
Short name T32
Test name
Test status
Simulation time 344418664 ps
CPU time 2.7 seconds
Started Jul 16 07:50:25 PM PDT 24
Finished Jul 16 07:50:30 PM PDT 24
Peak memory 217256 kb
Host smart-5bd3525d-edde-4ce6-a877-013479247e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247924765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.4247924765
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2808166827
Short name T663
Test name
Test status
Simulation time 30191368 ps
CPU time 0.89 seconds
Started Jul 16 07:50:28 PM PDT 24
Finished Jul 16 07:50:30 PM PDT 24
Peak memory 208032 kb
Host smart-59e7f506-f5e3-4f69-aa97-5f47ffd56522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808166827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2808166827
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2991875346
Short name T805
Test name
Test status
Simulation time 57324992 ps
CPU time 0.78 seconds
Started Jul 16 07:50:25 PM PDT 24
Finished Jul 16 07:50:28 PM PDT 24
Peak memory 206956 kb
Host smart-d31f7de3-260b-41f5-9fea-44a96c93d570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991875346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2991875346
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3617155452
Short name T254
Test name
Test status
Simulation time 12252642477 ps
CPU time 30.81 seconds
Started Jul 16 07:50:28 PM PDT 24
Finished Jul 16 07:51:01 PM PDT 24
Peak memory 234032 kb
Host smart-75694b64-7f2b-4f33-87ad-7a3b04a4b823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617155452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3617155452
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.475901687
Short name T833
Test name
Test status
Simulation time 39031732 ps
CPU time 0.72 seconds
Started Jul 16 07:50:45 PM PDT 24
Finished Jul 16 07:50:47 PM PDT 24
Peak memory 206328 kb
Host smart-4c331188-6456-4585-a9bd-19fb1910b045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475901687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.475901687
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.4253093576
Short name T601
Test name
Test status
Simulation time 1341391761 ps
CPU time 13.47 seconds
Started Jul 16 07:50:25 PM PDT 24
Finished Jul 16 07:50:41 PM PDT 24
Peak memory 233748 kb
Host smart-efe917de-8deb-447d-83f2-f761a20a5c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253093576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.4253093576
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3352876750
Short name T656
Test name
Test status
Simulation time 18413803 ps
CPU time 0.76 seconds
Started Jul 16 07:50:25 PM PDT 24
Finished Jul 16 07:50:28 PM PDT 24
Peak memory 206520 kb
Host smart-bef9b275-5b63-46be-b49c-790c97be4bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352876750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3352876750
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2562463956
Short name T387
Test name
Test status
Simulation time 66193720 ps
CPU time 0.77 seconds
Started Jul 16 07:50:48 PM PDT 24
Finished Jul 16 07:50:52 PM PDT 24
Peak memory 216908 kb
Host smart-e33304cf-714f-4ee0-b2e5-a915f7f8c4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562463956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2562463956
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3284170473
Short name T241
Test name
Test status
Simulation time 145462810508 ps
CPU time 326.62 seconds
Started Jul 16 07:50:46 PM PDT 24
Finished Jul 16 07:56:16 PM PDT 24
Peak memory 250356 kb
Host smart-a11f91b7-3899-41e2-a110-e50eae6ee4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284170473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3284170473
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1581545014
Short name T344
Test name
Test status
Simulation time 3091451022 ps
CPU time 25.19 seconds
Started Jul 16 07:50:46 PM PDT 24
Finished Jul 16 07:51:14 PM PDT 24
Peak memory 218764 kb
Host smart-37c723d6-9e49-4a7b-b402-c3e2bc5221d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581545014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1581545014
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_intercept.675085597
Short name T1014
Test name
Test status
Simulation time 1541904881 ps
CPU time 6.58 seconds
Started Jul 16 07:50:28 PM PDT 24
Finished Jul 16 07:50:36 PM PDT 24
Peak memory 228520 kb
Host smart-c153293d-561f-4724-8b7a-231d58dec6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675085597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.675085597
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2316869558
Short name T806
Test name
Test status
Simulation time 64055768 ps
CPU time 2.2 seconds
Started Jul 16 07:50:27 PM PDT 24
Finished Jul 16 07:50:31 PM PDT 24
Peak memory 225328 kb
Host smart-5556b3fc-899e-4145-ae48-0984b74b36f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316869558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2316869558
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.311036002
Short name T422
Test name
Test status
Simulation time 755055090 ps
CPU time 4.16 seconds
Started Jul 16 07:50:26 PM PDT 24
Finished Jul 16 07:50:32 PM PDT 24
Peak memory 233720 kb
Host smart-076012fc-386d-40ea-89ec-9553d73e07fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311036002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.311036002
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2706254767
Short name T229
Test name
Test status
Simulation time 3889001138 ps
CPU time 6.61 seconds
Started Jul 16 07:50:22 PM PDT 24
Finished Jul 16 07:50:29 PM PDT 24
Peak memory 225708 kb
Host smart-74dd3de2-58a8-4a9c-8b8d-cdeb8094b779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706254767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2706254767
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1073260395
Short name T165
Test name
Test status
Simulation time 561693187 ps
CPU time 5.93 seconds
Started Jul 16 07:50:46 PM PDT 24
Finished Jul 16 07:50:54 PM PDT 24
Peak memory 219936 kb
Host smart-e6100d7f-20db-406b-8cf4-5a2abc9d3e40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1073260395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1073260395
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1778547696
Short name T628
Test name
Test status
Simulation time 40260838296 ps
CPU time 49.9 seconds
Started Jul 16 07:50:29 PM PDT 24
Finished Jul 16 07:51:20 PM PDT 24
Peak memory 217432 kb
Host smart-77db904f-8352-488b-baea-a9c3cdeb13dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778547696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1778547696
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2398576581
Short name T706
Test name
Test status
Simulation time 1128793629 ps
CPU time 2.19 seconds
Started Jul 16 07:50:25 PM PDT 24
Finished Jul 16 07:50:29 PM PDT 24
Peak memory 208968 kb
Host smart-b09557f9-2d1c-4176-b78f-67a5f5406d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398576581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2398576581
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2976547181
Short name T6
Test name
Test status
Simulation time 478487475 ps
CPU time 8.8 seconds
Started Jul 16 07:50:27 PM PDT 24
Finished Jul 16 07:50:38 PM PDT 24
Peak memory 217256 kb
Host smart-47a8258a-2f11-4c06-bce8-19b878c07fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976547181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2976547181
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3103389435
Short name T397
Test name
Test status
Simulation time 119802662 ps
CPU time 0.84 seconds
Started Jul 16 07:50:24 PM PDT 24
Finished Jul 16 07:50:26 PM PDT 24
Peak memory 207976 kb
Host smart-7e808a35-9723-444d-8cc3-4d277706b957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103389435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3103389435
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1107042134
Short name T301
Test name
Test status
Simulation time 2278538017 ps
CPU time 6.07 seconds
Started Jul 16 07:50:24 PM PDT 24
Finished Jul 16 07:50:31 PM PDT 24
Peak memory 233876 kb
Host smart-b1018b43-0be5-47bb-b3aa-8d0a0918444e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107042134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1107042134
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.28943308
Short name T558
Test name
Test status
Simulation time 14960871 ps
CPU time 0.72 seconds
Started Jul 16 07:50:48 PM PDT 24
Finished Jul 16 07:50:52 PM PDT 24
Peak memory 206736 kb
Host smart-454a1a34-5c19-4f37-a08a-264f9a2fa09e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28943308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.28943308
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3768118605
Short name T102
Test name
Test status
Simulation time 309122607 ps
CPU time 5.6 seconds
Started Jul 16 07:50:46 PM PDT 24
Finished Jul 16 07:50:55 PM PDT 24
Peak memory 233932 kb
Host smart-f4822fbc-51bc-4cd2-a5ae-5082734b5e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768118605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3768118605
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3896599042
Short name T476
Test name
Test status
Simulation time 62692759 ps
CPU time 0.8 seconds
Started Jul 16 07:50:45 PM PDT 24
Finished Jul 16 07:50:48 PM PDT 24
Peak memory 207828 kb
Host smart-16d57c41-4c88-4f50-a8e4-251d54956c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896599042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3896599042
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3649516486
Short name T217
Test name
Test status
Simulation time 81616540988 ps
CPU time 583.82 seconds
Started Jul 16 07:50:46 PM PDT 24
Finished Jul 16 08:00:32 PM PDT 24
Peak memory 274976 kb
Host smart-ce9b212c-dfcb-4988-85e1-a72ecfe456c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649516486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3649516486
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2506305566
Short name T91
Test name
Test status
Simulation time 451494258767 ps
CPU time 285.7 seconds
Started Jul 16 07:50:45 PM PDT 24
Finished Jul 16 07:55:33 PM PDT 24
Peak memory 258404 kb
Host smart-b3696dc3-d195-4d12-aeb0-070368bff0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506305566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2506305566
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2836502124
Short name T516
Test name
Test status
Simulation time 1545100730 ps
CPU time 19.59 seconds
Started Jul 16 07:50:45 PM PDT 24
Finished Jul 16 07:51:07 PM PDT 24
Peak memory 238732 kb
Host smart-bcf9c44c-98bd-4319-8751-2ddadc3abe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836502124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2836502124
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3990255072
Short name T483
Test name
Test status
Simulation time 22235407837 ps
CPU time 34.28 seconds
Started Jul 16 07:50:44 PM PDT 24
Finished Jul 16 07:51:20 PM PDT 24
Peak memory 255116 kb
Host smart-a41b34aa-f278-4295-92d1-fb5e1b1dbaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990255072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3990255072
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3033816681
Short name T1003
Test name
Test status
Simulation time 2988708184 ps
CPU time 15.29 seconds
Started Jul 16 07:50:46 PM PDT 24
Finished Jul 16 07:51:05 PM PDT 24
Peak memory 233972 kb
Host smart-b4461172-c466-44ae-a922-8adb651874d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033816681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3033816681
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1749160791
Short name T593
Test name
Test status
Simulation time 657258748 ps
CPU time 10.83 seconds
Started Jul 16 07:50:44 PM PDT 24
Finished Jul 16 07:50:56 PM PDT 24
Peak memory 233788 kb
Host smart-42047f9a-a2be-4107-976a-d0a542b6a2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749160791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1749160791
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.4256097237
Short name T895
Test name
Test status
Simulation time 359963329 ps
CPU time 4.55 seconds
Started Jul 16 07:50:44 PM PDT 24
Finished Jul 16 07:50:49 PM PDT 24
Peak memory 233808 kb
Host smart-34782df6-52a7-4a7e-a13e-14ef2dc26fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256097237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.4256097237
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3297526243
Short name T834
Test name
Test status
Simulation time 831226596 ps
CPU time 4.44 seconds
Started Jul 16 07:50:48 PM PDT 24
Finished Jul 16 07:50:56 PM PDT 24
Peak memory 233780 kb
Host smart-3bffe472-e49a-4c51-956a-1673a38b330a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297526243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3297526243
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.4201295614
Short name T161
Test name
Test status
Simulation time 2741562685 ps
CPU time 8.45 seconds
Started Jul 16 07:50:46 PM PDT 24
Finished Jul 16 07:50:58 PM PDT 24
Peak memory 220320 kb
Host smart-a2ed8636-ac46-4e86-b0f7-c9b0e2b26153
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4201295614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.4201295614
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1179542011
Short name T69
Test name
Test status
Simulation time 19711345294 ps
CPU time 205.79 seconds
Started Jul 16 07:50:45 PM PDT 24
Finished Jul 16 07:54:12 PM PDT 24
Peak memory 252468 kb
Host smart-f4518771-2a1a-442c-9b56-6e7cab0d3e49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179542011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1179542011
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3896791556
Short name T563
Test name
Test status
Simulation time 7848875255 ps
CPU time 42.07 seconds
Started Jul 16 07:50:46 PM PDT 24
Finished Jul 16 07:51:31 PM PDT 24
Peak memory 217556 kb
Host smart-76481ffd-aaca-4377-b662-8874ff042d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896791556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3896791556
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1286893242
Short name T373
Test name
Test status
Simulation time 2018826253 ps
CPU time 5.83 seconds
Started Jul 16 07:50:45 PM PDT 24
Finished Jul 16 07:50:53 PM PDT 24
Peak memory 217352 kb
Host smart-62da2e1f-9b27-4165-a6d5-484d0f2a9e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286893242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1286893242
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.842523279
Short name T931
Test name
Test status
Simulation time 62850435 ps
CPU time 0.98 seconds
Started Jul 16 07:50:45 PM PDT 24
Finished Jul 16 07:50:47 PM PDT 24
Peak memory 208736 kb
Host smart-bf832678-4f85-4f34-b6b8-2fd962a82c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842523279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.842523279
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3488169020
Short name T630
Test name
Test status
Simulation time 64915844 ps
CPU time 0.74 seconds
Started Jul 16 07:50:45 PM PDT 24
Finished Jul 16 07:50:47 PM PDT 24
Peak memory 206964 kb
Host smart-085e5261-e52e-45a3-99c4-f5c188f8245b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488169020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3488169020
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1160063601
Short name T560
Test name
Test status
Simulation time 2492672544 ps
CPU time 5.69 seconds
Started Jul 16 07:50:45 PM PDT 24
Finished Jul 16 07:50:53 PM PDT 24
Peak memory 225724 kb
Host smart-5d524f96-f292-44d8-b09c-a6f2421c0b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160063601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1160063601
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.666792843
Short name T1004
Test name
Test status
Simulation time 13553581 ps
CPU time 0.72 seconds
Started Jul 16 07:50:45 PM PDT 24
Finished Jul 16 07:50:48 PM PDT 24
Peak memory 206348 kb
Host smart-4c360d56-255b-4d99-9e6b-16f433436b5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666792843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.666792843
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2330665089
Short name T652
Test name
Test status
Simulation time 32081904 ps
CPU time 2.68 seconds
Started Jul 16 07:50:48 PM PDT 24
Finished Jul 16 07:50:54 PM PDT 24
Peak memory 233692 kb
Host smart-f78c9ded-0af4-4205-9e33-ae4b4f4ce5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330665089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2330665089
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3749352258
Short name T1027
Test name
Test status
Simulation time 18718588 ps
CPU time 0.79 seconds
Started Jul 16 07:50:45 PM PDT 24
Finished Jul 16 07:50:47 PM PDT 24
Peak memory 207536 kb
Host smart-1ee5e2fc-bf64-46f5-ae0b-2fb85dcc0ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749352258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3749352258
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2711077816
Short name T502
Test name
Test status
Simulation time 48620968127 ps
CPU time 90.53 seconds
Started Jul 16 07:50:46 PM PDT 24
Finished Jul 16 07:52:20 PM PDT 24
Peak memory 242072 kb
Host smart-7d5cb9cd-9c44-4297-9fe1-d0b7ddba3582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711077816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2711077816
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.365688384
Short name T745
Test name
Test status
Simulation time 20515519 ps
CPU time 0.84 seconds
Started Jul 16 07:50:47 PM PDT 24
Finished Jul 16 07:50:51 PM PDT 24
Peak memory 217980 kb
Host smart-99386184-2bae-4297-a661-ed4025518527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365688384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.365688384
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3239704415
Short name T837
Test name
Test status
Simulation time 184477867 ps
CPU time 3.13 seconds
Started Jul 16 07:50:47 PM PDT 24
Finished Jul 16 07:50:53 PM PDT 24
Peak memory 225516 kb
Host smart-cb6c7c61-998c-426e-973c-337d3a814b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239704415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3239704415
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3289035839
Short name T48
Test name
Test status
Simulation time 11889108588 ps
CPU time 87.45 seconds
Started Jul 16 07:50:46 PM PDT 24
Finished Jul 16 07:52:17 PM PDT 24
Peak memory 250348 kb
Host smart-24a127b2-90a0-4a5c-b5a7-2c06dc42153b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289035839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3289035839
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.947887298
Short name T215
Test name
Test status
Simulation time 8365466407 ps
CPU time 9.02 seconds
Started Jul 16 07:50:46 PM PDT 24
Finished Jul 16 07:50:57 PM PDT 24
Peak memory 233896 kb
Host smart-bc271da0-1b1a-4fb6-87e3-2b2a8e0e30ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947887298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.947887298
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3150301202
Short name T875
Test name
Test status
Simulation time 1096093020 ps
CPU time 6.68 seconds
Started Jul 16 07:50:44 PM PDT 24
Finished Jul 16 07:50:51 PM PDT 24
Peak memory 225544 kb
Host smart-788c4cfa-9a4f-4fb4-9e93-154e6c667d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150301202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3150301202
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1232118921
Short name T572
Test name
Test status
Simulation time 976654846 ps
CPU time 2.34 seconds
Started Jul 16 07:50:44 PM PDT 24
Finished Jul 16 07:50:48 PM PDT 24
Peak memory 225448 kb
Host smart-d5838ae5-1a35-4ba9-978d-ce5a25fef143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232118921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1232118921
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.464587856
Short name T773
Test name
Test status
Simulation time 5503044941 ps
CPU time 16.82 seconds
Started Jul 16 07:50:44 PM PDT 24
Finished Jul 16 07:51:03 PM PDT 24
Peak memory 234256 kb
Host smart-aba0b6e4-e1da-41cb-b748-102360caec92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464587856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.464587856
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3416721461
Short name T739
Test name
Test status
Simulation time 10640143320 ps
CPU time 9.17 seconds
Started Jul 16 07:50:46 PM PDT 24
Finished Jul 16 07:50:59 PM PDT 24
Peak memory 223736 kb
Host smart-1cecba8e-83b8-4836-9631-a71b59f6bd29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3416721461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3416721461
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3787550034
Short name T748
Test name
Test status
Simulation time 53222222 ps
CPU time 0.98 seconds
Started Jul 16 07:50:47 PM PDT 24
Finished Jul 16 07:50:52 PM PDT 24
Peak memory 208292 kb
Host smart-797c1480-9962-4f61-8200-a8d24452ae40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787550034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3787550034
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1608036738
Short name T1015
Test name
Test status
Simulation time 6213720874 ps
CPU time 20.58 seconds
Started Jul 16 07:50:45 PM PDT 24
Finished Jul 16 07:51:07 PM PDT 24
Peak memory 217556 kb
Host smart-e8528e88-86d7-4ed2-a1aa-7a76fa3452c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608036738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1608036738
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2608226086
Short name T389
Test name
Test status
Simulation time 1499950960 ps
CPU time 6.18 seconds
Started Jul 16 07:50:46 PM PDT 24
Finished Jul 16 07:50:54 PM PDT 24
Peak memory 217352 kb
Host smart-e2307188-19b7-4e5d-96c1-a64986d97a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608226086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2608226086
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1175722932
Short name T940
Test name
Test status
Simulation time 99586871 ps
CPU time 1.39 seconds
Started Jul 16 07:50:45 PM PDT 24
Finished Jul 16 07:50:48 PM PDT 24
Peak memory 217324 kb
Host smart-bb9d592d-b752-4fea-bcac-f66073fa04eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175722932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1175722932
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.355081955
Short name T379
Test name
Test status
Simulation time 124626642 ps
CPU time 0.84 seconds
Started Jul 16 07:50:45 PM PDT 24
Finished Jul 16 07:50:48 PM PDT 24
Peak memory 206956 kb
Host smart-cb87e1d8-5e50-48bd-8e9e-b1741e1524f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355081955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.355081955
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1596823754
Short name T290
Test name
Test status
Simulation time 9303343413 ps
CPU time 19.03 seconds
Started Jul 16 07:50:44 PM PDT 24
Finished Jul 16 07:51:03 PM PDT 24
Peak memory 233884 kb
Host smart-6c8f74be-a02d-4dca-a23e-ab25af69abc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596823754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1596823754
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.478260673
Short name T463
Test name
Test status
Simulation time 42370814 ps
CPU time 0.73 seconds
Started Jul 16 07:50:46 PM PDT 24
Finished Jul 16 07:50:50 PM PDT 24
Peak memory 206380 kb
Host smart-d1825e14-e426-4da7-be11-dfce297e5b8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478260673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.478260673
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.875282276
Short name T523
Test name
Test status
Simulation time 228956406 ps
CPU time 5.05 seconds
Started Jul 16 07:50:50 PM PDT 24
Finished Jul 16 07:50:58 PM PDT 24
Peak memory 229444 kb
Host smart-3bdd7602-c3ec-41f4-909d-89576413bc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875282276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.875282276
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1703464256
Short name T626
Test name
Test status
Simulation time 18833623 ps
CPU time 0.8 seconds
Started Jul 16 07:50:46 PM PDT 24
Finished Jul 16 07:50:49 PM PDT 24
Peak memory 207516 kb
Host smart-aa611018-8557-4165-805c-6e3818007ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703464256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1703464256
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1877187969
Short name T823
Test name
Test status
Simulation time 3167552983 ps
CPU time 40.63 seconds
Started Jul 16 07:50:48 PM PDT 24
Finished Jul 16 07:51:32 PM PDT 24
Peak memory 239628 kb
Host smart-36dcb464-3fd2-4ed0-a0c0-ad88c3ba01ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877187969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1877187969
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.4104621965
Short name T319
Test name
Test status
Simulation time 3063154492 ps
CPU time 71.35 seconds
Started Jul 16 07:50:47 PM PDT 24
Finished Jul 16 07:52:01 PM PDT 24
Peak memory 250460 kb
Host smart-044c1cac-395c-4856-887e-92740d97a9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104621965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.4104621965
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1629075354
Short name T164
Test name
Test status
Simulation time 12785730732 ps
CPU time 41.72 seconds
Started Jul 16 07:50:48 PM PDT 24
Finished Jul 16 07:51:32 PM PDT 24
Peak memory 225652 kb
Host smart-135e14d2-6fa2-4b39-bea6-44124d7c904f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629075354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1629075354
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.46079546
Short name T199
Test name
Test status
Simulation time 20827320883 ps
CPU time 212.69 seconds
Started Jul 16 07:50:49 PM PDT 24
Finished Jul 16 07:54:25 PM PDT 24
Peak memory 271544 kb
Host smart-f5608c21-68f7-48c4-9b0c-f98e6742b7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46079546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.46079546
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2042440966
Short name T394
Test name
Test status
Simulation time 740596952 ps
CPU time 2.82 seconds
Started Jul 16 07:50:49 PM PDT 24
Finished Jul 16 07:50:55 PM PDT 24
Peak memory 225484 kb
Host smart-d0b1ec63-70ed-41a7-b047-1a690efa3fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042440966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2042440966
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1752530488
Short name T513
Test name
Test status
Simulation time 27307751970 ps
CPU time 39.91 seconds
Started Jul 16 07:50:49 PM PDT 24
Finished Jul 16 07:51:32 PM PDT 24
Peak memory 231504 kb
Host smart-f1383383-99fe-4de1-aacb-18ae9aba758f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752530488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1752530488
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2797005526
Short name T250
Test name
Test status
Simulation time 4241288438 ps
CPU time 10.81 seconds
Started Jul 16 07:50:47 PM PDT 24
Finished Jul 16 07:51:02 PM PDT 24
Peak memory 225636 kb
Host smart-8be3b59f-21b8-44f7-9b4f-88c2fb6d48c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797005526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2797005526
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2278519809
Short name T978
Test name
Test status
Simulation time 16597091261 ps
CPU time 8.16 seconds
Started Jul 16 07:50:48 PM PDT 24
Finished Jul 16 07:51:00 PM PDT 24
Peak memory 225668 kb
Host smart-abd51644-b156-409f-b83b-3b16f9b86ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278519809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2278519809
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3770991455
Short name T473
Test name
Test status
Simulation time 347958717 ps
CPU time 4.73 seconds
Started Jul 16 07:50:49 PM PDT 24
Finished Jul 16 07:50:57 PM PDT 24
Peak memory 220924 kb
Host smart-c27a317d-a3d4-40c0-9219-100a319c2833
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3770991455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3770991455
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3918503536
Short name T901
Test name
Test status
Simulation time 150668026529 ps
CPU time 508.61 seconds
Started Jul 16 07:50:49 PM PDT 24
Finished Jul 16 07:59:21 PM PDT 24
Peak memory 265148 kb
Host smart-2e89152f-e3e2-45c1-b29d-13c6d96f6d51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918503536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3918503536
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2845309375
Short name T607
Test name
Test status
Simulation time 3895237373 ps
CPU time 20.84 seconds
Started Jul 16 07:50:47 PM PDT 24
Finished Jul 16 07:51:11 PM PDT 24
Peak memory 217488 kb
Host smart-a098021d-00a6-4194-985d-7ce4f252ead2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845309375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2845309375
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3792334737
Short name T913
Test name
Test status
Simulation time 2429762371 ps
CPU time 10.01 seconds
Started Jul 16 07:50:48 PM PDT 24
Finished Jul 16 07:51:01 PM PDT 24
Peak memory 217452 kb
Host smart-e059e390-4d49-4456-80d5-47a1cb30357f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792334737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3792334737
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3088430701
Short name T609
Test name
Test status
Simulation time 141163026 ps
CPU time 1.8 seconds
Started Jul 16 07:50:45 PM PDT 24
Finished Jul 16 07:50:49 PM PDT 24
Peak memory 217320 kb
Host smart-3cbfe6eb-b833-419c-9a4c-e757afad0952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088430701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3088430701
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2209525644
Short name T360
Test name
Test status
Simulation time 116772516 ps
CPU time 0.89 seconds
Started Jul 16 07:50:48 PM PDT 24
Finished Jul 16 07:50:52 PM PDT 24
Peak memory 206952 kb
Host smart-2be8a393-2610-4ffe-b8ab-3fac85f9011f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209525644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2209525644
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1380421890
Short name T247
Test name
Test status
Simulation time 247498336 ps
CPU time 5.13 seconds
Started Jul 16 07:50:48 PM PDT 24
Finished Jul 16 07:50:56 PM PDT 24
Peak memory 225552 kb
Host smart-57ae3eb4-a1b9-40c0-ad59-6de184ef5004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380421890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1380421890
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2164589395
Short name T445
Test name
Test status
Simulation time 13341075 ps
CPU time 0.71 seconds
Started Jul 16 07:51:13 PM PDT 24
Finished Jul 16 07:51:15 PM PDT 24
Peak memory 205788 kb
Host smart-fb6c0219-38a3-4d47-8c9b-987dbcea8137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164589395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2164589395
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1696706237
Short name T536
Test name
Test status
Simulation time 1717207813 ps
CPU time 5.11 seconds
Started Jul 16 07:51:14 PM PDT 24
Finished Jul 16 07:51:22 PM PDT 24
Peak memory 225544 kb
Host smart-c94b75f3-7159-42dd-8d1b-fb707d0d40e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696706237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1696706237
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3739149066
Short name T605
Test name
Test status
Simulation time 66164495 ps
CPU time 0.75 seconds
Started Jul 16 07:50:49 PM PDT 24
Finished Jul 16 07:50:53 PM PDT 24
Peak memory 206432 kb
Host smart-88cfe444-8e77-490a-9413-c47f46f6431c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739149066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3739149066
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3778998358
Short name T597
Test name
Test status
Simulation time 419814049 ps
CPU time 8.59 seconds
Started Jul 16 07:51:16 PM PDT 24
Finished Jul 16 07:51:28 PM PDT 24
Peak memory 225572 kb
Host smart-23033cec-7f72-4f7b-b6cf-87c164c9be6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778998358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3778998358
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1090256220
Short name T1029
Test name
Test status
Simulation time 5136239776 ps
CPU time 130.15 seconds
Started Jul 16 07:51:13 PM PDT 24
Finished Jul 16 07:53:25 PM PDT 24
Peak memory 266784 kb
Host smart-ab041aea-f194-4605-b689-591c6a2bbd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090256220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1090256220
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1946025360
Short name T673
Test name
Test status
Simulation time 1543601194 ps
CPU time 22.24 seconds
Started Jul 16 07:51:15 PM PDT 24
Finished Jul 16 07:51:40 PM PDT 24
Peak memory 218728 kb
Host smart-9ab8a111-f2ec-4bc9-bdad-2e2a9a35b216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946025360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1946025360
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3847347455
Short name T337
Test name
Test status
Simulation time 6618015343 ps
CPU time 81.76 seconds
Started Jul 16 07:51:16 PM PDT 24
Finished Jul 16 07:52:41 PM PDT 24
Peak memory 249812 kb
Host smart-2f904d08-38ac-40da-a372-4afeb798df96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847347455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3847347455
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2866413391
Short name T987
Test name
Test status
Simulation time 20887634823 ps
CPU time 151.81 seconds
Started Jul 16 07:51:15 PM PDT 24
Finished Jul 16 07:53:50 PM PDT 24
Peak memory 253860 kb
Host smart-8ac4928a-9886-4048-974a-8ea59748150a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866413391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2866413391
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2277242960
Short name T303
Test name
Test status
Simulation time 473716999 ps
CPU time 3.08 seconds
Started Jul 16 07:51:14 PM PDT 24
Finished Jul 16 07:51:19 PM PDT 24
Peak memory 225552 kb
Host smart-c8a42733-4672-4ca2-8ce7-98143b561cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277242960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2277242960
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.256861425
Short name T230
Test name
Test status
Simulation time 789694381 ps
CPU time 2.98 seconds
Started Jul 16 07:51:14 PM PDT 24
Finished Jul 16 07:51:20 PM PDT 24
Peak memory 225580 kb
Host smart-a2783129-0194-4e4c-9ab0-b5da3ac9d51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256861425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.256861425
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.627198681
Short name T927
Test name
Test status
Simulation time 703554978 ps
CPU time 8.86 seconds
Started Jul 16 07:51:15 PM PDT 24
Finished Jul 16 07:51:27 PM PDT 24
Peak memory 241928 kb
Host smart-f09de3bc-a247-4e2f-a003-018951dea7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627198681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.627198681
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3321695755
Short name T242
Test name
Test status
Simulation time 1147664462 ps
CPU time 5.23 seconds
Started Jul 16 07:50:47 PM PDT 24
Finished Jul 16 07:50:56 PM PDT 24
Peak memory 233744 kb
Host smart-749cffaf-47c7-4883-8e07-dc25f188a354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321695755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3321695755
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3545047843
Short name T544
Test name
Test status
Simulation time 330079937 ps
CPU time 4.05 seconds
Started Jul 16 07:51:16 PM PDT 24
Finished Jul 16 07:51:24 PM PDT 24
Peak memory 224056 kb
Host smart-066001b0-9e20-46a1-94b4-9d8524fc7738
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3545047843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3545047843
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.475244342
Short name T843
Test name
Test status
Simulation time 69887547952 ps
CPU time 161.44 seconds
Started Jul 16 07:51:13 PM PDT 24
Finished Jul 16 07:53:57 PM PDT 24
Peak memory 240920 kb
Host smart-c16a7142-e2af-4b6e-87eb-a4285ecea35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475244342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.475244342
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1831179017
Short name T957
Test name
Test status
Simulation time 19339607707 ps
CPU time 16.03 seconds
Started Jul 16 07:50:49 PM PDT 24
Finished Jul 16 07:51:08 PM PDT 24
Peak memory 217720 kb
Host smart-6c5a612d-d953-4816-abb5-75ad1b4d4493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831179017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1831179017
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2496263372
Short name T465
Test name
Test status
Simulation time 17997854 ps
CPU time 0.7 seconds
Started Jul 16 07:50:51 PM PDT 24
Finished Jul 16 07:50:53 PM PDT 24
Peak memory 206584 kb
Host smart-2c479e3a-d93e-43a8-b0bb-3bef96fc9b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496263372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2496263372
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3843761969
Short name T367
Test name
Test status
Simulation time 61296980 ps
CPU time 0.92 seconds
Started Jul 16 07:50:47 PM PDT 24
Finished Jul 16 07:50:51 PM PDT 24
Peak memory 207636 kb
Host smart-df57ccd6-c5a8-41bc-883f-e63bcfd88385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843761969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3843761969
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.4069794919
Short name T1006
Test name
Test status
Simulation time 97866194 ps
CPU time 0.83 seconds
Started Jul 16 07:50:47 PM PDT 24
Finished Jul 16 07:50:51 PM PDT 24
Peak memory 206936 kb
Host smart-0289babd-accf-4654-b195-d1c0ec4c13da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069794919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4069794919
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2864004558
Short name T719
Test name
Test status
Simulation time 13873160303 ps
CPU time 41.96 seconds
Started Jul 16 07:51:13 PM PDT 24
Finished Jul 16 07:51:56 PM PDT 24
Peak memory 233924 kb
Host smart-7e2f1a34-80d5-480e-8d5b-9a55b0f52dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864004558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2864004558
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2441597456
Short name T77
Test name
Test status
Simulation time 30053771 ps
CPU time 0.72 seconds
Started Jul 16 07:51:13 PM PDT 24
Finished Jul 16 07:51:16 PM PDT 24
Peak memory 206392 kb
Host smart-b39858c8-bbdd-442a-8f1d-75a269856355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441597456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2441597456
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3773760229
Short name T1012
Test name
Test status
Simulation time 286072417 ps
CPU time 2.84 seconds
Started Jul 16 07:51:14 PM PDT 24
Finished Jul 16 07:51:20 PM PDT 24
Peak memory 233736 kb
Host smart-f85326b9-076e-45d8-967e-f1b6c0543a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773760229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3773760229
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3275408401
Short name T784
Test name
Test status
Simulation time 31493610 ps
CPU time 0.76 seconds
Started Jul 16 07:51:17 PM PDT 24
Finished Jul 16 07:51:22 PM PDT 24
Peak memory 206472 kb
Host smart-1cb9e3ef-7b29-43c2-b90b-cf1bb958cd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275408401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3275408401
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3248543124
Short name T515
Test name
Test status
Simulation time 7052115413 ps
CPU time 58.52 seconds
Started Jul 16 07:51:14 PM PDT 24
Finished Jul 16 07:52:15 PM PDT 24
Peak memory 250152 kb
Host smart-17d7983c-3c19-4df8-bce0-dee2c850e2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248543124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3248543124
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3807870390
Short name T216
Test name
Test status
Simulation time 89498373751 ps
CPU time 266.44 seconds
Started Jul 16 07:51:13 PM PDT 24
Finished Jul 16 07:55:41 PM PDT 24
Peak memory 258412 kb
Host smart-bd537883-10a0-40fe-8de2-a482e700fd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807870390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3807870390
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1733875328
Short name T424
Test name
Test status
Simulation time 357277542 ps
CPU time 4.47 seconds
Started Jul 16 07:51:14 PM PDT 24
Finished Jul 16 07:51:21 PM PDT 24
Peak memory 225628 kb
Host smart-c4362f36-22ce-4782-a9ee-01a0e7a56d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733875328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1733875328
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1445047576
Short name T989
Test name
Test status
Simulation time 826915059 ps
CPU time 15.05 seconds
Started Jul 16 07:51:13 PM PDT 24
Finished Jul 16 07:51:29 PM PDT 24
Peak memory 233808 kb
Host smart-f77b21d0-d3a6-4eff-9ce1-b905f1b3fc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445047576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1445047576
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3207787983
Short name T569
Test name
Test status
Simulation time 343684066 ps
CPU time 3.71 seconds
Started Jul 16 07:51:14 PM PDT 24
Finished Jul 16 07:51:21 PM PDT 24
Peak memory 233916 kb
Host smart-010e63c8-4647-41f1-b700-d7731d67ab6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207787983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3207787983
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3532597415
Short name T924
Test name
Test status
Simulation time 11537641319 ps
CPU time 34.05 seconds
Started Jul 16 07:51:14 PM PDT 24
Finished Jul 16 07:51:51 PM PDT 24
Peak memory 250292 kb
Host smart-06b03cb4-7c8b-49cd-94d8-4645cb84da52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532597415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3532597415
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.340682395
Short name T990
Test name
Test status
Simulation time 58567206113 ps
CPU time 36.45 seconds
Started Jul 16 07:51:17 PM PDT 24
Finished Jul 16 07:51:57 PM PDT 24
Peak memory 241776 kb
Host smart-d54d8e9d-b825-4a47-a8aa-b48379f78609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340682395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.340682395
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.799518001
Short name T825
Test name
Test status
Simulation time 10560628091 ps
CPU time 9.72 seconds
Started Jul 16 07:51:16 PM PDT 24
Finished Jul 16 07:51:29 PM PDT 24
Peak memory 233464 kb
Host smart-d0dd5161-19e2-45d5-97a4-ba136e6e8b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799518001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.799518001
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3213661903
Short name T556
Test name
Test status
Simulation time 893726146 ps
CPU time 4.26 seconds
Started Jul 16 07:51:14 PM PDT 24
Finished Jul 16 07:51:20 PM PDT 24
Peak memory 221336 kb
Host smart-7a867ef2-f3bb-4633-9050-f135945d2d5f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3213661903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3213661903
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2198597156
Short name T157
Test name
Test status
Simulation time 25016910076 ps
CPU time 136.37 seconds
Started Jul 16 07:51:15 PM PDT 24
Finished Jul 16 07:53:35 PM PDT 24
Peak memory 257836 kb
Host smart-08210646-d021-49e3-b800-0085b8e6d3c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198597156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2198597156
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.4114159937
Short name T577
Test name
Test status
Simulation time 109447304436 ps
CPU time 40.1 seconds
Started Jul 16 07:51:14 PM PDT 24
Finished Jul 16 07:51:56 PM PDT 24
Peak memory 217432 kb
Host smart-fa621988-f4f7-41cc-bec4-2883f03aec32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114159937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4114159937
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.469147470
Short name T708
Test name
Test status
Simulation time 1266723776 ps
CPU time 5.3 seconds
Started Jul 16 07:51:14 PM PDT 24
Finished Jul 16 07:51:21 PM PDT 24
Peak memory 217308 kb
Host smart-93f509e2-cc70-49d3-8e33-2c7c9382ce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469147470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.469147470
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3311496197
Short name T975
Test name
Test status
Simulation time 27066373 ps
CPU time 0.68 seconds
Started Jul 16 07:51:15 PM PDT 24
Finished Jul 16 07:51:20 PM PDT 24
Peak memory 206604 kb
Host smart-b0d8d4b3-a73a-4d58-961e-ad3c167a3d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311496197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3311496197
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2278536070
Short name T471
Test name
Test status
Simulation time 12398148 ps
CPU time 0.74 seconds
Started Jul 16 07:51:14 PM PDT 24
Finished Jul 16 07:51:17 PM PDT 24
Peak memory 206952 kb
Host smart-7561d932-e466-4589-bcf0-549d080f4b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278536070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2278536070
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2965250273
Short name T438
Test name
Test status
Simulation time 597835232 ps
CPU time 4.44 seconds
Started Jul 16 07:51:14 PM PDT 24
Finished Jul 16 07:51:21 PM PDT 24
Peak memory 220164 kb
Host smart-85024084-5a5b-4720-be3f-48b465ce892a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965250273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2965250273
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2397060132
Short name T482
Test name
Test status
Simulation time 13459756 ps
CPU time 0.72 seconds
Started Jul 16 07:47:48 PM PDT 24
Finished Jul 16 07:47:50 PM PDT 24
Peak memory 205824 kb
Host smart-ab7b2814-6d86-454b-a79b-7996e8f2a5b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397060132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
397060132
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.21132029
Short name T547
Test name
Test status
Simulation time 1394722725 ps
CPU time 7.07 seconds
Started Jul 16 07:47:47 PM PDT 24
Finished Jul 16 07:47:56 PM PDT 24
Peak memory 233716 kb
Host smart-596e1b4b-f4be-4918-b7c2-66cc09beadcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21132029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.21132029
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.354278958
Short name T466
Test name
Test status
Simulation time 140598191 ps
CPU time 0.77 seconds
Started Jul 16 07:47:42 PM PDT 24
Finished Jul 16 07:47:44 PM PDT 24
Peak memory 207496 kb
Host smart-642d628a-5da7-4f83-ada6-2e833bf4734b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354278958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.354278958
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2447583222
Short name T325
Test name
Test status
Simulation time 21401962610 ps
CPU time 82.81 seconds
Started Jul 16 07:47:49 PM PDT 24
Finished Jul 16 07:49:14 PM PDT 24
Peak memory 256148 kb
Host smart-2842f3fa-2be5-4fa0-b871-4293506ec43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447583222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2447583222
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1999078349
Short name T316
Test name
Test status
Simulation time 88347896046 ps
CPU time 210.17 seconds
Started Jul 16 07:47:50 PM PDT 24
Finished Jul 16 07:51:22 PM PDT 24
Peak memory 255172 kb
Host smart-a3dcf8ab-2b54-4a45-8b97-8df373e53527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999078349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1999078349
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2554064152
Short name T963
Test name
Test status
Simulation time 647029155 ps
CPU time 3.55 seconds
Started Jul 16 07:47:49 PM PDT 24
Finished Jul 16 07:47:54 PM PDT 24
Peak memory 233796 kb
Host smart-21cbb500-b342-4d69-b5cb-6fe26e478ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554064152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2554064152
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.819865027
Short name T249
Test name
Test status
Simulation time 234700782616 ps
CPU time 101.68 seconds
Started Jul 16 07:47:50 PM PDT 24
Finished Jul 16 07:49:33 PM PDT 24
Peak memory 258344 kb
Host smart-b0e825de-aba0-4716-bd73-07d03584b92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819865027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
819865027
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2199017530
Short name T997
Test name
Test status
Simulation time 5617449472 ps
CPU time 14.83 seconds
Started Jul 16 07:47:52 PM PDT 24
Finished Jul 16 07:48:08 PM PDT 24
Peak memory 225596 kb
Host smart-a14d8ad3-167b-49b2-b0ce-e14b107a9c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199017530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2199017530
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1291722231
Short name T691
Test name
Test status
Simulation time 2836621066 ps
CPU time 12.01 seconds
Started Jul 16 07:47:49 PM PDT 24
Finished Jul 16 07:48:03 PM PDT 24
Peak memory 225608 kb
Host smart-51c174e5-d434-4ad5-baec-9e5993d36282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291722231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1291722231
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1762391386
Short name T894
Test name
Test status
Simulation time 17107664 ps
CPU time 1.02 seconds
Started Jul 16 07:47:46 PM PDT 24
Finished Jul 16 07:47:48 PM PDT 24
Peak memory 218908 kb
Host smart-56be766a-c61b-4a17-b55b-b2fb30bad562
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762391386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1762391386
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2125626102
Short name T293
Test name
Test status
Simulation time 15773993762 ps
CPU time 21.31 seconds
Started Jul 16 07:47:46 PM PDT 24
Finished Jul 16 07:48:09 PM PDT 24
Peak memory 241040 kb
Host smart-d8889dae-2495-42e9-bba5-cabc4df062ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125626102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2125626102
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.4005316076
Short name T994
Test name
Test status
Simulation time 27755432531 ps
CPU time 22.65 seconds
Started Jul 16 07:47:45 PM PDT 24
Finished Jul 16 07:48:09 PM PDT 24
Peak memory 233872 kb
Host smart-87f8b1a3-fdcc-45ac-9c17-cfb2f560ac33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005316076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.4005316076
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.381148455
Short name T849
Test name
Test status
Simulation time 76800795 ps
CPU time 3.88 seconds
Started Jul 16 07:47:49 PM PDT 24
Finished Jul 16 07:47:55 PM PDT 24
Peak memory 224012 kb
Host smart-cc02af71-69f5-403b-9d3b-2e0f9503499e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=381148455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.381148455
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3290157112
Short name T80
Test name
Test status
Simulation time 68145041 ps
CPU time 1.13 seconds
Started Jul 16 07:47:49 PM PDT 24
Finished Jul 16 07:47:52 PM PDT 24
Peak memory 236356 kb
Host smart-d749920d-9686-4792-b88e-ba7318c0c86f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290157112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3290157112
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3578617993
Short name T24
Test name
Test status
Simulation time 3157592190 ps
CPU time 66.65 seconds
Started Jul 16 07:47:42 PM PDT 24
Finished Jul 16 07:48:50 PM PDT 24
Peak memory 266840 kb
Host smart-c578c4fe-5640-46cd-b10d-01deed22e781
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578617993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3578617993
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.4030476859
Short name T493
Test name
Test status
Simulation time 14822216244 ps
CPU time 26.79 seconds
Started Jul 16 07:47:49 PM PDT 24
Finished Jul 16 07:48:18 PM PDT 24
Peak memory 217420 kb
Host smart-991db38d-ae01-4c68-b0d5-04a9e33bf5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030476859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.4030476859
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.486598045
Short name T712
Test name
Test status
Simulation time 36511804 ps
CPU time 0.77 seconds
Started Jul 16 07:47:49 PM PDT 24
Finished Jul 16 07:47:52 PM PDT 24
Peak memory 206580 kb
Host smart-38ab2f50-6688-456d-98ed-541dcfb57d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486598045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.486598045
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3968480464
Short name T810
Test name
Test status
Simulation time 76945492 ps
CPU time 1.39 seconds
Started Jul 16 07:47:52 PM PDT 24
Finished Jul 16 07:47:55 PM PDT 24
Peak memory 217292 kb
Host smart-c2c152da-685f-42e2-b43a-4e4ea57226f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968480464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3968480464
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.274931417
Short name T489
Test name
Test status
Simulation time 281071190 ps
CPU time 0.93 seconds
Started Jul 16 07:47:49 PM PDT 24
Finished Jul 16 07:47:52 PM PDT 24
Peak memory 206916 kb
Host smart-18e47a22-f5af-4e26-9d11-3c65050a7007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274931417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.274931417
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2214516224
Short name T522
Test name
Test status
Simulation time 857152589 ps
CPU time 8.18 seconds
Started Jul 16 07:47:48 PM PDT 24
Finished Jul 16 07:47:57 PM PDT 24
Peak memory 241920 kb
Host smart-f0de48ab-328f-4ee1-b111-459923843616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214516224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2214516224
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3009692375
Short name T26
Test name
Test status
Simulation time 14138681 ps
CPU time 0.76 seconds
Started Jul 16 07:51:15 PM PDT 24
Finished Jul 16 07:51:19 PM PDT 24
Peak memory 206392 kb
Host smart-95662db7-9e41-40d0-994d-fb619c73b888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009692375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3009692375
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1252924177
Short name T850
Test name
Test status
Simulation time 755108441 ps
CPU time 3.13 seconds
Started Jul 16 07:51:15 PM PDT 24
Finished Jul 16 07:51:21 PM PDT 24
Peak memory 225524 kb
Host smart-215bdf3c-0146-4849-bc68-fc4ab1f21eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252924177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1252924177
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4279365317
Short name T425
Test name
Test status
Simulation time 59593095 ps
CPU time 0.76 seconds
Started Jul 16 07:51:13 PM PDT 24
Finished Jul 16 07:51:14 PM PDT 24
Peak memory 207880 kb
Host smart-8cfddc67-a545-4e6d-88f1-7dc3d662468e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279365317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4279365317
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2348773627
Short name T213
Test name
Test status
Simulation time 18909838074 ps
CPU time 49.54 seconds
Started Jul 16 07:51:15 PM PDT 24
Finished Jul 16 07:52:08 PM PDT 24
Peak memory 250272 kb
Host smart-2d6528d0-d611-43fa-80cd-0dd83dec0e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348773627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2348773627
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1653788345
Short name T588
Test name
Test status
Simulation time 4665563280 ps
CPU time 82.24 seconds
Started Jul 16 07:51:13 PM PDT 24
Finished Jul 16 07:52:37 PM PDT 24
Peak memory 263136 kb
Host smart-2e2ec764-4372-4783-874f-40c6272a290a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653788345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1653788345
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.395938324
Short name T68
Test name
Test status
Simulation time 182991562555 ps
CPU time 458.52 seconds
Started Jul 16 07:51:17 PM PDT 24
Finished Jul 16 07:58:59 PM PDT 24
Peak memory 265920 kb
Host smart-37cc48b9-e6d8-4b3b-8b5f-16331b851cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395938324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.395938324
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4248680448
Short name T800
Test name
Test status
Simulation time 244208473 ps
CPU time 6.43 seconds
Started Jul 16 07:51:15 PM PDT 24
Finished Jul 16 07:51:25 PM PDT 24
Peak memory 233728 kb
Host smart-86264a9f-9edd-4ad7-a2dc-5b6720ecc36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248680448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4248680448
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2641654752
Short name T645
Test name
Test status
Simulation time 6752997118 ps
CPU time 33.6 seconds
Started Jul 16 07:51:16 PM PDT 24
Finished Jul 16 07:51:53 PM PDT 24
Peak memory 242088 kb
Host smart-935f9146-5f65-4ddf-8d0c-1b70748807a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641654752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2641654752
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1490061377
Short name T949
Test name
Test status
Simulation time 9018328170 ps
CPU time 37.67 seconds
Started Jul 16 07:51:15 PM PDT 24
Finished Jul 16 07:51:56 PM PDT 24
Peak memory 233796 kb
Host smart-d3e112f7-828a-408e-9988-cad21dbef1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490061377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1490061377
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3057911477
Short name T711
Test name
Test status
Simulation time 10743886297 ps
CPU time 28.48 seconds
Started Jul 16 07:51:16 PM PDT 24
Finished Jul 16 07:51:48 PM PDT 24
Peak memory 233864 kb
Host smart-bae75c17-471f-4848-8c75-af2793fc0161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057911477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3057911477
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3218305372
Short name T62
Test name
Test status
Simulation time 6213371969 ps
CPU time 19.24 seconds
Started Jul 16 07:51:15 PM PDT 24
Finished Jul 16 07:51:38 PM PDT 24
Peak memory 240188 kb
Host smart-3a7d0eab-46fd-455b-bec3-0187cd8d9402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218305372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3218305372
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.469465559
Short name T270
Test name
Test status
Simulation time 806453189 ps
CPU time 3.34 seconds
Started Jul 16 07:51:15 PM PDT 24
Finished Jul 16 07:51:22 PM PDT 24
Peak memory 233740 kb
Host smart-7d7b7759-46d5-4cfe-9b81-64e96fdd8946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469465559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.469465559
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3277719282
Short name T595
Test name
Test status
Simulation time 3300398559 ps
CPU time 8.74 seconds
Started Jul 16 07:51:13 PM PDT 24
Finished Jul 16 07:51:23 PM PDT 24
Peak memory 223732 kb
Host smart-d660b90f-eba9-4058-af1c-6e2612a8f0e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3277719282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3277719282
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1491463677
Short name T93
Test name
Test status
Simulation time 28959464640 ps
CPU time 122.36 seconds
Started Jul 16 07:51:18 PM PDT 24
Finished Jul 16 07:53:24 PM PDT 24
Peak memory 258504 kb
Host smart-7a06e462-75b4-421b-b43f-54f00cf901fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491463677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1491463677
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2976084289
Short name T538
Test name
Test status
Simulation time 3822752238 ps
CPU time 28.6 seconds
Started Jul 16 07:51:17 PM PDT 24
Finished Jul 16 07:51:50 PM PDT 24
Peak memory 217536 kb
Host smart-423963e7-a7f9-4bb7-972f-85928488251c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976084289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2976084289
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.955097381
Short name T31
Test name
Test status
Simulation time 2030239093 ps
CPU time 2.76 seconds
Started Jul 16 07:51:14 PM PDT 24
Finished Jul 16 07:51:19 PM PDT 24
Peak memory 217408 kb
Host smart-7382d998-ee60-42d8-b55c-d0c780ce3e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955097381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.955097381
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2241933005
Short name T889
Test name
Test status
Simulation time 24128396 ps
CPU time 1.06 seconds
Started Jul 16 07:51:18 PM PDT 24
Finished Jul 16 07:51:23 PM PDT 24
Peak memory 208936 kb
Host smart-92feb553-aa74-4998-b066-99913a5230c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241933005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2241933005
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1634235834
Short name T668
Test name
Test status
Simulation time 28015608 ps
CPU time 0.79 seconds
Started Jul 16 07:51:15 PM PDT 24
Finished Jul 16 07:51:18 PM PDT 24
Peak memory 206944 kb
Host smart-aeaab2f5-b750-4fb5-8c61-55b92de3e825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634235834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1634235834
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2399373715
Short name T623
Test name
Test status
Simulation time 118472916 ps
CPU time 2.32 seconds
Started Jul 16 07:51:14 PM PDT 24
Finished Jul 16 07:51:20 PM PDT 24
Peak memory 225288 kb
Host smart-0b130946-900a-40b0-b2f8-36a2f25498d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399373715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2399373715
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3348238427
Short name T496
Test name
Test status
Simulation time 47377817 ps
CPU time 0.73 seconds
Started Jul 16 07:51:17 PM PDT 24
Finished Jul 16 07:51:21 PM PDT 24
Peak memory 205780 kb
Host smart-e576c4b4-b74d-47dc-b1fe-fb8a72556231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348238427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3348238427
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1144175618
Short name T611
Test name
Test status
Simulation time 14867579542 ps
CPU time 9.97 seconds
Started Jul 16 07:51:16 PM PDT 24
Finished Jul 16 07:51:30 PM PDT 24
Peak memory 233796 kb
Host smart-1594e9a7-f2d7-490d-852d-fb1881075bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144175618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1144175618
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1420489684
Short name T648
Test name
Test status
Simulation time 53065911 ps
CPU time 0.8 seconds
Started Jul 16 07:51:14 PM PDT 24
Finished Jul 16 07:51:17 PM PDT 24
Peak memory 207904 kb
Host smart-d7bab3a0-6ea5-4887-b56c-79072f30c5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420489684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1420489684
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3917712988
Short name T151
Test name
Test status
Simulation time 48727148771 ps
CPU time 168.68 seconds
Started Jul 16 07:51:23 PM PDT 24
Finished Jul 16 07:54:13 PM PDT 24
Peak memory 264868 kb
Host smart-25e0ae99-66bf-486f-8a05-9339afc54ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917712988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3917712988
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1966894026
Short name T982
Test name
Test status
Simulation time 27905153136 ps
CPU time 61.27 seconds
Started Jul 16 07:51:21 PM PDT 24
Finished Jul 16 07:52:25 PM PDT 24
Peak memory 234052 kb
Host smart-60fd0f03-f864-4e6a-a00f-04570a403a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966894026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1966894026
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3719828892
Short name T155
Test name
Test status
Simulation time 158142007091 ps
CPU time 257.33 seconds
Started Jul 16 07:51:14 PM PDT 24
Finished Jul 16 07:55:35 PM PDT 24
Peak memory 261588 kb
Host smart-31db5de9-dc68-4fa6-82c0-3609c1b1487d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719828892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3719828892
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.270780970
Short name T334
Test name
Test status
Simulation time 209955410 ps
CPU time 8.99 seconds
Started Jul 16 07:51:16 PM PDT 24
Finished Jul 16 07:51:28 PM PDT 24
Peak memory 225500 kb
Host smart-3d22d399-a41b-4634-9b6e-18f35c478e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270780970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.270780970
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3442537152
Short name T1022
Test name
Test status
Simulation time 6194615648 ps
CPU time 22.17 seconds
Started Jul 16 07:51:23 PM PDT 24
Finished Jul 16 07:51:47 PM PDT 24
Peak memory 241812 kb
Host smart-4f8904a6-3b13-4971-8747-ca975d81db94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442537152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3442537152
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.675351045
Short name T730
Test name
Test status
Simulation time 6147551824 ps
CPU time 25.1 seconds
Started Jul 16 07:51:21 PM PDT 24
Finished Jul 16 07:51:49 PM PDT 24
Peak memory 233888 kb
Host smart-ba0c7da5-47b3-4b91-b646-a9aae152f535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675351045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.675351045
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.553451701
Short name T468
Test name
Test status
Simulation time 57697392 ps
CPU time 2.74 seconds
Started Jul 16 07:51:16 PM PDT 24
Finished Jul 16 07:51:22 PM PDT 24
Peak memory 225556 kb
Host smart-fd8b16d3-b41e-4cde-83e1-55db7ef70bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553451701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.553451701
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3648156403
Short name T327
Test name
Test status
Simulation time 1166756218 ps
CPU time 10.12 seconds
Started Jul 16 07:51:19 PM PDT 24
Finished Jul 16 07:51:32 PM PDT 24
Peak memory 233692 kb
Host smart-59ade7aa-d233-4b88-87fb-6b666de528a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648156403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3648156403
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1101969273
Short name T152
Test name
Test status
Simulation time 41711711799 ps
CPU time 24.28 seconds
Started Jul 16 07:51:18 PM PDT 24
Finished Jul 16 07:51:46 PM PDT 24
Peak memory 250176 kb
Host smart-ca9ac9b7-501c-458a-88ce-ab51cadda1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101969273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1101969273
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1115124131
Short name T740
Test name
Test status
Simulation time 4434263519 ps
CPU time 13.15 seconds
Started Jul 16 07:51:16 PM PDT 24
Finished Jul 16 07:51:32 PM PDT 24
Peak memory 223224 kb
Host smart-4bc4fe47-88ce-4cca-bb64-7e6b83a8012d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1115124131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1115124131
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2771900985
Short name T312
Test name
Test status
Simulation time 50376771737 ps
CPU time 162.39 seconds
Started Jul 16 07:51:25 PM PDT 24
Finished Jul 16 07:54:09 PM PDT 24
Peak memory 258332 kb
Host smart-6ca7dbec-8f32-47b3-87a3-c8a161c70b6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771900985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2771900985
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.585844646
Short name T184
Test name
Test status
Simulation time 4167247532 ps
CPU time 9.9 seconds
Started Jul 16 07:51:17 PM PDT 24
Finished Jul 16 07:51:30 PM PDT 24
Peak memory 217472 kb
Host smart-5a485cd0-4449-4e24-88d7-724220af2b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585844646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.585844646
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.490830222
Short name T690
Test name
Test status
Simulation time 5017551097 ps
CPU time 4.43 seconds
Started Jul 16 07:51:15 PM PDT 24
Finished Jul 16 07:51:22 PM PDT 24
Peak memory 217420 kb
Host smart-2500d4a8-d714-4ef6-818d-9b3e7f4dc9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490830222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.490830222
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.826329525
Short name T973
Test name
Test status
Simulation time 572916386 ps
CPU time 2.85 seconds
Started Jul 16 07:51:18 PM PDT 24
Finished Jul 16 07:51:24 PM PDT 24
Peak memory 217400 kb
Host smart-77dc7959-2495-4ebc-95f3-a6c6bf79b953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826329525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.826329525
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3490994178
Short name T998
Test name
Test status
Simulation time 96897093 ps
CPU time 0.92 seconds
Started Jul 16 07:51:18 PM PDT 24
Finished Jul 16 07:51:22 PM PDT 24
Peak memory 207996 kb
Host smart-1e29d721-be9d-4cd4-9897-685b3198d8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490994178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3490994178
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.153562918
Short name T147
Test name
Test status
Simulation time 2868139446 ps
CPU time 10.7 seconds
Started Jul 16 07:51:23 PM PDT 24
Finished Jul 16 07:51:35 PM PDT 24
Peak memory 225716 kb
Host smart-66f7a3d4-3d5b-47d3-8a6b-bb40832cca84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153562918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.153562918
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4184245801
Short name T27
Test name
Test status
Simulation time 15180638 ps
CPU time 0.73 seconds
Started Jul 16 07:51:24 PM PDT 24
Finished Jul 16 07:51:27 PM PDT 24
Peak memory 206368 kb
Host smart-c61d6d05-efcd-4226-a665-791e54958053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184245801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4184245801
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.196902573
Short name T953
Test name
Test status
Simulation time 11090346620 ps
CPU time 8.62 seconds
Started Jul 16 07:51:21 PM PDT 24
Finished Jul 16 07:51:32 PM PDT 24
Peak memory 233836 kb
Host smart-025956e6-37fe-408a-b523-ad88ca4d48be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196902573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.196902573
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.4218896060
Short name T380
Test name
Test status
Simulation time 60455614 ps
CPU time 0.77 seconds
Started Jul 16 07:51:25 PM PDT 24
Finished Jul 16 07:51:27 PM PDT 24
Peak memory 207548 kb
Host smart-d63f18cf-9f6c-46b0-9c3f-b72c908d5a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218896060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.4218896060
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.4267511573
Short name T715
Test name
Test status
Simulation time 135457467404 ps
CPU time 110.57 seconds
Started Jul 16 07:51:24 PM PDT 24
Finished Jul 16 07:53:16 PM PDT 24
Peak memory 250240 kb
Host smart-0fc33a74-54ea-4275-a576-756a42a80a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267511573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.4267511573
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4151435100
Short name T830
Test name
Test status
Simulation time 6676336217 ps
CPU time 60.59 seconds
Started Jul 16 07:51:27 PM PDT 24
Finished Jul 16 07:52:30 PM PDT 24
Peak memory 253996 kb
Host smart-de7541d8-265e-4d82-82fe-11a4b86221ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151435100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.4151435100
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.484235220
Short name T447
Test name
Test status
Simulation time 215826454 ps
CPU time 3.31 seconds
Started Jul 16 07:51:21 PM PDT 24
Finished Jul 16 07:51:27 PM PDT 24
Peak memory 233776 kb
Host smart-bbc47ab7-960b-44d1-ada2-ac8e2430f6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484235220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.484235220
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3269365015
Short name T906
Test name
Test status
Simulation time 2089528197 ps
CPU time 15.1 seconds
Started Jul 16 07:51:26 PM PDT 24
Finished Jul 16 07:51:43 PM PDT 24
Peak memory 235904 kb
Host smart-8de12bd1-ab2b-4c27-96b3-e6e39b546e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269365015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3269365015
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4121568122
Short name T439
Test name
Test status
Simulation time 7670868403 ps
CPU time 28.41 seconds
Started Jul 16 07:51:20 PM PDT 24
Finished Jul 16 07:51:51 PM PDT 24
Peak memory 233928 kb
Host smart-6782a186-73f5-4c59-9981-ef29e5551fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121568122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4121568122
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2116666193
Short name T742
Test name
Test status
Simulation time 14249869557 ps
CPU time 99.1 seconds
Started Jul 16 07:51:21 PM PDT 24
Finished Jul 16 07:53:03 PM PDT 24
Peak memory 250816 kb
Host smart-7fcf7afb-e7d4-4516-b95a-a058cf040bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116666193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2116666193
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2536001558
Short name T682
Test name
Test status
Simulation time 560452396 ps
CPU time 3 seconds
Started Jul 16 07:51:24 PM PDT 24
Finished Jul 16 07:51:28 PM PDT 24
Peak memory 225612 kb
Host smart-638447bc-2f98-4208-844a-f45aebcda895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536001558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2536001558
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2785727955
Short name T881
Test name
Test status
Simulation time 720898427 ps
CPU time 7.37 seconds
Started Jul 16 07:51:24 PM PDT 24
Finished Jul 16 07:51:33 PM PDT 24
Peak memory 219816 kb
Host smart-c12ebd98-8808-4619-9086-bc3c1d792aa5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2785727955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2785727955
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.107575717
Short name T996
Test name
Test status
Simulation time 24648377011 ps
CPU time 74.38 seconds
Started Jul 16 07:51:26 PM PDT 24
Finished Jul 16 07:52:42 PM PDT 24
Peak memory 250248 kb
Host smart-8b957f7f-ea02-4ad8-94c4-278b3d8ca97e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107575717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.107575717
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3668611271
Short name T965
Test name
Test status
Simulation time 46473604 ps
CPU time 0.72 seconds
Started Jul 16 07:51:19 PM PDT 24
Finished Jul 16 07:51:23 PM PDT 24
Peak memory 206632 kb
Host smart-4c974274-d191-49d8-8b29-e467da2e3362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668611271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3668611271
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.4017500183
Short name T395
Test name
Test status
Simulation time 2535791114 ps
CPU time 9.35 seconds
Started Jul 16 07:51:19 PM PDT 24
Finished Jul 16 07:51:32 PM PDT 24
Peak memory 217404 kb
Host smart-0d85bd4e-b2f6-4287-98b0-42123b7a462b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017500183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.4017500183
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3944832728
Short name T517
Test name
Test status
Simulation time 30917600 ps
CPU time 0.97 seconds
Started Jul 16 07:51:17 PM PDT 24
Finished Jul 16 07:51:21 PM PDT 24
Peak memory 207728 kb
Host smart-d5cca1e8-680b-4de5-b911-1db6e5176bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944832728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3944832728
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1445078090
Short name T500
Test name
Test status
Simulation time 135292209 ps
CPU time 1 seconds
Started Jul 16 07:51:15 PM PDT 24
Finished Jul 16 07:51:20 PM PDT 24
Peak memory 207996 kb
Host smart-aecf6984-2b0c-403d-bd1b-72ee9c357482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445078090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1445078090
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2986525696
Short name T211
Test name
Test status
Simulation time 14332079957 ps
CPU time 24.36 seconds
Started Jul 16 07:51:23 PM PDT 24
Finished Jul 16 07:51:49 PM PDT 24
Peak memory 235932 kb
Host smart-25051232-a9b7-4690-a6d5-39c84d28a78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986525696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2986525696
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2339998903
Short name T511
Test name
Test status
Simulation time 31264304 ps
CPU time 0.75 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:51:44 PM PDT 24
Peak memory 206660 kb
Host smart-4a4c72c9-3da2-4275-ab4c-e2c6f31486d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339998903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2339998903
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2679985036
Short name T552
Test name
Test status
Simulation time 372944872 ps
CPU time 4.39 seconds
Started Jul 16 07:51:26 PM PDT 24
Finished Jul 16 07:51:33 PM PDT 24
Peak memory 233828 kb
Host smart-56123dae-52c1-43cf-85ca-a98dbbef084f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679985036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2679985036
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.950599470
Short name T382
Test name
Test status
Simulation time 108336061 ps
CPU time 0.74 seconds
Started Jul 16 07:51:23 PM PDT 24
Finished Jul 16 07:51:26 PM PDT 24
Peak memory 206468 kb
Host smart-1f39cee1-d2c0-47a3-a6ea-ee19c18d6bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950599470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.950599470
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3705524337
Short name T654
Test name
Test status
Simulation time 2597394188 ps
CPU time 39.14 seconds
Started Jul 16 07:51:29 PM PDT 24
Finished Jul 16 07:52:10 PM PDT 24
Peak memory 252884 kb
Host smart-fd63da37-9350-41c2-b56a-82a711af5249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705524337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3705524337
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2745371831
Short name T444
Test name
Test status
Simulation time 8017944848 ps
CPU time 69.6 seconds
Started Jul 16 07:51:26 PM PDT 24
Finished Jul 16 07:52:37 PM PDT 24
Peak memory 241028 kb
Host smart-0cca1d73-2c72-4952-a472-6e59925af22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745371831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2745371831
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1210941488
Short name T672
Test name
Test status
Simulation time 6616143185 ps
CPU time 17.84 seconds
Started Jul 16 07:51:28 PM PDT 24
Finished Jul 16 07:51:49 PM PDT 24
Peak memory 218796 kb
Host smart-5427a664-4e08-4882-8ef1-4e776bf42ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210941488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1210941488
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4083173783
Short name T900
Test name
Test status
Simulation time 154705215 ps
CPU time 2.52 seconds
Started Jul 16 07:51:27 PM PDT 24
Finished Jul 16 07:51:31 PM PDT 24
Peak memory 233712 kb
Host smart-8ed745f3-ce81-42a4-bba8-c074a95d99f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083173783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4083173783
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.3615947014
Short name T364
Test name
Test status
Simulation time 40630035 ps
CPU time 0.77 seconds
Started Jul 16 07:51:28 PM PDT 24
Finished Jul 16 07:51:31 PM PDT 24
Peak memory 216904 kb
Host smart-bcd175a8-f18b-4a42-becc-54442fbfeab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615947014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.3615947014
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2967970130
Short name T842
Test name
Test status
Simulation time 2066004178 ps
CPU time 20.07 seconds
Started Jul 16 07:51:28 PM PDT 24
Finished Jul 16 07:51:51 PM PDT 24
Peak memory 225532 kb
Host smart-a50c92ff-fa13-41c0-a980-25acc9df7144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967970130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2967970130
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2742588694
Short name T692
Test name
Test status
Simulation time 19264398020 ps
CPU time 55.7 seconds
Started Jul 16 07:51:26 PM PDT 24
Finished Jul 16 07:52:24 PM PDT 24
Peak memory 250252 kb
Host smart-c6db42a2-0379-4bb5-8c76-3102ddaf855d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742588694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2742588694
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2096385544
Short name T616
Test name
Test status
Simulation time 4174409416 ps
CPU time 12.21 seconds
Started Jul 16 07:51:33 PM PDT 24
Finished Jul 16 07:51:48 PM PDT 24
Peak memory 242100 kb
Host smart-0a9fe8d4-136e-42b1-8922-a2ad3f4db0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096385544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2096385544
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3451537736
Short name T275
Test name
Test status
Simulation time 3858619898 ps
CPU time 4.58 seconds
Started Jul 16 07:51:31 PM PDT 24
Finished Jul 16 07:51:38 PM PDT 24
Peak memory 225152 kb
Host smart-0cad1fb4-ac2b-467b-8e80-9f81b61db1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451537736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3451537736
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3423814946
Short name T430
Test name
Test status
Simulation time 2608327396 ps
CPU time 10.01 seconds
Started Jul 16 07:51:35 PM PDT 24
Finished Jul 16 07:51:49 PM PDT 24
Peak memory 224136 kb
Host smart-0947f951-b954-412c-b5c1-b37fa0f32f3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3423814946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3423814946
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1079565115
Short name T158
Test name
Test status
Simulation time 61060503975 ps
CPU time 556.7 seconds
Started Jul 16 07:51:26 PM PDT 24
Finished Jul 16 08:00:45 PM PDT 24
Peak memory 266788 kb
Host smart-ca35f241-4b8e-4294-b3ef-861900053e9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079565115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1079565115
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3233542310
Short name T339
Test name
Test status
Simulation time 2177302825 ps
CPU time 20.84 seconds
Started Jul 16 07:51:29 PM PDT 24
Finished Jul 16 07:51:52 PM PDT 24
Peak memory 217488 kb
Host smart-7ba4ddb1-b030-4ea9-b70c-77eea04acac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233542310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3233542310
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1225222948
Short name T797
Test name
Test status
Simulation time 12807343 ps
CPU time 0.71 seconds
Started Jul 16 07:51:31 PM PDT 24
Finished Jul 16 07:51:34 PM PDT 24
Peak memory 206640 kb
Host smart-97c29215-6357-4b28-9f31-30b5f1c5fa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225222948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1225222948
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.898201244
Short name T844
Test name
Test status
Simulation time 27160200 ps
CPU time 1.2 seconds
Started Jul 16 07:51:27 PM PDT 24
Finished Jul 16 07:51:30 PM PDT 24
Peak memory 209080 kb
Host smart-9b32adfc-a9f1-4f2a-be07-fc6d6e83e765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898201244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.898201244
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3824195506
Short name T950
Test name
Test status
Simulation time 93231283 ps
CPU time 0.94 seconds
Started Jul 16 07:51:31 PM PDT 24
Finished Jul 16 07:51:35 PM PDT 24
Peak memory 208004 kb
Host smart-973bc941-193d-450a-98cb-b03c0957f132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824195506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3824195506
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3875602775
Short name T856
Test name
Test status
Simulation time 256486469 ps
CPU time 2.82 seconds
Started Jul 16 07:51:36 PM PDT 24
Finished Jul 16 07:51:43 PM PDT 24
Peak memory 241936 kb
Host smart-528f0d1c-79c1-4af3-b43c-a0904e0840fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875602775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3875602775
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.185520150
Short name T831
Test name
Test status
Simulation time 33664056 ps
CPU time 0.72 seconds
Started Jul 16 07:51:31 PM PDT 24
Finished Jul 16 07:51:34 PM PDT 24
Peak memory 206344 kb
Host smart-269f86e6-a7ec-4679-8c58-e5e31774f14e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185520150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.185520150
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3114046456
Short name T279
Test name
Test status
Simulation time 95387974 ps
CPU time 2.1 seconds
Started Jul 16 07:51:36 PM PDT 24
Finished Jul 16 07:51:43 PM PDT 24
Peak memory 225492 kb
Host smart-28df8b5e-84af-459a-a2d8-8b52660bf03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114046456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3114046456
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2423771923
Short name T390
Test name
Test status
Simulation time 78985758 ps
CPU time 0.82 seconds
Started Jul 16 07:51:27 PM PDT 24
Finished Jul 16 07:51:30 PM PDT 24
Peak memory 207500 kb
Host smart-60fa1954-b919-48cc-a8a9-b42c0f7c463a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423771923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2423771923
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3979536431
Short name T1028
Test name
Test status
Simulation time 50647169 ps
CPU time 0.75 seconds
Started Jul 16 07:51:33 PM PDT 24
Finished Jul 16 07:51:37 PM PDT 24
Peak memory 216896 kb
Host smart-e6a1a52b-5f25-4f75-bdaa-409d86c0601c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979536431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3979536431
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1149054049
Short name T340
Test name
Test status
Simulation time 34047073575 ps
CPU time 52.93 seconds
Started Jul 16 07:51:34 PM PDT 24
Finished Jul 16 07:52:30 PM PDT 24
Peak memory 239264 kb
Host smart-c5869464-3d09-465c-a208-d4ec4ee21558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149054049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1149054049
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1886511179
Short name T264
Test name
Test status
Simulation time 128748944668 ps
CPU time 166.04 seconds
Started Jul 16 07:51:34 PM PDT 24
Finished Jul 16 07:54:24 PM PDT 24
Peak memory 256040 kb
Host smart-d70b4af2-653c-44c1-a3fe-7ca460168369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886511179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1886511179
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3951869586
Short name T709
Test name
Test status
Simulation time 385972694 ps
CPU time 7.38 seconds
Started Jul 16 07:51:32 PM PDT 24
Finished Jul 16 07:51:42 PM PDT 24
Peak memory 233804 kb
Host smart-4c1c86f4-8b19-4738-bbd3-09f0fd8e8001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951869586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3951869586
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.4201918328
Short name T452
Test name
Test status
Simulation time 31262602 ps
CPU time 0.74 seconds
Started Jul 16 07:51:28 PM PDT 24
Finished Jul 16 07:51:31 PM PDT 24
Peak memory 216884 kb
Host smart-e2ef5a4f-2bf0-4934-b0c5-549813cca67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201918328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.4201918328
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1353893123
Short name T39
Test name
Test status
Simulation time 703247905 ps
CPU time 5.48 seconds
Started Jul 16 07:51:32 PM PDT 24
Finished Jul 16 07:51:40 PM PDT 24
Peak memory 225556 kb
Host smart-7deae04f-d2a9-4261-a973-2a508228c4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353893123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1353893123
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.122462230
Short name T418
Test name
Test status
Simulation time 5750623478 ps
CPU time 53.85 seconds
Started Jul 16 07:51:33 PM PDT 24
Finished Jul 16 07:52:30 PM PDT 24
Peak memory 237112 kb
Host smart-f2db348a-789d-4839-be40-ea5e2b048d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122462230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.122462230
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2262953762
Short name T661
Test name
Test status
Simulation time 35126629533 ps
CPU time 10.39 seconds
Started Jul 16 07:51:33 PM PDT 24
Finished Jul 16 07:51:47 PM PDT 24
Peak memory 233860 kb
Host smart-cef4aa88-d8f3-4c68-bcd1-cd73f26d444d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262953762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2262953762
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1563375241
Short name T855
Test name
Test status
Simulation time 415249113 ps
CPU time 4.23 seconds
Started Jul 16 07:51:32 PM PDT 24
Finished Jul 16 07:51:39 PM PDT 24
Peak memory 233760 kb
Host smart-2c4a28ed-4109-4125-b87b-e01adf313fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563375241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1563375241
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3738699909
Short name T8
Test name
Test status
Simulation time 682265106 ps
CPU time 8.46 seconds
Started Jul 16 07:51:33 PM PDT 24
Finished Jul 16 07:51:44 PM PDT 24
Peak memory 221492 kb
Host smart-67724043-9fa2-4c79-b506-3fc72369b1f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3738699909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3738699909
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2896343102
Short name T179
Test name
Test status
Simulation time 4145930028 ps
CPU time 58.12 seconds
Started Jul 16 07:51:34 PM PDT 24
Finished Jul 16 07:52:36 PM PDT 24
Peak memory 237336 kb
Host smart-5f1a4693-765c-463a-8aec-63384bc501a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896343102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2896343102
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2216412938
Short name T343
Test name
Test status
Simulation time 7015328376 ps
CPU time 9.48 seconds
Started Jul 16 07:51:32 PM PDT 24
Finished Jul 16 07:51:44 PM PDT 24
Peak memory 217360 kb
Host smart-10014804-59ac-471d-92a2-fb39d39eab05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216412938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2216412938
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2924350585
Short name T413
Test name
Test status
Simulation time 4094305039 ps
CPU time 3.86 seconds
Started Jul 16 07:51:34 PM PDT 24
Finished Jul 16 07:51:40 PM PDT 24
Peak memory 218488 kb
Host smart-b2d7e026-5caa-453d-b3de-6cf3ed7e6131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924350585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2924350585
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.491465431
Short name T478
Test name
Test status
Simulation time 31939285 ps
CPU time 0.99 seconds
Started Jul 16 07:51:32 PM PDT 24
Finished Jul 16 07:51:35 PM PDT 24
Peak memory 208576 kb
Host smart-fbaf18c9-5dbd-4585-b22e-64acc0d7d691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491465431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.491465431
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2481647536
Short name T393
Test name
Test status
Simulation time 328339995 ps
CPU time 0.92 seconds
Started Jul 16 07:51:32 PM PDT 24
Finished Jul 16 07:51:35 PM PDT 24
Peak memory 206852 kb
Host smart-a2b4441c-8f1c-461d-8d21-73af5977a6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481647536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2481647536
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.207935433
Short name T908
Test name
Test status
Simulation time 681736110 ps
CPU time 4.69 seconds
Started Jul 16 07:51:27 PM PDT 24
Finished Jul 16 07:51:34 PM PDT 24
Peak memory 241892 kb
Host smart-93ed74d0-c5bf-410b-8d33-9ab49e58d806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207935433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.207935433
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2266649171
Short name T9
Test name
Test status
Simulation time 11553795 ps
CPU time 0.73 seconds
Started Jul 16 07:51:34 PM PDT 24
Finished Jul 16 07:51:37 PM PDT 24
Peak memory 205816 kb
Host smart-8571d6cd-9256-44b5-afd9-b42699ac6617
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266649171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2266649171
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1016644634
Short name T788
Test name
Test status
Simulation time 1446751599 ps
CPU time 2.3 seconds
Started Jul 16 07:51:35 PM PDT 24
Finished Jul 16 07:51:42 PM PDT 24
Peak memory 225536 kb
Host smart-3b7c6b1f-2df0-4559-af07-5ce035fd1292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016644634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1016644634
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1134021355
Short name T530
Test name
Test status
Simulation time 24481529 ps
CPU time 0.79 seconds
Started Jul 16 07:51:28 PM PDT 24
Finished Jul 16 07:51:31 PM PDT 24
Peak memory 207572 kb
Host smart-55c366c7-0dee-4aa8-ae91-39bb64b2f7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134021355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1134021355
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2292072596
Short name T4
Test name
Test status
Simulation time 21145325621 ps
CPU time 32.48 seconds
Started Jul 16 07:51:27 PM PDT 24
Finished Jul 16 07:52:02 PM PDT 24
Peak memory 238796 kb
Host smart-c3d511d6-09bb-46ec-9e6f-491b49599fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292072596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2292072596
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2738596715
Short name T905
Test name
Test status
Simulation time 30894850192 ps
CPU time 133.36 seconds
Started Jul 16 07:51:34 PM PDT 24
Finished Jul 16 07:53:51 PM PDT 24
Peak memory 250648 kb
Host smart-5a9e5359-efcc-4740-9e9c-f4570b3c71c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738596715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2738596715
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3824819810
Short name T635
Test name
Test status
Simulation time 12212346808 ps
CPU time 46.49 seconds
Started Jul 16 07:51:34 PM PDT 24
Finished Jul 16 07:52:24 PM PDT 24
Peak memory 225084 kb
Host smart-346b76a6-2884-4041-b83a-910738d9a729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824819810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3824819810
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.4078012671
Short name T731
Test name
Test status
Simulation time 181228927 ps
CPU time 3.07 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:51:47 PM PDT 24
Peak memory 225584 kb
Host smart-aa0adb80-d6e3-46dd-8e8f-ae520db36d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078012671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4078012671
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2629925951
Short name T721
Test name
Test status
Simulation time 41720183 ps
CPU time 0.89 seconds
Started Jul 16 07:51:35 PM PDT 24
Finished Jul 16 07:51:40 PM PDT 24
Peak memory 217088 kb
Host smart-ee486b1d-1ba3-4d4f-9762-61a2c3ca02bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629925951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2629925951
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1220427806
Short name T968
Test name
Test status
Simulation time 13026065619 ps
CPU time 15.01 seconds
Started Jul 16 07:51:33 PM PDT 24
Finished Jul 16 07:51:51 PM PDT 24
Peak memory 225656 kb
Host smart-72196a87-166b-4c99-8f45-c3287d075b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220427806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1220427806
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3975668465
Short name T665
Test name
Test status
Simulation time 4340341529 ps
CPU time 22.15 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:52:05 PM PDT 24
Peak memory 225728 kb
Host smart-05359a8e-130d-4f57-a7ad-778b5906673d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975668465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3975668465
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2782913762
Short name T474
Test name
Test status
Simulation time 29368492540 ps
CPU time 17.71 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:52:01 PM PDT 24
Peak memory 233888 kb
Host smart-35c5f79e-bbdc-463e-9d23-0ad2cfa15fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782913762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2782913762
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.4124674453
Short name T669
Test name
Test status
Simulation time 17683802777 ps
CPU time 6.02 seconds
Started Jul 16 07:51:31 PM PDT 24
Finished Jul 16 07:51:40 PM PDT 24
Peak memory 233796 kb
Host smart-c40bfabc-3a55-4761-bc87-532991fb997a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124674453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.4124674453
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.828220465
Short name T150
Test name
Test status
Simulation time 4674279218 ps
CPU time 5.84 seconds
Started Jul 16 07:51:36 PM PDT 24
Finished Jul 16 07:51:47 PM PDT 24
Peak memory 224036 kb
Host smart-72956b5c-6caa-4e71-a5bd-35f2e9eb4284
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=828220465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.828220465
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2063992191
Short name T494
Test name
Test status
Simulation time 80619850510 ps
CPU time 200.78 seconds
Started Jul 16 07:51:35 PM PDT 24
Finished Jul 16 07:55:01 PM PDT 24
Peak memory 251356 kb
Host smart-e766733e-82b5-4f9f-9719-3ff03ac0a6fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063992191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2063992191
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1978235233
Short name T542
Test name
Test status
Simulation time 1452620664 ps
CPU time 4.94 seconds
Started Jul 16 07:51:33 PM PDT 24
Finished Jul 16 07:51:40 PM PDT 24
Peak memory 217596 kb
Host smart-4deab31b-d923-4001-a644-09b106b9d0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978235233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1978235233
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2329671589
Short name T847
Test name
Test status
Simulation time 4444611026 ps
CPU time 3.79 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:51:47 PM PDT 24
Peak memory 217568 kb
Host smart-7a318c00-e58b-4360-8f00-61c94fe7a1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329671589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2329671589
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.941796906
Short name T704
Test name
Test status
Simulation time 22800028 ps
CPU time 0.7 seconds
Started Jul 16 07:51:31 PM PDT 24
Finished Jul 16 07:51:34 PM PDT 24
Peak memory 206512 kb
Host smart-d5663059-9fe8-42de-82cb-c378aeb134c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941796906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.941796906
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.175266017
Short name T643
Test name
Test status
Simulation time 70128740 ps
CPU time 0.89 seconds
Started Jul 16 07:51:33 PM PDT 24
Finished Jul 16 07:51:36 PM PDT 24
Peak memory 206852 kb
Host smart-2128104f-994e-458a-a2c5-266f7571b501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175266017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.175266017
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3531774606
Short name T869
Test name
Test status
Simulation time 12125797347 ps
CPU time 13.11 seconds
Started Jul 16 07:51:27 PM PDT 24
Finished Jul 16 07:51:42 PM PDT 24
Peak memory 250352 kb
Host smart-11cb0221-5257-458c-a21d-2808952ed3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531774606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3531774606
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.398491386
Short name T442
Test name
Test status
Simulation time 11723664 ps
CPU time 0.71 seconds
Started Jul 16 07:51:36 PM PDT 24
Finished Jul 16 07:51:42 PM PDT 24
Peak memory 205764 kb
Host smart-61827a61-f22b-450e-8e89-0db46673fa1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398491386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.398491386
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1201890574
Short name T581
Test name
Test status
Simulation time 245674140 ps
CPU time 3.96 seconds
Started Jul 16 07:51:36 PM PDT 24
Finished Jul 16 07:51:46 PM PDT 24
Peak memory 225516 kb
Host smart-947302a8-3e7a-48fb-bda3-378ec0b61a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201890574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1201890574
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2171670662
Short name T657
Test name
Test status
Simulation time 21923481 ps
CPU time 0.83 seconds
Started Jul 16 07:51:28 PM PDT 24
Finished Jul 16 07:51:31 PM PDT 24
Peak memory 207472 kb
Host smart-e5370beb-9144-4648-a6a3-ff8bfe5da39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171670662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2171670662
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2352983070
Short name T218
Test name
Test status
Simulation time 55873896689 ps
CPU time 116.94 seconds
Started Jul 16 07:51:36 PM PDT 24
Finished Jul 16 07:53:39 PM PDT 24
Peak memory 241488 kb
Host smart-cbae6f8c-8c27-4305-ad95-cc283b30d879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352983070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2352983070
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.444522835
Short name T736
Test name
Test status
Simulation time 3936670292 ps
CPU time 51.02 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:52:35 PM PDT 24
Peak memory 241368 kb
Host smart-bdb65be9-4819-4755-af35-9c4f1ac7013e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444522835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.444522835
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.291500462
Short name T156
Test name
Test status
Simulation time 11309180101 ps
CPU time 157.89 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:54:21 PM PDT 24
Peak memory 258052 kb
Host smart-b589e563-67a1-4fc5-af2a-ec74d139030f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291500462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.291500462
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1835830826
Short name T920
Test name
Test status
Simulation time 278905765 ps
CPU time 4.23 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:51:47 PM PDT 24
Peak memory 234932 kb
Host smart-59efda4e-ab81-4906-a10e-e86b8062d2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835830826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1835830826
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1236930731
Short name T909
Test name
Test status
Simulation time 16452979262 ps
CPU time 92.03 seconds
Started Jul 16 07:51:36 PM PDT 24
Finished Jul 16 07:53:14 PM PDT 24
Peak memory 257704 kb
Host smart-3af18737-2a53-4d6a-8b80-39073b3c738c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236930731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1236930731
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1661852967
Short name T922
Test name
Test status
Simulation time 563822730 ps
CPU time 5.75 seconds
Started Jul 16 07:51:29 PM PDT 24
Finished Jul 16 07:51:37 PM PDT 24
Peak memory 225540 kb
Host smart-c0d92090-17e7-42b7-bdbc-977d9f44445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661852967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1661852967
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1915845788
Short name T571
Test name
Test status
Simulation time 143113190 ps
CPU time 5.68 seconds
Started Jul 16 07:51:30 PM PDT 24
Finished Jul 16 07:51:38 PM PDT 24
Peak memory 225592 kb
Host smart-f70dfdf5-f435-4826-ad67-be159f6e01ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915845788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1915845788
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1614761050
Short name T651
Test name
Test status
Simulation time 11230213440 ps
CPU time 32.51 seconds
Started Jul 16 07:51:35 PM PDT 24
Finished Jul 16 07:52:13 PM PDT 24
Peak memory 257888 kb
Host smart-c51d0075-2353-4426-a483-35024fcc4f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614761050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1614761050
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3465998749
Short name T749
Test name
Test status
Simulation time 4850784383 ps
CPU time 4.14 seconds
Started Jul 16 07:51:30 PM PDT 24
Finished Jul 16 07:51:36 PM PDT 24
Peak memory 225688 kb
Host smart-658bdd49-4661-434a-a850-0094c768ef7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465998749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3465998749
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2986794486
Short name T696
Test name
Test status
Simulation time 3835082814 ps
CPU time 6.55 seconds
Started Jul 16 07:51:29 PM PDT 24
Finished Jul 16 07:51:38 PM PDT 24
Peak memory 221784 kb
Host smart-94b891e2-c776-4125-8238-7b2d6c57e59e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2986794486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2986794486
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4151059346
Short name T1030
Test name
Test status
Simulation time 13928773117 ps
CPU time 222.06 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:55:26 PM PDT 24
Peak memory 262548 kb
Host smart-812b6077-e279-4dde-9072-348eb35157c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151059346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4151059346
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1489916262
Short name T747
Test name
Test status
Simulation time 10769743976 ps
CPU time 27.29 seconds
Started Jul 16 07:51:34 PM PDT 24
Finished Jul 16 07:52:05 PM PDT 24
Peak memory 217496 kb
Host smart-a0916653-e6b7-44d5-bb9d-3c15cdf716e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489916262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1489916262
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1036878599
Short name T480
Test name
Test status
Simulation time 9702629401 ps
CPU time 16.81 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:52:00 PM PDT 24
Peak memory 217436 kb
Host smart-80c5c95b-d519-4b63-97e3-29d6783b0d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036878599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1036878599
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3510818434
Short name T1011
Test name
Test status
Simulation time 56629073 ps
CPU time 1.35 seconds
Started Jul 16 07:51:30 PM PDT 24
Finished Jul 16 07:51:34 PM PDT 24
Peak memory 217320 kb
Host smart-28493e9f-205b-4675-b496-aaf66079507d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510818434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3510818434
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.264320290
Short name T828
Test name
Test status
Simulation time 103617636 ps
CPU time 0.76 seconds
Started Jul 16 07:51:36 PM PDT 24
Finished Jul 16 07:51:43 PM PDT 24
Peak memory 206744 kb
Host smart-781e8405-cc30-4ab5-aa67-121524c2e559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264320290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.264320290
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1099091879
Short name T824
Test name
Test status
Simulation time 153770283136 ps
CPU time 35.95 seconds
Started Jul 16 07:51:36 PM PDT 24
Finished Jul 16 07:52:18 PM PDT 24
Peak memory 250096 kb
Host smart-94c71bb1-ef0e-4398-8995-dae29ba31eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099091879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1099091879
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1985497069
Short name T769
Test name
Test status
Simulation time 93673323 ps
CPU time 0.77 seconds
Started Jul 16 07:51:35 PM PDT 24
Finished Jul 16 07:51:40 PM PDT 24
Peak memory 205740 kb
Host smart-19e058b5-fba5-4802-985e-9c94ea1cc7ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985497069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1985497069
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1020085276
Short name T307
Test name
Test status
Simulation time 779323403 ps
CPU time 4.83 seconds
Started Jul 16 07:51:34 PM PDT 24
Finished Jul 16 07:51:42 PM PDT 24
Peak memory 225636 kb
Host smart-df7c8bac-4c3d-45ff-95dc-d8f60b8cf576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020085276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1020085276
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2156290667
Short name T896
Test name
Test status
Simulation time 13167366 ps
CPU time 0.72 seconds
Started Jul 16 07:51:36 PM PDT 24
Finished Jul 16 07:51:42 PM PDT 24
Peak memory 206776 kb
Host smart-b03286b7-917e-4da7-a3ae-fc7f6fad3d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156290667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2156290667
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3990218990
Short name T255
Test name
Test status
Simulation time 8196212482 ps
CPU time 82.68 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:53:05 PM PDT 24
Peak memory 251320 kb
Host smart-567b4781-46bf-47c2-90d2-f30f7439bf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990218990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3990218990
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2541264231
Short name T317
Test name
Test status
Simulation time 201396344819 ps
CPU time 306.72 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:56:49 PM PDT 24
Peak memory 250380 kb
Host smart-0f49261a-92d4-41c3-b353-7c50437811fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541264231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2541264231
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3874434102
Short name T481
Test name
Test status
Simulation time 44661518141 ps
CPU time 243.07 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:55:46 PM PDT 24
Peak memory 258572 kb
Host smart-c2fa3523-6afa-41a6-b127-66602eba15c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874434102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3874434102
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1495529294
Short name T244
Test name
Test status
Simulation time 1613096363 ps
CPU time 6.74 seconds
Started Jul 16 07:51:34 PM PDT 24
Finished Jul 16 07:51:45 PM PDT 24
Peak memory 241968 kb
Host smart-289b1e10-0ba2-4840-a723-833cea5b83aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495529294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1495529294
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2154832887
Short name T198
Test name
Test status
Simulation time 1357990527 ps
CPU time 20.4 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:52:03 PM PDT 24
Peak memory 223272 kb
Host smart-1abed71a-306e-4ab0-86c9-891c3d763c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154832887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2154832887
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3668835677
Short name T269
Test name
Test status
Simulation time 757420614 ps
CPU time 4.12 seconds
Started Jul 16 07:51:30 PM PDT 24
Finished Jul 16 07:51:36 PM PDT 24
Peak memory 225600 kb
Host smart-4540e8f2-7788-42ff-9cd0-a0e2049b8a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668835677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3668835677
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3209527191
Short name T81
Test name
Test status
Simulation time 1786877883 ps
CPU time 20.8 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:52:04 PM PDT 24
Peak memory 250156 kb
Host smart-630de4c9-7c1e-4bed-b534-6e0b656d5089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209527191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3209527191
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.4276905198
Short name T310
Test name
Test status
Simulation time 21063931825 ps
CPU time 18.21 seconds
Started Jul 16 07:51:30 PM PDT 24
Finished Jul 16 07:51:50 PM PDT 24
Peak memory 233904 kb
Host smart-ff00350f-aecc-41e3-9137-2e13c1e7edb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276905198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.4276905198
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3126636687
Short name T237
Test name
Test status
Simulation time 1201802019 ps
CPU time 8.24 seconds
Started Jul 16 07:51:32 PM PDT 24
Finished Jul 16 07:51:42 PM PDT 24
Peak memory 233792 kb
Host smart-4d53cca5-24a7-4884-a508-1cf14202bf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126636687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3126636687
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.4083473714
Short name T512
Test name
Test status
Simulation time 261096498 ps
CPU time 3.3 seconds
Started Jul 16 07:51:34 PM PDT 24
Finished Jul 16 07:51:40 PM PDT 24
Peak memory 220496 kb
Host smart-bf20735c-1e75-4192-bc12-846147dcc6eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4083473714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.4083473714
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1155512816
Short name T962
Test name
Test status
Simulation time 35131567843 ps
CPU time 270.42 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:56:13 PM PDT 24
Peak memory 258560 kb
Host smart-5c177734-edf0-4f6d-9f89-63ec125b4039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155512816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1155512816
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1425274873
Short name T501
Test name
Test status
Simulation time 274143986 ps
CPU time 5.58 seconds
Started Jul 16 07:51:36 PM PDT 24
Finished Jul 16 07:51:46 PM PDT 24
Peak memory 217376 kb
Host smart-be1cee42-3a5a-4ac0-bc3f-fa4cefa7f316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425274873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1425274873
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.364539047
Short name T543
Test name
Test status
Simulation time 7423778718 ps
CPU time 21.48 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:52:05 PM PDT 24
Peak memory 217508 kb
Host smart-1da81697-ef2a-437e-acc9-a3505f21f111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364539047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.364539047
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2154943583
Short name T933
Test name
Test status
Simulation time 97124301 ps
CPU time 2.24 seconds
Started Jul 16 07:51:33 PM PDT 24
Finished Jul 16 07:51:37 PM PDT 24
Peak memory 217320 kb
Host smart-8f21b50f-e3fa-44ca-87ef-4403d374aeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154943583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2154943583
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4212988107
Short name T353
Test name
Test status
Simulation time 90648295 ps
CPU time 0.97 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:51:44 PM PDT 24
Peak memory 208024 kb
Host smart-62dbb554-175d-4646-a7da-216df38f0bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212988107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4212988107
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2091364240
Short name T222
Test name
Test status
Simulation time 56235376244 ps
CPU time 39.24 seconds
Started Jul 16 07:51:31 PM PDT 24
Finished Jul 16 07:52:13 PM PDT 24
Peak memory 225220 kb
Host smart-2b8e6017-5d79-4e1a-a285-f5e6cfa3ade7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091364240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2091364240
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2856050111
Short name T354
Test name
Test status
Simulation time 21921381 ps
CPU time 0.73 seconds
Started Jul 16 07:51:39 PM PDT 24
Finished Jul 16 07:51:46 PM PDT 24
Peak memory 206332 kb
Host smart-e89b7eaa-db5a-4740-bdcb-fe312dbb0e6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856050111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2856050111
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3567381643
Short name T902
Test name
Test status
Simulation time 2122402827 ps
CPU time 5.19 seconds
Started Jul 16 07:51:39 PM PDT 24
Finished Jul 16 07:51:51 PM PDT 24
Peak memory 225760 kb
Host smart-9d52917b-bf6c-4f79-8314-679d7684b058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567381643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3567381643
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.4048565846
Short name T621
Test name
Test status
Simulation time 25465537 ps
CPU time 0.81 seconds
Started Jul 16 07:51:40 PM PDT 24
Finished Jul 16 07:51:46 PM PDT 24
Peak memory 207780 kb
Host smart-ea16dd3f-5dab-4f49-a246-bf49ef2e6df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048565846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.4048565846
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2910767773
Short name T260
Test name
Test status
Simulation time 2306790715 ps
CPU time 50.71 seconds
Started Jul 16 07:51:41 PM PDT 24
Finished Jul 16 07:52:37 PM PDT 24
Peak memory 251268 kb
Host smart-bf38b832-5de1-4a78-8455-273760ba63b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910767773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2910767773
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3496980991
Short name T239
Test name
Test status
Simulation time 20652294024 ps
CPU time 112.73 seconds
Started Jul 16 07:51:38 PM PDT 24
Finished Jul 16 07:53:37 PM PDT 24
Peak memory 251464 kb
Host smart-b5b3e9b6-dde6-4710-b5fb-5f8c3e308012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496980991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3496980991
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1519453258
Short name T459
Test name
Test status
Simulation time 43337699001 ps
CPU time 83.63 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:53:07 PM PDT 24
Peak memory 250420 kb
Host smart-4e0fc68b-13cc-4ca2-8def-7ed88402ba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519453258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1519453258
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.4147572166
Short name T796
Test name
Test status
Simulation time 1923211317 ps
CPU time 10.16 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:51:54 PM PDT 24
Peak memory 233708 kb
Host smart-23a7e440-ca68-4f64-b5b3-4a5b9cc404e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147572166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.4147572166
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3337769901
Short name T205
Test name
Test status
Simulation time 2183370515 ps
CPU time 30.77 seconds
Started Jul 16 07:51:40 PM PDT 24
Finished Jul 16 07:52:16 PM PDT 24
Peak memory 233904 kb
Host smart-f4ea6d46-e557-4de4-934e-32ed6791a182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337769901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3337769901
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3309866358
Short name T612
Test name
Test status
Simulation time 405564288 ps
CPU time 2.32 seconds
Started Jul 16 07:51:41 PM PDT 24
Finished Jul 16 07:51:49 PM PDT 24
Peak memory 225040 kb
Host smart-8458d0c6-521c-40ec-839d-1692ab29f8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309866358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3309866358
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2985399713
Short name T774
Test name
Test status
Simulation time 8607347237 ps
CPU time 50.11 seconds
Started Jul 16 07:51:39 PM PDT 24
Finished Jul 16 07:52:36 PM PDT 24
Peak memory 225700 kb
Host smart-24703f4d-b216-413a-9807-47ea8cf8082a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985399713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2985399713
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3374750265
Short name T449
Test name
Test status
Simulation time 40081240619 ps
CPU time 9.29 seconds
Started Jul 16 07:51:36 PM PDT 24
Finished Jul 16 07:51:52 PM PDT 24
Peak memory 225704 kb
Host smart-4eb11a4b-7ddd-4c81-b428-52208980f94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374750265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3374750265
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.861280044
Short name T622
Test name
Test status
Simulation time 25011326398 ps
CPU time 18.19 seconds
Started Jul 16 07:51:40 PM PDT 24
Finished Jul 16 07:52:04 PM PDT 24
Peak memory 225908 kb
Host smart-98a485be-79ed-4254-ae7a-cb16b090b26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861280044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.861280044
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1912006332
Short name T768
Test name
Test status
Simulation time 2195858962 ps
CPU time 5.95 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:51:49 PM PDT 24
Peak memory 221536 kb
Host smart-a233df6a-5ae1-4c0b-9efe-c4d9937b3989
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1912006332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1912006332
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1394394401
Short name T177
Test name
Test status
Simulation time 6999182101 ps
CPU time 69.99 seconds
Started Jul 16 07:51:51 PM PDT 24
Finished Jul 16 07:53:03 PM PDT 24
Peak memory 267108 kb
Host smart-fa09d1b4-e43d-4be3-a1c7-48d8e927490f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394394401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1394394401
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1252659332
Short name T85
Test name
Test status
Simulation time 921450998 ps
CPU time 14.85 seconds
Started Jul 16 07:51:38 PM PDT 24
Finished Jul 16 07:51:59 PM PDT 24
Peak memory 217396 kb
Host smart-6c0bd65f-dbc8-4b00-a3ce-1cd2a09bc4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252659332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1252659332
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.81131611
Short name T25
Test name
Test status
Simulation time 26489018 ps
CPU time 1.12 seconds
Started Jul 16 07:51:42 PM PDT 24
Finished Jul 16 07:51:48 PM PDT 24
Peak memory 208540 kb
Host smart-437ffab7-d0b7-462d-ab60-8a9ff7a8e499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81131611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.81131611
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.682570678
Short name T384
Test name
Test status
Simulation time 59166386 ps
CPU time 0.85 seconds
Started Jul 16 07:51:51 PM PDT 24
Finished Jul 16 07:51:53 PM PDT 24
Peak memory 206984 kb
Host smart-9f7817ed-ef04-4663-a309-63bc61362357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682570678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.682570678
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2648339655
Short name T287
Test name
Test status
Simulation time 6180610216 ps
CPU time 4.27 seconds
Started Jul 16 07:51:38 PM PDT 24
Finished Jul 16 07:51:49 PM PDT 24
Peak memory 233856 kb
Host smart-ece74138-4369-4820-8381-f02212ed4b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648339655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2648339655
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2965638392
Short name T365
Test name
Test status
Simulation time 11473226 ps
CPU time 0.74 seconds
Started Jul 16 07:51:40 PM PDT 24
Finished Jul 16 07:51:47 PM PDT 24
Peak memory 205796 kb
Host smart-625dfdcc-c9fa-47eb-b6a2-c98071789a0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965638392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2965638392
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.4107899739
Short name T887
Test name
Test status
Simulation time 2066426431 ps
CPU time 3.98 seconds
Started Jul 16 07:51:40 PM PDT 24
Finished Jul 16 07:51:50 PM PDT 24
Peak memory 225504 kb
Host smart-2a54746a-05dc-49db-b3f1-c3fceb2babb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107899739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.4107899739
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1692679331
Short name T591
Test name
Test status
Simulation time 45455296 ps
CPU time 0.79 seconds
Started Jul 16 07:51:43 PM PDT 24
Finished Jul 16 07:51:48 PM PDT 24
Peak memory 207820 kb
Host smart-21257148-23ba-4bae-99e6-116e8bfa9f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692679331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1692679331
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3519947665
Short name T311
Test name
Test status
Simulation time 3846053320 ps
CPU time 67.14 seconds
Started Jul 16 07:51:51 PM PDT 24
Finished Jul 16 07:53:00 PM PDT 24
Peak memory 266296 kb
Host smart-58b1edf5-ba36-4f44-97f2-7465d7b4f9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519947665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3519947665
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.672582349
Short name T350
Test name
Test status
Simulation time 20659564063 ps
CPU time 36.12 seconds
Started Jul 16 07:51:40 PM PDT 24
Finished Jul 16 07:52:22 PM PDT 24
Peak memory 241048 kb
Host smart-89e0486f-194d-40e3-8db5-b6046702cb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672582349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.672582349
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3056951007
Short name T347
Test name
Test status
Simulation time 1432346451 ps
CPU time 24.52 seconds
Started Jul 16 07:51:38 PM PDT 24
Finished Jul 16 07:52:09 PM PDT 24
Peak memory 237432 kb
Host smart-edfd3c05-25d7-48b9-967f-eb3c27b995e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056951007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3056951007
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1815218394
Short name T52
Test name
Test status
Simulation time 2358811009 ps
CPU time 9.89 seconds
Started Jul 16 07:51:38 PM PDT 24
Finished Jul 16 07:51:54 PM PDT 24
Peak memory 250168 kb
Host smart-c67c3f40-77fb-44d0-93a2-c11344e6ab53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815218394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1815218394
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.853448380
Short name T283
Test name
Test status
Simulation time 4162886779 ps
CPU time 16.63 seconds
Started Jul 16 07:51:40 PM PDT 24
Finished Jul 16 07:52:02 PM PDT 24
Peak memory 233920 kb
Host smart-87c69797-8fdc-4989-a67f-b889be7e06c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853448380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.853448380
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3042605418
Short name T974
Test name
Test status
Simulation time 1687933613 ps
CPU time 16.39 seconds
Started Jul 16 07:51:50 PM PDT 24
Finished Jul 16 07:52:08 PM PDT 24
Peak memory 225524 kb
Host smart-3d979167-7ffb-40ac-b7d1-b2691902e110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042605418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3042605418
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1562638600
Short name T1010
Test name
Test status
Simulation time 278756434 ps
CPU time 3.86 seconds
Started Jul 16 07:51:41 PM PDT 24
Finished Jul 16 07:51:51 PM PDT 24
Peak memory 225572 kb
Host smart-51742e4a-c7be-472b-b45c-6047489a1963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562638600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1562638600
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1598302286
Short name T458
Test name
Test status
Simulation time 294726819 ps
CPU time 1.95 seconds
Started Jul 16 07:51:38 PM PDT 24
Finished Jul 16 07:51:46 PM PDT 24
Peak memory 225556 kb
Host smart-c8465bb6-3aca-4848-81c9-6c34fe8356d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598302286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1598302286
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3118637830
Short name T859
Test name
Test status
Simulation time 968236599 ps
CPU time 7.26 seconds
Started Jul 16 07:51:42 PM PDT 24
Finished Jul 16 07:51:54 PM PDT 24
Peak memory 223088 kb
Host smart-b66d4e12-c205-4248-8bc8-b08708c31810
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3118637830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3118637830
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.675881441
Short name T999
Test name
Test status
Simulation time 21430566 ps
CPU time 0.79 seconds
Started Jul 16 07:51:42 PM PDT 24
Finished Jul 16 07:51:48 PM PDT 24
Peak memory 206596 kb
Host smart-74c6b68f-0906-4121-9aed-dd30384ab968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675881441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.675881441
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.4199345168
Short name T580
Test name
Test status
Simulation time 2421840971 ps
CPU time 9.82 seconds
Started Jul 16 07:51:39 PM PDT 24
Finished Jul 16 07:51:55 PM PDT 24
Peak memory 217468 kb
Host smart-aab3573e-a9db-45b8-8979-df6aadaae1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199345168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.4199345168
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.4099298224
Short name T408
Test name
Test status
Simulation time 133218070 ps
CPU time 1.26 seconds
Started Jul 16 07:51:37 PM PDT 24
Finished Jul 16 07:51:44 PM PDT 24
Peak memory 209164 kb
Host smart-21190441-2383-46ff-9631-2db3251a211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099298224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.4099298224
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.978336954
Short name T707
Test name
Test status
Simulation time 47308469 ps
CPU time 0.8 seconds
Started Jul 16 07:51:52 PM PDT 24
Finished Jul 16 07:51:54 PM PDT 24
Peak memory 206984 kb
Host smart-6f014ad2-f905-4ca6-b5fc-28516e2dc141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978336954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.978336954
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.94018425
Short name T258
Test name
Test status
Simulation time 581174257 ps
CPU time 3.39 seconds
Started Jul 16 07:51:42 PM PDT 24
Finished Jul 16 07:51:50 PM PDT 24
Peak memory 233732 kb
Host smart-ee119791-c025-460e-a8ba-1af80d3b7977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94018425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.94018425
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.162148542
Short name T10
Test name
Test status
Simulation time 10750565 ps
CPU time 0.71 seconds
Started Jul 16 07:47:58 PM PDT 24
Finished Jul 16 07:48:00 PM PDT 24
Peak memory 206408 kb
Host smart-cb57c28b-55a6-4556-af39-6c6ea52f1889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162148542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.162148542
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2221015786
Short name T84
Test name
Test status
Simulation time 289726267 ps
CPU time 3.22 seconds
Started Jul 16 07:47:57 PM PDT 24
Finished Jul 16 07:48:02 PM PDT 24
Peak memory 225548 kb
Host smart-b6d966d9-1ed3-479f-aa8e-db92f3067942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221015786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2221015786
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2683198408
Short name T497
Test name
Test status
Simulation time 47146242 ps
CPU time 0.83 seconds
Started Jul 16 07:48:04 PM PDT 24
Finished Jul 16 07:48:06 PM PDT 24
Peak memory 207908 kb
Host smart-0ca56748-213f-4662-bdf7-46a843ea146e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683198408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2683198408
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.671014693
Short name T1016
Test name
Test status
Simulation time 2719338523 ps
CPU time 21.78 seconds
Started Jul 16 07:47:58 PM PDT 24
Finished Jul 16 07:48:22 PM PDT 24
Peak memory 242084 kb
Host smart-d03aeec1-b24d-490f-8f48-c3f3e3180668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671014693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.671014693
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1708324999
Short name T403
Test name
Test status
Simulation time 6650478358 ps
CPU time 35.29 seconds
Started Jul 16 07:47:57 PM PDT 24
Finished Jul 16 07:48:34 PM PDT 24
Peak memory 225836 kb
Host smart-421b15c7-be5e-4196-87d8-4e8c445b2817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708324999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1708324999
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1828519941
Short name T490
Test name
Test status
Simulation time 178547240 ps
CPU time 4.64 seconds
Started Jul 16 07:47:56 PM PDT 24
Finished Jul 16 07:48:02 PM PDT 24
Peak memory 237616 kb
Host smart-33fb5230-4255-43de-862b-94d94e0e54ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828519941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1828519941
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.209358276
Short name T625
Test name
Test status
Simulation time 11795975 ps
CPU time 0.82 seconds
Started Jul 16 07:48:04 PM PDT 24
Finished Jul 16 07:48:06 PM PDT 24
Peak memory 216988 kb
Host smart-8ccba893-3bdd-4fa8-b498-7ffe9d7967c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209358276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
209358276
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1718850494
Short name T455
Test name
Test status
Simulation time 2151692572 ps
CPU time 9.39 seconds
Started Jul 16 07:48:03 PM PDT 24
Finished Jul 16 07:48:13 PM PDT 24
Peak memory 225664 kb
Host smart-37cecf99-1f2c-4ee0-be1d-6ef9f9ad3b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718850494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1718850494
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.992518085
Short name T754
Test name
Test status
Simulation time 29969408636 ps
CPU time 111.49 seconds
Started Jul 16 07:48:05 PM PDT 24
Finished Jul 16 07:49:58 PM PDT 24
Peak memory 225660 kb
Host smart-e9539d09-7bdc-47bd-bee0-59ec75a242bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992518085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.992518085
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1836565429
Short name T632
Test name
Test status
Simulation time 53418161 ps
CPU time 1.11 seconds
Started Jul 16 07:48:02 PM PDT 24
Finished Jul 16 07:48:04 PM PDT 24
Peak memory 218976 kb
Host smart-7708ff2b-06b6-4d7c-a9c4-f8717a5c1e1d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836565429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1836565429
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.612097666
Short name T804
Test name
Test status
Simulation time 20881633199 ps
CPU time 42.45 seconds
Started Jul 16 07:47:56 PM PDT 24
Finished Jul 16 07:48:39 PM PDT 24
Peak memory 253416 kb
Host smart-46c40c9e-27ea-4c5a-b881-beef35afc6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612097666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
612097666
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1614300319
Short name T267
Test name
Test status
Simulation time 6227803947 ps
CPU time 6.32 seconds
Started Jul 16 07:48:03 PM PDT 24
Finished Jul 16 07:48:10 PM PDT 24
Peak memory 225640 kb
Host smart-7c16c507-1c85-4b72-96bf-d492d2677c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614300319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1614300319
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.9855652
Short name T440
Test name
Test status
Simulation time 565142897 ps
CPU time 3.57 seconds
Started Jul 16 07:47:56 PM PDT 24
Finished Jul 16 07:48:01 PM PDT 24
Peak memory 221584 kb
Host smart-b499a9a4-6523-4df1-815e-94df4e02777e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=9855652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.9855652
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2601477759
Short name T34
Test name
Test status
Simulation time 12908523881 ps
CPU time 82.25 seconds
Started Jul 16 07:47:56 PM PDT 24
Finished Jul 16 07:49:20 PM PDT 24
Peak memory 267392 kb
Host smart-2d8449f7-6044-47a2-89c4-05f4efb6178d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601477759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2601477759
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1984861557
Short name T429
Test name
Test status
Simulation time 1549515420 ps
CPU time 14.37 seconds
Started Jul 16 07:48:06 PM PDT 24
Finished Jul 16 07:48:21 PM PDT 24
Peak memory 217388 kb
Host smart-4204a09a-53e5-4b64-bbac-6e73d9048b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984861557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1984861557
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2087567788
Short name T724
Test name
Test status
Simulation time 855343221 ps
CPU time 4.72 seconds
Started Jul 16 07:47:59 PM PDT 24
Finished Jul 16 07:48:05 PM PDT 24
Peak memory 217248 kb
Host smart-8130914f-07d2-4c2a-8fa3-28520bb428f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087567788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2087567788
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1952176148
Short name T348
Test name
Test status
Simulation time 132760488 ps
CPU time 2.07 seconds
Started Jul 16 07:47:56 PM PDT 24
Finished Jul 16 07:47:59 PM PDT 24
Peak memory 217288 kb
Host smart-ff994cb2-9822-460e-b87d-bb0cd4315de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952176148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1952176148
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1922890387
Short name T614
Test name
Test status
Simulation time 438786985 ps
CPU time 1.01 seconds
Started Jul 16 07:47:57 PM PDT 24
Finished Jul 16 07:48:00 PM PDT 24
Peak memory 208028 kb
Host smart-570004ff-662f-4aaf-b5a4-4b80539ad66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922890387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1922890387
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2714720709
Short name T624
Test name
Test status
Simulation time 590502121 ps
CPU time 9.35 seconds
Started Jul 16 07:47:57 PM PDT 24
Finished Jul 16 07:48:08 PM PDT 24
Peak memory 225504 kb
Host smart-c170a096-75a0-49c7-880d-e873e2bc09f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714720709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2714720709
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3095725862
Short name T610
Test name
Test status
Simulation time 11602667 ps
CPU time 0.73 seconds
Started Jul 16 07:47:59 PM PDT 24
Finished Jul 16 07:48:01 PM PDT 24
Peak memory 206292 kb
Host smart-818ddb4c-f757-47f7-a0cd-f638bdef14b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095725862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
095725862
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2920002047
Short name T918
Test name
Test status
Simulation time 371791943 ps
CPU time 5.8 seconds
Started Jul 16 07:47:57 PM PDT 24
Finished Jul 16 07:48:05 PM PDT 24
Peak memory 225496 kb
Host smart-7f7592ab-bb50-4748-a0e7-212b23a97601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920002047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2920002047
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.17764892
Short name T383
Test name
Test status
Simulation time 45392332 ps
CPU time 0.78 seconds
Started Jul 16 07:47:59 PM PDT 24
Finished Jul 16 07:48:02 PM PDT 24
Peak memory 207456 kb
Host smart-0eef38e7-7395-40f7-ba11-bc874457615a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17764892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.17764892
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3301252682
Short name T716
Test name
Test status
Simulation time 56574240355 ps
CPU time 208.73 seconds
Started Jul 16 07:47:59 PM PDT 24
Finished Jul 16 07:51:29 PM PDT 24
Peak memory 250264 kb
Host smart-88c68503-b4d9-482b-b57e-c9c835da78ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301252682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3301252682
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2700881910
Short name T819
Test name
Test status
Simulation time 3109983897 ps
CPU time 52.36 seconds
Started Jul 16 07:47:56 PM PDT 24
Finished Jul 16 07:48:50 PM PDT 24
Peak memory 250416 kb
Host smart-612f8d98-073b-4c9d-bdbd-4bf51bca82c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700881910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2700881910
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1891630141
Short name T882
Test name
Test status
Simulation time 7586147620 ps
CPU time 157.65 seconds
Started Jul 16 07:48:03 PM PDT 24
Finished Jul 16 07:50:41 PM PDT 24
Peak memory 258628 kb
Host smart-0fab698c-44c5-4711-aeeb-9fd274bcabc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891630141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1891630141
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3373879178
Short name T446
Test name
Test status
Simulation time 153466157 ps
CPU time 6.24 seconds
Started Jul 16 07:48:04 PM PDT 24
Finished Jul 16 07:48:11 PM PDT 24
Peak memory 242060 kb
Host smart-f24dcd2f-1674-4b1a-9302-f7fe7e9748fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373879178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3373879178
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2645669277
Short name T527
Test name
Test status
Simulation time 1856075483 ps
CPU time 8.37 seconds
Started Jul 16 07:48:05 PM PDT 24
Finished Jul 16 07:48:15 PM PDT 24
Peak memory 233804 kb
Host smart-50f85b57-db75-4b26-ba5e-26d799479772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645669277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2645669277
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.798879394
Short name T832
Test name
Test status
Simulation time 21821181304 ps
CPU time 29.91 seconds
Started Jul 16 07:48:03 PM PDT 24
Finished Jul 16 07:48:34 PM PDT 24
Peak memory 233848 kb
Host smart-face6fb5-6497-42b3-beef-142c83cdd886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798879394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.798879394
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.4017296571
Short name T776
Test name
Test status
Simulation time 107439539 ps
CPU time 1.04 seconds
Started Jul 16 07:47:57 PM PDT 24
Finished Jul 16 07:48:00 PM PDT 24
Peak memory 218940 kb
Host smart-dfb3c400-548d-483f-a4f6-5672a2eb33cc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017296571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.4017296571
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3765933100
Short name T907
Test name
Test status
Simulation time 796409009 ps
CPU time 5.97 seconds
Started Jul 16 07:47:57 PM PDT 24
Finished Jul 16 07:48:05 PM PDT 24
Peak memory 225520 kb
Host smart-b5265b2c-0184-407c-b195-a1fb790da354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765933100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3765933100
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.500993578
Short name T698
Test name
Test status
Simulation time 1744834640 ps
CPU time 7.66 seconds
Started Jul 16 07:48:04 PM PDT 24
Finished Jul 16 07:48:13 PM PDT 24
Peak memory 233876 kb
Host smart-058bc781-cf0c-42db-b2f4-892dec96a2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500993578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.500993578
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1279919675
Short name T653
Test name
Test status
Simulation time 229520156 ps
CPU time 5.55 seconds
Started Jul 16 07:48:05 PM PDT 24
Finished Jul 16 07:48:12 PM PDT 24
Peak memory 219848 kb
Host smart-c0b74aad-0016-45d3-9b0b-ced2b6f42f81
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1279919675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1279919675
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.604971407
Short name T415
Test name
Test status
Simulation time 514889383 ps
CPU time 1.92 seconds
Started Jul 16 07:47:56 PM PDT 24
Finished Jul 16 07:48:00 PM PDT 24
Peak memory 217492 kb
Host smart-fc4f125e-dfca-4485-8808-203e2919f7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604971407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.604971407
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1825305272
Short name T714
Test name
Test status
Simulation time 1660046798 ps
CPU time 5.23 seconds
Started Jul 16 07:48:05 PM PDT 24
Finished Jul 16 07:48:11 PM PDT 24
Peak memory 217364 kb
Host smart-fa6eb3cd-3ace-4198-a596-6208395a4d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825305272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1825305272
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1078650498
Short name T381
Test name
Test status
Simulation time 71232980 ps
CPU time 0.8 seconds
Started Jul 16 07:47:57 PM PDT 24
Finished Jul 16 07:48:00 PM PDT 24
Peak memory 206984 kb
Host smart-6d5af33b-3970-479a-9263-a12d282613a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078650498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1078650498
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2179737858
Short name T388
Test name
Test status
Simulation time 127091317 ps
CPU time 0.95 seconds
Started Jul 16 07:47:57 PM PDT 24
Finished Jul 16 07:48:00 PM PDT 24
Peak memory 206960 kb
Host smart-2aac09f2-eb84-45c2-bafe-006621312941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179737858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2179737858
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.441875817
Short name T827
Test name
Test status
Simulation time 475620770 ps
CPU time 4.33 seconds
Started Jul 16 07:47:56 PM PDT 24
Finished Jul 16 07:48:02 PM PDT 24
Peak memory 225524 kb
Host smart-ceeb9ffd-4105-489f-b2c6-6bf91d57f4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441875817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.441875817
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1927985977
Short name T1026
Test name
Test status
Simulation time 122628659 ps
CPU time 0.74 seconds
Started Jul 16 07:48:12 PM PDT 24
Finished Jul 16 07:48:16 PM PDT 24
Peak memory 206380 kb
Host smart-f9420521-f74d-434a-a838-827ccc39d3c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927985977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
927985977
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1043219625
Short name T826
Test name
Test status
Simulation time 496794485 ps
CPU time 5.37 seconds
Started Jul 16 07:48:21 PM PDT 24
Finished Jul 16 07:48:27 PM PDT 24
Peak memory 225572 kb
Host smart-fcf514ad-20ac-4d23-9fcd-636c7976f9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043219625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1043219625
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.385075152
Short name T555
Test name
Test status
Simulation time 41976544 ps
CPU time 0.84 seconds
Started Jul 16 07:48:03 PM PDT 24
Finished Jul 16 07:48:04 PM PDT 24
Peak memory 206496 kb
Host smart-962c6f6a-b7c5-4432-88ad-8ba361a67fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385075152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.385075152
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3203635356
Short name T1018
Test name
Test status
Simulation time 100892647277 ps
CPU time 147.34 seconds
Started Jul 16 07:48:11 PM PDT 24
Finished Jul 16 07:50:39 PM PDT 24
Peak memory 266644 kb
Host smart-b408db44-5b8a-45db-b8cb-10666a9b4b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203635356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3203635356
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.4125965924
Short name T492
Test name
Test status
Simulation time 59027166557 ps
CPU time 117.55 seconds
Started Jul 16 07:48:14 PM PDT 24
Finished Jul 16 07:50:14 PM PDT 24
Peak memory 241816 kb
Host smart-f6d5c95d-0252-42e6-9e03-7352774b90be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125965924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.4125965924
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1088850081
Short name T770
Test name
Test status
Simulation time 7211339404 ps
CPU time 55.19 seconds
Started Jul 16 07:48:12 PM PDT 24
Finished Jul 16 07:49:10 PM PDT 24
Peak memory 240244 kb
Host smart-956a058f-ea0e-4fb8-a231-db53bd37d4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088850081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1088850081
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.4125680972
Short name T868
Test name
Test status
Simulation time 661359514 ps
CPU time 4.54 seconds
Started Jul 16 07:48:11 PM PDT 24
Finished Jul 16 07:48:18 PM PDT 24
Peak memory 225560 kb
Host smart-7fc35829-8cf8-4bf7-95fe-9c47e0e2a289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125680972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4125680972
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3490482624
Short name T741
Test name
Test status
Simulation time 8942585795 ps
CPU time 47.36 seconds
Started Jul 16 07:48:09 PM PDT 24
Finished Jul 16 07:48:57 PM PDT 24
Peak memory 250348 kb
Host smart-586fa95d-deb1-487d-b389-de89589ae708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490482624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3490482624
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1639975100
Short name T300
Test name
Test status
Simulation time 504872334 ps
CPU time 4.09 seconds
Started Jul 16 07:48:16 PM PDT 24
Finished Jul 16 07:48:22 PM PDT 24
Peak memory 225540 kb
Host smart-f9bcd2be-e3a5-4a97-973f-c6ef9e4e3330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639975100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1639975100
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.346644682
Short name T549
Test name
Test status
Simulation time 907935502 ps
CPU time 7.21 seconds
Started Jul 16 07:48:13 PM PDT 24
Finished Jul 16 07:48:23 PM PDT 24
Peak memory 241872 kb
Host smart-9b87624f-ae0c-4826-9c94-8ece806a80a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346644682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.346644682
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.160951245
Short name T435
Test name
Test status
Simulation time 23653012 ps
CPU time 1.01 seconds
Started Jul 16 07:48:05 PM PDT 24
Finished Jul 16 07:48:07 PM PDT 24
Peak memory 217668 kb
Host smart-b347a4b7-bd09-4dbb-b5eb-51a8550543c5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160951245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.160951245
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1312987809
Short name T903
Test name
Test status
Simulation time 50144082012 ps
CPU time 28.92 seconds
Started Jul 16 07:48:09 PM PDT 24
Finished Jul 16 07:48:39 PM PDT 24
Peak memory 233844 kb
Host smart-3567b6b8-06b7-4a0f-a03e-04bdb0f35b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312987809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1312987809
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3185210666
Short name T921
Test name
Test status
Simulation time 24919317228 ps
CPU time 18.57 seconds
Started Jul 16 07:48:11 PM PDT 24
Finished Jul 16 07:48:30 PM PDT 24
Peak memory 233856 kb
Host smart-8f7cc68a-3c9b-4b11-8fa8-37f88dbae7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185210666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3185210666
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1852234479
Short name T453
Test name
Test status
Simulation time 936563976 ps
CPU time 5.59 seconds
Started Jul 16 07:48:19 PM PDT 24
Finished Jul 16 07:48:25 PM PDT 24
Peak memory 221440 kb
Host smart-74770e53-9f03-4f53-935a-dbd0e0d53dcf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1852234479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1852234479
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.468571122
Short name T603
Test name
Test status
Simulation time 11468861 ps
CPU time 0.73 seconds
Started Jul 16 07:48:10 PM PDT 24
Finished Jul 16 07:48:12 PM PDT 24
Peak memory 206644 kb
Host smart-6ffa094e-4dba-45b6-9e01-c40b9b3bb1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468571122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.468571122
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2129720629
Short name T688
Test name
Test status
Simulation time 3853646451 ps
CPU time 10.65 seconds
Started Jul 16 07:48:10 PM PDT 24
Finished Jul 16 07:48:21 PM PDT 24
Peak memory 217532 kb
Host smart-e8aef338-13b5-4a0a-a56b-8ba0535fcdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129720629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2129720629
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4141246366
Short name T400
Test name
Test status
Simulation time 65258139 ps
CPU time 2.1 seconds
Started Jul 16 07:48:12 PM PDT 24
Finished Jul 16 07:48:17 PM PDT 24
Peak memory 217360 kb
Host smart-f598de9d-0cce-4653-9588-f15357cc1401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141246366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4141246366
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1763849823
Short name T431
Test name
Test status
Simulation time 55860712 ps
CPU time 0.86 seconds
Started Jul 16 07:48:11 PM PDT 24
Finished Jul 16 07:48:14 PM PDT 24
Peak memory 206940 kb
Host smart-3cb00e4d-2b4d-48a8-b04b-91fdae96788f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763849823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1763849823
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1053594499
Short name T40
Test name
Test status
Simulation time 37582249408 ps
CPU time 44.39 seconds
Started Jul 16 07:48:12 PM PDT 24
Finished Jul 16 07:48:59 PM PDT 24
Peak memory 242036 kb
Host smart-9df8e764-83c9-4997-96cb-4aef7111c876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053594499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1053594499
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2043930875
Short name T750
Test name
Test status
Simulation time 13492784 ps
CPU time 0.74 seconds
Started Jul 16 07:48:13 PM PDT 24
Finished Jul 16 07:48:17 PM PDT 24
Peak memory 206372 kb
Host smart-11f08e51-7f19-43ee-bd04-289249213d10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043930875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
043930875
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.568048545
Short name T885
Test name
Test status
Simulation time 342774217 ps
CPU time 2.41 seconds
Started Jul 16 07:48:19 PM PDT 24
Finished Jul 16 07:48:23 PM PDT 24
Peak memory 225576 kb
Host smart-ad99a0ef-f5b0-4ccd-b128-02c384c219b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568048545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.568048545
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3276369544
Short name T454
Test name
Test status
Simulation time 30640574 ps
CPU time 0.81 seconds
Started Jul 16 07:48:10 PM PDT 24
Finished Jul 16 07:48:12 PM PDT 24
Peak memory 207488 kb
Host smart-51cc7936-8701-43bf-b0b9-484c40b9cf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276369544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3276369544
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2144802321
Short name T737
Test name
Test status
Simulation time 1177719563 ps
CPU time 12.5 seconds
Started Jul 16 07:48:14 PM PDT 24
Finished Jul 16 07:48:29 PM PDT 24
Peak memory 235820 kb
Host smart-d8d18ddc-36cc-451a-8f4c-0fcbfe552e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144802321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2144802321
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.4098761179
Short name T534
Test name
Test status
Simulation time 16180109050 ps
CPU time 176.61 seconds
Started Jul 16 07:48:19 PM PDT 24
Finished Jul 16 07:51:17 PM PDT 24
Peak memory 250472 kb
Host smart-d48413cb-5e5a-4731-a9b4-8b62d2c20626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098761179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.4098761179
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.4129330773
Short name T475
Test name
Test status
Simulation time 42975996442 ps
CPU time 37.75 seconds
Started Jul 16 07:48:12 PM PDT 24
Finished Jul 16 07:48:53 PM PDT 24
Peak memory 237664 kb
Host smart-3d3937ea-77ac-481c-898e-7d602e80e376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129330773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.4129330773
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2808273557
Short name T948
Test name
Test status
Simulation time 225686999 ps
CPU time 3.06 seconds
Started Jul 16 07:48:15 PM PDT 24
Finished Jul 16 07:48:20 PM PDT 24
Peak memory 233732 kb
Host smart-5cb487cb-948e-43a4-b7f8-28d48fd785ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808273557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2808273557
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1565581528
Short name T956
Test name
Test status
Simulation time 36905578731 ps
CPU time 117.77 seconds
Started Jul 16 07:48:10 PM PDT 24
Finished Jul 16 07:50:08 PM PDT 24
Peak memory 270428 kb
Host smart-2acb3b5a-7922-4f39-9efd-2150b9a641c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565581528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1565581528
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2899634049
Short name T195
Test name
Test status
Simulation time 191728760 ps
CPU time 5.09 seconds
Started Jul 16 07:48:16 PM PDT 24
Finished Jul 16 07:48:23 PM PDT 24
Peak memory 225484 kb
Host smart-596aeed3-fd40-40bb-910a-6660f35a0d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899634049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2899634049
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.439657626
Short name T276
Test name
Test status
Simulation time 2864097408 ps
CPU time 31.77 seconds
Started Jul 16 07:48:11 PM PDT 24
Finished Jul 16 07:48:45 PM PDT 24
Peak memory 233880 kb
Host smart-f8fdbf28-2152-4f5f-9fc8-397c9719f5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439657626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.439657626
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.811801343
Short name T410
Test name
Test status
Simulation time 119638435 ps
CPU time 1.08 seconds
Started Jul 16 07:48:16 PM PDT 24
Finished Jul 16 07:48:19 PM PDT 24
Peak memory 217644 kb
Host smart-529e0034-473e-49ec-8008-2571579d41d2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811801343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.811801343
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3170687042
Short name T520
Test name
Test status
Simulation time 12120089203 ps
CPU time 23 seconds
Started Jul 16 07:48:11 PM PDT 24
Finished Jul 16 07:48:35 PM PDT 24
Peak memory 225708 kb
Host smart-c290da01-a87e-4473-8675-82365780136f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170687042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3170687042
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2239826215
Short name T362
Test name
Test status
Simulation time 105215098 ps
CPU time 2.01 seconds
Started Jul 16 07:48:11 PM PDT 24
Finished Jul 16 07:48:14 PM PDT 24
Peak memory 225204 kb
Host smart-633f49fb-3b26-40ce-b95c-6f2d884cb2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239826215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2239826215
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.888064178
Short name T836
Test name
Test status
Simulation time 74607170205 ps
CPU time 404.59 seconds
Started Jul 16 07:48:12 PM PDT 24
Finished Jul 16 07:54:58 PM PDT 24
Peak memory 267548 kb
Host smart-c39d7323-f730-421d-bccb-7c4510f893a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888064178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.888064178
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.833061739
Short name T402
Test name
Test status
Simulation time 6786552116 ps
CPU time 14.77 seconds
Started Jul 16 07:48:11 PM PDT 24
Finished Jul 16 07:48:27 PM PDT 24
Peak memory 217568 kb
Host smart-d3646393-f155-4d5c-8743-78d272afc5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833061739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.833061739
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1574683642
Short name T694
Test name
Test status
Simulation time 7691030759 ps
CPU time 8.36 seconds
Started Jul 16 07:48:20 PM PDT 24
Finished Jul 16 07:48:29 PM PDT 24
Peak memory 217560 kb
Host smart-f66e6b02-ab5c-4118-989d-eff6c8a71844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574683642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1574683642
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2195798986
Short name T944
Test name
Test status
Simulation time 55188833 ps
CPU time 2.38 seconds
Started Jul 16 07:48:12 PM PDT 24
Finished Jul 16 07:48:18 PM PDT 24
Peak memory 217448 kb
Host smart-6f862007-cf0e-4ef3-a977-b4e404814b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195798986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2195798986
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3084718647
Short name T372
Test name
Test status
Simulation time 148616082 ps
CPU time 0.85 seconds
Started Jul 16 07:48:11 PM PDT 24
Finished Jul 16 07:48:14 PM PDT 24
Peak memory 206996 kb
Host smart-0fd0b3a5-2a5d-41ce-994e-64d03f0ef4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084718647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3084718647
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3179658323
Short name T829
Test name
Test status
Simulation time 1976451705 ps
CPU time 7.75 seconds
Started Jul 16 07:48:16 PM PDT 24
Finished Jul 16 07:48:26 PM PDT 24
Peak memory 233744 kb
Host smart-a61915f4-4dfa-49ae-aa83-3b106c25dd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179658323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3179658323
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3954299693
Short name T717
Test name
Test status
Simulation time 35395485 ps
CPU time 0.75 seconds
Started Jul 16 07:48:13 PM PDT 24
Finished Jul 16 07:48:17 PM PDT 24
Peak memory 206380 kb
Host smart-49da7e69-556a-406d-8e0a-df22f871ef05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954299693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
954299693
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.869774088
Short name T202
Test name
Test status
Simulation time 136518039 ps
CPU time 2.59 seconds
Started Jul 16 07:48:11 PM PDT 24
Finished Jul 16 07:48:15 PM PDT 24
Peak memory 225552 kb
Host smart-0588113a-ae85-4bee-8ec9-902fd8eafd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869774088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.869774088
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3659173464
Short name T778
Test name
Test status
Simulation time 47024395 ps
CPU time 0.78 seconds
Started Jul 16 07:48:11 PM PDT 24
Finished Jul 16 07:48:14 PM PDT 24
Peak memory 207440 kb
Host smart-911d2b86-cfcf-41a7-beba-ac19e8b5c186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659173464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3659173464
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.4095533443
Short name T321
Test name
Test status
Simulation time 3961848148 ps
CPU time 78.23 seconds
Started Jul 16 07:48:18 PM PDT 24
Finished Jul 16 07:49:37 PM PDT 24
Peak memory 264152 kb
Host smart-6dc0271f-7b08-476b-9573-a60c32700f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095533443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4095533443
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.489707856
Short name T262
Test name
Test status
Simulation time 23740922006 ps
CPU time 39 seconds
Started Jul 16 07:48:11 PM PDT 24
Finished Jul 16 07:48:51 PM PDT 24
Peak memory 250368 kb
Host smart-215048e7-a3c9-4333-8fc2-60365d6013d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489707856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.489707856
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2042439759
Short name T71
Test name
Test status
Simulation time 231405309954 ps
CPU time 535.97 seconds
Started Jul 16 07:48:13 PM PDT 24
Finished Jul 16 07:57:12 PM PDT 24
Peak memory 257832 kb
Host smart-85b985b7-4520-44d5-bf5f-ecbce6b416ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042439759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2042439759
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4208740154
Short name T330
Test name
Test status
Simulation time 3311243928 ps
CPU time 15.31 seconds
Started Jul 16 07:48:13 PM PDT 24
Finished Jul 16 07:48:31 PM PDT 24
Peak memory 225676 kb
Host smart-f82a7540-a7f8-489e-abe8-4fbc7c83af5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208740154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4208740154
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.388718834
Short name T568
Test name
Test status
Simulation time 2224882597 ps
CPU time 21.83 seconds
Started Jul 16 07:48:11 PM PDT 24
Finished Jul 16 07:48:35 PM PDT 24
Peak memory 241944 kb
Host smart-eda8801e-8f69-4fd4-9949-29f8343ae7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388718834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
388718834
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3902244515
Short name T185
Test name
Test status
Simulation time 1516483650 ps
CPU time 5.52 seconds
Started Jul 16 07:48:11 PM PDT 24
Finished Jul 16 07:48:18 PM PDT 24
Peak memory 233732 kb
Host smart-200922bb-3204-4aee-afa9-fd4a7a18bbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902244515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3902244515
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3663273388
Short name T729
Test name
Test status
Simulation time 19376589773 ps
CPU time 43.17 seconds
Started Jul 16 07:48:12 PM PDT 24
Finished Jul 16 07:48:58 PM PDT 24
Peak memory 241988 kb
Host smart-e504e0e1-2c5e-419e-9927-18e3b1cc9242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663273388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3663273388
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3654427323
Short name T780
Test name
Test status
Simulation time 91328524 ps
CPU time 1.07 seconds
Started Jul 16 07:48:19 PM PDT 24
Finished Jul 16 07:48:21 PM PDT 24
Peak memory 219008 kb
Host smart-ef860bb2-71c7-4343-b998-ff6cfadce1b9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654427323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3654427323
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3459356087
Short name T807
Test name
Test status
Simulation time 27357160071 ps
CPU time 23.92 seconds
Started Jul 16 07:48:16 PM PDT 24
Finished Jul 16 07:48:42 PM PDT 24
Peak memory 233860 kb
Host smart-b4c9f9c5-1834-4465-899c-818fb0e3394b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459356087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3459356087
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.4189369737
Short name T281
Test name
Test status
Simulation time 4742028089 ps
CPU time 8.32 seconds
Started Jul 16 07:48:16 PM PDT 24
Finished Jul 16 07:48:26 PM PDT 24
Peak memory 233860 kb
Host smart-efb9353e-3230-422a-b56e-628b61a1c3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189369737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4189369737
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3444032688
Short name T55
Test name
Test status
Simulation time 476571309 ps
CPU time 4.21 seconds
Started Jul 16 07:48:14 PM PDT 24
Finished Jul 16 07:48:21 PM PDT 24
Peak memory 223580 kb
Host smart-e1f3d5f7-abb2-45a4-a243-a705ad303d81
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3444032688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3444032688
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2558935218
Short name T535
Test name
Test status
Simulation time 14944753834 ps
CPU time 110.01 seconds
Started Jul 16 07:48:13 PM PDT 24
Finished Jul 16 07:50:06 PM PDT 24
Peak memory 235076 kb
Host smart-a7352228-044d-4518-8836-8c6f1f5a0fb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558935218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2558935218
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3580149402
Short name T942
Test name
Test status
Simulation time 2484421797 ps
CPU time 4.45 seconds
Started Jul 16 07:48:13 PM PDT 24
Finished Jul 16 07:48:20 PM PDT 24
Peak memory 217476 kb
Host smart-8bb4ecb0-c5d9-469e-836e-241fdf524e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580149402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3580149402
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.220998214
Short name T620
Test name
Test status
Simulation time 345380423 ps
CPU time 3.1 seconds
Started Jul 16 07:48:12 PM PDT 24
Finished Jul 16 07:48:17 PM PDT 24
Peak memory 217240 kb
Host smart-db529be8-9fac-46cd-b1e5-430f4f529110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220998214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.220998214
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1295901606
Short name T565
Test name
Test status
Simulation time 421542457 ps
CPU time 4.87 seconds
Started Jul 16 07:48:10 PM PDT 24
Finished Jul 16 07:48:16 PM PDT 24
Peak memory 217272 kb
Host smart-a5d431c1-cca5-442f-9a81-786f534fc30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295901606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1295901606
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1769467880
Short name T946
Test name
Test status
Simulation time 64139518 ps
CPU time 0.84 seconds
Started Jul 16 07:48:11 PM PDT 24
Finished Jul 16 07:48:13 PM PDT 24
Peak memory 206920 kb
Host smart-0f325d40-0a86-4b6d-b9a5-ce5f9478c78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769467880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1769467880
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2086334426
Short name T193
Test name
Test status
Simulation time 3531017852 ps
CPU time 15.31 seconds
Started Jul 16 07:48:16 PM PDT 24
Finished Jul 16 07:48:33 PM PDT 24
Peak memory 249976 kb
Host smart-f76fba44-1a36-45e1-b6c1-5d4793350651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086334426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2086334426
Directory /workspace/9.spi_device_upload/latest
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