Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2787417	1			T2	203		T3	2		T4	28546
all_values[1]	2787417	1			T2	203		T3	2		T4	28546
all_values[2]	2787417	1			T2	203		T3	2		T4	28546
all_values[3]	2787417	1			T2	203		T3	2		T4	28546
all_values[4]	2787417	1			T2	203		T3	2		T4	28546
all_values[5]	2787417	1			T2	203		T3	2		T4	28546
all_values[6]	2787417	1			T2	203		T3	2		T4	28546
all_values[7]	2787417	1			T2	203		T3	2		T4	28546

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22008795

1

T2

1624

T3

16

T4

228368

auto[1]

290541

1

T10

2804

T17

99

T19

68

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22270361

1

T2

1624

T3

16

T4

228243

auto[1]

28975

1

T4

125

T10

29

T13

20

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2753544	1			T2	203		T3	2		T4	28447
all_values[0]	auto[0]	auto[1]	14254	1			T4	99		T10	18		T13	10
all_values[0]	auto[1]	auto[0]	19345	1			T10	1		T17	8		T19	7
all_values[0]	auto[1]	auto[1]	274	1			T17	5		T19	2		T21	8
all_values[1]	auto[0]	auto[0]	2763197	1			T2	203		T3	2		T4	28533
all_values[1]	auto[0]	auto[1]	9446	1			T4	13		T10	1		T13	10
all_values[1]	auto[1]	auto[0]	14513	1			T10	699		T17	6		T19	5
all_values[1]	auto[1]	auto[1]	261	1			T10	2		T17	1		T19	4
all_values[2]	auto[0]	auto[0]	2751651	1			T2	203		T3	2		T4	28533
all_values[2]	auto[0]	auto[1]	3051	1			T4	13		T10	1		T36	34
all_values[2]	auto[1]	auto[0]	32506	1			T10	700		T17	6		T19	7
all_values[2]	auto[1]	auto[1]	209	1			T10	1		T17	2		T19	2
all_values[3]	auto[0]	auto[0]	2719516	1			T2	203		T3	2		T4	28546
all_values[3]	auto[0]	auto[1]	149	1			T17	6		T19	1		T44	1
all_values[3]	auto[1]	auto[0]	67590	1			T10	700		T17	10		T19	8
all_values[3]	auto[1]	auto[1]	162	1			T19	6		T44	2		T21	5
all_values[4]	auto[0]	auto[0]	2719100	1			T2	203		T3	2		T4	28546
all_values[4]	auto[0]	auto[1]	143	1			T10	1		T17	1		T19	5
all_values[4]	auto[1]	auto[0]	68013	1			T10	700		T17	8		T19	2
all_values[4]	auto[1]	auto[1]	161	1			T17	6		T19	2		T44	3
all_values[5]	auto[0]	auto[0]	2732760	1			T2	203		T3	2		T4	28546
all_values[5]	auto[0]	auto[1]	118	1			T10	3		T17	3		T19	1
all_values[5]	auto[1]	auto[0]	54388	1			T17	11		T19	6		T44	5
all_values[5]	auto[1]	auto[1]	151	1			T17	6		T19	2		T44	2
all_values[6]	auto[0]	auto[0]	2769348	1			T2	203		T3	2		T4	28546
all_values[6]	auto[0]	auto[1]	147	1			T17	1		T19	5		T44	4
all_values[6]	auto[1]	auto[0]	17753	1			T10	1		T17	8		T19	3
all_values[6]	auto[1]	auto[1]	169	1			T17	3		T19	4		T44	4
all_values[7]	auto[0]	auto[0]	2772237	1			T2	203		T3	2		T4	28546
all_values[7]	auto[0]	auto[1]	134	1			T10	2		T19	2		T44	2
all_values[7]	auto[1]	auto[0]	14900	1			T17	10		T19	4		T44	6
all_values[7]	auto[1]	auto[1]	146	1			T17	9		T19	4		T44	3